| d1ee80948144526b985afb44a0574248cf7da58a |
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13-Apr-2016 |
Vladimir Marko <vmarko@google.com> |
Move Assemblers to the Arena.
And clean up some APIs to return std::unique_ptr<> instead
of raw pointers that don't communicate ownership.
(cherry picked from commit 93205e395f777c1dd81d3f164cf9a4aec4bde45f)
Bug: 27505766
Change-Id: I3017302307a0253d661240750298802fb0d9585e
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| abdac47c3c471d034a5b81aec35bf4201ba86a88 |
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12-Feb-2016 |
Mark Mendell <mark.p.mendell@intel.com> |
Add X86/X86_64 support for CMOV from memory.
Add support for the memory form of CMOV. Add tests.
Change-Id: Ib9f5dbd3031c7e235ee3f2afdb7db75eed46277a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| c39dac148cce137ffd78a8e43499fba10c5c79e0 |
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21-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Support for x86 popcnt.
Change-Id: I0fc4e745764f1749a6437a199a594f3d8ea53eef
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| 9f51f26b815fb955a3b91df86d54acd3f41480e4 |
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30-Oct-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
X86: Add support for ucomis[sd] reg/memory form
Allow an Address as the second operand.
Change-Id: I4940829e2e4bfe0cddef3808265fdb638ac07b7e
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| bcee092d7b0cbb7181d428115ad98d25ce844061 |
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16-Sep-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Add X86 bsf and rotate instructions
These are for use in new intrinsics. Bsf (Bit Scan Forward) is used in
{Long,Integer}NumberOfTrailingZeros and the rotates are used in
{Long,Integer}Rotate{Left,Right}.
Change-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| 73f455ecb76d063846a82735eb80596ceee8cee3 |
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21-Aug-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
X86: Assembler support for near labels
The optimizing compiler uses 32 bit relative jumps for all forward
jumps, just in case the offset is too large to fit in one byte. Some of
the generated code knows that the jumps will in fact fit.
Add a 'NearLabel' class to the x86 and x86_64 assemblers. This will be
used to generate known short forward branches.
Add jecxz/jrcxz instructions, which only handle a short offset. They
will be used for intrinsics.
Add tests for the new instructions and NearLabel.
Change-Id: I11177f36394d35d63b32364b0e6289ee6d97de46
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| 8ae3ffb29489a127f2a6242c33845dac8d50e508 |
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13-Aug-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Add 'bsr' instruction to x86 and x86_64
Add support for 'bsr' instruction. Add tests.
Change-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| b9c4bbee9364a9351376fd1fec9604e7c84778d8 |
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01-Jul-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Add rep movsw to x86 and x86_64 instructions.
Add 'REP MOVSW' as a supported instruction for x86 32 and 64 bit.
Added tests.
Change-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| 970abfb65530b700f3a0cc8b90b131df5420cec3 |
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31-Jul-2015 |
agicsaki <agicsaki@google.com> |
Added repe_cmpsl instruction to x86, x86_64 assemblers
Support for this instruction has already been added to the disassembler
in commit 124b392d.
Change-Id: I6e8401a7b814618758427f5cc6b4992e265f937c
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| 7a08fb53bd13c74dec92256bef22a37250db1373 |
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15-Jul-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Optimizing: Add Non Temporal Move support for x86
Add moves that don't pollute the data cache. These can be used for
assigning large data structures.
Change-Id: I14d91ba6264f5ce2f128033d65d59b2536426643
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| 71311f868e2579fa5d40b24e620198734119d1a0 |
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27-Jul-2015 |
agicsaki <agicsaki@google.com> |
Added repe_cmpsw instruction to x86, x86_64 assemblers
Change-Id: I7634959eebb64d607f47497db320d5c2afdef16b
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| 21030dd59b1e350f6f43de39e3c4ce0886ff539c |
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07-May-2015 |
Andreas Gampe <agampe@google.com> |
ART: x86 indexOf intrinsics for the optimizing compiler
Add intrinsics implementations for indexOf in the optimizing
compiler. These are mostly ported from Quick. Add instruction
support to assemblers where necessary.
Change-Id: Ife90ed0245532a5c436a26fe84715dc357f353c8
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| 0a18601f141d864a26d4b74ff5613e69ae411483 |
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13-Apr-2015 |
Roland Levillain <rpl@google.com> |
Exercise the x86 and x86-64 FILD and FISTP instructions.
- Ensure the double- and quadword x87 (FPU) instructions for
integer loading (resp. fildl and fildll) are properly
generated by the x86 and x86-64 generators (resp.
X86Assembler::filds/X86_64Assembler::filds and
X86Assembler::fildl/X86_64Assembler::fildl).
- Ensure the double- and quadword x87 (FPU) instructions for
integer storing & popping (resp. filstpl and fistpll) are
properly generated by the x86 and x86-64 generators (resp.
X86Assembler::fistps/X86_64Assembler::fistps and
X86Assembler::fistpl/X86_64Assembler::fistpl).
These instructions can be used in the implementation of the
long-to-float and long-to-double Dex type conversions.
Change-Id: Iade52a9aee326d189d77d3dbd352a2b5dab52e46
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| 58d25fd052e999a24734b0cf856a1563e3d1b2d0 |
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03-Apr-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Implement more x86/x86_64 intrinsics
Implement CAS and bit reverse and byte reverse intrinsics that were
missing from x86 and x86_64 implementations.
Add assembler tests and compareAndSwapLong test.
Change-Id: Iabb2ff46036645df0a91f640288ef06090a64ee3
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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| 52c489645b6e9ae33623f1ec24143cde5444906e |
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16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
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| 647b9ed41cdb7cf302fd356627a3ba372419b78c |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for long-to-double in the optimizing compiler.
- Add support for the long-to-double Dex instruction in the
optimizing compiler.
- Enable requests of temporary FPU (double) registers during
code generation.
- Fix art::x86::X86Assembler::LoadLongConstant and extend
it to int64_t values.
- Have art::x86_64::X86_64Assembler::cvtsi2sd work with
64-bit operands.
- Generate x86, x86-64 and ARM (but not ARM64) code for
long to double HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd
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| 834b394ee759ed31c5371d8093d7cd8cd90014a8 |
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31-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Merge remote-tracking branch 'goog/dalvik-dev' into merge-art-to-dalvik-dev
Change-Id: I323e9e8c29c3e39d50d9aba93121b26266c52a46
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| 166db04e259ca51838c311891598664deeed85ad |
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26-Jul-2013 |
Ian Rogers <irogers@google.com> |
Move assembler out of runtime into compiler/utils.
Other directory layout bits of clean up. There is still work to separate quick
and portable in some files (e.g. argument visitor, proxy..).
Change-Id: If8fecffda8ba5c4c47a035f0c622c538c6b58351
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