| c3deddd9c2bf54fa6bec3dbd9ec7eae5fa22e220 |
|
08-Sep-2015 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Handle surface offsets exceeding 32 bits correctly
The slice_size and bo_size fields were getting truncated to 32 bits.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 0f8da82500ec542e269092c0718479e25eaff5f6 |
|
31-Mar-2015 |
Emil Velikov <emil.l.velikov@gmail.com> |
drm: remove drm_public macro
Some compilers (like the Oracle Studio), require that the function
declaration must be annotated with the same visibility attribute as the
definition. As annotating functions with drm_public is no longer
required just remove the macro.
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
/external/libdrm/radeon/radeon_surface.c
|
| 42465feb9759ef5a6d79d7e628510cd0a081f913 |
|
05-Apr-2015 |
Emil Velikov <emil.l.velikov@gmail.com> |
drm: rename libdrm{,_macros}.h
Provide a more meaningful name, considering what it does.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
/external/libdrm/radeon/radeon_surface.c
|
| eca91cf163d50090db36d0b2abbffcff813a2adf |
|
09-Jan-2015 |
Dave Airlie <airlied@redhat.com> |
radeon: align r600/700 fmask to 128 X blocks.
After much searching and empricial testing, and reading of
things I've no justifcation for this fix, other than it really
appears this is what the hw is doing or close enough.
It makes sense that each entry in the FMASK corresponds to
an entry in the CMASKm and the CMASK is organised into 128x128
blocks, but I can't find anything in any of the docs/info from AMD.
But I've spent a lot of time on this, and this seems to be the
simplest fix, in that we don't over allocate things too much,
once this fix in place we can nuke the extra multiplier in mesa.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| c866dc7c00e7f5f219901a9a81bf456a24d29cd1 |
|
26-Sep-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Always multiply pitch_bytes by nsamples, not by slice_pt
slice_pt is tileb[0] / tile_split, which isn't directly related to the
pitch.
This caused pitch_bytes to be too large in some cases.
[0] Tile size in bytes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 6281cf1b4310ff0b7670677cb4113a89ebf0b619 |
|
07-Sep-2014 |
Emil Velikov <emil.l.velikov@gmail.com> |
radeon: use drm_mmap/drm_munmap wrappers
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
/external/libdrm/radeon/radeon_surface.c
|
| 391bba9c4cd2825eadaa648df10e3d1c99c66e80 |
|
18-Aug-2014 |
Maks Naumov <maksqwe1@ukr.net> |
radeon: Fix surf->bankh init by default value when surf->tile_split == 0
Signed-off-by: Maks Naumov <maksqwe1@ukr.net>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 58ce9d6292c7033ff76bb2ef35da0e4c36de2389 |
|
31-Jul-2014 |
Maarten Lankhorst <maarten.lankhorst@canonical.com> |
radeon: Use symbol visibility.
All the bof_* symbols are now no longer exported.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 2169dce96c5503ef8f6e4bb008e989d0ef02ec8e |
|
26-Jul-2014 |
Marek Olšák <marek.olsak@amd.com> |
radeon: fix typo in sample split / fixes MSAA on Hawaii
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 72f84b85afbe762b86ea8c095fee01e7d406b131 |
|
15-Jul-2014 |
Thomas Klausner <wiz@NetBSD.org> |
radeon: Remove superfluous parentheses.
Signed-off-by: Thomas Klausner <wiz@NetBSD.org>
/external/libdrm/radeon/radeon_surface.c
|
| c2bc8ad438693262480ce1426bcf5c1d8ec4e808 |
|
17-Apr-2014 |
Samuel Li <samuel.li@amd.com> |
radeon: add Mullins chip family
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 1543c96e154d6801cf725c3b511d61604a378e03 |
|
10-Dec-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: avoid possible divide by 0 in surface manager
Some users report hitting a divide by 0 with the tile split in
certain apps. Tile_split shouldn't ever be 0 unless the surface
structure was not properly initialized. I think there may be some
cases where mesa uses an improperly initialized surface struct,
but I haven't had time to track it down.
Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=72425
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| c8a437f4c76527b3c8385699ccee07f35fe3f166 |
|
26-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Update unaligned offset for 2D->1D tiling transition on SI
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983
Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
/external/libdrm/radeon/radeon_surface.c
|
| 3f4648902296efa3a8cc0abc941d978637f0ee28 |
|
23-Nov-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: handle P16 pipe configs for Hawaii
/external/libdrm/radeon/radeon_surface.c
|
| f0e399d8f0c3c006687e0fc8e68268087607d5f5 |
|
18-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: don't overallocate stencil by 4 on SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 67d92404d62044972599dcef3011d17fca46eed5 |
|
22-Nov-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: implement 2D tiling for CIK
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| ce8af454259279c14c44bcd32c429640ca5e1691 |
|
14-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: fix mipmap level 0 and 1 alignment for SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| efcc456030334a692e2fce7bbd279df3aee13a6d |
|
24-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add hawaii chip family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 75f747b919e1b1cd852eeaa8e662e72273189fb2 |
|
19-Sep-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: fix pitch alignment for non-power-of-two mipmaps on SI
This fixes VM protection faults.
I have a new piglit test which can iterate over all possible widths, heights,
and depths (including NPOT) and tests mipmapping with various texture targets.
After this is committed, I'll make a new release of libdrm and bump
the libdrm version requirement in Mesa.
/external/libdrm/radeon/radeon_surface.c
|
| a48d6e5621fea701e36724cc144d9fe293332824 |
|
18-Sep-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 0ff7f2760d052503d5cf65ded34a66fe20ccec28 |
|
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add CIK chip families
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| e5e51c2110ebf6e1edaa14b7567c5d6a79008a90 |
|
24-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| c56729cc1564bb4204ca30a18499a78a39f48892 |
|
13-May-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add HAINAN family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| a36cdb858e21f287d7b51ded2f211f1c84bda90b |
|
08-Apr-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add si tiling support v5
v2: Only writte tile index if flags for it is set
v3: Remove useless allow2d scanout flags
v4: Split radeon_drm.h update to its own patch
v5: update against lastest next tree for radeon
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| ade2ad2d66ac341a12eca37bcb30d40199eb4e02 |
|
07-Mar-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeonsi: make sure tile_split field are not garbage
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 76ae1f4837ceb2c15ccf847e4abe2b5c4f66df85 |
|
24-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add OLAND family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 303ca37e722e68900cb7eb43ddbef8069b0c711b |
|
17-Jan-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix 1D tiling layout on SI.
Very similar to Evergreen, but slightly different rules for tile / slice
alignment. Fortunately, these map quite naturally onto the previous fixes for
linear aligned layout on SI.
2D tiling still needs more work here and possibly in the kernel.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| e32fff8e9ea8d522679eaab21a9555cab134fb36 |
|
16-Oct-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 |
|
30-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 77413e77b82a5d800c86b7d3b864d6cc797721c9 |
|
30-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: don't force stencil tile split to 0
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| b3d90bbc1d43bb11d8de25109f403b1b30533c34 |
|
29-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: don't take the stencil-specific codepath for buffers without stencil
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| b925022a3e4616665b388a78abab4e3270b4b4ec |
|
05-Sep-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.
Another corner case that isn't well-explained yet.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 45083e6d36125c64267c917da3d81e1e144ed33d |
|
04-Sep-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Memory footprint of SI mipmap base level is padded to powers of two.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 8572444fd0cda3e7b9557c09d2d0f7a9e049a2e7 |
|
31-Aug-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix layout of linear aligned mipmaps on SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 853429b939c792c4bc0bc91fdef696e3251b88d9 |
|
20-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: align r600 msaa buffers to a multiple of macrotile size * num samples
I am not sure whether this is needed, but better be safe than sorry.
/external/libdrm/radeon/radeon_surface.c
|
| 58545722d0ee52f112859322466d9366915575b5 |
|
19-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix allocation of MSAA surfaces on r600-r700
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 128803a107fde8ce36036e59437a536fc4d46553 |
|
07-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: tweak TILE_SPLIT for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| e14aedce64e365ef1a8726ed8c1ebed881d7a398 |
|
07-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: force 2D tiling for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 23372955730048bbcddafc74365d911f9a74fb13 |
|
29-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| ad66c17209811acdae21e44290a449523882a734 |
|
29-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: simplify ZS buffer checking on r600
Setting those flags has no effect anywhere else.
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| a1d462d2a6f720538eaf1199a94dd27cd04e8a54 |
|
17-Jun-2012 |
Dave Airlie <airlied@redhat.com> |
radeon/surface: free version after using it.
fixes leak in valgrind.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| d1fcfb17b9642ae351b03056a27b328f314ca80a |
|
13-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: force 1D array mode for z/stencil surface
On r6xx or evergreen z/stencil surface don't support linear or
linear aligned surface, force 1D tiled mode for those.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 2f56002cc0b5424902dfe2bd4024f7b825ecde67 |
|
11-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: enabled 2D tiling for evergreen only on fixed kernel
Due to a kernel bug, enabled 2D tiling for evergreen only on
newer fixed kernel.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 325e2e52a96ede6a19e891f769c803cb9ba85e10 |
|
11-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: always properly initialize stencil_offset field
Reported-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| c2b77a02d4e188cfa6d1b73a721946fd9b1d3577 |
|
06-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: fall back to 1D tiling only with broken kernels
Certain cards report the the wrong bank setup which causes
surface init to fail in the ddx and leads to no accel.
If we hit an invalid tiling parameter, just set a default
value and disable 2D tiling.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=43448
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 481234f2909c0506962a2f42da862da6a9b13fd8 |
|
16-May-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Add Southern Islands PCI IDs.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| c50cc24690938db53cd91ae9ff2fa0958693f80d |
|
14-Feb-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add TN surface support
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/radeon/radeon_surface.c
|
| 9b3ad51ae5fd9654df8ef75de845a519015150bb |
|
14-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: fix pitch alignment for scanout buffer
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 10c0837780b2d4a33568c16bb92527e196d6c05e |
|
03-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: fix surface API for good before anyone start relying on it
The mipmap level computation was wrong, we need to know the block
width, height, depth of compressed texture to properly compute this.
Change API to provide block width, height, depth instead of nblk_x,
nblk_y, nblk_z.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| 6a720cb8660975acea1100e61a88a92a7cb3856e |
|
02-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: surface fix macro -> micro tile fallback
We need to force 1D tiling only on old kernel the fallback was
broken along the way.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|
| c51f7f0e460dcadb9f1a56ecf1615810877c33c8 |
|
10-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.
v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
2D macro tile mode on r6xx for cubemap and array. Fix cubemap
to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
buffer just after depth one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/radeon/radeon_surface.c
|