| cddc3e03e4ec99c0268c03a126195173e519ed58 |
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04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/include/llvm/MC/MCSchedule.h
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| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/include/llvm/MC/MCSchedule.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/include/llvm/MC/MCSchedule.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/include/llvm/MC/MCSchedule.h
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| 135fe6ac5f5b80ef68c19b3ec7bb0063e28f2bab |
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22-Oct-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Speling fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 070156437752179833b1e5fddd50caa03fd7c12f |
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25-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.
Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| b86a0cdb674549d8493043331cecd9cbf53b80da |
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15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 674be02d525d4e24bc6943ed9274958c580bcfbc |
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10-Jan-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Fix include guards so they exactly match file names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 47579cf390c42e0577519e0a2b6044baece9df00 |
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09-Jan-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 8d4abb2446f80986ad5136bbec30c5da18cd6f4b |
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06-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: TargetSchedule interface for machine resources.
Expose the processor resources defined by the machine model to the
scheduler and other clients through the TargetSchedule interface.
Normalize each resource count with respect to other kinds of
resources. This allows scheduling heuristics to balance resources
against other kinds of resources and latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| fdd6fa89b960088b368231ec08e56a0c0b1e6930 |
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17-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Better handling of invalid latencies in the machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 6312cb099734263f348f36a31b8892b1373a7076 |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Generate IsBuffered flag for machine resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 39adb180bc2822146618b5bf9059eb7f134914b2 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Let NULL slip through again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 34301ceca8913f3126339f332d3dc6f2d7ac0d78 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| e127dfd0b175b5a336e61fecaad7fc2aec65d95c |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 97d552e5c71dd45e1a124e5a87550270a20a9062 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Don't use NULL as a fake keyword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 12886db4a7af74f17281695320c40248cb263f55 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| db7afac4575168c239ac9c570cb7897808f12e30 |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 3c0e5c9ecedb00d3c36fb2747b642bd3e38d0260 |
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16-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Guard fields by NDEBUG until they get used in the release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 99ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7b |
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14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel interface. To be implemented...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 72d048b69705f01d48bdef7b235ec96b24290767 |
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14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Define MC data tables for the new scheduling machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| d43b5c97cff06d7840b974ca84fa0639d2567968 |
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08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| ebd78710eb12794d9b8ca0307ae1f916e0ecbe80 |
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07-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
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07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCSchedule.h
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