| c777b2e58c0df1b8e7a8c0c8e78eb53d83549186 |
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29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions-v8.s
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| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
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01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions-v8.s
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| 4897151df698197f0eb5c4085545312dbb20c94d |
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05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions-v8.s
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| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
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05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions-v8.s
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