| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1b91231347c00bf1be46bdd5b27ae8c45fdc0d0c |
|
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b161955ffbda5ccb5293e0c76ef982acb6ec6661 |
|
23-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
|
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ea8ddd86b1e364a799e57fc0ac468a9c4a8f8bcf |
|
13-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 4a378b95aa0f24ba461e512608b8aaeaa803996f |
|
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| e29e2afc738348c74966ed81b3568779247c9fbd |
|
01-Jul-2013 |
Chad Rosier <mcrosier@apple.com> |
[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values. This should be the last fix due to fallout from r185094.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| a744d41a3f8af25938e12617abe2a8d32f6eabf6 |
|
28-Jun-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Fix pseudo-instructions for SRS (Store Return State).
The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is:
srsfa -> srsib
srsea -> srsia
srsfd -> srsdb
srsed -> srsda
This fixes <rdar://problem/14214734>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b7110cf5b5e4832e8ded6db7ab7577e3cfa2c462 |
|
27-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.
The current algorithm, LessRecord, uses the StringRef compare_numeric
function. This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:
T1
T1_W
T1_X
T1_XYZW
T1_Y
T1_Z
T2
T2_W
T2_X
T2_XYZW
T2_Y
T2_Z
In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another. However, in other parts
of the register bank, the scaling factors are different:
dEnum/dN = 5:
KC0_128_W
KC0_128_X
KC0_128_XYZW
KC0_128_Y
KC0_128_Z
KC0_129_W
KC0_129_X
KC0_129_XYZW
KC0_129_Y
KC0_129_Z
The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'. This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1. For example, the registers are now sorted as
follows:
T1
T2
T3
...
T0_W
T1_W
T2_W
...
T0_X
T1_X
T2_X
...
KC0_128_W
KC0_129_W
KC0_130_W
...
For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even
greater wins for targets with larger register files.
Patch reviewed by Jakob.
rdar://14006013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 4cbbbf49b69646ff990203ef3feae6a2726b8753 |
|
20-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
This reverts r155000.
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.
VFP instructions on v8/AArch32 share the same encoding space as cdp2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| bf811d602d1d81b93846c6cbbd1cec85f2f153cb |
|
18-Jun-2013 |
Kevin Enderby <enderby@apple.com> |
Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."
In the pre-matcher handler in the asm parser the ".w" (wide) qualifier
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.
Test cases for these were added.
rdar://14064574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
|
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2248cf590617cbe91eeb6a845ad06d675d9f2e91 |
|
05-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ee5e24cb3e987c74d4dce146b4f78e83fb2b56a8 |
|
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit upper-case BE/LE on setend instruction
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f86e436fb95670ed110818fefa403f21ae104639 |
|
13-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1ad3a410beff11913db0573942fb51b651d01a13 |
|
26-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 7c4cf030a898b5b4e0d2c66adf8dc068b1f1f070 |
|
17-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)
Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| d64ee4455a9d2fcec7e001c7f4c02d490bed5158 |
|
12-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 |
|
10-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| d65dfd83421f4d26e6dc20476718d7d9b6ba3f3b |
|
27-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit full range of valid ADR immediates.
This fixes an issue where trying to assemlbe valid ADR instructions would cause
LLVM to hit a failed assertion.
Patch by Keith Walker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1e8ed2537b3e4b2175cd9e62626f07606c62cfa0 |
|
23-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Convenience aliases for 'srs*' instructions.
Handle an implied 'sp' operand.
rdar://11466783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c1b7ca5ba28ded2d83ae534c8e072c2538d43295 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8ed97ef5f6980c689a5770ec30488601201e17c3 |
|
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 4acefe192f02849bcb2fd620a9f507c00d39a686 |
|
27-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Teach assembler to handle capitalised operation values for DSB instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
|
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| cac31de146e7131f411715dc6cb1958ea59bd754 |
|
26-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
|
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b22e70d835a88753d3ec6d5ee5e85b23fa6834b1 |
|
29-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
|
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 04b5d93250bef585631a583a85f6733b1bdc8c52 |
|
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8d11c6349f9bf276534907245946518042c1bb60 |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 27debd60a152d39e421c57bce511f16d8439a670 |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM/STM system instruction variants.
rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| e91e7bcadc445381adef5c5154e8e2cba074505f |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 840bf7eda7c81059a0aae9abd51262147c60d814 |
|
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 3bc8a3d3afe3ddda884a681002e24850099b719e |
|
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| af4edea67b007592f9474e07d27182956e37f7f5 |
|
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 23261af193e462b73257445053f9f6515e60e8c9 |
|
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2abba8496cb394af53b531e95067d5cae78bb9ee |
|
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 9f302c4fb3feeb36561a6eee0168ee5242d8ac20 |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| d2586daf069f480e924cd7dd2079dd39de331541 |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ee10ff89a2934636570cb17b756bf31b2a38aab5 |
|
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 71810ab7c0ecd6927dde1eee0c73169642f3764d |
|
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| cd20c58e980552daef182247005cf905fe8b06ba |
|
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 50965031848f391f98f11770b3823497d5bf5c15 |
|
20-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix tests for corrected MSR encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 9f45754750b03516db23b21021db72b20336ea85 |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding tests for STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2bd0118472de352745a2e038245fab4974f7c87e |
|
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ae13ba774083ef328a08290af649b4cd1156b40a |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 9c6712721c114f8e67b9a6b3cb1dd5d18b4cb435 |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 30b8b970e319b92300a9501f4578cb099e29a920 |
|
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove FIXME. TBB/TBH are Thumb mode only instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 3c4c879695eb282f01d89da87d5da0a141e7f6f8 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 356c759908e1c6b968293d54bc4aa26bc8415407 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some missing 'CHECK' lines and tidy up others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| bf841cf3360558d2939c9f1a244a7a7296f846df |
|
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1e0fff17f3182a2bef5e06cca996a8d16e53cb46 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2f25d9b9334662e846460e98a8fe2dae4f233068 |
|
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 63553c77cd1cf3b204d955fb65350db087aaff1d |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 96425c846494c1c20a4c931f4783571295ab170c |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 5df7ef6cdbdaaa6bf3bf12b959557a44fbf250a6 |
|
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c69c26d95e4dcffb3ab98c49f3672386b401d0f9 |
|
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix tests per now-correct encoding as of r137371.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 548340c4bfa596b602f286dfd3a8782817859d95 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f6713916fb4504aab617f0e317689acd878cc37f |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f8fce711e8b756adca63044f7d122648c960ab96 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| e1cf5902ec832cecdd5a94b9701930253d410741 |
|
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2c6363a62df95b74468d9a561bbcb9edddeb3507 |
|
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 71d3d67508176091575714dddf008b77db4089c9 |
|
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM update tests for CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c5b3c58ae8f954587bbb651dec7990744a29f12d |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| cf121c35c484ee17210fde1cecbd896348cd654a |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 43afb6ff1cf7b040e2d70abb47679e1357a329d5 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove obsolete FIXME reference in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 293a2ee3063953bb6f5bc828831f985f054782a3 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 70a0915cd135b48c557a5bc81b37e33f54fe150e |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 19b9d6912ab4d61666d5eed0a9c7d407d564ce1d |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8050a619145f30cdfee9c6ae1c5bdb1a32a4a71e |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests.
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ed398468b51c6eb5b2c9a5bccc8669854cf589a8 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USUB16 and USUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 953e2e81dec27fe40315100714eb15c967a9fc1e |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| fc2eb31a3c054f9611a2e88238fbb5a8842064a6 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| addec77b54fd77e99fd01f462a3fb8c3c89066fa |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 5f33d13da41f55e7421eee3bbfa410d07bd7af19 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for USAD8 and USADA8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 144da2c8f03834e76ddb617498be7ed864a5c192 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 41438398c13be01ec53c3ad6b08a6cab47e96735 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment copy/paste-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 29e85bc7285337973924501cad7e7effafd91e65 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQASX and UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 24a541b79fb9694b6edf19ee288b7c9063653512 |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 49f2ceddd25c75373f8a39fa25e8b9db33bcdacc |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 71725a099e6d0cba24a63f9c9063f6efee3bf76e |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2adba4156b83bd005bb704908bb36697e1ecabda |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UMAAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f36b0a2ee4fe1e67778b60daf6020574e62ca672 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 66c898224456990e511b71e498046736c0478079 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b6854ad2b1aad78660e7a3421d9c0dbdeaa3c975 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8b3fd56e0f61038ea45b0d1eaff57196d80579aa |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f1ae78af1796ec122e3cf75ab4826495eb5a4e8d |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TEQ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 7e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 36711e4a3c0b53000ea594233bd619dbf252558c |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for load/store exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 4f6f13db1a8a491ecab6af64549fbdc23cb5ba56 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 873db3eebae3cf1e0931149896f262d17a4dc79d |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SUB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| a46c658c6619e979a54ec1e4dc919b3a0319129a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM STM tests. Fix check: prefix for diagnostic tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 185f92e7d019bc52413a2b082d61e35c80f8b597 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f49433523e8a39db6d83503e312ae55160eed90a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 6ab4e3dd2375c3dcee06dde37437dc0c5a99aa24 |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 0e76edf8c05c5107acb687b898fea686ae756c38 |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| bf2845c0d8a77d24e9971871badeba8cee7b2648 |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 6808f21757f4f2be05a3b12a67d9360b4f9f62e2 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 44a456332f1f41d1e0b2815d93e47a88d501ee6e |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ce501030d9b0213d951fbf05f928ac75b06b5a3a |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b544f68b70475f06a8ec39c874297549edc0f695 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b206daaec1a2ec25e99fbdc413cd0866cec160b2 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 0ffd4a09dfb1ee56ec335fed0d15954f92cfa5b3 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for assembly parsing and encoding SMLA* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 7c9fbc0340aff9e20fd9009be23ffd279c1c0a7d |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 248e6c328c06afc2a6af6b95a1a8a41c1b53055c |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests.
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 9076b6e8f43c7eade7e0b667081f94df097e85c3 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SEL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8409f047312da0318af2a2fce162810ca3a95da3 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for SBC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 8ae45af7941dc3e78859ba3624676081590c435d |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for SADD/SASX parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| f790193aec11747bb35206d2c79e0c5ffbc6dc7f |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 86fdff0fa79b2c00cb68a2961cca0466eb50d666 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 616fbdf987170addd0d8f75f4fd677589d54cd75 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| a4c34ab54485f64d3b962a499526825a7a0d4bbc |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encodings tests for saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 10c7d70a4e843b3006db9f5f583d6f6f56cc245e |
|
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 61b1b21e9ad2b8af163a352766eeb159979f4ff2 |
|
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM PKH assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 88d1bc832ca5b458c8460929227be8eae6c6bdc3 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add parsing/encoding tests for ARM ORR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| a67851445902d1fc01fa2a37a3dfc347af949f84 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Consolidate ARM NOP encoding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c3635c2e928a7ecde11398ff272411f6dea2dcd2 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for MVN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ab40f4b737b0a87c4048a9ad2f0c02be735e3770 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 80d01dd3d19a84621324ac444c6749602df7a513 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 2317fe1584e02582c616c1c4d15954999ff5525a |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move mr[r]c[2] ARM tests and tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 1a2be4db5b12cb7bfa351bcebd5e94b0decb021f |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 5f16057d1e4b711d492091bc555693a03d4a1b6e |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 70d8fcfaa04eb20541b006a8fb97cbc1d3033cc4 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some testcases for ARM MLA/MLS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 3b14a5c5469176effb921d91d4494f0aa2919fd0 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 791feea10071223886e2fe2bfa0e1f4cb2c0ce74 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB assembly parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| 00a66653cbe56dfbdb831172b54097bf8256a191 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for EOR instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
|
| e77494e3e3da59afaa51d1bbcf732fa2851d865d |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 032434d622b6cd030a60bb9045a520c93b0d7d68 |
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14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 6f9f8845028d4d3b96c33417398034a71137d867 |
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14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 14ab1c3387a240a914cf8b1907bb3609bae72269 |
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14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for CMN/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| d986bc66bc56251c2b7d5b9a89df14c4760568fc |
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14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
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14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| f333d471d2cdd47d830dfe3a3e40efbb106c100d |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BX/BXJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 37023b05c84000373fcfc0871edad3c2b995be33 |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BLX/BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| fff76ee7ef007b2bb74804f165fee475e30ead0d |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 21101d60ce94f51651f71eeb61ceb8264eccac83 |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 76cbe02cdd57a297d9c6f1e5106e4718abd7ff9f |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| e52240c3705f3133eb8c4ebb4220054c68de2651 |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BIC' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 7ed6d22e9637c52b3511ac6907830251d1124e60 |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 59642c260064a0c9140e048d702a21830020487f |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'AND' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| da9f278c741e8ced7c1652720270918eb04ed348 |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'ADD' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 37ee464ea98544d3ed84cec6dde5f769ce003d5f |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| e8606dc7c878d4562da5e3e5609b9d7d734d498c |
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13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| dc89561fecf100d6c32d73c7b009fd73e51be688 |
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12-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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| 3f00e317064560ad11168d22030416d853829f6e |
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11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/basic-arm-instructions.s
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