| cddc3e03e4ec99c0268c03a126195173e519ed58 |
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04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| d59ad8a8013fd76177fb61c741562af3024d34cd |
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01-Oct-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 9b06dd6ca25fd1f8d2cf9227fdffc304c9f51564 |
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26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 0b926427670de6e0ed855ef93f220a3f51ed1eab |
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22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| e351865b65e92bea8ceeb32ad757d783d0ecea0f |
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16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| f4a1377322a9234c17b1d324c47248bdb5f62158 |
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13-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| ef1762b6a1d3353790bdb415788e7d8963e70372 |
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14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| af7da5cb993d1a2afad4816fe22c497d5adbef91 |
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29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 37ef65b9c1b93c386d13089d9ace6a1cc00e82dc |
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05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| c147b678206db510336ee95c3b55dc9c0ff19595 |
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17-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 457ee1a12e2c52624af7fdb81cf938f6d8d96572 |
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16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
reverting 172579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 490c7d97737ea7719efcea7321d3cfa3984b0027 |
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16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Akira,
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| ec3199f675b17b12fd779df557c6bff25aa4e862 |
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12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| 04376ebe9f203213ef1eb4c69396fe280dc8c8b1 |
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07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.
These changes are in the instruction td file.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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| ec65be84cd630d53233e7a37f0ef9d2303ac5153 |
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06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-alu-instructions.s
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