| cddc3e03e4ec99c0268c03a126195173e519ed58 |
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04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/test/MC/Mips/mips-expansions.s
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| 6948897e478cbd66626159776a8017b3c18579b9 |
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01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/test/MC/Mips/mips-expansions.s
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| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
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06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/test/MC/Mips/mips-expansions.s
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| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/test/MC/Mips/mips-expansions.s
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| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/test/MC/Mips/mips-expansions.s
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| ef1762b6a1d3353790bdb415788e7d8963e70372 |
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14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-expansions.s
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| 25df6a93f3324bd30f44dcb95fd17aff0a92d438 |
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22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
This patch that enables the Mips assembler to use symbols for offset for instructions
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-expansions.s
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| 2f68b311a1b0efb3cafeca3780f5c3d09a762a50 |
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10-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Initial assembler implementation of Mips load address macro
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-expansions.s
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| 9d577c861414c28967d77c2a1edf64b68efdeaee |
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04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-expansions.s
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