| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/test/MC/X86/x86-64.s
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/test/MC/X86/x86-64.s
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/test/MC/X86/x86-64.s
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/X86/x86-64.s
|
| c6f7c99809cece8c85e180c1b95e6159d8ea9613 |
|
14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| b9bc43852ceb74c845d28b96594e1ef4ae41329f |
|
08-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 6ee1464ba599f1afbed502fa1b3ac18c8577fd97 |
|
26-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 9b8b830f3fa6dca2275dcd86bdaf0d78ab1651a1 |
|
23-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 877d123bdb0198705884e4ca7980d2ab845d9888 |
|
22-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.
rdar://8612627 and rdar://14299221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 4e3170b63a31c515644846ce7a77631429d93050 |
|
22-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 |
|
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| f564a9389da68266f44314fe38ab399fd2211134 |
|
06-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 9765c6ecde9ca96c37fe3e27d360aadc387b6942 |
|
31-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
X86: Fix encoding of 'movd %xmm0, %rax'
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 0d82fe77f2b6f48b5fab131c1671169d154f8c69 |
|
11-Apr-2012 |
Charles Davis <cdavis@mines.edu> |
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 0f5ab7c5f392d8207a4b0c5bf1f8b274a9f410df |
|
13-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change the X86 assembler to not require a segment register on string
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 54427e52197ecd8c748736d7bbb431f2bf65c90e |
|
06-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| ec93b6decad4b95fd8a9531dc024b2b1881019bf |
|
05-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Make aliases for shld and shrd match gas. PR12173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 9d399b1fc2f7dfad72f5ff3328983acb805eaf10 |
|
24-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: alias cqo to cqto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 55c4127134d127ccd52cc2f4115af00084b28807 |
|
27-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 25f6dfd108801d1dc5877c420ef0dd47131aeda7 |
|
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
|
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| d521f2d2f1a866ba9f9e73ca566e2b486c15dc74 |
|
06-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| af45b3d8cb1b88d3cf775542996d78d8ce009274 |
|
05-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| a390a1aa48d8fa5085aa51b950f00d79dbb0c646 |
|
23-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 94d4c91bc5b2a84e6b93250599b6742777dbd35e |
|
22-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for assembling "movq" when it's correct to do so, while continuing
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 38c892624bc66cad98a81e080d235f4e33122562 |
|
21-Jun-2011 |
Bob Wilson <bob.wilson@apple.com> |
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 1bd15700a0eb3057d3e2d65070c3fc6b99e0d8a2 |
|
20-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Emit movq for 64-bit register to XMM register moves, but continue to accept
movd when assembling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 393c4047c05b6d7b5851d339e51bb2cc35f630c2 |
|
15-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 740e5b3586a474f1cea371cf6f652850e5420b90 |
|
14-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| d336de318eafd7643f65a901315920ec10ce05cd |
|
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| c6df9883da99915d1cfa491b381ffa703c61ed90 |
|
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 15f895179953b258e4ca20860d0d58f25f3a3edb |
|
09-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 96622aa063435b1de085489f0e3e49b5912c22da |
|
18-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Support explicit argument forms for the X86 string instructions.
For now, only the default segments are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 86d822df6d9a484b3672b2a909641262663a45dc |
|
04-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r126970: add 64-bit encoding tests for str with reg operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 00743c2218ff3f0f4edce972e2d88893a19e6ef8 |
|
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Use the same (%dx) hack for in[bwl] as for out[bwl].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| d86f482e4a9d71596e4f81afb0f7912ab3e40a7f |
|
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize loopz and loopnz as aliases for loope and loopne.
From Dimitry Andric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 87ca0e077d91b96a765b3b24cadfa8891026a33a |
|
22-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement xgetbv and xsetbv.
Patch by Jai Menon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 824a9076eaf8d109bc79f53e51b7d7a045f42552 |
|
19-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
implement PR9264: disambiguating 'bt mem, imm' as a btl.
This is reasonable to do since all bt-mem forms do the
same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 5ad596f9d27a67767118857471e63b55bfb152d6 |
|
18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize monitor/mwait with explicit register arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 3a5004dc3ee789bcbafd5b9733d3302e73e1187d |
|
11-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
Fix PR8946, a missing reg/reg form of movdqu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| c00210cef28b48b17408eb79e94691779da9d474 |
|
30-Dec-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Add another non-commutable instruction that gas accepts commuted forms for.
Fixes PR8861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 7ab3cc32d6bd3c3166184e27713c91f5317c7f85 |
|
25-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Generalize a previous change, fixing PR8855 - an valid large immediate
rejected by the mc assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 76331754d4a06e2394c15ae8f4870f4aeaf5ca1f |
|
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Allow a slash, '/', as a prefix separator for X86. rdar://8741045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| bfd2d26159c87262fcf462ea442f99478a2093c9 |
|
27-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement the data16 prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 5c7106b2e375edca4b63ab48b218654f978698a4 |
|
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Testcase for r120017.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| cbf5d74e6a99b6e38c9c05e08b6319ed0ce49650 |
|
21-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8524, apparently mainline gas accepts movq as an alias for movd
when transfering between i64 gprs and mmx regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 269f10b316b41fde5c9bf3f6e5c471f371862834 |
|
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
accept lret as an alias for lretl, fixing the reopened part of PR8592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 6b5e3978e3f720f6d2828068157b9d9687aee711 |
|
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
|
| 689cf3cb6222652b92fdbd52e96c1d2f421ac44e |
|
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement aliases for div/idiv that have an explicit A register operand,
implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 04a75abe234f1093f69a065d799b3271ccd09f99 |
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06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add aliases for movs between seg registers and mem. There are multiple
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 8c24b0c6996a8f03ff32766f0695dcf19577af59 |
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06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rework the rotate-by-1 instructions to be defined like the
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 235705b9ca08b66532528930adf9d9c23fd7b42b |
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06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| fb7000fcbde3b5257ac055e1e5abdee5df21842b |
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06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
correct suffix matching to search for s/l/t suffixes on
floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| acc473fcf9860567d4da60625944d48b075d28f8 |
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01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
"mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits. Support this memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| b501d4f673c0db267a76800339f9943f2ce6fe33 |
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01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Implement enough of the missing instalias support to get
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 0966ec08610c02c8556105f2fff88a7e7247a549 |
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22-Oct-2010 |
Andrew Trick <atrick@apple.com> |
Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 0b9325c97d031ab0e9a240d69a2be11ec1559e37 |
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21-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 87f4a1a4331e40cbba28e829561759d146273840 |
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19-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 7aef62ff8c72506cc9b77333d25f4aa8aa9cf9fe |
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18-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 508fc4708bb859391af8969614e67c84ab56c38c |
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05-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
gross hack (having the asmmatcher handle the alias).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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| 3286db670c689104c0df4f98fbb4a66f6e4d2db5 |
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01-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move X86 subdir up a level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86-64.s
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