| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
|
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
|
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
|
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b923d2f5f5958719214472906e9810de262ab447 |
|
17-Nov-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
|
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
|
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d8f2eb301c05b2d664a284df7604b82dad7ecab8 |
|
03-Sep-2013 |
Vincent Lejeune <vljn@ovi.com> |
TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
|
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5519dc9de88b36a2250db0faaf78c55f5e2c4d00 |
|
31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0 |
|
31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 54911a5303f44694c43608eedf2142e9d65d7c22 |
|
15-Jul-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Teaching llvm-tblgen to not emit a switch statement when there are no case statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 898b9f020d1089f679d1b1939fd6aafa9de4b411 |
|
25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4ffd89fa4d2788611187d1a534d2ed46adf1702c |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a9fa4fd9736f7d1066223f32fa54efbe86c0fceb |
|
28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 61131ab15fd593a2e295d79fe2714e7bc21f2ec8 |
|
25-Oct-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| becdf4d7cd0d5a3079339b6e177066b143d2f84c |
|
25-Oct-2012 |
Sebastian Pop <spop@codeaurora.org> |
add TableGen support to create relationship maps between instructions
Relationship maps are represented as InstrMapping records which are parsed by
TableGen and the information is used to construct mapping tables to represent
appropriate relations between instructions. These tables are emitted into
XXXGenInstrInfo.inc file along with the functions to query them.
Patch by Jyotsna Verma <jverma@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 562892034651ee4e29c31d03e55e8b8576f56369 |
|
12-Oct-2012 |
Richard Trieu <rtrieu@google.com> |
Change (!list.size() == 0) to (!list.empty()). No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 3f7b7f8ce0b050fc6a0100839d9c5a84198b2aed |
|
10-Oct-2012 |
Sean Silva <silvas@purdue.edu> |
tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6cfc806a6b82b60a3e923b6b89f2b4da62cdb50b |
|
10-Oct-2012 |
Sean Silva <silvas@purdue.edu> |
tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.
There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e3dbc98a4fc2a31102e4ace6317eac9cf16afb9c |
|
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
|
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 41be51b72cabfcef39efa7e5d2ce1250407cea7d |
|
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f2c64ef519b38a4328809b27b4a3a8e0c26e9709 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.
Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
|
07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6f36fa981a59461466e12e5056ba209d289b81b1 |
|
11-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.
Patch by Sean Silva!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| bf1aab15075884933e94a3aa950d88a7f16b5989 |
|
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 413b2e7539a1e41f8694abb809678ae48d1e6125 |
|
01-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 901b85888c2de6bf982c47ab69b7e83908b6a216 |
|
23-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Include cstdio in a few place that depended on getting it transitively through StringExtras.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| bcfa982c4866fee5f86dca8c4bfc7425a9629f0d |
|
15-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo."
We cannot limit the concatenated instruction names to 64K. ARM is
already at 32K, and it is easy to imagine a target with more
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 39bdc5526f9bb4985c5ea7711e603bb44707ed42 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to reduce size of static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| fac259814923d091942b230e7bd002a8d1130bc3 |
|
08-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 88d2fa438a5b9feb7da77e4beeaa00944ae4168e |
|
08-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Re-commit r152202 hopefully fixing the MSVC linker error.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 3c777947f4fdd94f061f8ac4a118a8db03da88a8 |
|
07-Mar-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r152202 as it's causing internal buildbot failures.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect
all 16-bit string table offsets. Also make sure the string to offset table
string is not larger than 65536 characters since larger string literals aren't
portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d3c9d9447ed7b5b8d3800b871ff162ae2df9fd5b |
|
07-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c667ba69ac342563c0886e20509e68705d78a0a5 |
|
10-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 133f9d989485376ce8ad0d6c61ba12e913fa6366 |
|
09-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64.
No change on i386.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 1a2f9886a2a60dbd41216468a240446bbfed3e76 |
|
22-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move various generated tables into read-only memory, fixing up const correctness along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 7c788888872233748da10a8177a9a1eb176c1bc8 |
|
01-Oct-2011 |
Peter Collingbourne <peter@pcc.me.uk> |
Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c291e2f5780c3a8470113a2a58c1fa680cd54b20 |
|
25-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 83a8031336a1155e6b0c3e9a84164324e08d1c8b |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 05bce0beee87512e52428d4b80f5a8e79a949576 |
|
30-Jul-2011 |
David Greene <greened@obbligato.org> |
Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f37dd02f7743ebd2424480361f5a7db510495c4f |
|
29-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Constify Inits
Make references to Inits const everywhere. This is the final step
before making them unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 20722b6cda6a8857a00e84133c8d8516400aca4d |
|
15-Jul-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5196c12e9fdec9ef3c63d96cb529c1c1cb732773 |
|
14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 16884415db751c75f2133bd04921393c792b1158 |
|
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d568b3f55294917d1cc701da14a8a7daeb6563e6 |
|
12-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d4a9066c93da9a5aab47ca228d82e796fdec70c0 |
|
11-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Make Inits Foldable
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 94b01f688256fca49decb239a8c84b003f18cdbc |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCInstrInfo registeration machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4db3748fcf39ac0001b9d02eb6bf803e309a5c19 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove RCBarriers from TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| bea6f615eefae279e53bbb63a31d2c3c67274c45 |
|
27-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| ae1920b1efa72c1789d562df4746110d0c2e10bd |
|
15-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.
Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 0f040a258ff6a2372fc232212b5e4189e8e7185d |
|
15-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c4af4638dfdab0dc3b6257276cfad2ee45053060 |
|
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c240bb0ede0541426254d0e0dc81d891beda4b22 |
|
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f523e476c2e199220306b367b7bd834978fb93d6 |
|
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5716180b1a863d345127fa8f9dfe0a931ab7370c |
|
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 73739d0bf19af3944aff6afaea2c4eda61061652 |
|
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5b55ff0c1555031c1c85f88d67c3b566750a9319 |
|
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.
--- Reverse-merging r109901 into '.':
U include/llvm/Target/TargetInstrDesc.h
U include/llvm/Target/Target.td
U utils/TableGen/InstrInfoEmitter.cpp
U utils/TableGen/CodeGenInstruction.cpp
U utils/TableGen/CodeGenInstruction.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 1844b1a5a483b8f01f29500a8d0d552447cbb7e5 |
|
31-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a606d955de3b0f777131d74162eb6f11b5f95d75 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 622dffde8691a33180e2368184b9f4efa6a86fbc |
|
09-Jun-2010 |
Eric Christopher <echristo@apple.com> |
How about ULL...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 99405df044f2c584242e711cc9023ec90356da82 |
|
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
|
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 70feca409e3a79c3d9295cbc81c257de6be8ef3e |
|
25-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e14d2e210dc7fe28009f44818a057622a73322e4 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.
This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6a91b18e5777f39e52e93221453abfa4553b6f93 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 01dcecc214918b29cf3712420457fef309eeaad6 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
revert 98912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a28bc686fa4f2375237aeab58530126462ae9b41 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
make inst_begin/inst_end iterate over InstructionsByEnumValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f65027842e82027dd6e8020586a299aaa548e355 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every
call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a7d479c7bd9723cabdd7c9e1e9a1e6e482f78e7e |
|
10-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file. Fix X86RecognizableInstr to use this instead of
parsing C code :).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 243a32f96b364811e2f9feadecfefb21b640321f |
|
15-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d2035203a0359eedbc1cf4ae77d43176e8455cd4 |
|
09-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Add DEBUG_DECLARE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 87563b39370d7adfd42b0f531409ff9bc2bfcc56 |
|
09-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Add DEBUG_VALUE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
|
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 799d697bf8d45ec404d0d105fc788ea5cf81c841 |
|
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 26207e5bf1123a793bd9b38bcda2f569a6b45ef2 |
|
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 23132b188ba651ba172380cd082cc286df73d440 |
|
24-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
prune the #includes in raw_ostream.h by moving a
member out of line. ftostr is not particularly speedy,
so that method is presumably not perf sensitive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| cb778a8634454c70d88955b3732f330a6cbe5b07 |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a938ac6223c5fd315ab745086d843df5e0604e09 |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make ptr_rc derive from a new PointerLikeRegClass tblgen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 1a55180238dbcf11113f610aea010447e51f595b |
|
03-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 88c7af096b09ad26cbcebfdf40151e04094b7460 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f8c7394781f7cf27ac52ca087e289436d36844da |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.
Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.
Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 15511cf1660cfd6bb8b8e8fca2db9450f50430ee |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b89be6150a8ea38fdaa2a242f6442e2d73326dab |
|
17-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
|
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e4c67cdab4a2ad2ff53183ad32e77e8608c9262d |
|
31-May-2008 |
Dan Gohman <gohman@apple.com> |
Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d35121ad00667d93ea779a722dbee7d022410815 |
|
29-May-2008 |
Dan Gohman <gohman@apple.com> |
Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.
This fixes "rdar://5791600", whatever that is ;-).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8370d38adee63b3a4d87bfe81be4aacc55fe7cda |
|
29-May-2008 |
Bill Wendling <isanbard@gmail.com> |
Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| ee4fa1977dd3a495a8857eef924ee5961db765c6 |
|
03-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags.
This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c9298235251b014e86a7368d92b589d093acb64a |
|
16-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 20ccded7dec5b90e58f649f4fb95b166a642b8cb |
|
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove isImplicitDef TargetInstrDesc flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| da47e6e0d003c873da960361549e57ee4617c301 |
|
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a22edc82cab86be4cb8876da1e6e78f82bb47a3e |
|
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| ba7e756c22446a17a72632b8d4ac66cbdaab33f7 |
|
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects. It would be really nice if we could
write patterns for copy instructions.
I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 214884ba03bb3ba791a14db51a61aaa694ddcff8 |
|
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
if an instr lacks a pattern, assume it has side effects (unless never has s-e is true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| bc0b9f70ae072d695e0eb7ceb729b3306b0679fe |
|
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
start inferring 'no side effects'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8926038785709391a6fb66a785dede520357c558 |
|
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Infer mayload
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 710e995889c71812743f3f33861c24273f4569a7 |
|
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
realize that instructions who match intrinsics that read memory read memory.
Also, instructions with any nodes that are SDNPMayLoad also read memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| dcc8b4f5d3f62ae84aae100638085dedeee91588 |
|
08-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 0ff23966feb90618bec4d085095ffbc28426e691 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8f707e15fbd09ca948b86419bcb0c92470827ac9 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 4764189298b17432f79f01f4b707fc0a0ba33a3c |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move M_* flags down in the file. Move SchedClass up in the
TargetInstrDescriptor class and shrink to 16-bits, saving a
word in TargetInstrDescriptor. Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| af3eb7c7583555ea5fd08e99f28b0042811e4dc2 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
the name field of instructions is never set to a non-empty string,
just unconditionally use the def name of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly. Change the
various flags from const variables to enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 834f1ce0312e3d00d836f9560cb63182c2c4570f |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2e48a70b35635165703838fc8d3796b664207aa1 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c8478d8b12c2d7e4cea32d0c9940f5cac2baa4dd |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e67bde5bb1959dbd7085981cb0bcf6f7c749f724 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
set the 'isstore' flag for instructions whose pattern is an
intrinsic that writes to memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2d51a4ce8f64a0e4aa70a52c46aafb22a31e47e4 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove some old hacky code that tried to infer whether a store
occured in a pattern, but failed miserably. The new code works for
any instruction that has a store in its pattern, including all the
x86 mem op mem instructions.
The only target-independent code that uses this is branch folding,
so this won't change anything in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a529a37fbd602d748e3e1b345db059ebe3ccf5b1 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5fbe27530415dcacd7afd591c4ba1d6df4374873 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
final cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| ef8339b11a0180c6df6ade4e9f4fd75a76ebc419 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
further simplifications and cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 951740afb41bbae2c8b034bab1911c9ec949ccf4 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
simplify some code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 7b11712ef2d41631137a3c124a58407702ffa8af |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
split enum emission out from InstrInfoEmitter into it's own tblgen backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2c36affc82b3eff0c731f20a10a121feed90a663 |
|
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
tblgen shouldn't include headers from llvm codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 3060910e290949a9ac5eda8726d030790c4d60ff |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6b1da9c39f0731d15cb743441bea6d4089efd9f8 |
|
14-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Add flags to indicate that there are "never" side effects or that there "may be"
side effects for machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 3dd298fb62e74b1e7a05547c0d403dac980d128f |
|
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Oops. Forgot these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 20ab29068d8a8ec31f26f022634f1e0bc4b1da56 |
|
12-Nov-2007 |
Owen Anderson <resistor@mac.com> |
Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b5910820ce8608b75cb88e6c4efd2d1a5858159a |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added TargetInstrDescriptor::numDefs - num of results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 08d52071bae2f8cc2e9aa6a451118b83d043813b |
|
26-Jul-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 88cc092ca5bd79480205ee7b01aa39c13f3e35d7 |
|
10-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Try committing again. Add OptionalDefOperand. Remove clobbersPred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c419bd3396cc035942b219efae30dd2890ae430f |
|
07-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
ImmutablePredicateOperand is no more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8012b077dd4d1c88e0221448c67147324c4e00cf |
|
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d45eddd214061bf12ad1e6b86497a41725e61d75 |
|
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 82a87a01723c095176c6940bcc63d3a7c8007b4b |
|
19-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| eaa91b0a1fc68984aae51f3c4b0cf29b38f89dac |
|
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b5c1c9c8e30d8498cdb2d0ee215f05ca8dc3e4e2 |
|
06-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5127ce09a4e4379f971280fab461a5f03befddbc |
|
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 3ab6dcfc54426ebdb3d0027187c11ad369af426f |
|
15-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 04677a3b49b2dfb151c4f77345702da489293627 |
|
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Recognize target instruction flag 'isReMaterializable'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a683f9ba1356e92a5e7243d9f80fe8a8b6f737c8 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Files missing from LABEL check in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| fb1aab0673a699c39281e3bdc1091c0ed8fd1d1c |
|
17-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add opcode to TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 0bb75004ff6c0ad26de7610cb873f81ea26fd6ca |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
ADd support for adding constraints to suboperands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f19683956275a85bc0cfa0ac08760fdcc790f510 |
|
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
allow ptr_rc to explicitly appear in an instructions operand list, it doesn't
have to be a subpart of a complex operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a1fd6504aaf62b87530e8230517957bad3facc96 |
|
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove M_2_ADDR_FLAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d9a7f4db5f996cce8b3a7f95f8dbac3c996a6625 |
|
07-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Mark predicate operands as such in operand info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a0cca4ae267bc28143e8f4737e119349d95e4825 |
|
07-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
simplify the way operand flags and constraints are handled, making it easier
to extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a818e92f8b7ac805c0c7a9747d427186048b1440 |
|
06-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
recognize ppc's blr instruction as predicated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| c51737f46ff3bd4379b576630c1b83ce163738c5 |
|
04-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clean up some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| e2ba8975883874633a1035c245af3b948b940b25 |
|
01-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add operand constraints to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| cd4317efcf334be10d9a98008a1445d6e12a7712 |
|
21-Jul-2006 |
Jim Laskey <jlaskey@mac.com> |
Eliminate data relocations by using NULL instead of global empty list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 60f09928a0d22d5927ff0a40fe9163cf1ba1014a |
|
21-Jul-2006 |
Jim Laskey <jlaskey@mac.com> |
Use an enumeration to eliminate data relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8d3af5e7d082dbd029c3987ceadbdcf9e49af6d7 |
|
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 21d03f2de0087d60dbf575d95924404a97852879 |
|
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
lib/Target/Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 9812f1ca97150be21906443dbef4ae689a4cd618 |
|
12-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Noop instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 108714c14fbd40fef641581a5bd85441ee06c621 |
|
03-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Set isStore of instructions with ISD::TRUNCSTORE root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| eff5c3623848152b60457318af8e23df25496449 |
|
02-May-2006 |
Chris Lattner <sabre@nondot.org> |
Put instruction names into the first non TargetInstrInfo namespace found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| afba446d99b3053a9aac0bbe04785601be5a4e97 |
|
01-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Formating
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6f6360d9abe3726d343b5641acb43bbc296bc8db |
|
01-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Mark instructions whose pattern is (store ...) isStore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 719c2fc97f7dbf2fdc3743f2324a33c02cbb8b0c |
|
20-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Don't fill in fields that no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f52e2618f3992aa673c738aa1d2e6c046a0b6f5a |
|
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
If we want to emit things in enum order, use getInstructionsByEnumValue to
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 42d24c71df88178eacf244a38b6c48847ee0d39b |
|
30-Dec-2005 |
Duraid Madina <duraid@octopus.com.au> |
almost got the HP-UX tester up.. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 65303d6bd777b76735ef179870678a1d14671c54 |
|
19-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 6cee630070b1a7183ed56a8404e812629f5ca538 |
|
01-Nov-2005 |
Jim Laskey <jlaskey@mac.com> |
Allow itineraries to be passed through the Target Machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| cb366d980a389e5b9c3fc2b9aae373c0ba2903c6 |
|
01-Nov-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Keep VC++ happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| b5a0c0ee059db5994d4fec7ebd03c048b4fcd308 |
|
31-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Emit itinerary class in instruction info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 366080c5e6b4b8e1f07829a2489cc5d21f51bf3b |
|
29-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 5f89bf0f9df54687f4474fe13f5d1a8635d85d5a |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
spell this variable right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8b50f9b8dcd6da00ddc961ecda967719eb745dee |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Expose a new flag to TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 9fdd6e3f50b7fdafff9aa0e1bac0bd2a78d03d71 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a marker at the end of the instruction enum list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 8d30c23d2638bdc9a3e4fc7ba764adf5df043ee5 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Emit this:
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };
instead of this:
static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };
For operand information, which does not require dynamic (startup-time)
initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d5aa3e26bb02732fddadecfd66112352a74742a0 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Emit real operand info for instructions. This currently works but is bad
in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 0e384b66a781fc0ff005f475a7ab151afa054fb0 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
For now, just emit empty operand info structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| d98958f4bdd5a41b1d30668c25fe259069a04f92 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
now that all of the targets are clean w.r.t. the number of operands for each
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| f372ae6ebcad9dabe4d4de73966822af902150fe |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
revert this change, which causes breakage, temporarily
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a3ac88d8ab4605f6c1c298a8cdaa89d16c3756b4 |
|
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
When emitting implicit use/def lists, only emit each unique list once. Though
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| dcfa353d7477ed90409cec7c89deb29e8f09c4ed |
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18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fill in the numOperands field of the TargetInstrDescriptor struct from the
.td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 3da94aec4d429b2ba0f65fa040c33650cade196b |
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22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| d6488671736d0a5aaee1218748b94d8c68f33716 |
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22-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Refactor code for numbering instructions into CodeGenTarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| aad75aa1a235ec1ab121ec2a9c745577493ed323 |
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02-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| cdd66b524f62ef6acd6bfa4e586edf8a406c4928 |
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28-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Add support for the isLoad and isStore flags, needed by the instruction scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 5b71d3af35f941585acb50de4909cff20f68680d |
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28-Sep-2004 |
Chris Lattner <sabre@nondot.org> |
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 2c38413b3f5420f45f2f8220b21862246d446dd0 |
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17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Do not #include files into the llvm namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 2d12b2cf7513e7ee855deec0de293311d676cb75 |
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01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Instructions no longer need to have names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| ec3524064c57fbc2c5976ca301bbaadc94006d07 |
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01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Add, and start using, the CodeGenInstruction class. This class represents
an instance of the Instruction tablegen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 803a5f6ecb1823280f80e3c4459aa58627d0484c |
|
01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 2082ebe8b3a5db302748828ab4f79a36d239c1d9 |
|
01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Finegrainify namespacification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 58505994cfad64d89c7b3825341396faa10e6ea1 |
|
31-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Support new flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| d0fde30ce850b78371fd1386338350591f9ff494 |
|
11-Nov-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Put all LLVM code into the llvm namespace, as per bug 109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 01d45827a1e512f3b19ba857772bf02baa3c0c4e |
|
20-Oct-2003 |
John Criswell <criswell@uiuc.edu> |
Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
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| 73ff5120eb8b8c0ccbfed8a17f1024c67a75f319 |
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08-Oct-2003 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:
if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}
was changed to:
for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 7884b750c33b750177b3f22af75c874c97f728d8 |
|
07-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Start using the CodeGeneratorWrappers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| bc01723605de979e67b1aea67385a029f851de34 |
|
06-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Switch code over to being a TableGenBackend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| a3ae6143c1ec9c39a7beb07960f89edd4736b018 |
|
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Finish the instruction info emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|
| 33ccf7edff6d784c7f6ea85ada2b67062272073e |
|
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Initial checkin of Instruction emitter, which just produces enum values so far
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/InstrInfoEmitter.cpp
|