| 33dfdc735e052d9c9b33883350e926d40220b6ac |
|
09-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make brw_set_saturate() use stdbool.
There was a chance for brw_wm_emit.c to screw up and pass (1 << 4) instead of
1, which would get converted to 0 when stored. Instead, use stdbool which
converts nonzero to true/1 like we want.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 5b83bdc154ec8d607a4c4d96171d0128e51abaec |
|
16-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix brw_swap_cmod() for LE/GE comparisons.
The idea here is to rewrite comparisons like 2 >= x with x <= 2; we want
to simply exchange arguments, not negate the condition. If equality was
part of the original comparison, it should remain part of the swapped
version.
This is the true cause of bug #50298. It didn't manifest itself on
Sandybridge because we embed the conditional modifier in the IF
instruction rather than emitting a CMP. All other platforms use CMP.
It also didn't manifest itself on the master branch because commit
be5f27a84d ("glsl: Refine the loop instruction counting.") papered over
the problem.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50298
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| f78f48b6d2c4034a62ab11a558c95901d2245c4a |
|
02-Apr-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove vestiges of function call support from the old VS backend.
This never worked. brwProgramStringNotify also explicitly rejects
programs that use CAL and RET. So there's no need for this to exist.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 3aa3c3f75894ca0eb08087c0ec3dd114eeae4bb7 |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: increase the brw eu instruction store size dynamically
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 10000'.
v2: comments from ken, do not hardcode the eu limit to (1024 * 1024)
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 0a17093eaf84696b05d04a45d6d51281f7b2786b |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: let the if_stack just store the instruction index
If dynamic instruction store size is enabled, while after
the brw_IF/ELSE() and before the brw_ENDIF() function, the
eu instruction store base address(p->store) may change.
Thus let if_stack just store the instruction index. This is
somehow more flexible and safe than store the instruction
memory address.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 3f5e938a9ded42ae8dc9ae2486e8d5c8b64cfe07 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace incorrect use of GLboolean with enum brw_compression.
brw_set_compression_control took a GLboolean as an argument, then
promptly used a switch statement to compare it with various enumeration
values. Clearly it's not actually a boolean.
Introduce a new enumeration type, enum brw_compression, and use that.
Found by converting GLboolean to bool; clang then gave warnings about
switching on a boolean and ultimately duplicated case errors.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 774fb90db3e83d5e7326b7a72e05ce805c306b24 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Get a ralloc context into brw_compile.
This would be so much easier if we were using C++; we could simply use
constructors and destructors. Instead, we have to update all the
callers.
While we're at it, ralloc various brw_wm_compile fields rather than
explicitly calloc/free'ing them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 1309d2ea723613f1e755dd7785d22456dd39bb08 |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_compile pointer to brw_set_src[01].
This makes it symmetric with brw_set_dest, which is convenient, and will
also allow for assertions to be made based off of intel->gen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 4847f802c28e595130bda14055cd52c9b1f51cd7 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of SEL instructions.
This is like what we do for add/mul, but we have to invert the
predicate to choose the other source instead.
This removes 5 extra moves of constants in nexuiz shaders. No
statistically significant performance difference on my Sandybridge
laptop (n=5).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 811c147220d2630b769e505ce4d40ef9108fe034 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of CMP instructions.
This is like what we do with add/mul, but we also have to flip the
conditional test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 245662f3083795e272fe9ef5d4cbeb6d048cf0e5 |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the instruction compression bits on gen6.
Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 32f2fd1c5d6088692551c80352b7d6fa35b0cd09 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| b010814e9c7ed30cbdd60a49d81a6ea774c8c3a3 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Spell "conditional" correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| c51c822ee02cb47ddba46da668577d51b7c02831 |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: rewrite the code for handling shader subroutine calls
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.c
|