| c4aaf85285fc9484e95e9cda89db9cc6923259f4 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move unit state setup to emit() time.
It is only needed in time for brw_psp_urb_cbs(), which is also an emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
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| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
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| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
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| acb4d5cd96d91320b8e5edb727ff3a268f04587f |
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25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move the GS state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.
The new API makes so much more sense, I'd like to forget how the old
one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
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| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
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| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| a47858e45efd95d798468cfff34616c0de200032 |
|
03-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add support for 2 threads in the GS.
This brings noop vertex shader throughput from 6.8M verts/sec to 10.4M
verts/sec using GL_QUADs on my GM45.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
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| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
|
03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 3149119cad6137fee967054c38c1060a30bfc52d |
|
02-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert GS unit to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_gs_state.c
|