Searched defs:RegIdx (Results 1 - 11 of 11) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMCallingConv.h210 unsigned RegIdx = State.getFirstUnallocated(RegList); local
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
216 State.AllocateReg(RegList[RegIdx++]);
251 unsigned RegIdx = State.getFirstUnallocated(RegList); local
253 if (RegIdx >= RegList.size())
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
H A DARMISelLowering.cpp3116 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); local
3117 if (RegIdx != array_lengthof(GPRArgRegs))
3118 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
/external/llvm/lib/CodeGen/
H A DSplitKit.h277 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
279 /// 1. No entry - the value is not mapped to Edit.get(RegIdx).
281 /// Edit.get(RegIdx). Each value is represented by a minimal live range at
283 /// of RegIdx in RegAssign.
295 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the
298 LiveRangeCalc &getLRCalc(unsigned RegIdx) { argument
299 return LRCalc[SpillMode != SM_Partition && RegIdx != 0];
302 /// defValue - define a value in RegIdx from ParentVNI at Idx.
307 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
309 /// forceRecompute - Force the live range of ParentVNI in RegIdx t
[all...]
H A DLiveVariables.cpp85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { argument
86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
88 VirtRegInfo.grow(RegIdx);
89 return VirtRegInfo[RegIdx];
H A DSplitKit.cpp362 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument
368 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
375 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
378 // This was the first time (RegIdx, ParentVNI) was mapped.
398 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { argument
400 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
413 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
419 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument
426 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
429 // so always begin RegIdx
652 unsigned RegIdx = AssignI.value(); local
829 unsigned RegIdx; local
845 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx); local
931 unsigned RegIdx = RegAssign.lookup(PHIVNI->def); local
972 unsigned RegIdx = RegAssign.lookup(Idx); local
1034 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); local
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/external/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset; local
416 if (RegIdx < 0) {
417 Offset = RegIdx;
418 RegIdx = 0;
423 Reg = RC->getRegister(RegIdx);
/external/llvm/lib/Target/AMDGPU/InstPrinter/
H A DAMDGPUInstPrinter.cpp213 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); local
215 O << Type << RegIdx; local
219 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
806 SDValue RegIdx = Node->getOperand(2); local
808 getMSACtrlReg(RegIdx), MVT::i32);
838 SDValue RegIdx = Node->getOperand(2); local
841 getMSACtrlReg(RegIdx), Value);
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp2305 unsigned RegIdx = X86::sub_16bit; local
2306 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp633 struct RegIdxOp RegIdx; member in union:__anon12651::MipsOperand::__anon12652
647 Op->RegIdx.Index = Index;
648 Op->RegIdx.RegInfo = RegInfo;
649 Op->RegIdx.Kind = RegKind;
659 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
660 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
662 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
668 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
670 return RegIdx
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/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5606 unsigned RegIdx = 3; local
5613 RegIdx = 4;
5615 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5617 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5619 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))

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