| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
|
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf7329d9a0169abbd6ec837dc8b682b2f2fd98cd |
|
14-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: produce friendly error for invalid inline asm
We used to perform an invalid operation on an MVT and crash, which wasn't much
fun.
Patch by Oliver Stannard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cb01efb7988d119d6e2aedab1740695aa6a9cc0c |
|
03-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.
rdar://12856873
Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0e536ee4cae5f7359e8a8db99edadc39a5c12132 |
|
31-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
Legalize: Improve legalization of long vector extends.
When an extend more than doubles the size of the elements (e.g., a zext
from v16i8 to v16i32), the normal legalization method of splitting the
vectors will run into problems as by the time the destination vector is
legal, the source vector is illegal. The end result is the operation
often becoming scalarized, with the typical horrible performance. For
example, on x86_64, the simple input of:
define void @bar(<16 x i8> %a, <16 x i32>* %p) nounwind {
%tmp = zext <16 x i8> %a to <16 x i32>
store <16 x i32> %tmp, <16 x i32>*%p
ret void
}
Generates:
.section __TEXT,__text,regular,pure_instructions
.section __TEXT,__const
.align 5
LCPI0_0:
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.long 255 ## 0xff
.section __TEXT,__text,regular,pure_instructions
.globl _bar
.align 4, 0x90
_bar:
vpunpckhbw %xmm0, %xmm0, %xmm1
vpunpckhwd %xmm0, %xmm1, %xmm2
vpmovzxwd %xmm1, %xmm1
vinsertf128 $1, %xmm2, %ymm1, %ymm1
vmovaps LCPI0_0(%rip), %ymm2
vandps %ymm2, %ymm1, %ymm1
vpmovzxbw %xmm0, %xmm3
vpunpckhwd %xmm0, %xmm3, %xmm3
vpmovzxbd %xmm0, %xmm0
vinsertf128 $1, %xmm3, %ymm0, %ymm0
vandps %ymm2, %ymm0, %ymm0
vmovaps %ymm0, (%rdi)
vmovaps %ymm1, 32(%rdi)
vzeroupper
ret
So instead we can check if there are legal types that enable us to split
more cleverly when the input vector is already legal such that we don't
turn it into an illegal type. If the extend is such that it's more than
doubling the size of the input we check if
- the number of vector elements is even,
- the source type is legal,
- the type of a split source is illegal,
- the type of an extended (by doubling element size) source is legal, and
- the type of that extended source when split is legal.
If the conditions are met, instead of just splitting both the
destination and the source types, we create an extend that only goes up
one "step" (doubling the element width), and the continue legalizing the
rest of the operation normally. The result is that this operates as a
new, more effecient, termination condition for the loop of "split the
operation until the destination type is legal."
With this change, the above example now compiles to:
_bar:
vpxor %xmm1, %xmm1, %xmm1
vpunpcklbw %xmm1, %xmm0, %xmm2
vpunpckhwd %xmm1, %xmm2, %xmm3
vpunpcklwd %xmm1, %xmm2, %xmm2
vinsertf128 $1, %xmm3, %ymm2, %ymm2
vpunpckhbw %xmm1, %xmm0, %xmm0
vpunpckhwd %xmm1, %xmm0, %xmm3
vpunpcklwd %xmm1, %xmm0, %xmm0
vinsertf128 $1, %xmm3, %ymm0, %ymm0
vmovaps %ymm0, 32(%rdi)
vmovaps %ymm2, (%rdi)
vzeroupper
ret
This generalizes a custom lowering that was added a while back to the
ARM backend. That lowering is no longer necessary, and is removed. The
testcases for it, however, provide excellent ARM tests for this change
and so remain.
rdar://14735100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1ea5928ddbd38e99507f7f18df8ec8a865c7799 |
|
29-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval cleanup: add helper functions to reduce code duplication.
Helper functions are added:
emitPostLd: emit a post-increment load operation with given size.
emitPostSt: emit a post-increment store operation with given size.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 214c37d1816b62a25525282817f7088a1e2ed1dc |
|
25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: don't expand atomicrmw inline on Cortex-M0
There's a barrier instruction so that should still be used, but most actual
atomic operations are going to need a platform decision on the correct
behaviour (either nop if single-threaded or OS-support otherwise).
rdar://problem/15287210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3115047182dfa0e4692901e897a58e5be3329423 |
|
25-Oct-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tweak usage of '*vfp' compiler_rt functions.
Only use them if the subtarget has ARM mode, as these routines are implemented
as ARM code.
rdar://15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e8d84d8936dc8fb4fc260b0601b37e93679de421 |
|
24-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Remove class abstraction from ARM struct byval lowering
This commit changes the struct byval lowering for arm to use inline
checks for the subtarget instead of a class abstraction to represent
the differences. The class abstraction was judged to be too much
code for this task.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6c0138e5fca970b126a76ee9252af462760c99c0 |
|
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Use non-VFP softcalls on embedded Darwinish targets
The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1
code to make use of VFP instructions by switching back to ARM mode, they make
no sense for M-class processors which don't even have an ARM mode.
Given that justification, in practice this is a platform ABI decision so the
actual check is based on that rather than CPU features.
rdar://problem/15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7014d274e4adb51cbb20201ab002057395b7dcaa |
|
17-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets
This commit implements the correct lowering of the
COPY_STRUCT_BYVAL_I32 pseudo-instruction for thumb1 targets.
Previously, the lowering of COPY_STRUCT_BYVAL_I32 generated the
post-increment forms of ldr/ldrh/ldrb instructions. Thumb1 does not
have the post-increment form of these instructions so the generated
assembly contained invalid instructions.
Passing the generated assembly to gcc caused it to complain with an
error like this:
Error: cannot honor width suffix -- `ldrb r3,[r0],#1'
and the integrated assembler would generate an object file with an
invalid instruction encoding.
This commit contains a small test case that demonstrates the problem
with thumb1 targets as well as an expanded test case that more
throughly tests the lowering of byval struct passing for arm,
thumb1, and thumb2 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6483751a362948bb83940e55f63226c27c472bc0 |
|
17-Oct-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Refactor lowering for COPY_STRUCT_BYVAL_I32
This commit refactors the lowering of the COPY_STRUCT_BYVAL_I32
pseudo-instruction in the ARM backend. We introduce a new helper
class that encapsulates all of the operations needed during the
lowering. The operations are implemented for each subtarget in
different subclasses. Currently only arm and thumb2 subtargets are
supported.
This refactoring was done to easily implement support for thumb1
subtargets. This initial patch does not add support for thumb1, but
is only a refactoring. A follow on patch will implement the support
for thumb1 subtargets.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 05ac87f864a34bff0e6f2a029d48eab3e4cb464a |
|
15-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval: fix a copy-paste error for thumb2.
PR17309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fb92f4645968724d2095ef95a7034d7e20d39b3f |
|
07-Oct-2013 |
Manman Ren <manman.ren@gmail.com> |
Struct byval: use the correct alignment for loads generated to load
from struct byval to registers.
We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.
The fix is to pass the alignment of the struct byval.
rdar://problem/15144402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4e54f41d6ce6b5a502d2f8496f1e8360ed953b7d |
|
04-Oct-2013 |
Matthias Braun <matze@braunis.de> |
ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bba9390fc6c0d536172c6bb4a9c93db557c1aff4 |
|
01-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 268c743a3ba44ada364938bc5ff9b1be219df54f |
|
26-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 541681c8485c18b564970c80180a798b2c1663e8 |
|
26-Sep-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
x = a + b (add)
y = a * x (mul)
z = y + b * y (mla)
Without distribution:
x = a + b (add)
z = x * x (mul)
This patch checks if a mul is a square of add/sub. If yes, skip
distribution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2a9af9f18eac90b0de739b6ceddf6c2209086303 |
|
13-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4897151df698197f0eb5c4085545312dbb20c94d |
|
05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 441c557708b5dbe91f1799baf790ad418c23ea70 |
|
29-Aug-2013 |
Cameron Esfahani <dirty@apple.com> |
Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 22266c1d4817fc30355a90bb264ede08482bba3a |
|
28-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a0b2d332c114571716746ba90c815cfb6f68d4ab |
|
23-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CodeGen for VMAXNM/VMINNM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 35eab1db2f21aee9678fe946a5d983a67285e7e4 |
|
22-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CodeGen support for VSEL.
This uses the ARMcmov pattern that Tim cleaned up in r188995.
Thanks to Simon Tatham for his floating point help!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bad8d4ca599024de8fdc6255a4b73bb294f49239 |
|
22-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 32c2bfda77d54ca6ad8e08d2de03daa7ae432305 |
|
20-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8775a51d94b277ca6ebe12a1d20bfc2bc5a53960 |
|
06-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement allowTruncateForTailCall
Now that it's in place, it seems silly not to let ARM make use of the extra
tail call opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7f22a64df583df9da6bdd74e2f928568276f837 |
|
30-Jul-2013 |
Saleem Abdulrasool <compnerd@compnerd.org> |
[ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.
Split the check of the value of the second operands to the ands. Move the cast
and variable declaration slightly higher to make it slightly easier to follow.
Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 17f99a991f2e270a34c53854ce80acc30754537b |
|
24-Jul-2013 |
Quentin Colombet <qcolombet@apple.com> |
[ARM][ISel] Improve the lowering of vector loads.
When vectors are built from a single value, the ARM lowering issues a
scalar_to_vector node.
This node is then always morphed into a move from the general purpose unit to
the vector unit.
When the value comes from a load, this can be simplified into a vector load to
the right lane.
This patch changes the lowering of insert_vector_elt to expose a vector
friendly pattern in this situation.
This is a step toward fixing <rdar://problem/14170854>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ad9a0d27d36f18dff2b2d37dd13b11ed2d07688b |
|
16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow printing of ARM atomic DAG nodes.
We'd forgotten to provide string representations for the special ARMISD atomic
nodes; this adds them in. No effect on CodeGen, just makes the output of
"-view-whatever-dags" slightly more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2f438131f115a3860ee344a827a091790d6dc13d |
|
16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 103ba845f09252d90a05109af7174f54bf412daf |
|
16-Jul-2013 |
Renato Golin <renato.golin@linaro.org> |
ARM EABI divmod support
This patch enables calls to __aeabi_idivmod when in EABI mode,
by using the remainder value returned on registers (R1),
enabled by the ARM triple "none-eabi". Note that Darwin and
GNUEABI triples will continue lowering on GNU style, that is,
using the stack for the remainder.
Still need to add SREM/UREM support fix for 64-bit lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b9df53a40b22c74ce3f3a7b4a7c0676a38cf5e73 |
|
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dc2d418dd29ad9396aea06f2b72c9a7d29b30940 |
|
08-Jul-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Improve codegen for generic vselect.
Fall back to by-element insert rather than building it up on the stack.
rdar://14351991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e2e5ff0240dfb90c6dbc93e7fc441f71bfde400 |
|
03-Jul-2013 |
Quentin Colombet <qcolombet@apple.com> |
[ARM] Improve the instruction selection of vector loads.
In the ARM back-end, build_vector nodes are lowered to a target specific
build_vector that uses floating point type.
This works well, unless the inserted bitcasts survive until instruction
selection. In that case, they incur moves between integer unit and floating
point unit that may result in inefficient code.
In other words, this conversion may introduce artificial dependencies when the
code leading to the build vector cannot be completed with a floating point type.
In particular, this happens when loads are not aligned.
Before this patch, in that case, the compiler generates general purpose loads
and creates the floating point vector from them, instead of directly using the
vector unit.
The patch uses a vector friendly sequence of code when the inserted bitcasts to
floating point survived DAGCombine.
This is done by a target specific DAGCombine that changes the target specific
build_vector into a sequence of insert_vector_elt that get rid of the bitcasts.
<rdar://problem/14170854>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a10c01a6c62792be825c562314a646437b21bfec |
|
03-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.
This patch makes use of that quirk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 40d0492cdea1023463a9902ee81b3c5251204039 |
|
01-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.
Thanks for pointing it out Eli!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d59fc0af0a3ebd13c7004511e64e3233dfe87b17 |
|
01-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.
A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bcd8e7ad4d1dd486675e774778b3409464380f62 |
|
28-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: ensure fixed-point conversions have sane types
We were generating intrinsics for NEON fixed-point conversions that didn't
exist (e.g. float -> i16). There are two cases to consider:
+ iN is smaller than float. In this case we can do the conversion but need an
extend or truncate as well.
+ iN is larger than float. In this case using the NEON conversion would be
incorrect so we don't perform any combining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6b97ebe9a32342207b24a5f73ebbf3070ec8d189 |
|
26-Jun-2013 |
Stephen Lin <stephenwlin@gmail.com> |
ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is not used for incompatible calling conventions.
(Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 41502e1af77443c31138cee309bd89898f23e33a |
|
18-Jun-2013 |
Michael Gottesman <mgottesman@apple.com> |
[ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implying that upper bits are always 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8493edfb4b61e5c63669fc19a55b640e1ad7aee1 |
|
18-Jun-2013 |
Michael Gottesman <mgottesman@apple.com> |
Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL.
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.
In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
|
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5a02fc4b5fa0eba4d0875db710400a74ada3b15f |
|
23-May-2013 |
Tim Northover <t.p.northover@gmail.com> |
ARM: implement @llvm.readcyclecounter intrinsic
This implements the @llvm.readcyclecounter intrinsic as the specific
MRC instruction specified in the ARM manuals for CPUs with the Power
Management extensions.
Older CPUs had slightly different methods which may also have to be
implemented eventually, but this should cover all v7 cases.
rdar://problem/13939186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 083bc97344d618884ef04bc1ba1fc4ddf14d867d |
|
20-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:
Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ...
FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.
We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.
This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4dc8bdf87d402ad8c91d9a72777d9576c5461e40 |
|
20-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace some bit operations with simpler ones. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 101a36117c2e5e760ebb2b476d6c5b2b52cac6e8 |
|
15-May-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM ISel: Don't create illegal types during LowerMUL
The transformation happening here is that we want to turn a
"mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have
to make sure that X still has a valid vector type - possibly recreate an
extension to a smaller type. In case of a extload of a memory type smaller than
64 bit we used create a ext(load()). The problem with doing this - instead of
recreating an extload - is that an illegal type is exposed.
This patch fixes this by creating extloads instead of ext(load()) sequences.
Fixes PR15970.
radar://13871383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d26c93d3a8a484c5b42f06163ae5de787f0ac276 |
|
13-May-2013 |
Lang Hames <lhames@gmail.com> |
Correctly preserve the input chain for potential tailcall nodes whose
return values are bitcasts.
The chain had previously been being clobbered with the entry node to
the dag, which sometimes caused other code in the function to be
erroneously deleted when tailcall optimization kicked in.
<rdar://problem/13827621>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 44b6b530e94d5b05e1b2ddbb174c477b0ce56638 |
|
08-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
For r181148: fixed warning 'enumeral and non-enumeral type in conditional expression'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 46abfcf4187432da728cbe452c32143da077e07f |
|
05-May-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
For ARM backend, fixed "byval" attribute support.
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:
PR15293:
%artz = type { i32 }
define void @foo(%artz* byval %s)
define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.
Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
Parameter stored in GPRs; NCRN += ParamSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f65e4932f83ac0c36594d97fca73dc9a9fd26672 |
|
30-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Refactoring patch.
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.
This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.
2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.
3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 81fef0267b6971b32a618a655d91f472cedfcaf2 |
|
23-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add more tests for r179925 to verify correct handling of signext/zeroext; strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3a1b4f82233308b7551cdaa70f70a3f493e1b22d |
|
23-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Lowercase "is" boolean variable prefix for consistency within function, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 78e3c90419ffbe969bd38c7a198300af42fb66fc |
|
22-Apr-2013 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for 5.5 Parameter Passing --> Stage C:
-- C.4 and C.5 statements, when NSAA is not equal to SP.
-- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
variadic procedure.
Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
No exceptions, no CPRCs here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8b71994fde0f0fcdf7a8260dc773fb7376b1231f |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 456ca048af35163b9f52187e92a23ee0a9f059e8 |
|
20-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 69394f2997561788c3b2e4688ac0fcc99d259256 |
|
20-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
|
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5ad5f5931e34d5be410b1e901640bc1c2d308612 |
|
19-Mar-2013 |
Renato Golin <renato.golin@linaro.org> |
Improve long vector sext/zext lowering on ARM
The ARM backend currently has poor codegen for long sext/zext
operations, such as v8i8 -> v8i32. This patch addresses this
by performing a custom expansion in ARMISelLowering. It also
adds/changes the cost of such lowering in ARMTTI.
This partially addresses PR14867.
Patch by Pete Couperus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7bf504c58fcf1345f0278d6dab3840a45a623965 |
|
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Creating a vector from a lane of another.
The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.
rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 65da9f1ce14800c137fcd8c32f3ad12c9bebd9bf |
|
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
Clean up code format a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7ccf46395e02ecaff6e6cab6ad258c69893efd55 |
|
02-Mar-2013 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 21c0aa74bdeae6303204c9b0c2fc154562fbb373 |
|
02-Mar-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Fix v2f32 float intrinsics
Mark them as expand, they are not legal as our backend does not match them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b8f307b2d6b5fb1380803ff91696902bebbef7c6 |
|
01-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
Add support for using non-pic code for arm and thumb1 when emitting the sjlj
dispatch code. As far as I can tell the thumb2 code is behaving as expected.
I was able to compile and run the associated test case for both arm and thumb1.
rdar://13066352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a6ca70369366d549f104ee72822c6f591ea0ece0 |
|
28-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Tidy up; no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 279706e90e12e9418d4e8f9415d5f3ed33a99bdb |
|
28-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Style; no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b302a4e6b572a360d7153d2e1e14b53f053c282d |
|
27-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: FMA is legal only if VFP4 is available.
rdar://13306723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0a4da9c6a12371bb8bb36ef5cbb6922e0138dde2 |
|
27-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
Remove this instance of dl as it's defined in a previous scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
|
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e68542e67e5c0f8d4bbdae0dde6ccd24525a18e3 |
|
13-Feb-2013 |
David Peixotto <dpeixott@codeaurora.org> |
Test commit. Fixed typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d9316dacf5bb8c02631f782c7f2fc24fb8d788f3 |
|
12-Feb-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM NEON: Handle v16i8 and v8i16 reverse shuffles
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.
uint8_t Arr[N];
for (i = 0; i < N; ++i)
Arr[N - i - 1] = ...
radar://13171760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc7432744476281511704c7e07bf89e20c215601 |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to ARM return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0f156af8312a0f3ce88e5c006bf2a52691039ceb |
|
30-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0adfdedacbb87df8cc8b8311365a15fae004977e |
|
29-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix 64-bit atomic operations in Thumb mode.
The ARM and Thumb variants of LDREXD and STREXD have different constraints and
take different operands. Previously the code expanding atomic operations didn't
take this into account and asserted in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4a9256f265a7fcccd1f04518b55fd751f3a920a8 |
|
25-Jan-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
|
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
|
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 103b4a571ef01e4717c3c6d9db6506a3abd6cc0b |
|
20-Dec-2012 |
Bob Wilson <bob.wilson@apple.com> |
Revert "Adding support for llvm.arm.neon.vaddl[su].* and"
This reverts r170694. The operations can be represented in IR without
adding any new intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 332bd799512142e23d35105483520acbffff72c8 |
|
20-Dec-2012 |
Renato Golin <rengolin@systemcall.org> |
Adding support for llvm.arm.neon.vaddl[su].* and
llvm.arm.neon.vsub[su].* intrinsics.
Patch by Pete Couperus <pjcoup@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 37a942cd52725b1d390989a8267a764b42fcb5d3 |
|
19-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the explicit MachineInstrBuilder(MI) constructor.
Use the version that also takes an MF reference instead.
It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.
Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0340557fb830e3669c4c48a2cd99d7703bdda452 |
|
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
|
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a61b17c18a67f1b3faef2f2108379c4337ce9bb7 |
|
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7d34267df63e23be1957f738de783c145febb7af |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 61f4dfe3693bf68b20748d82ac4dd9bf2f356699 |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e07f85eb76a0254d3adbdf8b5d61ff5c07858cef |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bade0345d190427a08b2b947bc94f4d8ca5d7717 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8163ca76f0b0d336c5436364ffb3b85be1162e7a |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6a1b5cc7c60d54608bbe579b06497b7ade42dbc8 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Stylistic tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2766a47310b05228e9bbc536d9f3a593fc31cd12 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8a7186dbc2df4879f511b2ae6f2bce25ad37d965 |
|
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
This compiles to the followings before:
push {lr}
mov r2, #0
cmp r1, #99
bhi LBB0_2
@ BB#1: @ %bb1
ldrh r2, [r0]
LBB0_2: @ %bb2
uxth r0, r2
cmp r0, #23
bhi LBB0_4
@ BB#3: @ %bb3
bl _bar
LBB0_4: @ %exit
pop {lr}
bx lr
The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 105ab4fe4bffcaf339e4943b98c6155a0883284a |
|
05-Dec-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Appease GCC's -Wparentheses.
(TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c8e7045c8a3b3fb9ee8f4a7d4d4a52a46b3d420a |
|
04-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM custom lower ctpop for vector types. Patch by Pete Couperus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cb4953089bb845afedeaaf5dfd03d8d5639fd656 |
|
30-Nov-2012 |
Sebastian Pop <spop@codeaurora.org> |
Codegen failure for vmull with small vectors
Codegen was failing with an assertion because of unexpected vector
operands when legalizing the selection DAG for a MUL instruction.
The asserting code was legalizing multiplies for vectors of size 128
bits. It uses a custom lowering to try and detect cases where it can
use a VMULL instruction instead of a VMOVL + VMUL. The code was
looking for input operands to the MUL that had been sign or zero
extended. If it found the extended operands it would drop the
sign/zero extension and use the original vector size as input to a
VMULL instruction.
The code assumed that the original input vector was 64 bits so that
after dropping the extension it would fit directly into a D register
and could be used as an operand of a VMULL instruction. The input
code that trigger the failure used a vector of <4 x i8> that was
sign extended to <4 x i32>. It was not safe to drop the sign
extension in this case because the original vector is only 32 bits
wide. The fix is to insert a sign extension for the vector to reach
the required 64 bit size. In this particular example, the vector would
need to be sign extented to a <4 x i16>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 35b3df6e31f9aac70fb471d74e39f899dfbd689f |
|
29-Nov-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 350c00843bad22c5391e33e9e39a78d5d0983c8c |
|
28-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Implement CanLowerReturn so large vectors get expanded into sret.
Fixes 14337.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 43147afd71f6da4e7369a4ab9c681e5b4e0cf8c7 |
|
17-Nov-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e56764bad10621ac9dcf9d3541533ff2cb0f88b4 |
|
16-Nov-2012 |
Weiming Zhao <weimingz@codeaurora.org> |
Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b1a392e7c50da5789cf5da879c5b81b72c751c21 |
|
16-Nov-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
This fixes PR14359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 846ce8ea67362d8b6d93ebae66f23e3c68dce9df |
|
15-Nov-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works.
Patch by Pete Couperus. Fixes PR12540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 116bd168e1dd46ed5b1b46aabfc566128836fb70 |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Revert changing FNEG of v4f32 to Expand. It's legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b916904e685208a815a32e1ef24c1b49b3abb0cd |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make FNEG and FABS of v4f32 Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 490104720db9e1e0eb9cc27e88e2d7288ac27ff0 |
|
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b341fac05a890272024dcc5c7e47d10b22d62b92 |
|
10-Nov-2012 |
Evan Cheng <evan.cheng@apple.com> |
Disable the Thumb no-return call optimization:
mov lr, pc
b.w _foo
The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.
rdar://12663632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b3235b128f383559a7a9b9119896e406b347879c |
|
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r167620; this can be implemented using an existing CL option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d054eda44114df411a2749e7b6b85d27509a0af1 |
|
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Add support for -mstrict-align compiler option for ARM targets.
rdar://12340498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e7bd51980a1341fb60322e5922cfcc0c9b92b165 |
|
07-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers. Previously, the register we being marked as implicitly defined, but
not killed. In some cases this would cause the register scavenger to spill a
dead register.
Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 43934aee71746576b6e16663f382401b8693c83a |
|
02-Nov-2012 |
Quentin Colombet <qcolombet@apple.com> |
Vext Lowering was missing opportunities
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9a419f656e278b96e9dfe739cd63c7bff9a4e1fd |
|
30-Oct-2012 |
Quentin Colombet <qcolombet@apple.com> |
Change ForceSizeOpt attribute into MinSize attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 80acd97266f6f165285ae9303dea9654f87a2a87 |
|
27-Oct-2012 |
Quentin Colombet <qcolombet@apple.com> |
[code size][ARM] Emit regular call instructions instead of the move, branch sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0d3c8d5d16caa4c4f1310699722aa2cbe2844f21 |
|
19-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
ARM:
Removed extra stack frame object for fixed byval arguments,
VarArgsStyleRegisters invocation was reworked due to some improper usage in
past. PR14099 also demonstrates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b52ba9f8a896b6717d6395ad59f6550e1fa475b0 |
|
16-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue:
Stack is formed improperly for long structures passed as byval arguments for
EABI mode.
If we took AAPCS reference, we can found the next statements:
A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).
B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).
So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.
Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.
Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.
P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bb1078ea1370fd0cc32f52b1b53f0b245ded42e7 |
|
15-Oct-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e6c3cc8dc5437069f71a38188173835ba4fb0dc1 |
|
13-Oct-2012 |
Manman Ren <mren@apple.com> |
ARM: tail-call inside a function where part of a byval argument is on caller's
local frame causes problem.
For example:
void f(StructToPass s) {
g(&s, sizeof(s));
}
will cause problem with tail-call since part of s is passed via registers and
saved in f's local frame. When g tries to access s, part of s may be corrupted
since f's local frame is popped out before the tail-call.
The current fix is to disable tail-call if getVarArgsRegSaveSize is not 0 for
the caller. This is a conservative approach, if we can prove the address of
s or part of s is not taken and passed to g, it should be okay to perform
tail-call.
rdar://12442472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4346fa9437116bbdb10acddb982c230f46696737 |
|
13-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Mark VSELECT as 'expand'.
The backend already pattern matches to form VBSL when it can. We may want to
teach it to use the vbsl intrinsics at some point to prevent machine licm from
mucking with this, but using the Expand is completely correct.
http://llvm.org/bugs/show_bug.cgi?id=13831
http://llvm.org/bugs/show_bug.cgi?id=13961
Patch by Peter Couperus <peter.couperus@st.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2c2cb3c09f856975027becadb22dcca370683f30 |
|
10-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix for LDRB instruction:
SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer
that described in .td.
7 ops is needed, but SDNode with only 6 is created.
In more details:
In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset
operand is defined as am2offset_imm. am2offset_imm is complex parameter type,
and actually it consists from dummy register and imm itself. As I understood
trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy
register was not added to SDNode, and it cause crash in Peephole Optimizer pass.
The problem fixed by setting up additional dummy reg when emitting
LDRB_POST_IMM instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 661afe75e81431a66de3ed8e22d5aa91443367b3 |
|
10-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue description:
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.
Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.
Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
|
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eb1641d54a7eda7717304bc4d55d059208d8ebed |
|
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
|
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d6d10ae1519f0eb71c1db46c2cc77321d02c6ee6 |
|
26-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d10eab0a95dcfff6390cc73b50ca07fd8b98b0bc |
|
18-Sep-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte
aligned address. Based on patch by David Peixotto.
Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 616471d4bfe4717fa86259ff4534703357b3b723 |
|
13-Sep-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
This patch introduces A15 as a target in LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a1fb1d2ed7342c7e6b491a78af073b5320bc9867 |
|
08-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a7390fadbaa8da49649d76786555c93bcb680de6 |
|
07-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Custom DAGCombine for and/or/xor are for all ARMs.
The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 951543491fcc01486a926f0dcb37815ffff2051f |
|
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Fix self-host; ensure signedness is consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ba8562af4440753ba6175ccd54d71f79f5c4f3dc |
|
06-Sep-2012 |
James Molloy <james.molloy@arm.com> |
Improve codegen for BUILD_VECTORs on ARM.
If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 67514e90669ec9ffd954c1fcb6f8979bafcabe8a |
|
04-Sep-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 05e80f27148b1dc19925755d56b6466df840da44 |
|
31-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix a couple of typos in EmitAtomic.
Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.
rdar://problem/12203728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a0708d1109c2c1a3cf911a4761a10ad69a28455e |
|
20-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.
The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating
duplicate successor list entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0a8f8980000b753ef77dfc64cc7d9803d5dcc8ce |
|
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the CAND/COR/CXOR custom ISD nodes and their select code.
These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 864c8702ba0da2208212e84f146fbbe5c77866ed |
|
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dcd2342d32e92912cc457fe6ce4cd8a72c93c06b |
|
18-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1f1ab3e9c4dbef6a2d610b29903592986be09a10 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add comment, clean up code. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 053b5b0b3c34d4763511b6dcd8e0150f8e9dd083 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle ARM MOVCC optimization in PeepholeOptimizer.
Use the target independent select analysis hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2860b7ea3a1d60213ee7228bd274bc4f8b170772 |
|
16-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.
This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a99c508c8d34c073619b71d4f50cb28110cb1a2a |
|
15-Aug-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| df8320313bf31c77d6dde4010235d82d871518cb |
|
13-Aug-2012 |
Nadav Rotem <nrotem@apple.com> |
Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISDNode has more than one user.
rdar://11876519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a7016d6fc1c9935ede7b3dc2f39c8cdab14e40e0 |
|
12-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
architecture
It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0faf46c640c6747f1add89ba06631cebc4fa3afd |
|
12-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimpleVT can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bcc4c1d2d1b6877418de92835c537d79d44363a6 |
|
09-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3 |
|
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e94ac8871a1ac79bece57335d2abece0feed9c02 |
|
03-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the ARM GHC calling convention, this patch was in 3.0,
but somehow managed to be dropped later.
Patch by Karel Gardas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 242204784bae63da503c2f509a38c532085f0eb1 |
|
25-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Don't assume an SDNode is a constant.
Before accessing a node as a ConstandSDNode, make sure it actually is one.
No testcase of non-trivial size.
rdar://11948669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8d8d961de4878b17dca9d8b23666df223f6d654b |
|
18-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.
Based on Evan's suggestion without a commitable test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 49b446fa0a0daabebdb18a8ef884acda353399cf |
|
18-Jul-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eda9fdf979bd1c017304f8e9331f2c7df5df2d1c |
|
19-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: use NOEN loads and stores if possible when handling struct byval.
This change is to be enabled in clang.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 307473dec0e2fa966037d04725a40b33669dddc8 |
|
15-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: optimization for sub+abs.
This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi
For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.
rdar: 11633193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ad5c8808923ed5b24b586cec544e45cee539e529 |
|
11-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Re-enable the CMN instruction.
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 68f25571e759c1fcf2da206109647259f49f7416 |
|
01-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: properly handle alignment for struct byval.
Factor out the expansion code into a function.
This change is to be enabled in clang.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 763a75dbf719242e7f99c6447d20b9bffb75dfa2 |
|
01-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: support struct byval in llvm
We handle struct byval by inserting a pseudo op, which will be expanded to a
loop at ExpandISelPseudos.
A separate patch for clang will be submitted to enable struct byval.
rdar://9877866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 027c32a14ee953079e768b84ff329b37c442e208 |
|
20-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the right register class for LDRrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| aaf723dd2bccc052d2dd28e3cc4db76f2a3e2fb0 |
|
05-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 39af9449a26054ffbf879f5a7f75da2022e4b235 |
|
04-May-2012 |
Matt Beaumont-Gay <matthewbg@google.com> |
Pacify GCC's -Wreturn-type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fd5abd546e8e035755005a654d60d6f5f74cfe2c |
|
04-May-2012 |
Hans Wennborg <hans@hanshq.net> |
Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ff73d8fef9a94ceb2fc35d9371deeb0214c0eeee |
|
30-Apr-2012 |
Bob Wilson <bob.wilson@apple.com> |
Don't introduce illegal types when creating vmull operations. <rdar://11324364>
ARM BUILD_VECTORs created after type legalization cannot use i8 or i16
operands, since those types are not legal. Instead use i32 operands, which
will be implicitly truncated by the BUILD_VECTOR to match the element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3aef2ff514c879f98571fb91ddbe1142466a6266 |
|
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Handle llvm.fma.* intrinsics. rdar://10914096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf010eb9110009d745382bf15131fbe556562ffe |
|
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a long standing tail call optimization bug. When a libcall is emitted
legalizer always use the DAG entry node. This is wrong when the libcall is
emitted as a tail call since it effectively folds the return node. If
the return node's input chain is not the entry (i.e. call, load, or store)
use that as the tail call input chain.
PR12419
rdar://9770785
rdar://11195178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7f354557089d93cc681c440f9e064c906e1fbd58 |
|
09-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
When performing a truncating store, it's possible to rearrange the data
in-register, such that we can use a single vector store rather then a
series of scalar stores.
For func_4_8 the generated code
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vmov.u16 r0, d16[3]
strb r0, [r2, #3]
vmov.u16 r0, d16[2]
strb r0, [r2, #2]
vmov.u16 r0, d16[1]
strb r0, [r2, #1]
vmov.u16 r0, d16[0]
strb r0, [r2]
bx lr
becomes
vldr d16, LCPI0_0
vmov d17, r0, r1
vadd.i16 d16, d17, d16
vuzp.8 d16, d17
vst1.32 {d16[0]}, [r2, :32]
bx lr
I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll,
but I couldn't think of a way to judiciously apply this combine.
This
ldrh r0, [r0, #4]
strh r0, [r1]
becomes
vldr d16, [r0]
vmov.u16 r0, d16[2]
vmov.32 d16[0], r0
vuzp.16 d16, d17
vst1.32 {d16[0]}, [r1, :32]
PR11158
rdar://10703339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 96b66d65c23a596447ce3b14775f5c803fec47b3 |
|
09-Apr-2012 |
Chad Rosier <mcrosier@apple.com> |
Update comments and remove unnecessary isVolatile() check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d4f020a3af325630973df8d3a084d0b0e3b68ebc |
|
07-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ba4d45737f6e1094195823b33fb9868570ae1701 |
|
06-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
There is no portable std::abs overload for int64_t, use the llvm::abs64
which exists for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 70fbea7c7598c8803a325ffca98069ff013a2994 |
|
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Allow negative immediates in ARM and Thumb2 compares.
ARM and Thumb2 mode can use cmn instructions to compare against negative
immediates. Thumb1 mode can't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1c80f56268fa91f9c0c4d0a32b5d61e7b900c6d4 |
|
30-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c0a9f820d851baf66577a87c69ef383df41bbe32 |
|
29-Mar-2012 |
Lang Hames <lhames@gmail.com> |
Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0e5233a9e5ee9385c6a940e3985194d77bee0bbb |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| acf2077ca497980a066e8e7bb81ceec0de82d5da |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2d7ea04e2822bbe5faad0eefceb7a300ea01224e |
|
19-Mar-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Perform mul combine when multiplying wiht negative constants.
Patch by Weiming Zhao!
This fixes PR12212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c1f6f42049696e7357fb4837e1b25dabbaed3fe6 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes to match coding standards. Fix an issue or two exposed by that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 45b5f88938f59c495209512b545f289bf2cca90a |
|
15-Mar-2012 |
Lang Hames <lhames@gmail.com> |
Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc501a3ec9d97e372ecb1bd9cf32d861da46b2c9 |
|
02-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
Neuter the optimization I implemented with r107852 and r108258 which turn some
floating point equality comparisons into integer ones with -ffast-math. The
issue is the optimization causes +0.0 != -0.0.
Now the optimization is only done when one side is known to be 0.0. The other
side's sign bit is masked off for the comparison.
rdar://10964603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c54f6348861517398f17e85f41b30c4dd079fc3d |
|
24-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARM target to register masks.
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| db9538923eb95df48e9a6abe7e3b0ba8435915d7 |
|
24-Feb-2012 |
Dan Gohman <gohman@apple.com> |
When emitting a cmp with 0 for a lowered select, mask out the high
bits of the value carying the boolean condition, as their contents
are undefined. This fixes rdar://10887484.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5fb468a6b308b643edf61f1731b6d95fd1a03bf4 |
|
23-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bits
of x are zero. This optimizes rev + lsr 16 to rev16.
rdar://10750814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c892aeb26601cc5109490d30c7e170cb07f84428 |
|
23-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 07043279f60622243d16d8a3f60805960482083c |
|
21-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Proper support for a bastardized darwin-eabi hybird ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 873fd5f75332023ee8d8b4f9a85351f25e7f1e90 |
|
20-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Improve generated code for extending loads and some trunc stores on ARM.
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bdf9db6f4905fcbbcdbdfed328ea8b36b655dd45 |
|
14-Feb-2012 |
Bill Wendling <isanbard@gmail.com> |
Don't reserve the R0 and R1 registers here. We don't use these registers, and
marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1de886c1fa932b9c33d1f9d34698bafa9cdabebd |
|
10-Feb-2012 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Make valgrind happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6edd5884c91aea72661ed899b0c91dfb4f0ea80f |
|
29-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanups for EABI standard functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f349cb8f33665bf854b4d0a05012d958072febd4 |
|
29-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use base AAPCS for varargs functions even for AAPCS-VFP CC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 810d6d3354a31f24125abef831e4afccbbbe973d |
|
16-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Refactor variables unused under non-assert builds (& remove two entirely unused variables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ed4c8c633c52a40ad1a3e8687f290be4aeb1f0e8 |
|
15-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8f37a2422ea948b71d0992ab3f82dab07a54ce52 |
|
07-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Match SelectionDAG logic for enabling movt.
Darwin doesn't do static, and ELF targets only support static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f321e1075eabae96f62b1f2570d9dee5d10b8200 |
|
07-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f4aea8f34946d4d2b101b8e3c6db95c18be80173 |
|
23-Dec-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2f21e8c5ba62ec98e7dec9c65e35a3b4e7fdaf4d |
|
15-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
|
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3e0dc0606aed30b1fa6e1abcecf2cbf5e9ac1af9 |
|
11-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d440f678fb0fd6a8735bc315bd6f63fe8a71e8bd |
|
10-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Revert r146322 to appease buildbots. Original commit message:
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8c0b807e8fc9a14f61cc81589e4e81ea78ac57b4 |
|
10-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| effab8fa2413e96b6a2ce2bbeefe35fe478ee028 |
|
10-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Splats can contain undef's; make sure to handle them correctly. PR11526.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3b0887e291eec345c4848888c4604aff4f5f1e19 |
|
08-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 72590c973837f7d56638feb511a79574391f0eac |
|
08-Dec-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
|
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0861f5793a1834f02b522fb86fb037cd592c134f |
|
27-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move code into anonymous namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eaab6ef6eb12fc950f1d4371b297d9b7ca9d4c66 |
|
16-Nov-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d9190c0f148b218ab046deadd0c7ae475414cde5 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eaa192af18677c4dc5894e049514d8a6b1d6d7c2 |
|
15-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 15f58c56e9a4150abeea04469c9105edb8acad99 |
|
11-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 14e809c87210877a675977d247ff4453db82d9b2 |
|
10-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5207bf2177e9ef1e68d9408ea4b44f1c8a5ef9c0 |
|
08-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
|
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f1f26aefaf0bc02e732a1d36e664165d228901a |
|
08-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 65fd6564b8aedd053845c81ede1ac594acb470e4 |
|
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a1e78888d95375194e7513bef3e18d9f1b7d45bf |
|
03-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Fixed parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1a1d1fcc0b955420cdbe0b94bd01c46d4e96b429 |
|
02-Nov-2011 |
Lang Hames <lhames@gmail.com> |
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6f3ddef7c51f03945644ad0e69068dfb24d4b092 |
|
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf923b815d6da97367e3eedab69230918bf128a3 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 62c1d00dfd38996f381edae55e1028b8e52a1107 |
|
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2ba60e593012ba9b2a9d20b86733eadca288bcb2 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 75757f9fd13bffc51a6aa30eefe706c4f84d0913 |
|
26-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Make sure short memsets on ARM lower to stores, even when optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 015cca6c08a5da57b78796d82ab2679e8f5dabe1 |
|
26-Oct-2011 |
James Molloy <james.molloy@arm.com> |
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de39d86f26c5fa244a11d79988f26f52accabaf0 |
|
26-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f31151f34ec37dd49bdf998e9e352d572f4a8e06 |
|
26-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert part of r142530. The patch potentially hurts performance especially
on Darwin platforms where -Os means optimize for size without hurting
performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5c89cb8cd613c5a9d2bb2d6ab68afe8c2b41db70 |
|
25-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Don't crash on variable insertelement on ARM. PR10258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 692c1d85353249124caa1885cfeda513146c6d81 |
|
24-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b8dcb314f7f9c5c0f068a322c689a64881d78b70 |
|
22-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 767f8be9eed51f41c8ad03de7684761f82bf26c9 |
|
20-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add missing operand. <rdar://problem/10313323>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cdd8e46bec4e975d00a5abea808d8eb4138515c5 |
|
19-Oct-2011 |
James Molloy <james.molloy@arm.com> |
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 922ad78776a2a45fd79602475636077edfdf94fc |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b677a135acb2fc5dabb94d8f7fd0839e43dea092 |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 15a1a226be46dfaaa15c537daa9722b6216a981d |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Emit the MOVT instruction only if the # LPads is > 64K.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a5871dc1044ff31906f3a2cfc639c7fcd0a14c76 |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
For Thumb mode, we need to use a constant pool if the value is too large to be
used with the CMP instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 85f3a0a4c4c1953a06ea463c6b5d6b88d62b58b4 |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 952cb50fee7181265c0feb4f656dbbe8c0101dfb |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 564392bd3f6df4ba139d3be34017ed2a826f78bb |
|
19-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The value we're comparing against may be too large for the ARM CMP
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b9fecf4e077cfd54884ce96ef6bd9febf0d84191 |
|
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
The immediate may be too large for the CMP instruction. Move it into a register
and use that in the CMP.
<rdar://problem/10305266>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 90b7b12f012d9234488277a323231e0b7a8d12ac |
|
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9d45de252c7c3851c0159db4dcaa31e93598b29e |
|
18-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7f5f0dae33c8a105b51532d5ceb3339ac2ce0cbc |
|
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7b0207f1e89f08b2e2d233b8cc6ba6fcb2a0f4d |
|
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
A landing pad could have more than one predecessor. In that case, we want that
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ad952ad8f05a1c5082a6b7ac8627008fa24d722a |
|
18-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 17001ce25cc205ac1cd2604492c2bce310964220 |
|
18-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a48ed4fc8fddc819460e7ea0646709a7fd701e67 |
|
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Don't renumber the blocks here. This could cause problems later on if another
pass renumbers the blocks again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5bc85286ff8940e52edc7be1c8df120f98343ee1 |
|
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a call to EmitSjLjDispatchBlock.
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 24bb92556614434a5c5c2246b19e71d85426cab3 |
|
17-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add comment explaining that the order of processing doesn't matter here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 004a24b44ce79746a5333b7bf841b4234a936b51 |
|
15-Oct-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 918f2155e90613bcf222ac5499f845d231bdfd57 |
|
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Mark registers as DEAD because they're really just clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 46995fa7e2eead5759d13ddc64ef073c1d527f12 |
|
15-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5d79859f66fa1540d5a1c1e9e4f4e080e6e956f1 |
|
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Make sure that the register is in the register class before adding it as a machine op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 969c9ef0dd271905136f21a6c51dd0839ef01cce |
|
15-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Mark the invoke call instruction as implicitly defining the callee-saved registers.
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e4d0429de3d44a4c5b02b3d27cb0b78520609ba |
|
14-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ef2c86f8760f717882821987664bf5e7604ffe20 |
|
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Reapply r141365 now that PR11107 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eba564ceace5861a321c230acf5df32e55ed9be5 |
|
10-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2acf638216d98a4dcfed41828a4764cf9e68b4d4 |
|
08-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Take all of the invoke basic blocks and make the dispatch basic block their new
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f1083d4139720b41457528f81919d9587e442862 |
|
08-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ce370cfd891386d613d4bd0d28449d2705705d16 |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
do. This will be useful later on with the new SJLJ stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6d2f9cec715c50bca44816d9bdea97f8b63bf2a0 |
|
07-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Reenable tail calls for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2fef4573df6fd645f4401302d21c16e72418e3a8 |
|
07-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 244455e6d6bb95c5e556ace66adb148dbcd16a27 |
|
07-Oct-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Peephole optimization for ABS on ARM.
Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 217f0e9ca494a1752c591f50f04b4143eb1763c5 |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the correct vreg here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 083a8eb063657866ff595980fc03a16b791d08df |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate the dispatch code for a 'thumb' function. This is very similar to the
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 95ce2e9c52ea220f5090d9e8bacabf8e62f88d06 |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate the dispatch table for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e29fa1df55584b6f07290a91e33bf742f1c549e4 |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5e2cbc11337fca72ec962c8d8c29661d0e7c69ac |
|
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
Place the immediate to OR into a register so that it works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 04f15b4f2f38fb0dd8315676e6cff599cdbd6f0f |
|
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
* Set the low bit of the return address when we are in thumb mode.
* Some code cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 930193cb5544bd010a0a2bc795c9006913e2c595 |
|
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Add the MBBs before inserting the instructions. Doing it afterwards could lead
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5cbef19a1d9860534a573f446970f5c65758fb66 |
|
06-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Get the proper call site numbers for the landing pads. Also remove a magic
number (18) for the proper addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bb73468e2bfb21160266691e9cdc4c4ea4256b22 |
|
05-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Look at the number of entries in the jump table and jump to a 'trap' block if
the value exceeds that number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2a85015313b585c2a6d2a59d5bfc99a5ebe88f30 |
|
05-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Checkpoint for SJLJ EH code.
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ff4216a68a5a142259c631b1370bff270bfd7e49 |
|
04-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7e4aefd0f78441bef3b9eb683ecccbed9582b8a |
|
03-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Check-pointing the new SjLj EH lowering.
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fe31e673506ef9a1080eaa684b43b34178c6f447 |
|
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the new ARMConstantPoolSymbol class to handle external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5bb779976a7d8e48408051ec2289fe69206dc072 |
|
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Switch over to using ARMConstantPoolConstant for global variables, functions,
and block addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4ebbf7b8a8e80532bd2ddf7209e62689c1698a96 |
|
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9b88d2d7827d19ef05d3f11faf56e4f28aaa7072 |
|
29-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG.
rdar://10196296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8f418b11d23c05850c37d2f2c1933fefcae25719 |
|
26-Sep-2011 |
David Meyer <pdox@google.com> |
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
|
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3af7a67629292840f0dbae8fad4e333b009e69dd |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR.
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 74bf18cceaa4d83c816ffda04592c00a16de60c4 |
|
16-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7cc156647ff448f03898b3d80ecdc22d46430b57 |
|
16-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b04546ff5b1a7a03eec1076900c945223bf494cc |
|
13-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4a51708448e8958d8d1a375c055f1b98c8e20926 |
|
06-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7df496d2ad1ecbc86d454a5cea2ae3e0928197ee |
|
02-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Null-initialize to shut up -Wuninitialized warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4d3f3294535a3b622c715f2d9675d4f3e86c3378 |
|
31-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
64-bit atomic cmpxchg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2bdffe488203a08a2ca98548a157e0eaf39d4b2d |
|
31-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 342e3161d9dd4fa485b47788aa0266f9c91c3832 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb |
|
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2753ae314f656eab6d42c918469ce4ebf422cee5 |
|
27-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence GCC warnings and make an array const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 069e2ed794a90cb5108a35627ee148866795f140 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Atomic load/store on ARM/Thumb.
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4dfe220ad55e0f1e5edbf7cdd07f88497ddfdf25 |
|
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM expansion of pre-indexed store pseudos should maintain memoperands.
Partial fix for rdar://9945172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1f6a329f79b3568d379142f921f59c4143ddaa14 |
|
12-Aug-2011 |
Duncan Sands <baldrick@free.fr> |
Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7b8f46cf9e31d730acc25be771462e2a6a1a1dfb |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6cd5716f611b1acb8f4ce02f6953fc68a29fc237 |
|
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix typo in pre-indexed store lowering.
rdar://9915869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 19dec207fcc0f04902b7f097b7771ba7abba43fb |
|
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 26689ac37ebec3b358588089415509285e558de9 |
|
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 989f61e6c03b4717838b73aeaac7a38e2d8bb06a |
|
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ef7f1e71f722fcca863c7d354f408e72181ff891 |
|
29-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'Q' constraint.
Fixes rdar://9866494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 14648468011c92a4210f8118721d58c25043daf8 |
|
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c5a8c861c9f008d777f5da6a77c253fea2bfe2f1 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 92a202213bb4c20301abf6ab64e46df3695e60bf |
|
21-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e721f5c8d3ea2cc2cc8c3c308ce8bdd8a3fc3b32 |
|
13-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1
Previous codegen looks like this:
mov r1, r0
cmp r1, #1
mov r0, #0
moveq r0, #1
The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
cmp r0, #1
movne r0, #0
rdar://9758317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
|
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8dc41f33f7ff668f7dd56f37bd33fbd4ed82889d |
|
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add more info to FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a7603982dbf9e240ecc7ed6eddcd1cdb868107ac |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."
Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.
rdar://9572992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5e653c925c7da969c3fb5fa9a46263ffb160b81e |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d5dc9eca2beece0faa85e7cbf17182fe7fcd0b36 |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1070f82569be2602640e15e3a0a3eda55228b8aa |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
We'll return a null RC by default if we can't match.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 89bd71fc53fc95f2526e07ec338a8c998e9ead8d |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 09b4467ac556e82ba5ff368b035d38697d8459da |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Capitalize the unsigned part of the initializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 35e6d4d6b6f975157beb1ff8c939fac6699d710c |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Rename Pair to RCPair lacking any better naming ideas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 73744df0c467895bac9e25d5c62f34a0a8fcc4f9 |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add support for the 'h' constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a8cca80d4ac9ad94223b31e1c2203a30825529ed |
|
01-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.
No functional change.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fa6f5917af0ee34e6a8d6d6eaffe89024d5d7a04 |
|
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Remove getRegClassForInlineAsmConstraint from the ARM port.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 118c9a0c494c97fe23c43f3e2aca553aea3a4f16 |
|
28-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove warning: 'c0' may be used uninitialized in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ef01edf1e938ef89e598ec558c50ceb2681c5ac4 |
|
24-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT
(between floating-point and integer, Advanced SIMD). Basically the VCVT
immediate operand that specifies the number of fraction bits corresponds to a
floating-point multiply or divide by the corresponding power of 2.
For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a
combination of VMUL and VCVT (floating-point to integer) as follows:
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
vmul.f32 d16, d17, d16
vcvt.s32.f32 d16, d16
becomes:
vcvt.s32.f32 d16, d16, #3
Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a
combinations of VCVT (integer to floating-point) and VDIV as follows:
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
vcvt.f32.s32 d16, d16
vdiv.f32 d16, d17, d16
becomes:
vcvt.f32.s32 d16, d16, #3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1312ca8be679b332bb712328085e50121d4b94ec |
|
22-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Handle the memory-ness of all U+ ARM constraints.
Noticed on inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1396c403897e3d3e04fbf59f6c5fe77cbbab74a6 |
|
18-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused but set variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c75448c74051200602a8006bab45d747e61a5c3c |
|
16-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Mark ldrexd/strexd w/ volatile memory by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 689edc8b2845f7a6cf9403722de2000598f68489 |
|
16-Jun-2011 |
Chad Rosier <mcrosier@apple.com> |
Revision r128665 added an optimization to make use of NEON multiplier
accumulator forwarding. Specifically (from SVN log entry):
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7a10ab7d6f50b59580cc8ab1eb52d562e81f28d8 |
|
15-Jun-2011 |
Bob Wilson <bob.wilson@apple.com> |
A minor simplification: no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf188aeae7a579fb71480be7d32a2edc4d56d827 |
|
15-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
the bits being cleared by the AND are not demanded by the BFI.
The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).
rdar://9609030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 189531f317d0b3a082f78cc2da44128e4ff8e17d |
|
15-Jun-2011 |
Tanya Lattner <tonic@nondot.org> |
Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add.
Includes a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9a767330f555f21d6ef311d3a348d3a44f306d35 |
|
14-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a86686e643323762bf9383a0897a55257611aa74 |
|
10-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
Provide an ARMCCState subclass of CCState so that ARM clients will always set
CallOrPrologue correctly and eliminate the existing setter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a2e979565b2704ccb76d8e8d384723702b770c53 |
|
10-Jun-2011 |
Cameron Zwarich <zwarich@apple.com> |
A CCState was being created without setting whether it is in the Call or Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.
This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 471e4224809f51652c71f319532697a879a75a0d |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cf714d44b89864cf92d9c73508154457d0c65d9c |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.
Backend part of rdar://9037836 and part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5f8fd54f0891aa47f467498454f6a3df8ae62704 |
|
29-May-2011 |
John McCall <rjmccall@apple.com> |
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7eebab2a82cf13d0166299c7eb4f6234e16c8a5d |
|
29-May-2011 |
John McCall <rjmccall@apple.com> |
I didn't mean to commit these residues of a personal project.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 832a9d1a76d30ffd295453e93e8eb52948e5813e |
|
29-May-2011 |
John McCall <rjmccall@apple.com> |
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a0112d0c39aa31fe555ecf7296923ca30f68f811 |
|
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de64aaf6c8ab3a170b2e5a5b0968595503b5aad4 |
|
28-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
and add some basic tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4abce0c90b0c7c7c859951069baf0c0a70e085a9 |
|
27-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1ec11fb8b502971071a57b8b2de129f86bd41de0 |
|
22-May-2011 |
Renato Golin <renato.golin@arm.com> |
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0b65599015f0b51304d941ba4a14aaf0d1734341 |
|
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2e6496026f41d2c05ff038d14df9972f8a27fb94 |
|
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert r131664 and fix it in instcombine instead. rdar://9467055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 28e2b1d29ad409479f0c6a3aa3f663c847b5994a |
|
19-May-2011 |
Mon P Wang <wangmp@apple.com> |
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| db28247522af0a6190c9cab8dc32e7d4df9f5509 |
|
18-May-2011 |
Tanya Lattner <tonic@nondot.org> |
Handle perfect shuffle case that generates a vrev for vectors of floats.
Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b936e3006f04f60aca4c4de4a3604ec141ab0a45 |
|
18-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d48fda46f5b65f87e92a2bb94a722417bd5cc758 |
|
18-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2a8eb722c7bb0fac2fe09a876f3471dcb25f465e |
|
18-May-2011 |
Tanya Lattner <tonic@nondot.org> |
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 141ec63962b6fca66ab0007ffc6e50de46a22b6f |
|
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7d336c0c68f00f18c214fe5e689628f099a0f6d7 |
|
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
compare-and-swap intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 61512ba251097888963a8f07a35605564bcfc537 |
|
11-May-2011 |
Bill Wendling <isanbard@gmail.com> |
Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e1a56ae7478c7495a753229f4bbe27eb9a44442c |
|
03-May-2011 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily disable use of divmod compiler-rt functions for iOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cca82149adef8306a295abdc963213ae3b11bbb6 |
|
03-May-2011 |
Dan Gohman <gohman@apple.com> |
Add an unfolded offset field to LSR's Formula record. This is used to
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5ac179ccd2a03996f7b5ae7f12b5f45b8d38d832 |
|
30-Apr-2011 |
Eric Christopher <echristo@apple.com> |
80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7da8821b4c491b1c2ce7ac2374e46d8abdba518 |
|
26-Apr-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.
rdar://9326019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1c3af779fc6b184204efd7e98dc16e475c251e7f |
|
23-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.
Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.
Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c8578948c9b35080dedd6527abf4f48fc4de43d3 |
|
21-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove -use-divmod-libcall. Let targets opt in when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e341e8ce1ada854e7f8fcfcf18bb2e17be2ac0ee |
|
20-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
Excise unintended hunk in 129858. <rdar://problem/7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c73158730d43e7c8bdef32b2107566a6e78a8538 |
|
20-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2cc40138537abc39c360f0c83a7c78014b9b9ba1 |
|
19-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Remove some duplicate op action entries and reorganize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9eec66e604f09ed9779bc438d0dc4fa9d24db44c |
|
15-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
forget to right shift the source by 32 first. rdar://9287902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5af60ce2a8d4dc820664c9dc5fbbcff428402c15 |
|
13-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0aacbcc2e60fd06652280a9105eb2f8f9378efc |
|
12-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4da0c7c0c9081107bea5f6bac440f0f1eb47748f |
|
08-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 274d8d4eba8224b64e0bbc7196011ae7e0477453 |
|
07-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0433b21c989e7d4817574b950387355fe05f59b5 |
|
07-Apr-2011 |
Tanya Lattner <tonic@nondot.org> |
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2c69f8eec6a51114799e3e80fa4903c5e3fc429c |
|
07-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-divmod-libcall to a target neutral option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b48c791515659c7572dea7e1d53059f58fb3121f |
|
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 493cba1b32ebd4064e56a2387099b790c8c32c0c |
|
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Revert r128946 while I figure out why it broke the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 76634dfabb02507b73c0baed6fdd98bd5e703c60 |
|
06-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Give RSBS and RSCS the pseudo treatment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 76706013131247121a3a153f378946a0cb0e319c |
|
05-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f05b1dcf870346094f8aaee8e387c92d3e47e98d |
|
05-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Revamp the SjLj "dispatch setup" intrinsic.
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4071a711126a2a75585a32b96bb5d15ea267a915 |
|
02-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e23e815ad1136721acdfcce76975a37c8a2c036 |
|
01-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
rdar://8911343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 463d358f1dfdd28a6900f2f109a160be71d2a8ef |
|
31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ee2e0e347e253d103ebbb0c59fcb48ca2d80b7ef |
|
31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't try to create zero-sized stack objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9 |
|
31-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
can be recognized. This fixes <rdar://problem/9183078>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 92e3916c3b750f7eb4f41e14e401434b713e558b |
|
30-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3007d3331b30dcb575125b81543cd145448dd673 |
|
29-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
<rdar://problem/8875309> and <rdar://problem/9057191>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 78fe9ababead2168f7196c6a47402cf499a0aaf7 |
|
29-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 29aeed1bf8c70eec381d5cbf7de2710b5157d526 |
|
26-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Fix the bfi handling for or (and a mask) (and b mask). We need the two
masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1, #1
not #0, however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 485fafc8406db8552ba5e3ff871a6ee32694ad90 |
|
21-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7a90e04fc76392972bd8bd0ddee5c934c22c1393 |
|
19-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ae16d6b9722dd6ff4a606308e3a14d200f3a903f |
|
19-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0d4c9d94f68fc561ebb11709ed99367e490af003 |
|
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a24cb40be24e854faa8fb2c2148422a19c4a0ea5 |
|
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 69a05a7b9205fd4628ed614d1845f3879f6be949 |
|
15-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 21a6179c9daaaa38be40b53d6993404856e20dc1 |
|
14-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 79f56c9618e60c390932a6866929b82c9a6d6f96 |
|
08-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1b772f99622dc89b807541c0d7477286aa369976 |
|
08-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4faa0e19521f700ad10bfea69e141fc46c45f78b |
|
05-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused conditional negate operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c24ab5c654debe47d5693e287d4dc2e151c0ba0e |
|
28-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix a typo which cause dag combine crash. rdar://9059537.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f222e595c0137b8a9571408257f7000c2fb95473 |
|
28-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Support for byval parameters on ARM. Will be enabled by a forthcoming
patch to the front-end. Radar 7662569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e573fb32556ba8430ccd723f71233cdf56b76340 |
|
23-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
More fcopysign correctness and performance fix.
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
|
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7973f350b78e0bef8567f441f3255c846f5432ac |
|
11-Feb-2011 |
Nate Begeman <natebegeman@mac.com> |
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.
This avoids moving each element to the integer register file and calling __divsi3 etc. on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c143dd4f63889ca6b4f656200f43a1fa7bbf1c34 |
|
11-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix buggy fcopysign lowering.
This
define float @foo(float %x, float %y) nounwind readnone {
entry:
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
ret float %0
}
Was compiled to:
vmov s0, r1
bic r0, r0, #-2147483648
vmov s1, r0
vcmpe.f32 s0, #0
vmrs apsr_nzcv, fpscr
it lt
vneglt.f32 s1, s1
vmov r0, s1
bx lr
This fails to copy the sign of -0.0f because it's lost during the float to int
conversion. Also, it's sub-optimal when the inputs are in GPR registers.
Now it uses integer and + or operations when it's profitable. And it's correct!
lsrs r1, r1, #31
bfi r0, r1, #31, #1
bx lr
rdar://8984306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| aa26102db47ac7041a54728cf856de4dca700880 |
|
07-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious typo which caused an isel assertion. rdar://8964854.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1c3ef90cab9a563427bdd3c2fcd875c717750562 |
|
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 31959b19a72608051888160514977875a8027dfc |
|
02-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.
This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []
to
ldr r12, []
str r12, []
rdar://8944252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
|
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5899a60d2fb02f7e2d094d710babbe1d3bd97254 |
|
24-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide correct registers for EH stuff on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 53519f015e3e84e9f57b677cc8724805a6009b73 |
|
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
|
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 32cec0a75678401ce079bb31fa748ae0d6613e2d |
|
19-Jan-2011 |
Andrew Trick <atrick@apple.com> |
For ARM subtargets with useNEONForSinglePrecisionFP, double count uses
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7fa75ce11d8f491d9f68c3cabe60f6fc70787748 |
|
19-Jan-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc8475bde993cc0fa6101427e73e8a9cf7d1c3a4 |
|
19-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 |
|
17-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 41262da6cc8e61d7ae5e021a41964d50c964e390 |
|
15-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Fix 80-cols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c9df025e33ac435adb3b3318d237c36ca7cec659 |
|
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 55d42003368c57d3a41c5f464d39b8440050d558 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 70f85730b199839891166b2a0acff126d1cc7c12 |
|
08-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add an explanatory message for an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 697970286ac61ff5bf4659d51a2cf9e0a2b7800d |
|
07-Jan-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Eliminate variable only used in debug builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 11a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56 |
|
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Lower some BUILD_VECTORS using VEXT+shuffle.
Patch by Tim Northover.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5e8b833707e6d59576d91b23a2c24e596eace60e |
|
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0521928ae7cc492f3f45ef0e0cedc349102489c5 |
|
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3c904694fc769ce9e12455b43b94144a99325110 |
|
23-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 316009054ef25fd12f95d97ac9282dede2392e1a |
|
21-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3a75b9bc8fed6c7f3f30470d3f3e28ac83df9d40 |
|
18-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add some missing entries in ARMTargetLowering::getTargetNodeName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 836c6245ad7e8f2b9f72c2a9e4cb1df101eaf2c7 |
|
16-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Don't handle -arm-long-calls in fast isel for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef |
|
14-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 30fb13f97a197823f66da4df98625a9b3585ece9 |
|
13-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Generalize BFI isel lowering a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a9688c4b5769be7a6a89350888b3173c97fe87ed |
|
11-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 40f8f6264d5af2c38e797e0dc59827cd231e8ff7 |
|
07-Dec-2010 |
Jay Foad <jay.foad@gmail.com> |
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1bf891ae6e174ac92c1091be0c62891f4676beb8 |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix and re-enable tail call optimization of expanded libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3d2125c9dbac695c93f42c0f59fd040e413fd711 |
|
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b1dfa7a8e0c1972231bee636afd5239b009ba4da |
|
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VLD2-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 364a72a8e5810561613491bef0de6f301ee4925c |
|
28-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 626613d5e8805db1f40e956faf47c87bea3aee44 |
|
23-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1f190c8bdf1d74c029c85b0865c983f3f9cafb31 |
|
19-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
These instructions are thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9684a7c1281e7d7f6d7ab7c3f8484fe2138f39bc |
|
18-Nov-2010 |
Tanya Lattner <tonic@nondot.org> |
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d5448bb6e845bd6c2dcb98156f49a73842759ab0 |
|
18-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Split up ARM LowerShift function.
This function was being called from two different places for completely
unrelated reasons. During type legalization, it was called to expand 64-bit
shift operations. During operation legalization, it was called to handle
Neon vector shifts. The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function. I don't have a particular testcase for this; I just noticed it
by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf5be2654ee396710e28d83d2afebd6f22720c52 |
|
10-Nov-2010 |
Nate Begeman <natebegeman@mac.com> |
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 54f92563806e87f47acd04fd71e4189d35d11005 |
|
09-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Do not use MEMBARRIER_MCR for any Thumb code.
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3a2429a86c50a89c3321c741b85fa7d1fe668b38 |
|
09-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the ARMConstantPoolValue modifier string to an enumeration. This will
help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c24cb3551ed66830b53362f593269873cb53a0c4 |
|
09-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for ARM's specialized vector-compare-against-zero instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 36fa3ea566c66b42e4dd7b4394be2f1e071647b8 |
|
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 080c09229739ec2b13f7bccc361994a8d26b4ed2 |
|
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add codegen and encoding support for the immediate form of vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 416941d50fec5ebdc4ae3b113a0db1320c3b2a87 |
|
04-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 60f4870c221d0496254c78c6e61bc00e4540fc1b |
|
04-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d966817f3cb87897cbec29c967b974924fe939ba |
|
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3468c2ee20e26ded1a5182edcc72e36fb09c909b |
|
03-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for extractelement with a variable operand for the element number.
For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cdfad36b401be6fc709ea4051f9de58e1a30bcc9 |
|
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dfed19fe2c34c1209108afa58e8ab014ffd894e2 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bc7deb0f758d2544fc4c36433668340cbf4835cf |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 24645a1a6d317acfc16303237704f32364fb2f0f |
|
01-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
NEON does not support truncating vector stores. Radar 8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f74a4298163a7d0b500c7f7a818829c153dc942e |
|
30-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d7e473c629a5e4fb1584fb5c5c1b0c1e142fdc8f |
|
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1fa9d301a83569e8b0f4224097e0869c8a06f879 |
|
28-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix compiler warnings about signed/unsigned comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f20700ca773acb0d79ce69ad5834e00884ad31f0 |
|
27-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5c2d428f43e83912e8f20e6f917fe11236741bfb |
|
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable ARM fastcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 76f920d316dc6a9e5e77c8e36f9312d1708e376b |
|
22-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e4d31593c5b0693480e697d7aeb0a24edcf53870 |
|
21-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Fix crash introduced in 116852. 8573915.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e4ad387a5a88dae20f0f7578e55170bbc8eee2a9 |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 575cd148cedec66af0adc266c5d7ecdbe1641d7e |
|
19-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Enable using vdup for vector constants which are splat of
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fd52906478a17c1459607a9e458578d4289cdfa6 |
|
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Don't mark argument value stores as immutable, as otherwise the post-RA
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1dd5a2f4e127a99914359cf39f19b3a9916d6be1 |
|
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused ARMISD::AND selection DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4f922f2cca58d794671afedc22f82d96aeb46afa |
|
28-Sep-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
User proper libcall names & condcodes while compiling for ARM EABI.
Patch by Evzen Muller!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 02aba73a9ec04d0de9424422249af3948ca9573a |
|
28-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it. Radar 8465431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fff606d7b2d65495050360056acc65ec667a93b5 |
|
24-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable code placement optimization pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 637d89fe0eca4fa2b9c95f6c15eb69a99bae83bc |
|
23-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for ELF PLT references for ARM MC asm printing. Adding a
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b68987e4bff7cd269e0cb40b30851e9c2195db99 |
|
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VDUPLANE DAG combiner to just return the result instead of calling
CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0b8ccb82527616d0fabe5083e69a05e1950caff2 |
|
23-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 861416757246f7e2d42cc465137d520105f569ab |
|
22-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc448ff89b4fb7721de9da0b96fd00c13160c4c7 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert a couple more places to use the new getStore()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 65ffec49f73d1f8856211b107712c58cc9636b78 |
|
21-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 75f0288b7dff1fcb24d9d61ea3e9547ba21382e4 |
|
18-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6f2ccefdc069b6bd2e8f8b110fc3205b821a17a7 |
|
11-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Split out some of the calling convention bits so that they can be
used for fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4725ca746ae815f68627657fc4135a285670a4a4 |
|
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eb0c3d372906df9c61a31651a0ba278034447e94 |
|
03-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0b69cf1198dadbb7bdfc385334b67f60f756539 |
|
02-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0b4aa7d11b9a55d602b7398da4495a3b6eba5018 |
|
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
it sets the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3cc3283fcbb90924196cc38ee5977b35c4ee28b5 |
|
25-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b31a11b466281b7e01cfde007b2041eefa2341e4 |
|
20-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2003bcfbd243716e5599f65705b515c2a229c7d3 |
|
18-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand ZERO_EXTEND operations for NEON vector types.
Testcase from Nick Lewycky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7aaf5bf3db44c94bd630e07d63c3a4a1d92e44f4 |
|
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow more cases of undef shuffle indices and add tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ca5e47d3f84dcf3dfbc6706bf1041e7029f3ce0a |
|
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 703af3ab128addcd061e0761b059a919da2a4066 |
|
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily disable tail calls on ARM to work around some linker problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fcba5e6b645df89ae6b93911fe0f80b08fa6b44c |
|
11-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de2b151dbf125af49717807b9cfc1f6f7a5b9ea6 |
|
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Consider this code snippet:
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long 1075344593 @ float 2.382130e+00
.long 1067316150 @ float 1.234000e+00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 11db068721d44fd5f9b0c2a3a4c90f813d2eae9c |
|
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5818032521e9e76873ec82104a7c22ffb9d9b277 |
|
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete some unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ac096808a3accc516ae7c193c9a2c1392bf3301a |
|
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4bd828f78139b9bab561102c5b9c40133ad375ca |
|
10-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c9aed19747608b7688a64f2f382a008889f8e57d |
|
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.
This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a54db0c48597d68e54528d0ae129f1f1ea4c0b50 |
|
04-Aug-2010 |
Dale Johannesen <dalej@apple.com> |
Remove switch for disabling ARM tail calls. They
seem to be working correctly. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 67b453b0d1ed7ab42a9408a6eb00131e160eb421 |
|
04-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
(absolute difference with accumulate) intrinsics. Radar 8228576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1fb583128c6682bb8a7c74eafa810a9270cc8df |
|
03-Aug-2010 |
Nate Begeman <natebegeman@mac.com> |
Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3d5792a5aaa735c35e5cb66b615ada9f7b6fa052 |
|
29-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Refactor ARM-specific DAG combining in preparation for adding some more
transformations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f630c712b17cae45e8cf9bc670c8b1695c37c3c6 |
|
29-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Implement vector constants which are splat of
integers with mov + vdup. 8003375. This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cec36f4c1118dc8388910d4753fe7cbf88d2d793 |
|
24-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c2723a57f35dd69bd261faaa71ee7aa05f40a87d |
|
24-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Use the appropriate register class for an i32 when adding ARM::LR to the
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3144687df78731ac4ddbc716a24b951678a73f57 |
|
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 30d35b8720cb148eb4cc417b3710e0d66ce5ec95 |
|
22-Jul-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Mark an assert-only variable as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4a863e2c75145432fd660ee65e61b578c5e90ac9 |
|
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ab695889c67fb499bd902e8a969d0ff02ce66788 |
|
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bc565014357a89c91a46a647714cb0d256186cc9 |
|
21-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4f6b4674be5473319ac5e70c76fd5cb964da2128 |
|
21-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 26ede6834e8a435bd7a6670cb34f64d3f8e2599d |
|
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Removed un-used code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d70f57b254114841892425a40944268d38ae0bcd |
|
20-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e1102caf86c8e09387ac7ee83aae4e69d2d35fc4 |
|
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 350afb16ecab216d5ea887b93112b24ba87ececb |
|
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
revert so I can get the right PR# in the log message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0bb9895a78368a75a3bfe2cb54ac6953b990515a |
|
19-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5423856e44a7e4b173af211b0fb0675c44945a58 |
|
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dd7d28a17b19d03115592de74e8291e47afbcc72 |
|
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
add BFI to getTargetNodeName()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 15a2f2eff80485e0f02a01300fde04d0b2f84a91 |
|
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix logic think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 469bbdb597f27d6900c95b6d8ae20a45b79ce91b |
|
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 60108e96bbc5432f4fe06ba313e64448e97a0e15 |
|
16-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7e3f0d26908b82bc6a3699251e0d38821610bca7 |
|
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9e82bf12a03117bfce78217662d5cf8e74aef357 |
|
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cba270d042862bca213b812656a2181b0de0578e |
|
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions. This simplifies some things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 218977b53eb215e5534db2f727d109ab18817cc1 |
|
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6dce00ced45b5bd1b7f34fe6f2d70c50fc090664 |
|
13-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
avoid replicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c7a797b82bc44b0aace62033d7e1ac7058ef45c6 |
|
12-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove some code that doesn't appear to do anything. All the ARM call
instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cbeeae23c31d32b833c9c7c3e8984e4cbcf22f45 |
|
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5d115a0ff9634149ef021ec9335a47c52aaaafb0 |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Check for FiniteOnlyFPMath as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4ff7ab612c66fb7ecf547242d6906be6ec3fa604 |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 515fe3a58877c745a922252a4492e866a2f1e42e |
|
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7835f1fcdbb58093377c9e3476f45a2638565762 |
|
08-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e97f968a69d90ee61fbe16d1740ab7f7ea18d1bf |
|
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
they've been tested to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c66e150b2cb1f2f8e2f4eb124b9177ffc6ef3a74 |
|
07-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
|
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b5b5057a709a6dc8e99c6e57bdea89c2b53dd4de |
|
02-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM function alignments were off by a power of two. svn 83242 changed
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 90c64f4aac95ebfcdeb8ad78a373fdb9e61b002c |
|
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove initialized but otherwise unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a2c6f457a4954d8e38b4c2c69b011cdfa123ad02 |
|
26-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f6799394d5a656fa5adec4619d60c5f79fdb43f5 |
|
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
It's now possible to run code placement pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
|
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
|
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 86fe66db3ad19bc20dbb9803e4bf032aa6cd1924 |
|
25-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e39fdbe1187b74f8c415adb9f807fa56f1e055aa |
|
23-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Do not do tail calls to external symbols. If the
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5def57aaf477e3383cbd1b925233098a54273146 |
|
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
When using libcall expansions for the atomic intrinsics, the explicit
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 56a1a69a35ca2ee0d1249d705de8936096c6f008 |
|
21-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dc076da4d25a447982c0629da91e322eda511cbf |
|
19-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix error message to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0110ac66ebd1e59e6ac163e13670f36d091084f6 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ef6eb9c7ab7967790566c5e2d47977d89fc060ee |
|
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 68741be5e6a4a0e633928e4d86eea38aa07a2ca0 |
|
19-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable Expand handling of atomics for subtargets that can't do them inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c66cdf74a9f1ee12cb9bff39cbd6bc518fbc2d3e |
|
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Enable tail calls on ARM by default, with some
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| df50d7e238c4802eb2de04646b8f7ff7327730a0 |
|
18-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Last round of changes for ARM tail calls.
Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0d8ba3303b40a150f70ff63f04f57160984492c1 |
|
18-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7072cf62a52787c461e3371ad36e1754e8a0dc97 |
|
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c73993b67815c96bb270034bdc7b7e8edc16d614 |
|
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
simplify code a bit and add a more explanatory assert for cases that
previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7616b646f1436d11ce0cb16f52ffa10b5522b0ac |
|
17-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
format and 80-column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 07f6e805b1e832a2c34a83862cec27736bb471bf |
|
16-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 46df4eb46e784036cf895db271fe29e1cf2a975a |
|
16-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6470a116f17b70aba0c2e7ee751551a5ac9797f6 |
|
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 827b2106fe39c4195f5f5393b6bab70cc297657d |
|
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add basic support for NEON modified immediates besides VMOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d3c4284849ccfbc501483ec3c0810d1d9ef853b6 |
|
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename functions referring to VMOV immediates to refer to NEON "modified
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1114f568bc35cf13064c864df44194630449bec5 |
|
12-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1a913ed17875d1a0fb490e1266b74c057c76a94b |
|
11-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 53dd2454d5a38af455a9b23a16b0cca8e691b070 |
|
08-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Further changes for Neon vector shuffles:
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cf296fa1629f02e63aa1264a619a65cfc66ef173 |
|
05-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Improvements to tail call code. No functional effect
unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8fa8e7fe95db6a8c8581ccfe9db2c9faac819f8d |
|
04-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
More thoroughly disable tails calls by default.
8060143, although this doesn't fix the real problem with tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 40cbe7d5d41d22d32e8ce773548f510fd1ee0ed9 |
|
04-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 51e28e634880849ed9f7c02e93c08d25dd70291b |
|
03-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c10f5434b4ad0758f948c52c18d5740c7f44e8b3 |
|
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0798eddd07b8dc827a4e6e9028c4c3a8d9444286 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Update the saved stack pointer in the sjlj function context following either
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a65850230af7f13d9111450f645886b968dea2a2 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
back out 104862/104869. Can reuse stacksave after all. Very cool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ad9aaf038e1886013ef7118608182c479c986a97 |
|
27-May-2010 |
Jim Grosbach <grosbach@apple.com> |
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 23ff7cff52702a8bff904d8ab4c9ca67cc19d6ca |
|
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ab3912e3ce5a58a6dbdc2780ae489162faa5452d |
|
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c7cf10c97ef08dc3dbe917e16908cc9bd3d888e6 |
|
24-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 069e4348685e5e7a472787fc9950a081633bf928 |
|
23-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
VDUP doesn't support vectors with 64-bit elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
|
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5eb195153950bc7ebfc30649494a78b2096b5ef8 |
|
22-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| be751cfe9cbcc760e24599a59e5b9699d4d4f9e0 |
|
22-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7d87ee1584bffe361b39f8cec7a39131c8c4efc |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1cc3984148be113c6e5e470f23c9ddbd37679c5f |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 63b8845e786d1204d41952da938518baa3159a97 |
|
20-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 211ffa13519cadfb7f9baf4c8447fa055bf38fe8 |
|
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 28dad2a5caccf579f7430acd3af8fa6e6f8b575e |
|
18-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4878b8415fd524489b4bee5f90e969f6ccb253d4 |
|
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a9790d739a7970dd516c57f56d67cf9aa01b9d39 |
|
15-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4782b1e2caf0030eab1112c12dd4a2ffca688ecd |
|
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
v4i64 and v8i64 are only synthesizable when NEON is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 06b666c7056376b8aaf40be0dc00b97b2cfceb6c |
|
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 22c687b6421d9cc03351ddb0c7fd3d45382bc01a |
|
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
|
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fb3611daad2bdf9fd50fe5ef1167fe6a8c950031 |
|
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 603afbfe2ac8ccc21283b149a76a81eb44b956b0 |
|
10-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model vld2 / vst2 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4b77f6a85a206f4a4cd23f8cdf710f2574a5ac42 |
|
07-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 29402132f3e890a2771818f44987ede213297431 |
|
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b1dc393bd56365ad8fabb51f22c2f3ace707c39a |
|
05-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de8aa4ed9c8d3654e08eda3973e0500ddc7ac0fd |
|
05-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f3f061d74e19543be61e797127c54546668600c |
|
17-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3a1588a2e38d57de3c4277f071f2316fb3dbc37a |
|
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0dbdca5a8594cbc2961faa37e3eadcd6e265fa90 |
|
15-Apr-2010 |
Anders Carlsson <andersca@mac.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e7b52526d386cd0d3a08b8daa7db67839649bb37 |
|
15-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add -arm-long-calls option to force calls to be indirect. This makes the
kernel linker happier when dealing with kexts.
Radar 7805069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101303 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 164cd8b8d305f93a1520fc1354d896acd1d002f4 |
|
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6a234f07faf164e62f0799fa87f5742528cc043a |
|
14-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle a v2f64 formal parameter that is split between registers and memory
such that the entire second half is in memory. Radar 7855014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0910c4534d323d101729d796e70805d3c2f0716 |
|
07-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Expand SELECT and SELECT_CC for NEON vector types.
Radar 7770501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
|
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
|
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 100f090adde26005b9f1eca96871dff52825b27b |
|
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
|
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 35075a7e81338c0eea00d1bac6e0d4ffb9c82c82 |
|
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
tweak the arm if conversion heuristic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fceabef52cfdb9243f483af9030797a343cca2d9 |
|
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 76a312b7d1c2b41394696510506967cd0794b831 |
|
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 341ab138fb3b7b7ebe12371481641f8681cd4e9d |
|
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific fp <-> int nodes when still I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f0d500768d1a42e91c6324e6c8677cbe26df6e27 |
|
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 33cc5cb9837469dabf31cc5a474e2c27d2b7d144 |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.
Radar 7459078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 505ad8bed3321bc4b99af8fba4844efe2fe9e67a |
|
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 631379e79c0971c5bac13629b8caf8912ed4c35c |
|
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add substarget feature for FP16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bec3dd25c76c825c179ef35794a8fa3620cf2559 |
|
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add codegen support for FP16 on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bdc38e5aa27bf57b4315b961a172e250bcb1bd69 |
|
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 94a1c631dbcad0c92032259444aa40b795b3d283 |
|
09-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
|
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e742bb53a3e68b88eac172782fd99cd98f89f4b3 |
|
24-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f9a4b7653d2a838b344dc3cd38b37f7803059d79 |
|
24-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f6c4c141ffa9c8b13e90dce2f2285c4479ff403 |
|
18-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1b58cab38ca788be1e64815ab65dfd43e66c98b6 |
|
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a87ded2695e5bce30dbd0d2d2ac10c571bf1d161 |
|
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 90cfc130d618ecb0539e475c343ed805ee124f8d |
|
30-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cb9a6aab02f07cda005c7c078d8e4a3463017866 |
|
19-Jan-2010 |
Bob Wilson <bob.wilson@apple.com> |
Wrap some comments to 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3482c8003ad0c88469b7333aaf658036e3fd0468 |
|
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Patch by David Conrad:
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 867bbbfff7752b86be14f38644599e9da88a5f78 |
|
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Name change for consistency. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5efaed3bf46c829ff8767fd804815c5471f83310 |
|
15-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 09bf003983bb35190ce9932c4edc9a7635f379c0 |
|
14-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
ARM "l" constraint for inline asm means R0-R7, also for Thumb2.
This is consistent with llvm-gcc's arm/constraints.md.
Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 15913c999e5fb03cd26de00a48dd3cf1780ffb43 |
|
13-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix pasto
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
|
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 102ebf16b6eb46e3021b9e8db8a1bc163bc64639 |
|
21-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Delete the instruction just before the function terminates for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fda60d35c247c239857ebaae8650b06f1154e68e |
|
18-Dec-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix libstdc++ build on ARM linux and part of PR5770.
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.
Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.
For a patch that make us detect problems like this earlier, take a look at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html
With that patch we assert as soon and the new instruction is added to the garbage set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5afffaed5c0095930020947322633f0d0b02ffed |
|
18-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c67b556b5b9c45f393e62fa7ffd4c70b932af2be |
|
15-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
nand atomic requires opposite operand ordering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7c03dbd8ede6f43063df56eaa6d63f7ae1721892 |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add ARMv6 memory and sync barrier instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a36c8f2c2e6a20080e6784a73e30fc2c8c67c584 |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c3c2354ec9b56c3097752537020150da8694dd62 |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
atomic binary operations up to 32-bits wide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e801dc4a7b89f68f40ff2753de988c482d4d117f |
|
12-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Framework for atomic binary operations. The emitter for the pseudo instructions
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5278eb802fae2ee1a7b2a428596bc364d8bcd9db |
|
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3728e96a6c0f68f4f5b656c2372e9cbbe6e74d86 |
|
10-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d831cda3e74235704f163d5a18352584d537517a |
|
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Support inline asm 'w' constraint for 128-bit vector types.
- Also support the 'q' NEON registers asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 324f4f163350487243d3a93b2a79f5eb2edc3b03 |
|
03-Dec-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize canonical forms of vector shuffles where the same vector is used for
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5cdc3a949af0cef7f2163f8a7acbf3049c226321 |
|
24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
|
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
|
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 06b53c0d51f029eb754b40350faf5ba4b33c4bcb |
|
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
isLegalICmpImmediate should take a signed integer; code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 77e4751011da2d6afa930ab91f7baee39e7c7e89 |
|
11-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 |
|
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e7e0d62efda2445b735052ca45bd74fb002e34c3 |
|
06-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b62d257cf5adf89599e185e8cbd2b15e05e054dd |
|
03-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert previous change to a comment. The BlockAddresses go in the
constant pool so they don't get wrapped separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 907eebd5a6779e8539ef7bf63550a5b72de76ab2 |
|
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Put BlockAddresses into ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2ae0eec1c03fa005136b8724faab38048878f253 |
|
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bcf2f2c1592c96b3adcfd784e0699e8c55f65e5b |
|
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit logical shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b4a976c304e98fb4160549a92e35610b310dfd93 |
|
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64-bit arithmetic shift right inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c2b879fcfe3834597948d5dd6044a3f32baee275 |
|
31-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Expand 64 bit left shift inline rather than using the libcall. For now, this
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9eda68988e7772c40f6125750a965ddb85acc25f |
|
31-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 929ffa241480bfe8b45c48cc64a8e0de38ec2421 |
|
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c1382b745faa62bc6f2570a193bce6aee8d78885 |
|
30-Oct-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
This fixes functions like
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ddb16df91257e4c4d2be5343e2c7c7ecbfbe8bf4 |
|
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM codegen for indirect branches.
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c59420867eec22f7fb562b5b53deffe98b511505 |
|
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 39382427f1095f089d73a7dd3d9a371dea75b781 |
|
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use fconsts and fconstd to materialize small fp constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 20d108140e8a4ba9b5e2dd1662e26e5c2282d567 |
|
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Most of the NEON shuffle instructions do not support 64-bit element types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2095659a8551fb222d145bc8dfa6cf5d15048e42 |
|
21-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Match more patterns to movt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 174101e13a6f24f6f2737e043194f0ffae925bb3 |
|
20-Oct-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Random #include pruning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 934f98b5368c10a77599dab7dd6ec969c8b2f385 |
|
16-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert svn r80498 and replace it with a different solution. The only problem
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e72142aa5b8bcd9266a5a2f88e4e227dd178f233 |
|
14-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 73d64a6fd3294b2b265d4ca7b5c9f76989459fb7 |
|
13-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
NEON VLD/VST are now fully implemented. For operations that expand to
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 249fb339ad9d4b921a04de738b9c67d27e328bb7 |
|
07-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
and register spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 048e36f5369b500c15c7e74933904983724981bc |
|
02-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
getFunctionAlignment should return log2 alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 48e19352840a5f7012493ead894e81a2dbec1778 |
|
23-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0696fdf3220c4cdd7fc518274048a35091cc17b1 |
|
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand vector floating-point conversions not supported by NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 642b32910425ce98059cf659c7cca84670435568 |
|
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand some more vector operations not supported by Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1633076c47f10a8d8735e81588e9cb07ac32efc8 |
|
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Neon does not support vector divide or remainder. Expand them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 74dc72e89bba8c67d2c9e455bad20f067b180499 |
|
16-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expand all v2f64 arithmetic operations for Neon.
Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cd3b9a4f17cf78f208765ab2ab01f2019a9e5651 |
|
10-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2ba62ef7f201b2e8f61c6988e76b40c7c8a6a191 |
|
09-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 63476a80404125e5196b6c09113c1d4796da0604 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8a3198b770c9fa7e8319a96bcbcfd85202342eef |
|
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for generating code for vst{234}lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 243fcc5a6901e75e7ca5c374e706a634593ec17f |
|
01-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generate code for vld{234}_lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3fb2b1ede30193b59a651328a946174196b20610 |
|
01-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Clean up LSDA name generation and use for SJLJ exception handling. This
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b00c03bb3548d1c2fd7ae95d6921d1aebbd5ca87 |
|
30-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
Remove the assertion and generalize the code for ARM NEON stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 71624cc7861c5ceaa72786aef2cd290bbb7fa33c |
|
29-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not assert on too wide splats we don't support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c |
|
29-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b5fb4282cd2968be81a853c0f3199d167e402bdf |
|
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hopefully the final missing part :(
scalar_to_vector is fully legal now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fdf189ac9709bd4b645f23010689fd4686c37cc8 |
|
27-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Transform float scalar_to_vector into subreg accesses.
No idea whether this is profitable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 31fb12f93a30cca700a20088e97d8b05d13d5fca |
|
26-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1cb852b0ea0a63cd9b93306e2397d97a0688192c |
|
26-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand scalar_to_vector - we don't have any isel logic for it now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ce392eb3ea16b781de89b7ff8f42c39f8b3df30e |
|
22-Aug-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c692cb77aaa8b16bcc7fe0c70d47adce94c43911 |
|
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
now using shuffles instead of intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 051cfd683f698b0061656fbff01d3971d2f3d58c |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1c8e581832440a114c9587d41473d107de4cac74 |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 62e84f177d4519bf719d188496faf8b6c247e3a7 |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e6c2b90410ae8c8f5a9a89e35de1dcc62840dbf |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Expand EXTRACT_SUBVECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5da894f5c45ad7130158e4d85fea93ae450692ba |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide vext.{16,32}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0ac234b1b3a88946ad8bb52677764f3e3eeb8b3 |
|
21-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de95c1b88be44d4af916af8fba9d7940b7e98e32 |
|
19-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| af5663405834ca7cf4a847f2efa2d624ce99b1d8 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f865ea85bd9d3e04aa795ee03cfc8db339f8c9b9 |
|
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 088880cb192fb6dd5b1bf85af62023c5ca3da38f |
|
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bc9b754091ea281e769e487f396b40f6675b9edb |
|
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turn on if-conversion for thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 72977a45a8ad9d9524c9b49399e89fb9a3a676ed |
|
14-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Allow targets to specify their choice of calling conventions per
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e6c835f42418c0fae6b63908d3c576a26d64cab2 |
|
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 lsr hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 59bc0604e5283d4f57d074a99891e6b744b4d333 |
|
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 22cac0d9b328ef89a6aafdbda9cd0cea71f8ce46 |
|
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Now that all the legal Neon shuffles (or at least the ones that have been
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c1d287b4b73487b6ab094a253a7357addc1d8b84 |
|
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0ce371082565330672c276f76297f46b362d74b7 |
|
14-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
|
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bfcbb507c232bd386b37abcbc5f478d8a9cccde9 |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a fixme message about canonicalizing floating-point vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bab812b4b0126839fe6e026aad54c90164c89765 |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert r78852 for now. I want to do this differently, but I don't have time
to fix it tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 28865062c1ef60e47f0ac23a5ebc22eaf0d1b184 |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d06791f6d0b302eeee7189ea8182565594ffdc0e |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use cast<> instead of dyn_cast<> in places where the type is known.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| af385baa1d0438104a67b63a61b264c7cde43c50 |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VDUP shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d8e1757eacbcbae6657558f40fdada4279a9d1ed |
|
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Recognize Neon VREV shuffles during legalization instead of selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bff392384ddb032c732c38ec78b91d7a25dcf467 |
|
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add catch block handling to SjLj exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 007ea274f4ab85bfc7698240eb5afd5a779ec330 |
|
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 764ab52dd80310a205c9888bf166d09dab858f90 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b0abb4dc4203b903d8d0b48a952ba0a6312eeeb7 |
|
11-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1b747ad8a0694b86e8d98a8b9a05ddfe74ec0cd3 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d6662add687f20cffa0755e410efbb40de4dcf23 |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
SimpleValueType-ify a few more methods on TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b36ec86c01e3c3238dca621648f017aef96dda60 |
|
06-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement Neon VST[234] operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 058c251d4ac23bb3f9ca66eb0e465fa2c6c66f42 |
|
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
hardfloat case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 14d9495403e4c0129119a79322ee4e744b2eced8 |
|
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 567d14f07cd62bfb9dd0edd90144a0a840450f7a |
|
05-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Missed pieces for ARM HardFP ABI.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4a3d35abefa3a1f6558ef88b25f2a320c76d5328 |
|
05-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a599bff101095e528198ae85739fe8b97ffba82b |
|
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
results to fixed registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 916afdbc2d4af2596894c4ccc179b4445fe659a7 |
|
04-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Minor cleanup. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a6d658620f1b8803825d3d3adc5d5ed9b36dc422 |
|
03-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 80ec2792b2b271eca55743a3cc4c8bca214fa705 |
|
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert ctors/dtors section to be in TLOF instead of
TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b620724e614c6594e7b269b6ea7d8483947ea944 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
|
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cf661e2c562e7b3ac35ff2aed916615356e0f2c1 |
|
30-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5657c01949dca6c012ac60d242d1a8d2ffdf5603 |
|
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e7c329bf4b48ba3a4539183dc2d0804db6f4042a |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8bb9e48752b4a88e512ceb8fb802e2cdf8150e7b |
|
26-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM Neon VREV instructions.
Patch by Anton Korzh, with some modifications from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 66ac53165e17b7c76b8c69e57bde623d44ec492e |
|
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
|
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4fb63d088bca9fc31e54eb1619e2cb448c3a4b53 |
|
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3eadf00b46fbb2aa59b8771a8d8bdf1bfd7f9141 |
|
14-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove an extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d2559bf3f30cc7400483825414489ec0fb36481a |
|
13-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
|
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 |
|
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ab7c09b6b6f4516a631fd6788918c237c83939af |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7f6aa2b162e5daaf7b9ccf05d749597d3d7cf460 |
|
08-Jul-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove the vicmp and vfcmp instructions. Because we never had a release with
these instructions, no autoupgrade or backwards compatibility support is
provided.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5b9fcd1c8e9f2b7964a82cd383441f568890b561 |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add some more Thumb2 multiplication instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d27c9fc403ae906c60ca3dfee72001f7e1930492 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 sign / zero extend with rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e88d5cee9d6b02bc786df806395a718464908064 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0412957764de44f63657360a22ce5445a8c87628 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c0309b48b560f119982c02a81416c8c1fd208648 |
|
29-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 24062ac5be1a33d1ef76d399613b7d48a684116e |
|
26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 has CLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5bafff36c798608a189c517d37527e4a38863071 |
|
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b1019480b6806c38432ad3357ae7d756573c0835 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7a42b08be8836149ea4e3f95ddcc42e198561df3 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8557c2bcb8002169d890eb8485e9a1d7219e4343 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| cd828618b8c6ec58df94aec0f5546f009f2fd0d5 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove UseThumbBacktraces. Just check if subtarget is darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 385f5a99ecc7fee48a7539bc63d3e1d3b5089c0d |
|
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Address review comments: add 3 ARM calling conventions.
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73530 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0eebf653a7b2978e7761f8d068b6fbec22aea0f6 |
|
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2f95461ee2edf896ef4a45dff40b9f20bcb31de3 |
|
22-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
for ARM. This fixes rdar://6908807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e6abdffe06d293b68c498251b5dc9f5dba78dece |
|
18-May-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f95701286664df01a5683a71c9a02c056fed0aa7 |
|
14-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Update the names of the exception handling sjlj instrinsics to
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6ebf7bc7405ee79d27d50b70f0c1a474cbea820d |
|
13-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0e0da734bbdfa1d3f55cd04db31d83b97e4556f7 |
|
13-May-2009 |
Jim Grosbach <grosbach@apple.com> |
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8091524d98ca648c195224fab599f1c6afdd880a |
|
25-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Change LowerCallResult method so that CCValAssign::BCvt can be used with
f64 types. This is not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d55bd51f311fb00c639da6161584b06cf7cb5e27 |
|
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4d59e1d666d3187aff11c9b11fe8a9eccade3f26 |
|
24-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 998e125a87d49f28c714d8223a37746850401057 |
|
20-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e3fa9ef936068ab395e9c68062cfcae2d0321208 |
|
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Move the AddLiveIn function definition closer to its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e65586b37b141cd3ef1515b840d6397ecda12396 |
|
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rearrange code to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| dee46d7f6d61ca628725b54c2d24154ebe70ed96 |
|
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Clean up formatting, remove trailing whitespace, fix comment typos and
punctuation. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1f595bb42950088ccb8246e6b065a96027b46ec6 |
|
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2c7dab18648f3d0d6e9373de31065ec3c896c224 |
|
08-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3795: Apply Dan's suggested fix for
ARMTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 30eae3c02244e18747f9f0dca6946d86d0ccb7f5 |
|
07-Apr-2009 |
Jim Grosbach <grosbach@apple.com> |
PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf6396bed0597238110aad5b680fd18a4f8769fa |
|
01-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2a14c521cab397531862415378b67fb3ac00d053 |
|
21-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix a few more indentation problems and an 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2dc4f54324a65665aed78840bc9d6d5ea5d6e7d1 |
|
20-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
No functional changes. Fix indentation and whitespace only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1606e8e4cd937e6de6681f686c266cf61722d972 |
|
13-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.
Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1980a5acd8509ea34ee2dec5e13de5dbe16af2d |
|
12-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend. These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).
Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently
with the recently added cp constant select optimization, but is a
very general xform. For example, we now compile the second example
in const-select.ll to:
_test:
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
seta %al
movzbl %al, %eax
movl 4(%esp), %ecx
movsbl (%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal 4(%eax), %ecx
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
cmovbe %eax, %ecx
movsbl (%ecx), %eax
ret
This passes multisource and dejagnu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6501153fc036741a90c616083014b0f8499678fb |
|
09-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 667d4b8de6dea70195ff12ef39a4deebffa2f5c7 |
|
07-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b67284057ee130114055309eabe0bcd1af13777d |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc versions of BuildMI from ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e8d7230f480654cdb8ff1c3d0a38e1e9ab0bd55f |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0f502f6f44f2756f5cb7b17d8f1d8eae000d51b4 |
|
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Add some DL propagation to places that didn't
have it yet. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
|
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4469c53cfc60e011d26f88594f7a690895f7f526 |
|
26-Jan-2009 |
Chris Lattner <sabre@nondot.org> |
silence a warning when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bb46f52027416598a662dc1c58f48d9d56b1a65b |
|
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 73e0914848662404cf2aa18eb049ff5aae543388 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ae94e594164b193236002516970aeec4c4574768 |
|
05-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a8103dad4e84e031c5845e18268655cc0bfbdb8d |
|
04-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r60519. It was causing a bootstrap failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eb83dfde66b4614fe48a572ea2ee1d7b91bcbc19 |
|
04-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3eb22e835f253ffd42a050caffa48eb08bdfc8d8 |
|
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c7c77297e28189c3c3bccd6e261a84970704b760 |
|
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
|
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
|
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
|
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0bb41608e94adfe9884bc188457c4f6ae47ea43c |
|
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8106b0a995512a847d3d9fb18cbb575c4d3913f2 |
|
08-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Delete an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7794f2a3a7778bdbc9bdd861db1fe914450e0470 |
|
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d1b3da621bf5134d304d02177a2c6ff912b0d18e |
|
25-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 78d60458d558877a5bf7e326511e302bcf75b8ee |
|
11-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
add support for returning i128, PR2532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
|
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 |
|
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
|
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
|
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1f13c686df75ddbbe15b208606ece4846d7479a8 |
|
28-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 29e4bdbf27c5f03b12dd2bc41d9ccb0d5f3dfdf4 |
|
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 110cf48752dcf86c6d95698c08805f1dd534ac83 |
|
01-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARM / Thumb soft FP support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 276dcbdc8db6614cfd5004dc7dc35e437ddf9c58 |
|
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b8cafe3427a168414400e5dfcbea78996792d2c3 |
|
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
|
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
|
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
|
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 00fee65fd21f9615d1a604b8b7d42cd16a3f6b47 |
|
14-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e179584f9b740cf3a36bde70f8cab40de59b8081 |
|
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f72d1a73029ed3bfb1f8ced755a1aeeb36fb4f1 |
|
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bf1caa98549317a8fe84b6f67a2209db9eeededc |
|
12-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 |
|
06-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 48a65511d0a9d01cba7e146f9aa1187000a290d3 |
|
04-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Eliminate some redundant code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 334dc1f58d617dcff969a2e107febaae42bbc883 |
|
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c6c391daddbafa722d9ca87d18f204e9a6e617a3 |
|
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
|
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b625f2f8960de32bc973092aaee8ac62863006fe |
|
30-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f9c98e650d2795b8edfae8e1560c221029df218b |
|
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f1b1c5ed1a91cf23cfa65a24caefce6235d2fed3 |
|
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
implement a trivial readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 27a6c7380fa4dfc8e1837a8dd67967d063b26544 |
|
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
|
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73 |
|
08-Nov-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
[ARM] Implement __builtin_thread_pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f1ba1cad387dc52f3c2c5afc665edf9caad00992 |
|
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e0703c84ddeb1a1276de4e38210c1127ef5df130 |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this to a common place :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc05f402ea22e8a9ae465d209b65be7e857a89ff |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4102eb57bbeecbbf5b5b5122ed1ecd4cd5487878 |
|
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 7b73a5d6dead3fa765cdde8316a19ac8930cc60d |
|
19-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 65a3323b0a1369067be131c3d3fe8442f5ac2df3 |
|
18-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f96e4de403453e57aea75bcac1ed99af686d33c4 |
|
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 525178cdbf00720ea8bce297a7d65b0cca0ab439 |
|
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
|
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
|
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
|
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a99be51bf5cdac1438069d4b01766c47704961c8 |
|
05-Jul-2007 |
Gabor Greif <ggreif@gmail.com> |
Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0e1d37904abbf7e8c4c478408253dd995f3040f4 |
|
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Reflects the chanegs made to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e2446c607611ce868857d9b853aa8703bf0da4b8 |
|
26-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 97e604e7d861cfdfba9fcf720854a3399729bef0 |
|
20-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Be more conservative of duplicating blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 277f0741c5ea123b30360c382a153df238c31cae |
|
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow predicated immediate ARM to ARM calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 144fd1ff0f1548ec9c4e835dec19ac2d5e46e902 |
|
01-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Set ARM ifcvt duplication limit to 3 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e5e7ce458a2062dd9a8b495f4d73d359e0e269de |
|
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Silence some compilation warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f8cbd147c0ae4ec2df0f3bbff65def0ffd784c1 |
|
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Set ARM if-conversion block size threshold to 10 instructions for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8dd86c14d46b2deb1e1335d495acc579d70bf60f |
|
17-May-2007 |
Dale Johannesen <dalej@apple.com> |
More effective breakdown of memcpy into repeated load/store. These are now
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5d3d44a84815b848d4493f693a0579efcc2ce42f |
|
15-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix previous patch. GOTOFF can be used only when the symbol has internal
linkage or hidden visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 930d161ba23c9bd9e7dc9586742725b08a8e622d |
|
14-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
and used in the same module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 97c9bb5cc6c2f936493ae5e8f577ecbfc1f750ce |
|
04-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e8e5495474d67cd5151bd88e502be3f46ace7a85 |
|
03-May-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Debug support for arm-linux.
Patch by Raul Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0b0a9a90a423efb91dd4efdfd866ad37aa72ee8e |
|
03-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 64f4fa5e0eb505eec3a72041bec6b3a7f7739ded |
|
27-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b1df8f2750cb8df55f7e15985ef5c86f9092cbe1 |
|
27-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin runtime library does not have these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0ae4a3357a556261f25b1584a2d9914637c69e65 |
|
22-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement PIC for arm-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5a3d40d88fbfe79ad7ed5802ff4fd1498c4c820b |
|
13-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| e11529438cd825935410750881f6dd6b04806db2 |
|
11-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| eb13d1b710c385437f30f944de44a5b7053069f3 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
restore support for negative strides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 37caf8c68e71333b6d1a663efac088439681ad45 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove dead target hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b445d0cbb9b299ba8ec7be2494e35c501b6d3a93 |
|
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 0a7baa24d17be1a3f4dc5bca53bc89a30dbc24db |
|
04-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b2c594f350c13f7faa263dfeba93d81b6ed964e9 |
|
03-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Arm supports negative strides as well, add them. This lets us compile:
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 6e0784da77672df0263b6291490c5df5dcadd56e |
|
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
to be folded into non-store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c4e3f8e736ecea7cd44a0fae75b1b3092567cbcd |
|
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add support for the 'w' inline asm register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9996663fc6d50128a4897ff3568d311496e9d944 |
|
02-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
- Divides the comparisons in two types: comparisons that only use N and Z
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 3074d9df96b1b5fa3920672ef7555d3fbbc5bb65 |
|
01-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add i16 address mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c9addb74883fef318140272768422656a694341f |
|
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| caaf69107ece8bd9864fed4d64e2a84fa5f8cd4b |
|
28-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove isLegalAddressImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4 |
|
27-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fa4bce2b76c8557cfd0794beef86efe5fb0087fa |
|
21-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 8e59e163db8cd3e7b4c96e438fbedf78bff06707 |
|
20-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
do not share old induction variables when this would result in invalid
instructions (that would have to be split later)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 64c88d741e51281edc15dcfc27dfaa500a89d43b |
|
20-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
mov lr, pc
bx lr
So, the function was not called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1719e13da087914ccad3906d5cf8a4e92ba386eb |
|
20-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5 |
|
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 368f20fda4a1cb9afdc2788a754b9ffe59afd391 |
|
16-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Only ARMv6 has BSWAP.
Fix MultiSource/Applications/aha test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 277074721680253b151efd49d0263a07fafbec3d |
|
16-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added isLegalAddressExpression(). Only allows X +/- C for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 961f879ed8642e63db712d0528680a48076fa760 |
|
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Zero is always a legal AM immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b01fad6d19ac83f9c97eee16af438507383f36d8 |
|
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b582b1b1fcbbad4295fd75f49be6dd0596df910f |
|
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| d0b82b301d700217a716526f9329bb031e0d6578 |
|
07-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1d9baccc9b4d664a944f82eef9f708125e3f1552 |
|
06-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use new SDIselParamAttr enumeration. This removes "magick" constants
from formal attributes' flags processing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 600c383e5c96d4b107b3e6ed4515eac25246cb02 |
|
23-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Fix stack alignment in functions with varargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
|
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
|
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 876eaf1135b40869f59fb27c87a7d626459e9181 |
|
13-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| fc4034259f8424364d8622f579335c421c9615bd |
|
03-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 9a2ef9509e76869c3d658fb3e321d9b9e9d479d9 |
|
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b0636156effd9a3563d905cbbfee59826c63e2a2 |
|
02-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Thumb does not have clz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 193f8508809c5eab36181f442146cb40e0182138 |
|
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Specify the right CC for comparison libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b6ab2547cb4e4c7b237d88ad11316a69b111f88e |
|
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Observe -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| c60e76d139a96cc8bb7454929172cdb992e16971 |
|
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 5cbf985dcbc89fba3208e7baf8b6f488b06d3ec9 |
|
30-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
confusion with external linkage types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
|
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
|
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 2576f136458bda873208399e4c8a5e21ee14b362 |
|
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use bl to call Thumb fuctions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| 970a419633ba41cac44ae636543f192ea632fe00 |
|
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
isDarwin -> isTargetDarwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|
| a8e2989ece6dc46df59b0768184028257f913843 |
|
19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMISelLowering.cpp
|