ARMISelLowering.cpp revision 515fe3a58877c745a922252a4492e866a2f1e42e
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/Function.h" 29#include "llvm/GlobalValue.h" 30#include "llvm/Instruction.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Type.h" 33#include "llvm/CodeGen/CallingConvLower.h" 34#include "llvm/CodeGen/MachineBasicBlock.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineFunction.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineRegisterInfo.h" 39#include "llvm/CodeGen/PseudoSourceValue.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/MC/MCSectionMachO.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/ADT/VectorExtras.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/Support/CommandLine.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/raw_ostream.h" 49#include <sstream> 50using namespace llvm; 51 52STATISTIC(NumTailCalls, "Number of tail calls"); 53 54// This option should go away when tail calls fully work. 55static cl::opt<bool> 56EnableARMTailCalls("arm-tail-calls", cl::Hidden, 57 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 58 cl::init(true)); 59 60static cl::opt<bool> 61EnableARMLongCalls("arm-long-calls", cl::Hidden, 62 cl::desc("Generate calls via indirect call instructions"), 63 cl::init(false)); 64 65static cl::opt<bool> 66ARMInterworking("arm-interworking", cl::Hidden, 67 cl::desc("Enable / disable ARM interworking (for debugging only)"), 68 cl::init(true)); 69 70static cl::opt<bool> 71EnableARMCodePlacement("arm-code-placement", cl::Hidden, 72 cl::desc("Enable code placement pass for ARM"), 73 cl::init(false)); 74 75static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 76 CCValAssign::LocInfo &LocInfo, 77 ISD::ArgFlagsTy &ArgFlags, 78 CCState &State); 79static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 80 CCValAssign::LocInfo &LocInfo, 81 ISD::ArgFlagsTy &ArgFlags, 82 CCState &State); 83static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 84 CCValAssign::LocInfo &LocInfo, 85 ISD::ArgFlagsTy &ArgFlags, 86 CCState &State); 87static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 88 CCValAssign::LocInfo &LocInfo, 89 ISD::ArgFlagsTy &ArgFlags, 90 CCState &State); 91 92void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 93 EVT PromotedBitwiseVT) { 94 if (VT != PromotedLdStVT) { 95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 97 PromotedLdStVT.getSimpleVT()); 98 99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 } 103 104 EVT ElemTy = VT.getVectorElementType(); 105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); 107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) 108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 109 if (ElemTy != MVT::i32) { 110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 114 } 115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); 119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 121 if (VT.isInteger()) { 122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 125 } 126 127 // Promote all bit-wise operations. 128 if (VT.isInteger() && VT != PromotedBitwiseVT) { 129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 130 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 131 PromotedBitwiseVT.getSimpleVT()); 132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 133 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 134 PromotedBitwiseVT.getSimpleVT()); 135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 137 PromotedBitwiseVT.getSimpleVT()); 138 } 139 140 // Neon does not support vector divide/remainder operations. 141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 147} 148 149void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 150 addRegisterClass(VT, ARM::DPRRegisterClass); 151 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 152} 153 154void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 155 addRegisterClass(VT, ARM::QPRRegisterClass); 156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 157} 158 159static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 161 return new TargetLoweringObjectFileMachO(); 162 163 return new ARMElfTargetObjectFile(); 164} 165 166ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 167 : TargetLowering(TM, createTLOF(TM)) { 168 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 169 170 if (Subtarget->isTargetDarwin()) { 171 // Uses VFP for Thumb libfuncs if available. 172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 173 // Single-precision floating-point arithmetic. 174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 178 179 // Double-precision floating-point arithmetic. 180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 184 185 // Single-precision comparisons. 186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 194 195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 203 204 // Double-precision comparisons. 205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 213 214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 222 223 // Floating-point to integer conversions. 224 // i64 conversions are done via library routines even when generating VFP 225 // instructions, so use the same ones. 226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 230 231 // Conversions between floating types. 232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 234 235 // Integer to floating-point conversions. 236 // i64 conversions are done via library routines even when generating VFP 237 // instructions, so use the same ones. 238 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 239 // e.g., __floatunsidf vs. __floatunssidfvfp. 240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 244 } 245 } 246 247 // These libcalls are not available in 32-bit. 248 setLibcallName(RTLIB::SHL_I128, 0); 249 setLibcallName(RTLIB::SRL_I128, 0); 250 setLibcallName(RTLIB::SRA_I128, 0); 251 252 // Libcalls should use the AAPCS base standard ABI, even if hard float 253 // is in effect, as per the ARM RTABI specification, section 4.1.2. 254 if (Subtarget->isAAPCS_ABI()) { 255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i), 257 CallingConv::ARM_AAPCS); 258 } 259 } 260 261 if (Subtarget->isThumb1Only()) 262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 263 else 264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 268 269 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 270 } 271 272 if (Subtarget->hasNEON()) { 273 addDRTypeForNEON(MVT::v2f32); 274 addDRTypeForNEON(MVT::v8i8); 275 addDRTypeForNEON(MVT::v4i16); 276 addDRTypeForNEON(MVT::v2i32); 277 addDRTypeForNEON(MVT::v1i64); 278 279 addQRTypeForNEON(MVT::v4f32); 280 addQRTypeForNEON(MVT::v2f64); 281 addQRTypeForNEON(MVT::v16i8); 282 addQRTypeForNEON(MVT::v8i16); 283 addQRTypeForNEON(MVT::v4i32); 284 addQRTypeForNEON(MVT::v2i64); 285 286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 287 // neither Neon nor VFP support any arithmetic operations on it. 288 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 292 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand); 295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 296 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 312 313 // Neon does not support some operations on v1i64 and v2i64 types. 314 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 315 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); 317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); 318 319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 320 setTargetDAGCombine(ISD::SHL); 321 setTargetDAGCombine(ISD::SRL); 322 setTargetDAGCombine(ISD::SRA); 323 setTargetDAGCombine(ISD::SIGN_EXTEND); 324 setTargetDAGCombine(ISD::ZERO_EXTEND); 325 setTargetDAGCombine(ISD::ANY_EXTEND); 326 setTargetDAGCombine(ISD::SELECT_CC); 327 } 328 329 computeRegisterProperties(); 330 331 // ARM does not have f32 extending load. 332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 333 334 // ARM does not have i1 sign extending load. 335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 336 337 // ARM supports all 4 flavors of integer indexed load / store. 338 if (!Subtarget->isThumb1Only()) { 339 for (unsigned im = (unsigned)ISD::PRE_INC; 340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 341 setIndexedLoadAction(im, MVT::i1, Legal); 342 setIndexedLoadAction(im, MVT::i8, Legal); 343 setIndexedLoadAction(im, MVT::i16, Legal); 344 setIndexedLoadAction(im, MVT::i32, Legal); 345 setIndexedStoreAction(im, MVT::i1, Legal); 346 setIndexedStoreAction(im, MVT::i8, Legal); 347 setIndexedStoreAction(im, MVT::i16, Legal); 348 setIndexedStoreAction(im, MVT::i32, Legal); 349 } 350 } 351 352 // i64 operation support. 353 if (Subtarget->isThumb1Only()) { 354 setOperationAction(ISD::MUL, MVT::i64, Expand); 355 setOperationAction(ISD::MULHU, MVT::i32, Expand); 356 setOperationAction(ISD::MULHS, MVT::i32, Expand); 357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 359 } else { 360 setOperationAction(ISD::MUL, MVT::i64, Expand); 361 setOperationAction(ISD::MULHU, MVT::i32, Expand); 362 if (!Subtarget->hasV6Ops()) 363 setOperationAction(ISD::MULHS, MVT::i32, Expand); 364 } 365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 368 setOperationAction(ISD::SRL, MVT::i64, Custom); 369 setOperationAction(ISD::SRA, MVT::i64, Custom); 370 371 // ARM does not have ROTL. 372 setOperationAction(ISD::ROTL, MVT::i32, Expand); 373 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 374 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 376 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 377 378 // Only ARMv6 has BSWAP. 379 if (!Subtarget->hasV6Ops()) 380 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 381 382 // These are expanded into libcalls. 383 if (!Subtarget->hasDivide()) { 384 // v7M has a hardware divider 385 setOperationAction(ISD::SDIV, MVT::i32, Expand); 386 setOperationAction(ISD::UDIV, MVT::i32, Expand); 387 } 388 setOperationAction(ISD::SREM, MVT::i32, Expand); 389 setOperationAction(ISD::UREM, MVT::i32, Expand); 390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 392 393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 398 399 setOperationAction(ISD::TRAP, MVT::Other, Legal); 400 401 // Use the default implementation. 402 setOperationAction(ISD::VASTART, MVT::Other, Custom); 403 setOperationAction(ISD::VAARG, MVT::Other, Expand); 404 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 405 setOperationAction(ISD::VAEND, MVT::Other, Expand); 406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 409 // FIXME: Shouldn't need this, since no register is used, but the legalizer 410 // doesn't yet know how to not do that for SjLj. 411 setExceptionSelectorRegister(ARM::R0); 412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise 414 // use the default expansion. 415 bool canHandleAtomics = 416 (Subtarget->hasV7Ops() || 417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())); 418 if (canHandleAtomics) { 419 // membarrier needs custom lowering; the rest are legal and handled 420 // normally. 421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 422 } else { 423 // Set them all for expansion, which will force libcalls. 424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand); 426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand); 427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand); 429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand); 430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand); 432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand); 433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand); 435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand); 436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand); 438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand); 439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand); 441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand); 442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand); 444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand); 445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand); 447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand); 448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 449 // Since the libcalls include locking, fold in the fences 450 setShouldFoldAtomicFences(true); 451 } 452 // 64-bit versions are always libcalls (for now) 453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand); 454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand); 455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand); 456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand); 457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand); 458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand); 459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); 460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); 461 462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 463 if (!Subtarget->hasV6Ops()) { 464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 466 } 467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 468 469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) 470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 471 // iff target supports vfp2. 472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 473 474 // We want to custom lower some of our intrinsics. 475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 476 if (Subtarget->isTargetDarwin()) { 477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 479 } 480 481 setOperationAction(ISD::SETCC, MVT::i32, Expand); 482 setOperationAction(ISD::SETCC, MVT::f32, Expand); 483 setOperationAction(ISD::SETCC, MVT::f64, Expand); 484 setOperationAction(ISD::SELECT, MVT::i32, Expand); 485 setOperationAction(ISD::SELECT, MVT::f32, Expand); 486 setOperationAction(ISD::SELECT, MVT::f64, Expand); 487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 490 491 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 492 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 493 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 494 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 495 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 496 497 // We don't support sin/cos/fmod/copysign/pow 498 setOperationAction(ISD::FSIN, MVT::f64, Expand); 499 setOperationAction(ISD::FSIN, MVT::f32, Expand); 500 setOperationAction(ISD::FCOS, MVT::f32, Expand); 501 setOperationAction(ISD::FCOS, MVT::f64, Expand); 502 setOperationAction(ISD::FREM, MVT::f64, Expand); 503 setOperationAction(ISD::FREM, MVT::f32, Expand); 504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 507 } 508 setOperationAction(ISD::FPOW, MVT::f64, Expand); 509 setOperationAction(ISD::FPOW, MVT::f32, Expand); 510 511 // Various VFP goodness 512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 513 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 514 if (Subtarget->hasVFP2()) { 515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 519 } 520 // Special handling for half-precision FP. 521 if (!Subtarget->hasFP16()) { 522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 524 } 525 } 526 527 // We have target-specific dag combine patterns for the following nodes: 528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 529 setTargetDAGCombine(ISD::ADD); 530 setTargetDAGCombine(ISD::SUB); 531 setTargetDAGCombine(ISD::MUL); 532 533 setStackPointerRegisterToSaveRestore(ARM::SP); 534 535 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 536 setSchedulingPreference(Sched::RegPressure); 537 else 538 setSchedulingPreference(Sched::Hybrid); 539 540 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 541 542 if (EnableARMCodePlacement) 543 benefitFromCodePlacementOpt = true; 544} 545 546const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 547 switch (Opcode) { 548 default: return 0; 549 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 550 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 551 case ARMISD::CALL: return "ARMISD::CALL"; 552 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 553 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 554 case ARMISD::tCALL: return "ARMISD::tCALL"; 555 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 556 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 557 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 558 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 559 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 560 case ARMISD::CMP: return "ARMISD::CMP"; 561 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 562 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 563 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 564 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 565 case ARMISD::CMOV: return "ARMISD::CMOV"; 566 case ARMISD::CNEG: return "ARMISD::CNEG"; 567 568 case ARMISD::RBIT: return "ARMISD::RBIT"; 569 570 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 571 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 572 case ARMISD::SITOF: return "ARMISD::SITOF"; 573 case ARMISD::UITOF: return "ARMISD::UITOF"; 574 575 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 576 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 577 case ARMISD::RRX: return "ARMISD::RRX"; 578 579 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 580 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 581 582 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 583 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 584 585 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 586 587 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 588 589 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 590 591 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 592 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER"; 593 594 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 595 case ARMISD::VCGE: return "ARMISD::VCGE"; 596 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 597 case ARMISD::VCGT: return "ARMISD::VCGT"; 598 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 599 case ARMISD::VTST: return "ARMISD::VTST"; 600 601 case ARMISD::VSHL: return "ARMISD::VSHL"; 602 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 603 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 604 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 605 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 606 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 607 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 608 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 609 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 610 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 611 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 612 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 613 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 614 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 615 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 616 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 617 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 618 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 619 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 620 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 621 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 622 case ARMISD::VDUP: return "ARMISD::VDUP"; 623 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 624 case ARMISD::VEXT: return "ARMISD::VEXT"; 625 case ARMISD::VREV64: return "ARMISD::VREV64"; 626 case ARMISD::VREV32: return "ARMISD::VREV32"; 627 case ARMISD::VREV16: return "ARMISD::VREV16"; 628 case ARMISD::VZIP: return "ARMISD::VZIP"; 629 case ARMISD::VUZP: return "ARMISD::VUZP"; 630 case ARMISD::VTRN: return "ARMISD::VTRN"; 631 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 632 case ARMISD::FMAX: return "ARMISD::FMAX"; 633 case ARMISD::FMIN: return "ARMISD::FMIN"; 634 } 635} 636 637/// getRegClassFor - Return the register class that should be used for the 638/// specified value type. 639TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 640 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 641 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 642 // load / store 4 to 8 consecutive D registers. 643 if (Subtarget->hasNEON()) { 644 if (VT == MVT::v4i64) 645 return ARM::QQPRRegisterClass; 646 else if (VT == MVT::v8i64) 647 return ARM::QQQQPRRegisterClass; 648 } 649 return TargetLowering::getRegClassFor(VT); 650} 651 652/// getFunctionAlignment - Return the Log2 alignment of this function. 653unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { 654 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2; 655} 656 657Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 658 unsigned NumVals = N->getNumValues(); 659 if (!NumVals) 660 return Sched::RegPressure; 661 662 for (unsigned i = 0; i != NumVals; ++i) { 663 EVT VT = N->getValueType(i); 664 if (VT.isFloatingPoint() || VT.isVector()) 665 return Sched::Latency; 666 } 667 668 if (!N->isMachineOpcode()) 669 return Sched::RegPressure; 670 671 // Load are scheduled for latency even if there instruction itinerary 672 // is not available. 673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 674 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 675 if (TID.mayLoad()) 676 return Sched::Latency; 677 678 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData(); 679 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2) 680 return Sched::Latency; 681 return Sched::RegPressure; 682} 683 684//===----------------------------------------------------------------------===// 685// Lowering Code 686//===----------------------------------------------------------------------===// 687 688/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 689static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 690 switch (CC) { 691 default: llvm_unreachable("Unknown condition code!"); 692 case ISD::SETNE: return ARMCC::NE; 693 case ISD::SETEQ: return ARMCC::EQ; 694 case ISD::SETGT: return ARMCC::GT; 695 case ISD::SETGE: return ARMCC::GE; 696 case ISD::SETLT: return ARMCC::LT; 697 case ISD::SETLE: return ARMCC::LE; 698 case ISD::SETUGT: return ARMCC::HI; 699 case ISD::SETUGE: return ARMCC::HS; 700 case ISD::SETULT: return ARMCC::LO; 701 case ISD::SETULE: return ARMCC::LS; 702 } 703} 704 705/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 706static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 707 ARMCC::CondCodes &CondCode2) { 708 CondCode2 = ARMCC::AL; 709 switch (CC) { 710 default: llvm_unreachable("Unknown FP condition!"); 711 case ISD::SETEQ: 712 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 713 case ISD::SETGT: 714 case ISD::SETOGT: CondCode = ARMCC::GT; break; 715 case ISD::SETGE: 716 case ISD::SETOGE: CondCode = ARMCC::GE; break; 717 case ISD::SETOLT: CondCode = ARMCC::MI; break; 718 case ISD::SETOLE: CondCode = ARMCC::LS; break; 719 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 720 case ISD::SETO: CondCode = ARMCC::VC; break; 721 case ISD::SETUO: CondCode = ARMCC::VS; break; 722 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 723 case ISD::SETUGT: CondCode = ARMCC::HI; break; 724 case ISD::SETUGE: CondCode = ARMCC::PL; break; 725 case ISD::SETLT: 726 case ISD::SETULT: CondCode = ARMCC::LT; break; 727 case ISD::SETLE: 728 case ISD::SETULE: CondCode = ARMCC::LE; break; 729 case ISD::SETNE: 730 case ISD::SETUNE: CondCode = ARMCC::NE; break; 731 } 732} 733 734//===----------------------------------------------------------------------===// 735// Calling Convention Implementation 736//===----------------------------------------------------------------------===// 737 738#include "ARMGenCallingConv.inc" 739 740// APCS f64 is in register pairs, possibly split to stack 741static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 742 CCValAssign::LocInfo &LocInfo, 743 CCState &State, bool CanFail) { 744 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 745 746 // Try to get the first register. 747 if (unsigned Reg = State.AllocateReg(RegList, 4)) 748 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 749 else { 750 // For the 2nd half of a v2f64, do not fail. 751 if (CanFail) 752 return false; 753 754 // Put the whole thing on the stack. 755 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 756 State.AllocateStack(8, 4), 757 LocVT, LocInfo)); 758 return true; 759 } 760 761 // Try to get the second register. 762 if (unsigned Reg = State.AllocateReg(RegList, 4)) 763 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 764 else 765 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 766 State.AllocateStack(4, 4), 767 LocVT, LocInfo)); 768 return true; 769} 770 771static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 772 CCValAssign::LocInfo &LocInfo, 773 ISD::ArgFlagsTy &ArgFlags, 774 CCState &State) { 775 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 776 return false; 777 if (LocVT == MVT::v2f64 && 778 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 779 return false; 780 return true; // we handled it 781} 782 783// AAPCS f64 is in aligned register pairs 784static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 785 CCValAssign::LocInfo &LocInfo, 786 CCState &State, bool CanFail) { 787 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 788 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 789 790 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 791 if (Reg == 0) { 792 // For the 2nd half of a v2f64, do not just fail. 793 if (CanFail) 794 return false; 795 796 // Put the whole thing on the stack. 797 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 798 State.AllocateStack(8, 8), 799 LocVT, LocInfo)); 800 return true; 801 } 802 803 unsigned i; 804 for (i = 0; i < 2; ++i) 805 if (HiRegList[i] == Reg) 806 break; 807 808 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 809 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 810 LocVT, LocInfo)); 811 return true; 812} 813 814static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 815 CCValAssign::LocInfo &LocInfo, 816 ISD::ArgFlagsTy &ArgFlags, 817 CCState &State) { 818 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 819 return false; 820 if (LocVT == MVT::v2f64 && 821 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 822 return false; 823 return true; // we handled it 824} 825 826static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 827 CCValAssign::LocInfo &LocInfo, CCState &State) { 828 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 829 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 830 831 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 832 if (Reg == 0) 833 return false; // we didn't handle it 834 835 unsigned i; 836 for (i = 0; i < 2; ++i) 837 if (HiRegList[i] == Reg) 838 break; 839 840 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 841 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 842 LocVT, LocInfo)); 843 return true; 844} 845 846static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 847 CCValAssign::LocInfo &LocInfo, 848 ISD::ArgFlagsTy &ArgFlags, 849 CCState &State) { 850 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 851 return false; 852 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 853 return false; 854 return true; // we handled it 855} 856 857static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 858 CCValAssign::LocInfo &LocInfo, 859 ISD::ArgFlagsTy &ArgFlags, 860 CCState &State) { 861 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, 862 State); 863} 864 865/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 866/// given CallingConvention value. 867CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 868 bool Return, 869 bool isVarArg) const { 870 switch (CC) { 871 default: 872 llvm_unreachable("Unsupported calling convention"); 873 case CallingConv::C: 874 case CallingConv::Fast: 875 // Use target triple & subtarget features to do actual dispatch. 876 if (Subtarget->isAAPCS_ABI()) { 877 if (Subtarget->hasVFP2() && 878 FloatABIType == FloatABI::Hard && !isVarArg) 879 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 880 else 881 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 882 } else 883 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 884 case CallingConv::ARM_AAPCS_VFP: 885 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 886 case CallingConv::ARM_AAPCS: 887 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 888 case CallingConv::ARM_APCS: 889 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 890 } 891} 892 893/// LowerCallResult - Lower the result values of a call into the 894/// appropriate copies out of appropriate physical registers. 895SDValue 896ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 897 CallingConv::ID CallConv, bool isVarArg, 898 const SmallVectorImpl<ISD::InputArg> &Ins, 899 DebugLoc dl, SelectionDAG &DAG, 900 SmallVectorImpl<SDValue> &InVals) const { 901 902 // Assign locations to each value returned by this call. 903 SmallVector<CCValAssign, 16> RVLocs; 904 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 905 RVLocs, *DAG.getContext()); 906 CCInfo.AnalyzeCallResult(Ins, 907 CCAssignFnForNode(CallConv, /* Return*/ true, 908 isVarArg)); 909 910 // Copy all of the result registers out of their specified physreg. 911 for (unsigned i = 0; i != RVLocs.size(); ++i) { 912 CCValAssign VA = RVLocs[i]; 913 914 SDValue Val; 915 if (VA.needsCustom()) { 916 // Handle f64 or half of a v2f64. 917 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 918 InFlag); 919 Chain = Lo.getValue(1); 920 InFlag = Lo.getValue(2); 921 VA = RVLocs[++i]; // skip ahead to next loc 922 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 923 InFlag); 924 Chain = Hi.getValue(1); 925 InFlag = Hi.getValue(2); 926 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 927 928 if (VA.getLocVT() == MVT::v2f64) { 929 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 930 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 931 DAG.getConstant(0, MVT::i32)); 932 933 VA = RVLocs[++i]; // skip ahead to next loc 934 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 935 Chain = Lo.getValue(1); 936 InFlag = Lo.getValue(2); 937 VA = RVLocs[++i]; // skip ahead to next loc 938 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 939 Chain = Hi.getValue(1); 940 InFlag = Hi.getValue(2); 941 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 942 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 943 DAG.getConstant(1, MVT::i32)); 944 } 945 } else { 946 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 947 InFlag); 948 Chain = Val.getValue(1); 949 InFlag = Val.getValue(2); 950 } 951 952 switch (VA.getLocInfo()) { 953 default: llvm_unreachable("Unknown loc info!"); 954 case CCValAssign::Full: break; 955 case CCValAssign::BCvt: 956 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); 957 break; 958 } 959 960 InVals.push_back(Val); 961 } 962 963 return Chain; 964} 965 966/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 967/// by "Src" to address "Dst" of size "Size". Alignment information is 968/// specified by the specific parameter attribute. The copy will be passed as 969/// a byval function parameter. 970/// Sometimes what we are copying is the end of a larger object, the part that 971/// does not fit in registers. 972static SDValue 973CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 974 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 975 DebugLoc dl) { 976 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 977 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 978 /*isVolatile=*/false, /*AlwaysInline=*/false, 979 NULL, 0, NULL, 0); 980} 981 982/// LowerMemOpCallTo - Store the argument to the stack. 983SDValue 984ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 985 SDValue StackPtr, SDValue Arg, 986 DebugLoc dl, SelectionDAG &DAG, 987 const CCValAssign &VA, 988 ISD::ArgFlagsTy Flags) const { 989 unsigned LocMemOffset = VA.getLocMemOffset(); 990 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 991 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 992 if (Flags.isByVal()) { 993 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 994 } 995 return DAG.getStore(Chain, dl, Arg, PtrOff, 996 PseudoSourceValue::getStack(), LocMemOffset, 997 false, false, 0); 998} 999 1000void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1001 SDValue Chain, SDValue &Arg, 1002 RegsToPassVector &RegsToPass, 1003 CCValAssign &VA, CCValAssign &NextVA, 1004 SDValue &StackPtr, 1005 SmallVector<SDValue, 8> &MemOpChains, 1006 ISD::ArgFlagsTy Flags) const { 1007 1008 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1009 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1010 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1011 1012 if (NextVA.isRegLoc()) 1013 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1014 else { 1015 assert(NextVA.isMemLoc()); 1016 if (StackPtr.getNode() == 0) 1017 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1018 1019 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1020 dl, DAG, NextVA, 1021 Flags)); 1022 } 1023} 1024 1025/// LowerCall - Lowering a call into a callseq_start <- 1026/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1027/// nodes. 1028SDValue 1029ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1030 CallingConv::ID CallConv, bool isVarArg, 1031 bool &isTailCall, 1032 const SmallVectorImpl<ISD::OutputArg> &Outs, 1033 const SmallVectorImpl<SDValue> &OutVals, 1034 const SmallVectorImpl<ISD::InputArg> &Ins, 1035 DebugLoc dl, SelectionDAG &DAG, 1036 SmallVectorImpl<SDValue> &InVals) const { 1037 MachineFunction &MF = DAG.getMachineFunction(); 1038 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1039 bool IsSibCall = false; 1040 // Temporarily disable tail calls so things don't break. 1041 if (!EnableARMTailCalls) 1042 isTailCall = false; 1043 if (isTailCall) { 1044 // Check if it's really possible to do a tail call. 1045 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1046 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1047 Outs, OutVals, Ins, DAG); 1048 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1049 // detected sibcalls. 1050 if (isTailCall) { 1051 ++NumTailCalls; 1052 IsSibCall = true; 1053 } 1054 } 1055 1056 // Analyze operands of the call, assigning locations to each operand. 1057 SmallVector<CCValAssign, 16> ArgLocs; 1058 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1059 *DAG.getContext()); 1060 CCInfo.AnalyzeCallOperands(Outs, 1061 CCAssignFnForNode(CallConv, /* Return*/ false, 1062 isVarArg)); 1063 1064 // Get a count of how many bytes are to be pushed on the stack. 1065 unsigned NumBytes = CCInfo.getNextStackOffset(); 1066 1067 // For tail calls, memory operands are available in our caller's stack. 1068 if (IsSibCall) 1069 NumBytes = 0; 1070 1071 // Adjust the stack pointer for the new arguments... 1072 // These operations are automatically eliminated by the prolog/epilog pass 1073 if (!IsSibCall) 1074 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1075 1076 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1077 1078 RegsToPassVector RegsToPass; 1079 SmallVector<SDValue, 8> MemOpChains; 1080 1081 // Walk the register/memloc assignments, inserting copies/loads. In the case 1082 // of tail call optimization, arguments are handled later. 1083 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1084 i != e; 1085 ++i, ++realArgIdx) { 1086 CCValAssign &VA = ArgLocs[i]; 1087 SDValue Arg = OutVals[realArgIdx]; 1088 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1089 1090 // Promote the value if needed. 1091 switch (VA.getLocInfo()) { 1092 default: llvm_unreachable("Unknown loc info!"); 1093 case CCValAssign::Full: break; 1094 case CCValAssign::SExt: 1095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1096 break; 1097 case CCValAssign::ZExt: 1098 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1099 break; 1100 case CCValAssign::AExt: 1101 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1102 break; 1103 case CCValAssign::BCvt: 1104 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1105 break; 1106 } 1107 1108 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1109 if (VA.needsCustom()) { 1110 if (VA.getLocVT() == MVT::v2f64) { 1111 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1112 DAG.getConstant(0, MVT::i32)); 1113 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1114 DAG.getConstant(1, MVT::i32)); 1115 1116 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1117 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1118 1119 VA = ArgLocs[++i]; // skip ahead to next loc 1120 if (VA.isRegLoc()) { 1121 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1122 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1123 } else { 1124 assert(VA.isMemLoc()); 1125 1126 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1127 dl, DAG, VA, Flags)); 1128 } 1129 } else { 1130 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1131 StackPtr, MemOpChains, Flags); 1132 } 1133 } else if (VA.isRegLoc()) { 1134 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1135 } else if (!IsSibCall) { 1136 assert(VA.isMemLoc()); 1137 1138 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1139 dl, DAG, VA, Flags)); 1140 } 1141 } 1142 1143 if (!MemOpChains.empty()) 1144 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1145 &MemOpChains[0], MemOpChains.size()); 1146 1147 // Build a sequence of copy-to-reg nodes chained together with token chain 1148 // and flag operands which copy the outgoing args into the appropriate regs. 1149 SDValue InFlag; 1150 // Tail call byval lowering might overwrite argument registers so in case of 1151 // tail call optimization the copies to registers are lowered later. 1152 if (!isTailCall) 1153 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1154 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1155 RegsToPass[i].second, InFlag); 1156 InFlag = Chain.getValue(1); 1157 } 1158 1159 // For tail calls lower the arguments to the 'real' stack slot. 1160 if (isTailCall) { 1161 // Force all the incoming stack arguments to be loaded from the stack 1162 // before any new outgoing arguments are stored to the stack, because the 1163 // outgoing stack slots may alias the incoming argument stack slots, and 1164 // the alias isn't otherwise explicit. This is slightly more conservative 1165 // than necessary, because it means that each store effectively depends 1166 // on every argument instead of just those arguments it would clobber. 1167 1168 // Do not flag preceeding copytoreg stuff together with the following stuff. 1169 InFlag = SDValue(); 1170 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1171 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1172 RegsToPass[i].second, InFlag); 1173 InFlag = Chain.getValue(1); 1174 } 1175 InFlag =SDValue(); 1176 } 1177 1178 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1179 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1180 // node so that legalize doesn't hack it. 1181 bool isDirect = false; 1182 bool isARMFunc = false; 1183 bool isLocalARMFunc = false; 1184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1185 1186 if (EnableARMLongCalls) { 1187 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1188 && "long-calls with non-static relocation model!"); 1189 // Handle a global address or an external symbol. If it's not one of 1190 // those, the target's already in a register, so we don't need to do 1191 // anything extra. 1192 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1193 const GlobalValue *GV = G->getGlobal(); 1194 // Create a constant pool entry for the callee address 1195 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1196 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1197 ARMPCLabelIndex, 1198 ARMCP::CPValue, 0); 1199 // Get the address of the callee into a register 1200 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1201 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1202 Callee = DAG.getLoad(getPointerTy(), dl, 1203 DAG.getEntryNode(), CPAddr, 1204 PseudoSourceValue::getConstantPool(), 0, 1205 false, false, 0); 1206 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1207 const char *Sym = S->getSymbol(); 1208 1209 // Create a constant pool entry for the callee address 1210 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1211 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1212 Sym, ARMPCLabelIndex, 0); 1213 // Get the address of the callee into a register 1214 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1215 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1216 Callee = DAG.getLoad(getPointerTy(), dl, 1217 DAG.getEntryNode(), CPAddr, 1218 PseudoSourceValue::getConstantPool(), 0, 1219 false, false, 0); 1220 } 1221 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1222 const GlobalValue *GV = G->getGlobal(); 1223 isDirect = true; 1224 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1225 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1226 getTargetMachine().getRelocationModel() != Reloc::Static; 1227 isARMFunc = !Subtarget->isThumb() || isStub; 1228 // ARM call to a local ARM function is predicable. 1229 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1230 // tBX takes a register source operand. 1231 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1232 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1233 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1234 ARMPCLabelIndex, 1235 ARMCP::CPValue, 4); 1236 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1237 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1238 Callee = DAG.getLoad(getPointerTy(), dl, 1239 DAG.getEntryNode(), CPAddr, 1240 PseudoSourceValue::getConstantPool(), 0, 1241 false, false, 0); 1242 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1243 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1244 getPointerTy(), Callee, PICLabel); 1245 } else 1246 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 1247 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1248 isDirect = true; 1249 bool isStub = Subtarget->isTargetDarwin() && 1250 getTargetMachine().getRelocationModel() != Reloc::Static; 1251 isARMFunc = !Subtarget->isThumb() || isStub; 1252 // tBX takes a register source operand. 1253 const char *Sym = S->getSymbol(); 1254 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1255 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1256 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1257 Sym, ARMPCLabelIndex, 4); 1258 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1259 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1260 Callee = DAG.getLoad(getPointerTy(), dl, 1261 DAG.getEntryNode(), CPAddr, 1262 PseudoSourceValue::getConstantPool(), 0, 1263 false, false, 0); 1264 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1265 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1266 getPointerTy(), Callee, PICLabel); 1267 } else 1268 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 1269 } 1270 1271 // FIXME: handle tail calls differently. 1272 unsigned CallOpc; 1273 if (Subtarget->isThumb()) { 1274 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1275 CallOpc = ARMISD::CALL_NOLINK; 1276 else 1277 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1278 } else { 1279 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1280 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1281 : ARMISD::CALL_NOLINK; 1282 } 1283 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) { 1284 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 1285 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); 1286 InFlag = Chain.getValue(1); 1287 } 1288 1289 std::vector<SDValue> Ops; 1290 Ops.push_back(Chain); 1291 Ops.push_back(Callee); 1292 1293 // Add argument registers to the end of the list so that they are known live 1294 // into the call. 1295 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1296 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1297 RegsToPass[i].second.getValueType())); 1298 1299 if (InFlag.getNode()) 1300 Ops.push_back(InFlag); 1301 1302 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1303 if (isTailCall) 1304 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1305 1306 // Returns a chain and a flag for retval copy to use. 1307 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1308 InFlag = Chain.getValue(1); 1309 1310 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1311 DAG.getIntPtrConstant(0, true), InFlag); 1312 if (!Ins.empty()) 1313 InFlag = Chain.getValue(1); 1314 1315 // Handle result values, copying them out of physregs into vregs that we 1316 // return. 1317 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1318 dl, DAG, InVals); 1319} 1320 1321/// MatchingStackOffset - Return true if the given stack call argument is 1322/// already available in the same position (relatively) of the caller's 1323/// incoming argument stack. 1324static 1325bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1326 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1327 const ARMInstrInfo *TII) { 1328 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1329 int FI = INT_MAX; 1330 if (Arg.getOpcode() == ISD::CopyFromReg) { 1331 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1332 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 1333 return false; 1334 MachineInstr *Def = MRI->getVRegDef(VR); 1335 if (!Def) 1336 return false; 1337 if (!Flags.isByVal()) { 1338 if (!TII->isLoadFromStackSlot(Def, FI)) 1339 return false; 1340 } else { 1341 return false; 1342 } 1343 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1344 if (Flags.isByVal()) 1345 // ByVal argument is passed in as a pointer but it's now being 1346 // dereferenced. e.g. 1347 // define @foo(%struct.X* %A) { 1348 // tail call @bar(%struct.X* byval %A) 1349 // } 1350 return false; 1351 SDValue Ptr = Ld->getBasePtr(); 1352 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1353 if (!FINode) 1354 return false; 1355 FI = FINode->getIndex(); 1356 } else 1357 return false; 1358 1359 assert(FI != INT_MAX); 1360 if (!MFI->isFixedObjectIndex(FI)) 1361 return false; 1362 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1363} 1364 1365/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1366/// for tail call optimization. Targets which want to do tail call 1367/// optimization should implement this function. 1368bool 1369ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1370 CallingConv::ID CalleeCC, 1371 bool isVarArg, 1372 bool isCalleeStructRet, 1373 bool isCallerStructRet, 1374 const SmallVectorImpl<ISD::OutputArg> &Outs, 1375 const SmallVectorImpl<SDValue> &OutVals, 1376 const SmallVectorImpl<ISD::InputArg> &Ins, 1377 SelectionDAG& DAG) const { 1378 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1379 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1380 bool CCMatch = CallerCC == CalleeCC; 1381 1382 // Look for obvious safe cases to perform tail call optimization that do not 1383 // require ABI changes. This is what gcc calls sibcall. 1384 1385 // Do not sibcall optimize vararg calls unless the call site is not passing 1386 // any arguments. 1387 if (isVarArg && !Outs.empty()) 1388 return false; 1389 1390 // Also avoid sibcall optimization if either caller or callee uses struct 1391 // return semantics. 1392 if (isCalleeStructRet || isCallerStructRet) 1393 return false; 1394 1395 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1396 // emitEpilogue is not ready for them. 1397 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1398 // LR. This means if we need to reload LR, it takes an extra instructions, 1399 // which outweighs the value of the tail call; but here we don't know yet 1400 // whether LR is going to be used. Probably the right approach is to 1401 // generate the tail call here and turn it back into CALL/RET in 1402 // emitEpilogue if LR is used. 1403 if (Subtarget->isThumb1Only()) 1404 return false; 1405 1406 // For the moment, we can only do this to functions defined in this 1407 // compilation, or to indirect calls. A Thumb B to an ARM function, 1408 // or vice versa, is not easily fixed up in the linker unlike BL. 1409 // (We could do this by loading the address of the callee into a register; 1410 // that is an extra instruction over the direct call and burns a register 1411 // as well, so is not likely to be a win.) 1412 1413 // It might be safe to remove this restriction on non-Darwin. 1414 1415 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1416 // but we need to make sure there are enough registers; the only valid 1417 // registers are the 4 used for parameters. We don't currently do this 1418 // case. 1419 if (isa<ExternalSymbolSDNode>(Callee)) 1420 return false; 1421 1422 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1423 const GlobalValue *GV = G->getGlobal(); 1424 if (GV->isDeclaration() || GV->isWeakForLinker()) 1425 return false; 1426 } 1427 1428 // If the calling conventions do not match, then we'd better make sure the 1429 // results are returned in the same way as what the caller expects. 1430 if (!CCMatch) { 1431 SmallVector<CCValAssign, 16> RVLocs1; 1432 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 1433 RVLocs1, *DAG.getContext()); 1434 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1435 1436 SmallVector<CCValAssign, 16> RVLocs2; 1437 CCState CCInfo2(CallerCC, false, getTargetMachine(), 1438 RVLocs2, *DAG.getContext()); 1439 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1440 1441 if (RVLocs1.size() != RVLocs2.size()) 1442 return false; 1443 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1444 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1445 return false; 1446 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1447 return false; 1448 if (RVLocs1[i].isRegLoc()) { 1449 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1450 return false; 1451 } else { 1452 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1453 return false; 1454 } 1455 } 1456 } 1457 1458 // If the callee takes no arguments then go on to check the results of the 1459 // call. 1460 if (!Outs.empty()) { 1461 // Check if stack adjustment is needed. For now, do not do this if any 1462 // argument is passed on the stack. 1463 SmallVector<CCValAssign, 16> ArgLocs; 1464 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 1465 ArgLocs, *DAG.getContext()); 1466 CCInfo.AnalyzeCallOperands(Outs, 1467 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1468 if (CCInfo.getNextStackOffset()) { 1469 MachineFunction &MF = DAG.getMachineFunction(); 1470 1471 // Check if the arguments are already laid out in the right way as 1472 // the caller's fixed stack objects. 1473 MachineFrameInfo *MFI = MF.getFrameInfo(); 1474 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1475 const ARMInstrInfo *TII = 1476 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1477 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1478 i != e; 1479 ++i, ++realArgIdx) { 1480 CCValAssign &VA = ArgLocs[i]; 1481 EVT RegVT = VA.getLocVT(); 1482 SDValue Arg = OutVals[realArgIdx]; 1483 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1484 if (VA.getLocInfo() == CCValAssign::Indirect) 1485 return false; 1486 if (VA.needsCustom()) { 1487 // f64 and vector types are split into multiple registers or 1488 // register/stack-slot combinations. The types will not match 1489 // the registers; give up on memory f64 refs until we figure 1490 // out what to do about this. 1491 if (!VA.isRegLoc()) 1492 return false; 1493 if (!ArgLocs[++i].isRegLoc()) 1494 return false; 1495 if (RegVT == MVT::v2f64) { 1496 if (!ArgLocs[++i].isRegLoc()) 1497 return false; 1498 if (!ArgLocs[++i].isRegLoc()) 1499 return false; 1500 } 1501 } else if (!VA.isRegLoc()) { 1502 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1503 MFI, MRI, TII)) 1504 return false; 1505 } 1506 } 1507 } 1508 } 1509 1510 return true; 1511} 1512 1513SDValue 1514ARMTargetLowering::LowerReturn(SDValue Chain, 1515 CallingConv::ID CallConv, bool isVarArg, 1516 const SmallVectorImpl<ISD::OutputArg> &Outs, 1517 const SmallVectorImpl<SDValue> &OutVals, 1518 DebugLoc dl, SelectionDAG &DAG) const { 1519 1520 // CCValAssign - represent the assignment of the return value to a location. 1521 SmallVector<CCValAssign, 16> RVLocs; 1522 1523 // CCState - Info about the registers and stack slots. 1524 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 1525 *DAG.getContext()); 1526 1527 // Analyze outgoing return values. 1528 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1529 isVarArg)); 1530 1531 // If this is the first return lowered for this function, add 1532 // the regs to the liveout set for the function. 1533 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1534 for (unsigned i = 0; i != RVLocs.size(); ++i) 1535 if (RVLocs[i].isRegLoc()) 1536 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1537 } 1538 1539 SDValue Flag; 1540 1541 // Copy the result values into the output registers. 1542 for (unsigned i = 0, realRVLocIdx = 0; 1543 i != RVLocs.size(); 1544 ++i, ++realRVLocIdx) { 1545 CCValAssign &VA = RVLocs[i]; 1546 assert(VA.isRegLoc() && "Can only return in registers!"); 1547 1548 SDValue Arg = OutVals[realRVLocIdx]; 1549 1550 switch (VA.getLocInfo()) { 1551 default: llvm_unreachable("Unknown loc info!"); 1552 case CCValAssign::Full: break; 1553 case CCValAssign::BCvt: 1554 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1555 break; 1556 } 1557 1558 if (VA.needsCustom()) { 1559 if (VA.getLocVT() == MVT::v2f64) { 1560 // Extract the first half and return it in two registers. 1561 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1562 DAG.getConstant(0, MVT::i32)); 1563 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1564 DAG.getVTList(MVT::i32, MVT::i32), Half); 1565 1566 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1567 Flag = Chain.getValue(1); 1568 VA = RVLocs[++i]; // skip ahead to next loc 1569 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1570 HalfGPRs.getValue(1), Flag); 1571 Flag = Chain.getValue(1); 1572 VA = RVLocs[++i]; // skip ahead to next loc 1573 1574 // Extract the 2nd half and fall through to handle it as an f64 value. 1575 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1576 DAG.getConstant(1, MVT::i32)); 1577 } 1578 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1579 // available. 1580 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1581 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1582 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1583 Flag = Chain.getValue(1); 1584 VA = RVLocs[++i]; // skip ahead to next loc 1585 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1586 Flag); 1587 } else 1588 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1589 1590 // Guarantee that all emitted copies are 1591 // stuck together, avoiding something bad. 1592 Flag = Chain.getValue(1); 1593 } 1594 1595 SDValue result; 1596 if (Flag.getNode()) 1597 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1598 else // Return Void 1599 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1600 1601 return result; 1602} 1603 1604// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1605// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1606// one of the above mentioned nodes. It has to be wrapped because otherwise 1607// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1608// be used to form addressing mode. These wrapped nodes will be selected 1609// into MOVi. 1610static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1611 EVT PtrVT = Op.getValueType(); 1612 // FIXME there is no actual debug info here 1613 DebugLoc dl = Op.getDebugLoc(); 1614 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1615 SDValue Res; 1616 if (CP->isMachineConstantPoolEntry()) 1617 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1618 CP->getAlignment()); 1619 else 1620 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1621 CP->getAlignment()); 1622 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1623} 1624 1625SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1626 SelectionDAG &DAG) const { 1627 MachineFunction &MF = DAG.getMachineFunction(); 1628 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1629 unsigned ARMPCLabelIndex = 0; 1630 DebugLoc DL = Op.getDebugLoc(); 1631 EVT PtrVT = getPointerTy(); 1632 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1633 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1634 SDValue CPAddr; 1635 if (RelocM == Reloc::Static) { 1636 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1637 } else { 1638 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1639 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1640 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex, 1641 ARMCP::CPBlockAddress, 1642 PCAdj); 1643 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1644 } 1645 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1646 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1647 PseudoSourceValue::getConstantPool(), 0, 1648 false, false, 0); 1649 if (RelocM == Reloc::Static) 1650 return Result; 1651 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1652 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1653} 1654 1655// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1656SDValue 1657ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1658 SelectionDAG &DAG) const { 1659 DebugLoc dl = GA->getDebugLoc(); 1660 EVT PtrVT = getPointerTy(); 1661 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1662 MachineFunction &MF = DAG.getMachineFunction(); 1663 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1664 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1665 ARMConstantPoolValue *CPV = 1666 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1667 ARMCP::CPValue, PCAdj, "tlsgd", true); 1668 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1669 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1670 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1671 PseudoSourceValue::getConstantPool(), 0, 1672 false, false, 0); 1673 SDValue Chain = Argument.getValue(1); 1674 1675 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1676 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1677 1678 // call __tls_get_addr. 1679 ArgListTy Args; 1680 ArgListEntry Entry; 1681 Entry.Node = Argument; 1682 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext()); 1683 Args.push_back(Entry); 1684 // FIXME: is there useful debug info available here? 1685 std::pair<SDValue, SDValue> CallResult = 1686 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()), 1687 false, false, false, false, 1688 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 1689 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 1690 return CallResult.first; 1691} 1692 1693// Lower ISD::GlobalTLSAddress using the "initial exec" or 1694// "local exec" model. 1695SDValue 1696ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 1697 SelectionDAG &DAG) const { 1698 const GlobalValue *GV = GA->getGlobal(); 1699 DebugLoc dl = GA->getDebugLoc(); 1700 SDValue Offset; 1701 SDValue Chain = DAG.getEntryNode(); 1702 EVT PtrVT = getPointerTy(); 1703 // Get the Thread Pointer 1704 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1705 1706 if (GV->isDeclaration()) { 1707 MachineFunction &MF = DAG.getMachineFunction(); 1708 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1709 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1710 // Initial exec model. 1711 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1712 ARMConstantPoolValue *CPV = 1713 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1714 ARMCP::CPValue, PCAdj, "gottpoff", true); 1715 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1716 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1717 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1718 PseudoSourceValue::getConstantPool(), 0, 1719 false, false, 0); 1720 Chain = Offset.getValue(1); 1721 1722 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1723 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 1724 1725 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1726 PseudoSourceValue::getConstantPool(), 0, 1727 false, false, 0); 1728 } else { 1729 // local exec model 1730 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff"); 1731 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1732 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1733 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1734 PseudoSourceValue::getConstantPool(), 0, 1735 false, false, 0); 1736 } 1737 1738 // The address of the thread local variable is the add of the thread 1739 // pointer with the offset of the variable. 1740 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1741} 1742 1743SDValue 1744ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 1745 // TODO: implement the "local dynamic" model 1746 assert(Subtarget->isTargetELF() && 1747 "TLS not implemented for non-ELF targets"); 1748 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1749 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 1750 // otherwise use the "Local Exec" TLS Model 1751 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 1752 return LowerToTLSGeneralDynamicModel(GA, DAG); 1753 else 1754 return LowerToTLSExecModels(GA, DAG); 1755} 1756 1757SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 1758 SelectionDAG &DAG) const { 1759 EVT PtrVT = getPointerTy(); 1760 DebugLoc dl = Op.getDebugLoc(); 1761 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1762 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1763 if (RelocM == Reloc::PIC_) { 1764 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 1765 ARMConstantPoolValue *CPV = 1766 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT"); 1767 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1768 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1769 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1770 CPAddr, 1771 PseudoSourceValue::getConstantPool(), 0, 1772 false, false, 0); 1773 SDValue Chain = Result.getValue(1); 1774 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 1775 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 1776 if (!UseGOTOFF) 1777 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1778 PseudoSourceValue::getGOT(), 0, 1779 false, false, 0); 1780 return Result; 1781 } else { 1782 // If we have T2 ops, we can materialize the address directly via movt/movw 1783 // pair. This is always cheaper. 1784 if (Subtarget->useMovt()) { 1785 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 1786 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 1787 } else { 1788 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1789 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1790 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1791 PseudoSourceValue::getConstantPool(), 0, 1792 false, false, 0); 1793 } 1794 } 1795} 1796 1797SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 1798 SelectionDAG &DAG) const { 1799 MachineFunction &MF = DAG.getMachineFunction(); 1800 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1801 unsigned ARMPCLabelIndex = 0; 1802 EVT PtrVT = getPointerTy(); 1803 DebugLoc dl = Op.getDebugLoc(); 1804 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1805 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1806 SDValue CPAddr; 1807 if (RelocM == Reloc::Static) 1808 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1809 else { 1810 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1811 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 1812 ARMConstantPoolValue *CPV = 1813 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj); 1814 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1815 } 1816 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1817 1818 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1819 PseudoSourceValue::getConstantPool(), 0, 1820 false, false, 0); 1821 SDValue Chain = Result.getValue(1); 1822 1823 if (RelocM == Reloc::PIC_) { 1824 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1825 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1826 } 1827 1828 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 1829 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1830 PseudoSourceValue::getGOT(), 0, 1831 false, false, 0); 1832 1833 return Result; 1834} 1835 1836SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 1837 SelectionDAG &DAG) const { 1838 assert(Subtarget->isTargetELF() && 1839 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 1840 MachineFunction &MF = DAG.getMachineFunction(); 1841 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1842 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1843 EVT PtrVT = getPointerTy(); 1844 DebugLoc dl = Op.getDebugLoc(); 1845 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1846 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1847 "_GLOBAL_OFFSET_TABLE_", 1848 ARMPCLabelIndex, PCAdj); 1849 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1850 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1851 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1852 PseudoSourceValue::getConstantPool(), 0, 1853 false, false, 0); 1854 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1855 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1856} 1857 1858SDValue 1859ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 1860 DebugLoc dl = Op.getDebugLoc(); 1861 SDValue Val = DAG.getConstant(0, MVT::i32); 1862 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), 1863 Op.getOperand(1), Val); 1864} 1865 1866SDValue 1867ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 1868 DebugLoc dl = Op.getDebugLoc(); 1869 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 1870 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 1871} 1872 1873SDValue 1874ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 1875 const ARMSubtarget *Subtarget) const { 1876 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1877 DebugLoc dl = Op.getDebugLoc(); 1878 switch (IntNo) { 1879 default: return SDValue(); // Don't custom lower most intrinsics. 1880 case Intrinsic::arm_thread_pointer: { 1881 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1882 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1883 } 1884 case Intrinsic::eh_sjlj_lsda: { 1885 MachineFunction &MF = DAG.getMachineFunction(); 1886 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1887 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1888 EVT PtrVT = getPointerTy(); 1889 DebugLoc dl = Op.getDebugLoc(); 1890 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1891 SDValue CPAddr; 1892 unsigned PCAdj = (RelocM != Reloc::PIC_) 1893 ? 0 : (Subtarget->isThumb() ? 4 : 8); 1894 ARMConstantPoolValue *CPV = 1895 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex, 1896 ARMCP::CPLSDA, PCAdj); 1897 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1898 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1899 SDValue Result = 1900 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1901 PseudoSourceValue::getConstantPool(), 0, 1902 false, false, 0); 1903 1904 if (RelocM == Reloc::PIC_) { 1905 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1906 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1907 } 1908 return Result; 1909 } 1910 } 1911} 1912 1913static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 1914 const ARMSubtarget *Subtarget) { 1915 DebugLoc dl = Op.getDebugLoc(); 1916 SDValue Op5 = Op.getOperand(5); 1917 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue(); 1918 // v6 and v7 can both handle barriers directly, but need handled a bit 1919 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should 1920 // never get here. 1921 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER; 1922 if (Subtarget->hasV7Ops()) 1923 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0)); 1924 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()) 1925 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0), 1926 DAG.getConstant(0, MVT::i32)); 1927 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 1928 return SDValue(); 1929} 1930 1931static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 1932 MachineFunction &MF = DAG.getMachineFunction(); 1933 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 1934 1935 // vastart just stores the address of the VarArgsFrameIndex slot into the 1936 // memory location argument. 1937 DebugLoc dl = Op.getDebugLoc(); 1938 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1939 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1940 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1941 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 1942 false, false, 0); 1943} 1944 1945SDValue 1946ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 1947 SelectionDAG &DAG) const { 1948 SDNode *Node = Op.getNode(); 1949 DebugLoc dl = Node->getDebugLoc(); 1950 EVT VT = Node->getValueType(0); 1951 SDValue Chain = Op.getOperand(0); 1952 SDValue Size = Op.getOperand(1); 1953 SDValue Align = Op.getOperand(2); 1954 1955 // Chain the dynamic stack allocation so that it doesn't modify the stack 1956 // pointer when other instructions are using the stack. 1957 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1958 1959 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue(); 1960 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment(); 1961 if (AlignVal > StackAlign) 1962 // Do this now since selection pass cannot introduce new target 1963 // independent node. 1964 Align = DAG.getConstant(-(uint64_t)AlignVal, VT); 1965 1966 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up 1967 // using a "add r, sp, r" instead. Negate the size now so we don't have to 1968 // do even more horrible hack later. 1969 MachineFunction &MF = DAG.getMachineFunction(); 1970 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1971 if (AFI->isThumb1OnlyFunction()) { 1972 bool Negate = true; 1973 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size); 1974 if (C) { 1975 uint32_t Val = C->getZExtValue(); 1976 if (Val <= 508 && ((Val & 3) == 0)) 1977 Negate = false; 1978 } 1979 if (Negate) 1980 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size); 1981 } 1982 1983 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1984 SDValue Ops1[] = { Chain, Size, Align }; 1985 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3); 1986 Chain = Res.getValue(1); 1987 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1988 DAG.getIntPtrConstant(0, true), SDValue()); 1989 SDValue Ops2[] = { Res, Chain }; 1990 return DAG.getMergeValues(Ops2, 2, dl); 1991} 1992 1993SDValue 1994ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 1995 SDValue &Root, SelectionDAG &DAG, 1996 DebugLoc dl) const { 1997 MachineFunction &MF = DAG.getMachineFunction(); 1998 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1999 2000 TargetRegisterClass *RC; 2001 if (AFI->isThumb1OnlyFunction()) 2002 RC = ARM::tGPRRegisterClass; 2003 else 2004 RC = ARM::GPRRegisterClass; 2005 2006 // Transform the arguments stored in physical registers into virtual ones. 2007 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2008 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2009 2010 SDValue ArgValue2; 2011 if (NextVA.isMemLoc()) { 2012 MachineFrameInfo *MFI = MF.getFrameInfo(); 2013 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2014 2015 // Create load node to retrieve arguments from the stack. 2016 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2017 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2018 PseudoSourceValue::getFixedStack(FI), 0, 2019 false, false, 0); 2020 } else { 2021 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2022 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2023 } 2024 2025 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2026} 2027 2028SDValue 2029ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2030 CallingConv::ID CallConv, bool isVarArg, 2031 const SmallVectorImpl<ISD::InputArg> 2032 &Ins, 2033 DebugLoc dl, SelectionDAG &DAG, 2034 SmallVectorImpl<SDValue> &InVals) 2035 const { 2036 2037 MachineFunction &MF = DAG.getMachineFunction(); 2038 MachineFrameInfo *MFI = MF.getFrameInfo(); 2039 2040 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2041 2042 // Assign locations to all of the incoming arguments. 2043 SmallVector<CCValAssign, 16> ArgLocs; 2044 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 2045 *DAG.getContext()); 2046 CCInfo.AnalyzeFormalArguments(Ins, 2047 CCAssignFnForNode(CallConv, /* Return*/ false, 2048 isVarArg)); 2049 2050 SmallVector<SDValue, 16> ArgValues; 2051 2052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2053 CCValAssign &VA = ArgLocs[i]; 2054 2055 // Arguments stored in registers. 2056 if (VA.isRegLoc()) { 2057 EVT RegVT = VA.getLocVT(); 2058 2059 SDValue ArgValue; 2060 if (VA.needsCustom()) { 2061 // f64 and vector types are split up into multiple registers or 2062 // combinations of registers and stack slots. 2063 if (VA.getLocVT() == MVT::v2f64) { 2064 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2065 Chain, DAG, dl); 2066 VA = ArgLocs[++i]; // skip ahead to next loc 2067 SDValue ArgValue2; 2068 if (VA.isMemLoc()) { 2069 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2070 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2071 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2072 PseudoSourceValue::getFixedStack(FI), 0, 2073 false, false, 0); 2074 } else { 2075 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2076 Chain, DAG, dl); 2077 } 2078 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2079 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2080 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2081 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2082 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2083 } else 2084 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2085 2086 } else { 2087 TargetRegisterClass *RC; 2088 2089 if (RegVT == MVT::f32) 2090 RC = ARM::SPRRegisterClass; 2091 else if (RegVT == MVT::f64) 2092 RC = ARM::DPRRegisterClass; 2093 else if (RegVT == MVT::v2f64) 2094 RC = ARM::QPRRegisterClass; 2095 else if (RegVT == MVT::i32) 2096 RC = (AFI->isThumb1OnlyFunction() ? 2097 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2098 else 2099 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2100 2101 // Transform the arguments in physical registers into virtual ones. 2102 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2103 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2104 } 2105 2106 // If this is an 8 or 16-bit value, it is really passed promoted 2107 // to 32 bits. Insert an assert[sz]ext to capture this, then 2108 // truncate to the right size. 2109 switch (VA.getLocInfo()) { 2110 default: llvm_unreachable("Unknown loc info!"); 2111 case CCValAssign::Full: break; 2112 case CCValAssign::BCvt: 2113 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 2114 break; 2115 case CCValAssign::SExt: 2116 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2117 DAG.getValueType(VA.getValVT())); 2118 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2119 break; 2120 case CCValAssign::ZExt: 2121 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2122 DAG.getValueType(VA.getValVT())); 2123 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2124 break; 2125 } 2126 2127 InVals.push_back(ArgValue); 2128 2129 } else { // VA.isRegLoc() 2130 2131 // sanity check 2132 assert(VA.isMemLoc()); 2133 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2134 2135 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 2136 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true); 2137 2138 // Create load nodes to retrieve arguments from the stack. 2139 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2140 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2141 PseudoSourceValue::getFixedStack(FI), 0, 2142 false, false, 0)); 2143 } 2144 } 2145 2146 // varargs 2147 if (isVarArg) { 2148 static const unsigned GPRArgRegs[] = { 2149 ARM::R0, ARM::R1, ARM::R2, ARM::R3 2150 }; 2151 2152 unsigned NumGPRs = CCInfo.getFirstUnallocated 2153 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2154 2155 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 2156 unsigned VARegSize = (4 - NumGPRs) * 4; 2157 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2158 unsigned ArgOffset = CCInfo.getNextStackOffset(); 2159 if (VARegSaveSize) { 2160 // If this function is vararg, store any remaining integer argument regs 2161 // to their spots on the stack so that they may be loaded by deferencing 2162 // the result of va_next. 2163 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2164 AFI->setVarArgsFrameIndex( 2165 MFI->CreateFixedObject(VARegSaveSize, 2166 ArgOffset + VARegSaveSize - VARegSize, 2167 true)); 2168 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2169 getPointerTy()); 2170 2171 SmallVector<SDValue, 4> MemOps; 2172 for (; NumGPRs < 4; ++NumGPRs) { 2173 TargetRegisterClass *RC; 2174 if (AFI->isThumb1OnlyFunction()) 2175 RC = ARM::tGPRRegisterClass; 2176 else 2177 RC = ARM::GPRRegisterClass; 2178 2179 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); 2180 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2181 SDValue Store = 2182 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2183 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()), 2184 0, false, false, 0); 2185 MemOps.push_back(Store); 2186 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2187 DAG.getConstant(4, getPointerTy())); 2188 } 2189 if (!MemOps.empty()) 2190 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2191 &MemOps[0], MemOps.size()); 2192 } else 2193 // This will point to the next argument passed via stack. 2194 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2195 } 2196 2197 return Chain; 2198} 2199 2200/// isFloatingPointZero - Return true if this is +0.0. 2201static bool isFloatingPointZero(SDValue Op) { 2202 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2203 return CFP->getValueAPF().isPosZero(); 2204 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2205 // Maybe this has already been legalized into the constant pool? 2206 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2207 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2208 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2209 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2210 return CFP->getValueAPF().isPosZero(); 2211 } 2212 } 2213 return false; 2214} 2215 2216/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2217/// the given operands. 2218SDValue 2219ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2220 SDValue &ARMCC, SelectionDAG &DAG, 2221 DebugLoc dl) const { 2222 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2223 unsigned C = RHSC->getZExtValue(); 2224 if (!isLegalICmpImmediate(C)) { 2225 // Constant does not fit, try adjusting it by one? 2226 switch (CC) { 2227 default: break; 2228 case ISD::SETLT: 2229 case ISD::SETGE: 2230 if (isLegalICmpImmediate(C-1)) { 2231 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2232 RHS = DAG.getConstant(C-1, MVT::i32); 2233 } 2234 break; 2235 case ISD::SETULT: 2236 case ISD::SETUGE: 2237 if (C > 0 && isLegalICmpImmediate(C-1)) { 2238 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2239 RHS = DAG.getConstant(C-1, MVT::i32); 2240 } 2241 break; 2242 case ISD::SETLE: 2243 case ISD::SETGT: 2244 if (isLegalICmpImmediate(C+1)) { 2245 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2246 RHS = DAG.getConstant(C+1, MVT::i32); 2247 } 2248 break; 2249 case ISD::SETULE: 2250 case ISD::SETUGT: 2251 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) { 2252 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2253 RHS = DAG.getConstant(C+1, MVT::i32); 2254 } 2255 break; 2256 } 2257 } 2258 } 2259 2260 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2261 ARMISD::NodeType CompareType; 2262 switch (CondCode) { 2263 default: 2264 CompareType = ARMISD::CMP; 2265 break; 2266 case ARMCC::EQ: 2267 case ARMCC::NE: 2268 // Uses only Z Flag 2269 CompareType = ARMISD::CMPZ; 2270 break; 2271 } 2272 ARMCC = DAG.getConstant(CondCode, MVT::i32); 2273 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); 2274} 2275 2276static bool canBitcastToInt(SDNode *Op) { 2277 return Op->hasOneUse() && 2278 ISD::isNormalLoad(Op) && 2279 Op->getValueType(0) == MVT::f32; 2280} 2281 2282static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) { 2283 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2284 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2285 Ld->getChain(), Ld->getBasePtr(), 2286 Ld->getSrcValue(), Ld->getSrcValueOffset(), 2287 Ld->isVolatile(), Ld->isNonTemporal(), 2288 Ld->getAlignment()); 2289 2290 llvm_unreachable("Unknown VFP cmp argument!"); 2291} 2292 2293/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2294SDValue 2295ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, 2296 SDValue &ARMCC, SelectionDAG &DAG, 2297 DebugLoc dl) const { 2298 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || 2299 CC == ISD::SETNE || CC == ISD::SETUNE) && 2300 canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) { 2301 // If there are no othter uses of the CMP operands, and the condition 2302 // code is EQ oe NE, we can optimize it to an integer comparison. 2303 if (CC == ISD::SETOEQ) 2304 CC = ISD::SETEQ; 2305 else if (CC == ISD::SETUNE) 2306 CC = ISD::SETNE; 2307 LHS = bitcastToInt(LHS, DAG); 2308 RHS = bitcastToInt(RHS, DAG); 2309 return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2310 } 2311 2312 SDValue Cmp; 2313 if (!isFloatingPointZero(RHS)) 2314 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); 2315 else 2316 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); 2317 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); 2318} 2319 2320SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2321 EVT VT = Op.getValueType(); 2322 SDValue LHS = Op.getOperand(0); 2323 SDValue RHS = Op.getOperand(1); 2324 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2325 SDValue TrueVal = Op.getOperand(2); 2326 SDValue FalseVal = Op.getOperand(3); 2327 DebugLoc dl = Op.getDebugLoc(); 2328 2329 if (LHS.getValueType() == MVT::i32) { 2330 SDValue ARMCC; 2331 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2332 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2333 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); 2334 } 2335 2336 ARMCC::CondCodes CondCode, CondCode2; 2337 FPCCToARMCC(CC, CondCode, CondCode2); 2338 2339 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 2340 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2341 SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2342 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2343 ARMCC, CCR, Cmp); 2344 if (CondCode2 != ARMCC::AL) { 2345 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 2346 // FIXME: Needs another CMP because flag can have but one use. 2347 SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl); 2348 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2349 Result, TrueVal, ARMCC2, CCR, Cmp2); 2350 } 2351 return Result; 2352} 2353 2354SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2355 SDValue Chain = Op.getOperand(0); 2356 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2357 SDValue LHS = Op.getOperand(2); 2358 SDValue RHS = Op.getOperand(3); 2359 SDValue Dest = Op.getOperand(4); 2360 DebugLoc dl = Op.getDebugLoc(); 2361 2362 if (LHS.getValueType() == MVT::i32) { 2363 SDValue ARMCC; 2364 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2365 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2366 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2367 Chain, Dest, ARMCC, CCR,Cmp); 2368 } 2369 2370 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2371 ARMCC::CondCodes CondCode, CondCode2; 2372 FPCCToARMCC(CC, CondCode, CondCode2); 2373 2374 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 2375 SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2376 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2377 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 2378 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 2379 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2380 if (CondCode2 != ARMCC::AL) { 2381 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 2382 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 2383 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2384 } 2385 return Res; 2386} 2387 2388SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2389 SDValue Chain = Op.getOperand(0); 2390 SDValue Table = Op.getOperand(1); 2391 SDValue Index = Op.getOperand(2); 2392 DebugLoc dl = Op.getDebugLoc(); 2393 2394 EVT PTy = getPointerTy(); 2395 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2396 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2397 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2398 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2399 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2400 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2401 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2402 if (Subtarget->isThumb2()) { 2403 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2404 // which does another jump to the destination. This also makes it easier 2405 // to translate it to TBB / TBH later. 2406 // FIXME: This might not work if the function is extremely large. 2407 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2408 Addr, Op.getOperand(2), JTI, UId); 2409 } 2410 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2411 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 2412 PseudoSourceValue::getJumpTable(), 0, 2413 false, false, 0); 2414 Chain = Addr.getValue(1); 2415 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 2416 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2417 } else { 2418 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 2419 PseudoSourceValue::getJumpTable(), 0, false, false, 0); 2420 Chain = Addr.getValue(1); 2421 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2422 } 2423} 2424 2425static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 2426 DebugLoc dl = Op.getDebugLoc(); 2427 unsigned Opc; 2428 2429 switch (Op.getOpcode()) { 2430 default: 2431 assert(0 && "Invalid opcode!"); 2432 case ISD::FP_TO_SINT: 2433 Opc = ARMISD::FTOSI; 2434 break; 2435 case ISD::FP_TO_UINT: 2436 Opc = ARMISD::FTOUI; 2437 break; 2438 } 2439 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 2440 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 2441} 2442 2443static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2444 EVT VT = Op.getValueType(); 2445 DebugLoc dl = Op.getDebugLoc(); 2446 unsigned Opc; 2447 2448 switch (Op.getOpcode()) { 2449 default: 2450 assert(0 && "Invalid opcode!"); 2451 case ISD::SINT_TO_FP: 2452 Opc = ARMISD::SITOF; 2453 break; 2454 case ISD::UINT_TO_FP: 2455 Opc = ARMISD::UITOF; 2456 break; 2457 } 2458 2459 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 2460 return DAG.getNode(Opc, dl, VT, Op); 2461} 2462 2463SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2464 // Implement fcopysign with a fabs and a conditional fneg. 2465 SDValue Tmp0 = Op.getOperand(0); 2466 SDValue Tmp1 = Op.getOperand(1); 2467 DebugLoc dl = Op.getDebugLoc(); 2468 EVT VT = Op.getValueType(); 2469 EVT SrcVT = Tmp1.getValueType(); 2470 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); 2471 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 2472 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT); 2473 SDValue Cmp = getVFPCmp(Tmp1, FP0, 2474 ISD::SETLT, ARMCC, DAG, dl); 2475 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2476 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 2477} 2478 2479SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 2480 MachineFunction &MF = DAG.getMachineFunction(); 2481 MachineFrameInfo *MFI = MF.getFrameInfo(); 2482 MFI->setReturnAddressIsTaken(true); 2483 2484 EVT VT = Op.getValueType(); 2485 DebugLoc dl = Op.getDebugLoc(); 2486 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2487 if (Depth) { 2488 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 2489 SDValue Offset = DAG.getConstant(4, MVT::i32); 2490 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 2491 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 2492 NULL, 0, false, false, 0); 2493 } 2494 2495 // Return LR, which contains the return address. Mark it an implicit live-in. 2496 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass); 2497 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 2498} 2499 2500SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2501 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2502 MFI->setFrameAddressIsTaken(true); 2503 2504 EVT VT = Op.getValueType(); 2505 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 2506 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2507 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 2508 ? ARM::R7 : ARM::R11; 2509 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2510 while (Depth--) 2511 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 2512 false, false, 0); 2513 return FrameAddr; 2514} 2515 2516/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to 2517/// expand a bit convert where either the source or destination type is i64 to 2518/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 2519/// operand type is illegal (e.g., v2f32 for a target that doesn't support 2520/// vectors), since the legalizer won't know what to do with that. 2521static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 2522 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2523 DebugLoc dl = N->getDebugLoc(); 2524 SDValue Op = N->getOperand(0); 2525 2526 // This function is only supposed to be called for i64 types, either as the 2527 // source or destination of the bit convert. 2528 EVT SrcVT = Op.getValueType(); 2529 EVT DstVT = N->getValueType(0); 2530 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 2531 "ExpandBIT_CONVERT called for non-i64 type"); 2532 2533 // Turn i64->f64 into VMOVDRR. 2534 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 2535 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2536 DAG.getConstant(0, MVT::i32)); 2537 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2538 DAG.getConstant(1, MVT::i32)); 2539 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT, 2540 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 2541 } 2542 2543 // Turn f64->i64 into VMOVRRD. 2544 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 2545 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 2546 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 2547 // Merge the pieces into a single i64 value. 2548 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 2549 } 2550 2551 return SDValue(); 2552} 2553 2554/// getZeroVector - Returns a vector of specified type with all zero elements. 2555/// 2556static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2557 assert(VT.isVector() && "Expected a vector type"); 2558 2559 // Zero vectors are used to represent vector negation and in those cases 2560 // will be implemented with the NEON VNEG instruction. However, VNEG does 2561 // not support i64 elements, so sometimes the zero vectors will need to be 2562 // explicitly constructed. For those cases, and potentially other uses in 2563 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted 2564 // to their dest type. This ensures they get CSE'd. 2565 SDValue Vec; 2566 SDValue Cst = DAG.getTargetConstant(0, MVT::i8); 2567 SmallVector<SDValue, 8> Ops; 2568 MVT TVT; 2569 2570 if (VT.getSizeInBits() == 64) { 2571 Ops.assign(8, Cst); TVT = MVT::v8i8; 2572 } else { 2573 Ops.assign(16, Cst); TVT = MVT::v16i8; 2574 } 2575 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2576 2577 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2578} 2579 2580/// getOnesVector - Returns a vector of specified type with all bits set. 2581/// 2582static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2583 assert(VT.isVector() && "Expected a vector type"); 2584 2585 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their 2586 // dest type. This ensures they get CSE'd. 2587 SDValue Vec; 2588 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8); 2589 SmallVector<SDValue, 8> Ops; 2590 MVT TVT; 2591 2592 if (VT.getSizeInBits() == 64) { 2593 Ops.assign(8, Cst); TVT = MVT::v8i8; 2594 } else { 2595 Ops.assign(16, Cst); TVT = MVT::v16i8; 2596 } 2597 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2598 2599 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2600} 2601 2602/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 2603/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2604SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 2605 SelectionDAG &DAG) const { 2606 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2607 EVT VT = Op.getValueType(); 2608 unsigned VTBits = VT.getSizeInBits(); 2609 DebugLoc dl = Op.getDebugLoc(); 2610 SDValue ShOpLo = Op.getOperand(0); 2611 SDValue ShOpHi = Op.getOperand(1); 2612 SDValue ShAmt = Op.getOperand(2); 2613 SDValue ARMCC; 2614 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 2615 2616 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 2617 2618 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2619 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2620 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 2621 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2622 DAG.getConstant(VTBits, MVT::i32)); 2623 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 2624 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2625 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 2626 2627 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2628 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2629 ARMCC, DAG, dl); 2630 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 2631 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, 2632 CCR, Cmp); 2633 2634 SDValue Ops[2] = { Lo, Hi }; 2635 return DAG.getMergeValues(Ops, 2, dl); 2636} 2637 2638/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 2639/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2640SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 2641 SelectionDAG &DAG) const { 2642 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2643 EVT VT = Op.getValueType(); 2644 unsigned VTBits = VT.getSizeInBits(); 2645 DebugLoc dl = Op.getDebugLoc(); 2646 SDValue ShOpLo = Op.getOperand(0); 2647 SDValue ShOpHi = Op.getOperand(1); 2648 SDValue ShAmt = Op.getOperand(2); 2649 SDValue ARMCC; 2650 2651 assert(Op.getOpcode() == ISD::SHL_PARTS); 2652 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2653 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2654 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 2655 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2656 DAG.getConstant(VTBits, MVT::i32)); 2657 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 2658 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 2659 2660 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2661 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2662 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2663 ARMCC, DAG, dl); 2664 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 2665 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC, 2666 CCR, Cmp); 2667 2668 SDValue Ops[2] = { Lo, Hi }; 2669 return DAG.getMergeValues(Ops, 2, dl); 2670} 2671 2672static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 2673 const ARMSubtarget *ST) { 2674 EVT VT = N->getValueType(0); 2675 DebugLoc dl = N->getDebugLoc(); 2676 2677 if (!ST->hasV6T2Ops()) 2678 return SDValue(); 2679 2680 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 2681 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 2682} 2683 2684static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 2685 const ARMSubtarget *ST) { 2686 EVT VT = N->getValueType(0); 2687 DebugLoc dl = N->getDebugLoc(); 2688 2689 // Lower vector shifts on NEON to use VSHL. 2690 if (VT.isVector()) { 2691 assert(ST->hasNEON() && "unexpected vector shift"); 2692 2693 // Left shifts translate directly to the vshiftu intrinsic. 2694 if (N->getOpcode() == ISD::SHL) 2695 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2696 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 2697 N->getOperand(0), N->getOperand(1)); 2698 2699 assert((N->getOpcode() == ISD::SRA || 2700 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 2701 2702 // NEON uses the same intrinsics for both left and right shifts. For 2703 // right shifts, the shift amounts are negative, so negate the vector of 2704 // shift amounts. 2705 EVT ShiftVT = N->getOperand(1).getValueType(); 2706 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 2707 getZeroVector(ShiftVT, DAG, dl), 2708 N->getOperand(1)); 2709 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 2710 Intrinsic::arm_neon_vshifts : 2711 Intrinsic::arm_neon_vshiftu); 2712 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2713 DAG.getConstant(vshiftInt, MVT::i32), 2714 N->getOperand(0), NegatedCount); 2715 } 2716 2717 // We can get here for a node like i32 = ISD::SHL i32, i64 2718 if (VT != MVT::i64) 2719 return SDValue(); 2720 2721 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 2722 "Unknown shift to lower!"); 2723 2724 // We only lower SRA, SRL of 1 here, all others use generic lowering. 2725 if (!isa<ConstantSDNode>(N->getOperand(1)) || 2726 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 2727 return SDValue(); 2728 2729 // If we are in thumb mode, we don't have RRX. 2730 if (ST->isThumb1Only()) return SDValue(); 2731 2732 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 2733 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2734 DAG.getConstant(0, MVT::i32)); 2735 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2736 DAG.getConstant(1, MVT::i32)); 2737 2738 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 2739 // captures the result into a carry flag. 2740 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 2741 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 2742 2743 // The low part is an ARMISD::RRX operand, which shifts the carry in. 2744 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 2745 2746 // Merge the pieces into a single i64 value. 2747 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 2748} 2749 2750static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 2751 SDValue TmpOp0, TmpOp1; 2752 bool Invert = false; 2753 bool Swap = false; 2754 unsigned Opc = 0; 2755 2756 SDValue Op0 = Op.getOperand(0); 2757 SDValue Op1 = Op.getOperand(1); 2758 SDValue CC = Op.getOperand(2); 2759 EVT VT = Op.getValueType(); 2760 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 2761 DebugLoc dl = Op.getDebugLoc(); 2762 2763 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 2764 switch (SetCCOpcode) { 2765 default: llvm_unreachable("Illegal FP comparison"); break; 2766 case ISD::SETUNE: 2767 case ISD::SETNE: Invert = true; // Fallthrough 2768 case ISD::SETOEQ: 2769 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2770 case ISD::SETOLT: 2771 case ISD::SETLT: Swap = true; // Fallthrough 2772 case ISD::SETOGT: 2773 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2774 case ISD::SETOLE: 2775 case ISD::SETLE: Swap = true; // Fallthrough 2776 case ISD::SETOGE: 2777 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2778 case ISD::SETUGE: Swap = true; // Fallthrough 2779 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 2780 case ISD::SETUGT: Swap = true; // Fallthrough 2781 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 2782 case ISD::SETUEQ: Invert = true; // Fallthrough 2783 case ISD::SETONE: 2784 // Expand this to (OLT | OGT). 2785 TmpOp0 = Op0; 2786 TmpOp1 = Op1; 2787 Opc = ISD::OR; 2788 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2789 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 2790 break; 2791 case ISD::SETUO: Invert = true; // Fallthrough 2792 case ISD::SETO: 2793 // Expand this to (OLT | OGE). 2794 TmpOp0 = Op0; 2795 TmpOp1 = Op1; 2796 Opc = ISD::OR; 2797 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2798 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 2799 break; 2800 } 2801 } else { 2802 // Integer comparisons. 2803 switch (SetCCOpcode) { 2804 default: llvm_unreachable("Illegal integer comparison"); break; 2805 case ISD::SETNE: Invert = true; 2806 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2807 case ISD::SETLT: Swap = true; 2808 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2809 case ISD::SETLE: Swap = true; 2810 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2811 case ISD::SETULT: Swap = true; 2812 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 2813 case ISD::SETULE: Swap = true; 2814 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 2815 } 2816 2817 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 2818 if (Opc == ARMISD::VCEQ) { 2819 2820 SDValue AndOp; 2821 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 2822 AndOp = Op0; 2823 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 2824 AndOp = Op1; 2825 2826 // Ignore bitconvert. 2827 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) 2828 AndOp = AndOp.getOperand(0); 2829 2830 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 2831 Opc = ARMISD::VTST; 2832 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); 2833 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); 2834 Invert = !Invert; 2835 } 2836 } 2837 } 2838 2839 if (Swap) 2840 std::swap(Op0, Op1); 2841 2842 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 2843 2844 if (Invert) 2845 Result = DAG.getNOT(dl, Result, VT); 2846 2847 return Result; 2848} 2849 2850/// isNEONModifiedImm - Check if the specified splat value corresponds to a 2851/// valid vector constant for a NEON instruction with a "modified immediate" 2852/// operand (e.g., VMOV). If so, return either the constant being 2853/// splatted or the encoded value, depending on the DoEncode parameter. The 2854/// format of the encoded value is: bit12=Op, bits11-8=Cmode, 2855/// bits7-0=Immediate. 2856static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 2857 unsigned SplatBitSize, SelectionDAG &DAG, 2858 bool isVMOV, bool DoEncode) { 2859 unsigned Op, Cmode, Imm; 2860 EVT VT; 2861 2862 // SplatBitSize is set to the smallest size that splats the vector, so a 2863 // zero vector will always have SplatBitSize == 8. However, NEON modified 2864 // immediate instructions others than VMOV do not support the 8-bit encoding 2865 // of a zero vector, and the default encoding of zero is supposed to be the 2866 // 32-bit version. 2867 if (SplatBits == 0) 2868 SplatBitSize = 32; 2869 2870 Op = 0; 2871 switch (SplatBitSize) { 2872 case 8: 2873 // Any 1-byte value is OK. Op=0, Cmode=1110. 2874 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 2875 Cmode = 0xe; 2876 Imm = SplatBits; 2877 VT = MVT::i8; 2878 break; 2879 2880 case 16: 2881 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 2882 VT = MVT::i16; 2883 if ((SplatBits & ~0xff) == 0) { 2884 // Value = 0x00nn: Op=x, Cmode=100x. 2885 Cmode = 0x8; 2886 Imm = SplatBits; 2887 break; 2888 } 2889 if ((SplatBits & ~0xff00) == 0) { 2890 // Value = 0xnn00: Op=x, Cmode=101x. 2891 Cmode = 0xa; 2892 Imm = SplatBits >> 8; 2893 break; 2894 } 2895 return SDValue(); 2896 2897 case 32: 2898 // NEON's 32-bit VMOV supports splat values where: 2899 // * only one byte is nonzero, or 2900 // * the least significant byte is 0xff and the second byte is nonzero, or 2901 // * the least significant 2 bytes are 0xff and the third is nonzero. 2902 VT = MVT::i32; 2903 if ((SplatBits & ~0xff) == 0) { 2904 // Value = 0x000000nn: Op=x, Cmode=000x. 2905 Cmode = 0; 2906 Imm = SplatBits; 2907 break; 2908 } 2909 if ((SplatBits & ~0xff00) == 0) { 2910 // Value = 0x0000nn00: Op=x, Cmode=001x. 2911 Cmode = 0x2; 2912 Imm = SplatBits >> 8; 2913 break; 2914 } 2915 if ((SplatBits & ~0xff0000) == 0) { 2916 // Value = 0x00nn0000: Op=x, Cmode=010x. 2917 Cmode = 0x4; 2918 Imm = SplatBits >> 16; 2919 break; 2920 } 2921 if ((SplatBits & ~0xff000000) == 0) { 2922 // Value = 0xnn000000: Op=x, Cmode=011x. 2923 Cmode = 0x6; 2924 Imm = SplatBits >> 24; 2925 break; 2926 } 2927 2928 if ((SplatBits & ~0xffff) == 0 && 2929 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 2930 // Value = 0x0000nnff: Op=x, Cmode=1100. 2931 Cmode = 0xc; 2932 Imm = SplatBits >> 8; 2933 SplatBits |= 0xff; 2934 break; 2935 } 2936 2937 if ((SplatBits & ~0xffffff) == 0 && 2938 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 2939 // Value = 0x00nnffff: Op=x, Cmode=1101. 2940 Cmode = 0xd; 2941 Imm = SplatBits >> 16; 2942 SplatBits |= 0xffff; 2943 break; 2944 } 2945 2946 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 2947 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 2948 // VMOV.I32. A (very) minor optimization would be to replicate the value 2949 // and fall through here to test for a valid 64-bit splat. But, then the 2950 // caller would also need to check and handle the change in size. 2951 return SDValue(); 2952 2953 case 64: { 2954 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 2955 if (!isVMOV) 2956 return SDValue(); 2957 uint64_t BitMask = 0xff; 2958 uint64_t Val = 0; 2959 unsigned ImmMask = 1; 2960 Imm = 0; 2961 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 2962 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 2963 Val |= BitMask; 2964 Imm |= ImmMask; 2965 } else if ((SplatBits & BitMask) != 0) { 2966 return SDValue(); 2967 } 2968 BitMask <<= 8; 2969 ImmMask <<= 1; 2970 } 2971 // Op=1, Cmode=1110. 2972 Op = 1; 2973 Cmode = 0xe; 2974 SplatBits = Val; 2975 VT = MVT::i64; 2976 break; 2977 } 2978 2979 default: 2980 llvm_unreachable("unexpected size for isNEONModifiedImm"); 2981 return SDValue(); 2982 } 2983 2984 if (DoEncode) 2985 return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32); 2986 return DAG.getTargetConstant(SplatBits, VT); 2987} 2988 2989 2990/// getNEONModImm - If this is a valid vector constant for a NEON instruction 2991/// with a "modified immediate" operand (e.g., VMOV) of the specified element 2992/// size, return the encoded value for that immediate. The ByteSize field 2993/// indicates the number of bytes of each element [1248]. 2994SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, 2995 SelectionDAG &DAG) { 2996 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 2997 APInt SplatBits, SplatUndef; 2998 unsigned SplatBitSize; 2999 bool HasAnyUndefs; 3000 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 3001 HasAnyUndefs, ByteSize * 8)) 3002 return SDValue(); 3003 3004 if (SplatBitSize > ByteSize * 8) 3005 return SDValue(); 3006 3007 return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), 3008 SplatBitSize, DAG, isVMOV, true); 3009} 3010 3011static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3012 bool &ReverseVEXT, unsigned &Imm) { 3013 unsigned NumElts = VT.getVectorNumElements(); 3014 ReverseVEXT = false; 3015 Imm = M[0]; 3016 3017 // If this is a VEXT shuffle, the immediate value is the index of the first 3018 // element. The other shuffle indices must be the successive elements after 3019 // the first one. 3020 unsigned ExpectedElt = Imm; 3021 for (unsigned i = 1; i < NumElts; ++i) { 3022 // Increment the expected index. If it wraps around, it may still be 3023 // a VEXT but the source vectors must be swapped. 3024 ExpectedElt += 1; 3025 if (ExpectedElt == NumElts * 2) { 3026 ExpectedElt = 0; 3027 ReverseVEXT = true; 3028 } 3029 3030 if (ExpectedElt != static_cast<unsigned>(M[i])) 3031 return false; 3032 } 3033 3034 // Adjust the index value if the source operands will be swapped. 3035 if (ReverseVEXT) 3036 Imm -= NumElts; 3037 3038 return true; 3039} 3040 3041/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3042/// instruction with the specified blocksize. (The order of the elements 3043/// within each block of the vector is reversed.) 3044static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3045 unsigned BlockSize) { 3046 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3047 "Only possible block sizes for VREV are: 16, 32, 64"); 3048 3049 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3050 if (EltSz == 64) 3051 return false; 3052 3053 unsigned NumElts = VT.getVectorNumElements(); 3054 unsigned BlockElts = M[0] + 1; 3055 3056 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3057 return false; 3058 3059 for (unsigned i = 0; i < NumElts; ++i) { 3060 if ((unsigned) M[i] != 3061 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3062 return false; 3063 } 3064 3065 return true; 3066} 3067 3068static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3069 unsigned &WhichResult) { 3070 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3071 if (EltSz == 64) 3072 return false; 3073 3074 unsigned NumElts = VT.getVectorNumElements(); 3075 WhichResult = (M[0] == 0 ? 0 : 1); 3076 for (unsigned i = 0; i < NumElts; i += 2) { 3077 if ((unsigned) M[i] != i + WhichResult || 3078 (unsigned) M[i+1] != i + NumElts + WhichResult) 3079 return false; 3080 } 3081 return true; 3082} 3083 3084/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3085/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3086/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3087static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3088 unsigned &WhichResult) { 3089 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3090 if (EltSz == 64) 3091 return false; 3092 3093 unsigned NumElts = VT.getVectorNumElements(); 3094 WhichResult = (M[0] == 0 ? 0 : 1); 3095 for (unsigned i = 0; i < NumElts; i += 2) { 3096 if ((unsigned) M[i] != i + WhichResult || 3097 (unsigned) M[i+1] != i + WhichResult) 3098 return false; 3099 } 3100 return true; 3101} 3102 3103static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3104 unsigned &WhichResult) { 3105 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3106 if (EltSz == 64) 3107 return false; 3108 3109 unsigned NumElts = VT.getVectorNumElements(); 3110 WhichResult = (M[0] == 0 ? 0 : 1); 3111 for (unsigned i = 0; i != NumElts; ++i) { 3112 if ((unsigned) M[i] != 2 * i + WhichResult) 3113 return false; 3114 } 3115 3116 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3117 if (VT.is64BitVector() && EltSz == 32) 3118 return false; 3119 3120 return true; 3121} 3122 3123/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3124/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3125/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3126static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3127 unsigned &WhichResult) { 3128 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3129 if (EltSz == 64) 3130 return false; 3131 3132 unsigned Half = VT.getVectorNumElements() / 2; 3133 WhichResult = (M[0] == 0 ? 0 : 1); 3134 for (unsigned j = 0; j != 2; ++j) { 3135 unsigned Idx = WhichResult; 3136 for (unsigned i = 0; i != Half; ++i) { 3137 if ((unsigned) M[i + j * Half] != Idx) 3138 return false; 3139 Idx += 2; 3140 } 3141 } 3142 3143 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3144 if (VT.is64BitVector() && EltSz == 32) 3145 return false; 3146 3147 return true; 3148} 3149 3150static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3151 unsigned &WhichResult) { 3152 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3153 if (EltSz == 64) 3154 return false; 3155 3156 unsigned NumElts = VT.getVectorNumElements(); 3157 WhichResult = (M[0] == 0 ? 0 : 1); 3158 unsigned Idx = WhichResult * NumElts / 2; 3159 for (unsigned i = 0; i != NumElts; i += 2) { 3160 if ((unsigned) M[i] != Idx || 3161 (unsigned) M[i+1] != Idx + NumElts) 3162 return false; 3163 Idx += 1; 3164 } 3165 3166 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3167 if (VT.is64BitVector() && EltSz == 32) 3168 return false; 3169 3170 return true; 3171} 3172 3173/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3174/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3175/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3176static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3177 unsigned &WhichResult) { 3178 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3179 if (EltSz == 64) 3180 return false; 3181 3182 unsigned NumElts = VT.getVectorNumElements(); 3183 WhichResult = (M[0] == 0 ? 0 : 1); 3184 unsigned Idx = WhichResult * NumElts / 2; 3185 for (unsigned i = 0; i != NumElts; i += 2) { 3186 if ((unsigned) M[i] != Idx || 3187 (unsigned) M[i+1] != Idx) 3188 return false; 3189 Idx += 1; 3190 } 3191 3192 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3193 if (VT.is64BitVector() && EltSz == 32) 3194 return false; 3195 3196 return true; 3197} 3198 3199 3200static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3201 // Canonicalize all-zeros and all-ones vectors. 3202 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode()); 3203 if (ConstVal->isNullValue()) 3204 return getZeroVector(VT, DAG, dl); 3205 if (ConstVal->isAllOnesValue()) 3206 return getOnesVector(VT, DAG, dl); 3207 3208 EVT CanonicalVT; 3209 if (VT.is64BitVector()) { 3210 switch (Val.getValueType().getSizeInBits()) { 3211 case 8: CanonicalVT = MVT::v8i8; break; 3212 case 16: CanonicalVT = MVT::v4i16; break; 3213 case 32: CanonicalVT = MVT::v2i32; break; 3214 case 64: CanonicalVT = MVT::v1i64; break; 3215 default: llvm_unreachable("unexpected splat element type"); break; 3216 } 3217 } else { 3218 assert(VT.is128BitVector() && "unknown splat vector size"); 3219 switch (Val.getValueType().getSizeInBits()) { 3220 case 8: CanonicalVT = MVT::v16i8; break; 3221 case 16: CanonicalVT = MVT::v8i16; break; 3222 case 32: CanonicalVT = MVT::v4i32; break; 3223 case 64: CanonicalVT = MVT::v2i64; break; 3224 default: llvm_unreachable("unexpected splat element type"); break; 3225 } 3226 } 3227 3228 // Build a canonical splat for this value. 3229 SmallVector<SDValue, 8> Ops; 3230 Ops.assign(CanonicalVT.getVectorNumElements(), Val); 3231 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], 3232 Ops.size()); 3233 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res); 3234} 3235 3236// If this is a case we can't handle, return null and let the default 3237// expansion code take care of it. 3238static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3239 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3240 DebugLoc dl = Op.getDebugLoc(); 3241 EVT VT = Op.getValueType(); 3242 3243 APInt SplatBits, SplatUndef; 3244 unsigned SplatBitSize; 3245 bool HasAnyUndefs; 3246 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3247 if (SplatBitSize <= 64) { 3248 // Check if an immediate VMOV works. 3249 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3250 SplatUndef.getZExtValue(), 3251 SplatBitSize, DAG, true, false); 3252 if (Val.getNode()) 3253 return BuildSplat(Val, VT, DAG, dl); 3254 } 3255 } 3256 3257 // Scan through the operands to see if only one value is used. 3258 unsigned NumElts = VT.getVectorNumElements(); 3259 bool isOnlyLowElement = true; 3260 bool usesOnlyOneValue = true; 3261 bool isConstant = true; 3262 SDValue Value; 3263 for (unsigned i = 0; i < NumElts; ++i) { 3264 SDValue V = Op.getOperand(i); 3265 if (V.getOpcode() == ISD::UNDEF) 3266 continue; 3267 if (i > 0) 3268 isOnlyLowElement = false; 3269 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3270 isConstant = false; 3271 3272 if (!Value.getNode()) 3273 Value = V; 3274 else if (V != Value) 3275 usesOnlyOneValue = false; 3276 } 3277 3278 if (!Value.getNode()) 3279 return DAG.getUNDEF(VT); 3280 3281 if (isOnlyLowElement) 3282 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3283 3284 // If all elements are constants, fall back to the default expansion, which 3285 // will generate a load from the constant pool. 3286 if (isConstant) 3287 return SDValue(); 3288 3289 // Use VDUP for non-constant splats. 3290 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3291 if (usesOnlyOneValue && EltSize <= 32) 3292 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3293 3294 // Vectors with 32- or 64-bit elements can be built by directly assigning 3295 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 3296 // will be legalized. 3297 if (EltSize >= 32) { 3298 // Do the expansion with floating-point types, since that is what the VFP 3299 // registers are defined to use, and since i64 is not legal. 3300 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3301 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3302 SmallVector<SDValue, 8> Ops; 3303 for (unsigned i = 0; i < NumElts; ++i) 3304 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i))); 3305 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3306 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3307 } 3308 3309 return SDValue(); 3310} 3311 3312/// isShuffleMaskLegal - Targets can use this to indicate that they only 3313/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 3314/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 3315/// are assumed to be legal. 3316bool 3317ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 3318 EVT VT) const { 3319 if (VT.getVectorNumElements() == 4 && 3320 (VT.is128BitVector() || VT.is64BitVector())) { 3321 unsigned PFIndexes[4]; 3322 for (unsigned i = 0; i != 4; ++i) { 3323 if (M[i] < 0) 3324 PFIndexes[i] = 8; 3325 else 3326 PFIndexes[i] = M[i]; 3327 } 3328 3329 // Compute the index in the perfect shuffle table. 3330 unsigned PFTableIndex = 3331 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3332 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3333 unsigned Cost = (PFEntry >> 30); 3334 3335 if (Cost <= 4) 3336 return true; 3337 } 3338 3339 bool ReverseVEXT; 3340 unsigned Imm, WhichResult; 3341 3342 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3343 return (EltSize >= 32 || 3344 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 3345 isVREVMask(M, VT, 64) || 3346 isVREVMask(M, VT, 32) || 3347 isVREVMask(M, VT, 16) || 3348 isVEXTMask(M, VT, ReverseVEXT, Imm) || 3349 isVTRNMask(M, VT, WhichResult) || 3350 isVUZPMask(M, VT, WhichResult) || 3351 isVZIPMask(M, VT, WhichResult) || 3352 isVTRN_v_undef_Mask(M, VT, WhichResult) || 3353 isVUZP_v_undef_Mask(M, VT, WhichResult) || 3354 isVZIP_v_undef_Mask(M, VT, WhichResult)); 3355} 3356 3357/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3358/// the specified operations to build the shuffle. 3359static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3360 SDValue RHS, SelectionDAG &DAG, 3361 DebugLoc dl) { 3362 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3363 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3364 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3365 3366 enum { 3367 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3368 OP_VREV, 3369 OP_VDUP0, 3370 OP_VDUP1, 3371 OP_VDUP2, 3372 OP_VDUP3, 3373 OP_VEXT1, 3374 OP_VEXT2, 3375 OP_VEXT3, 3376 OP_VUZPL, // VUZP, left result 3377 OP_VUZPR, // VUZP, right result 3378 OP_VZIPL, // VZIP, left result 3379 OP_VZIPR, // VZIP, right result 3380 OP_VTRNL, // VTRN, left result 3381 OP_VTRNR // VTRN, right result 3382 }; 3383 3384 if (OpNum == OP_COPY) { 3385 if (LHSID == (1*9+2)*9+3) return LHS; 3386 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3387 return RHS; 3388 } 3389 3390 SDValue OpLHS, OpRHS; 3391 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 3392 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 3393 EVT VT = OpLHS.getValueType(); 3394 3395 switch (OpNum) { 3396 default: llvm_unreachable("Unknown shuffle opcode!"); 3397 case OP_VREV: 3398 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 3399 case OP_VDUP0: 3400 case OP_VDUP1: 3401 case OP_VDUP2: 3402 case OP_VDUP3: 3403 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 3404 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 3405 case OP_VEXT1: 3406 case OP_VEXT2: 3407 case OP_VEXT3: 3408 return DAG.getNode(ARMISD::VEXT, dl, VT, 3409 OpLHS, OpRHS, 3410 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 3411 case OP_VUZPL: 3412 case OP_VUZPR: 3413 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3414 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 3415 case OP_VZIPL: 3416 case OP_VZIPR: 3417 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3418 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 3419 case OP_VTRNL: 3420 case OP_VTRNR: 3421 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3422 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 3423 } 3424} 3425 3426static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 3427 SDValue V1 = Op.getOperand(0); 3428 SDValue V2 = Op.getOperand(1); 3429 DebugLoc dl = Op.getDebugLoc(); 3430 EVT VT = Op.getValueType(); 3431 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 3432 SmallVector<int, 8> ShuffleMask; 3433 3434 // Convert shuffles that are directly supported on NEON to target-specific 3435 // DAG nodes, instead of keeping them as shuffles and matching them again 3436 // during code selection. This is more efficient and avoids the possibility 3437 // of inconsistencies between legalization and selection. 3438 // FIXME: floating-point vectors should be canonicalized to integer vectors 3439 // of the same time so that they get CSEd properly. 3440 SVN->getMask(ShuffleMask); 3441 3442 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3443 if (EltSize <= 32) { 3444 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 3445 int Lane = SVN->getSplatIndex(); 3446 // If this is undef splat, generate it via "just" vdup, if possible. 3447 if (Lane == -1) Lane = 0; 3448 3449 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3450 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 3451 } 3452 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 3453 DAG.getConstant(Lane, MVT::i32)); 3454 } 3455 3456 bool ReverseVEXT; 3457 unsigned Imm; 3458 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 3459 if (ReverseVEXT) 3460 std::swap(V1, V2); 3461 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 3462 DAG.getConstant(Imm, MVT::i32)); 3463 } 3464 3465 if (isVREVMask(ShuffleMask, VT, 64)) 3466 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 3467 if (isVREVMask(ShuffleMask, VT, 32)) 3468 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 3469 if (isVREVMask(ShuffleMask, VT, 16)) 3470 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 3471 3472 // Check for Neon shuffles that modify both input vectors in place. 3473 // If both results are used, i.e., if there are two shuffles with the same 3474 // source operands and with masks corresponding to both results of one of 3475 // these operations, DAG memoization will ensure that a single node is 3476 // used for both shuffles. 3477 unsigned WhichResult; 3478 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 3479 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3480 V1, V2).getValue(WhichResult); 3481 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 3482 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3483 V1, V2).getValue(WhichResult); 3484 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 3485 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3486 V1, V2).getValue(WhichResult); 3487 3488 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3489 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3490 V1, V1).getValue(WhichResult); 3491 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3492 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3493 V1, V1).getValue(WhichResult); 3494 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3495 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3496 V1, V1).getValue(WhichResult); 3497 } 3498 3499 // If the shuffle is not directly supported and it has 4 elements, use 3500 // the PerfectShuffle-generated table to synthesize it from other shuffles. 3501 unsigned NumElts = VT.getVectorNumElements(); 3502 if (NumElts == 4) { 3503 unsigned PFIndexes[4]; 3504 for (unsigned i = 0; i != 4; ++i) { 3505 if (ShuffleMask[i] < 0) 3506 PFIndexes[i] = 8; 3507 else 3508 PFIndexes[i] = ShuffleMask[i]; 3509 } 3510 3511 // Compute the index in the perfect shuffle table. 3512 unsigned PFTableIndex = 3513 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3514 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3515 unsigned Cost = (PFEntry >> 30); 3516 3517 if (Cost <= 4) 3518 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 3519 } 3520 3521 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 3522 if (EltSize >= 32) { 3523 // Do the expansion with floating-point types, since that is what the VFP 3524 // registers are defined to use, and since i64 is not legal. 3525 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3526 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3527 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1); 3528 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2); 3529 SmallVector<SDValue, 8> Ops; 3530 for (unsigned i = 0; i < NumElts; ++i) { 3531 if (ShuffleMask[i] < 0) 3532 Ops.push_back(DAG.getUNDEF(EltVT)); 3533 else 3534 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3535 ShuffleMask[i] < (int)NumElts ? V1 : V2, 3536 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 3537 MVT::i32))); 3538 } 3539 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3540 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3541 } 3542 3543 return SDValue(); 3544} 3545 3546static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 3547 EVT VT = Op.getValueType(); 3548 DebugLoc dl = Op.getDebugLoc(); 3549 SDValue Vec = Op.getOperand(0); 3550 SDValue Lane = Op.getOperand(1); 3551 assert(VT == MVT::i32 && 3552 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && 3553 "unexpected type for custom-lowering vector extract"); 3554 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 3555} 3556 3557static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3558 // The only time a CONCAT_VECTORS operation can have legal types is when 3559 // two 64-bit vectors are concatenated to a 128-bit vector. 3560 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 3561 "unexpected CONCAT_VECTORS"); 3562 DebugLoc dl = Op.getDebugLoc(); 3563 SDValue Val = DAG.getUNDEF(MVT::v2f64); 3564 SDValue Op0 = Op.getOperand(0); 3565 SDValue Op1 = Op.getOperand(1); 3566 if (Op0.getOpcode() != ISD::UNDEF) 3567 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3568 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), 3569 DAG.getIntPtrConstant(0)); 3570 if (Op1.getOpcode() != ISD::UNDEF) 3571 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3572 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), 3573 DAG.getIntPtrConstant(1)); 3574 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); 3575} 3576 3577SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 3578 switch (Op.getOpcode()) { 3579 default: llvm_unreachable("Don't know how to custom lower this!"); 3580 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3581 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 3582 case ISD::GlobalAddress: 3583 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 3584 LowerGlobalAddressELF(Op, DAG); 3585 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3586 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3587 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 3588 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 3589 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 3590 case ISD::VASTART: return LowerVASTART(Op, DAG); 3591 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 3592 case ISD::SINT_TO_FP: 3593 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 3594 case ISD::FP_TO_SINT: 3595 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 3596 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 3597 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3598 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3599 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 3600 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 3601 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 3602 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 3603 Subtarget); 3604 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 3605 case ISD::SHL: 3606 case ISD::SRL: 3607 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 3608 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 3609 case ISD::SRL_PARTS: 3610 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 3611 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 3612 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 3613 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3614 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3615 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 3616 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 3617 } 3618 return SDValue(); 3619} 3620 3621/// ReplaceNodeResults - Replace the results of node with an illegal result 3622/// type with new values built out of custom code. 3623void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 3624 SmallVectorImpl<SDValue>&Results, 3625 SelectionDAG &DAG) const { 3626 SDValue Res; 3627 switch (N->getOpcode()) { 3628 default: 3629 llvm_unreachable("Don't know how to custom expand this!"); 3630 break; 3631 case ISD::BIT_CONVERT: 3632 Res = ExpandBIT_CONVERT(N, DAG); 3633 break; 3634 case ISD::SRL: 3635 case ISD::SRA: 3636 Res = LowerShift(N, DAG, Subtarget); 3637 break; 3638 } 3639 if (Res.getNode()) 3640 Results.push_back(Res); 3641} 3642 3643//===----------------------------------------------------------------------===// 3644// ARM Scheduler Hooks 3645//===----------------------------------------------------------------------===// 3646 3647MachineBasicBlock * 3648ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 3649 MachineBasicBlock *BB, 3650 unsigned Size) const { 3651 unsigned dest = MI->getOperand(0).getReg(); 3652 unsigned ptr = MI->getOperand(1).getReg(); 3653 unsigned oldval = MI->getOperand(2).getReg(); 3654 unsigned newval = MI->getOperand(3).getReg(); 3655 unsigned scratch = BB->getParent()->getRegInfo() 3656 .createVirtualRegister(ARM::GPRRegisterClass); 3657 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3658 DebugLoc dl = MI->getDebugLoc(); 3659 bool isThumb2 = Subtarget->isThumb2(); 3660 3661 unsigned ldrOpc, strOpc; 3662 switch (Size) { 3663 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3664 case 1: 3665 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3666 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB; 3667 break; 3668 case 2: 3669 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3670 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3671 break; 3672 case 4: 3673 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3674 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3675 break; 3676 } 3677 3678 MachineFunction *MF = BB->getParent(); 3679 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3680 MachineFunction::iterator It = BB; 3681 ++It; // insert the new blocks after the current block 3682 3683 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3684 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3685 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3686 MF->insert(It, loop1MBB); 3687 MF->insert(It, loop2MBB); 3688 MF->insert(It, exitMBB); 3689 3690 // Transfer the remainder of BB and its successor edges to exitMBB. 3691 exitMBB->splice(exitMBB->begin(), BB, 3692 llvm::next(MachineBasicBlock::iterator(MI)), 3693 BB->end()); 3694 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3695 3696 // thisMBB: 3697 // ... 3698 // fallthrough --> loop1MBB 3699 BB->addSuccessor(loop1MBB); 3700 3701 // loop1MBB: 3702 // ldrex dest, [ptr] 3703 // cmp dest, oldval 3704 // bne exitMBB 3705 BB = loop1MBB; 3706 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 3707 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 3708 .addReg(dest).addReg(oldval)); 3709 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3710 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3711 BB->addSuccessor(loop2MBB); 3712 BB->addSuccessor(exitMBB); 3713 3714 // loop2MBB: 3715 // strex scratch, newval, [ptr] 3716 // cmp scratch, #0 3717 // bne loop1MBB 3718 BB = loop2MBB; 3719 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval) 3720 .addReg(ptr)); 3721 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 3722 .addReg(scratch).addImm(0)); 3723 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3724 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3725 BB->addSuccessor(loop1MBB); 3726 BB->addSuccessor(exitMBB); 3727 3728 // exitMBB: 3729 // ... 3730 BB = exitMBB; 3731 3732 MI->eraseFromParent(); // The instruction is gone now. 3733 3734 return BB; 3735} 3736 3737MachineBasicBlock * 3738ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 3739 unsigned Size, unsigned BinOpcode) const { 3740 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3741 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3742 3743 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3744 MachineFunction *MF = BB->getParent(); 3745 MachineFunction::iterator It = BB; 3746 ++It; 3747 3748 unsigned dest = MI->getOperand(0).getReg(); 3749 unsigned ptr = MI->getOperand(1).getReg(); 3750 unsigned incr = MI->getOperand(2).getReg(); 3751 DebugLoc dl = MI->getDebugLoc(); 3752 3753 bool isThumb2 = Subtarget->isThumb2(); 3754 unsigned ldrOpc, strOpc; 3755 switch (Size) { 3756 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3757 case 1: 3758 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3759 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 3760 break; 3761 case 2: 3762 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3763 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3764 break; 3765 case 4: 3766 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3767 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3768 break; 3769 } 3770 3771 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3772 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3773 MF->insert(It, loopMBB); 3774 MF->insert(It, exitMBB); 3775 3776 // Transfer the remainder of BB and its successor edges to exitMBB. 3777 exitMBB->splice(exitMBB->begin(), BB, 3778 llvm::next(MachineBasicBlock::iterator(MI)), 3779 BB->end()); 3780 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3781 3782 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3783 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 3784 unsigned scratch2 = (!BinOpcode) ? incr : 3785 RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 3786 3787 // thisMBB: 3788 // ... 3789 // fallthrough --> loopMBB 3790 BB->addSuccessor(loopMBB); 3791 3792 // loopMBB: 3793 // ldrex dest, ptr 3794 // <binop> scratch2, dest, incr 3795 // strex scratch, scratch2, ptr 3796 // cmp scratch, #0 3797 // bne- loopMBB 3798 // fallthrough --> exitMBB 3799 BB = loopMBB; 3800 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 3801 if (BinOpcode) { 3802 // operand order needs to go the other way for NAND 3803 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 3804 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 3805 addReg(incr).addReg(dest)).addReg(0); 3806 else 3807 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 3808 addReg(dest).addReg(incr)).addReg(0); 3809 } 3810 3811 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2) 3812 .addReg(ptr)); 3813 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 3814 .addReg(scratch).addImm(0)); 3815 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3816 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3817 3818 BB->addSuccessor(loopMBB); 3819 BB->addSuccessor(exitMBB); 3820 3821 // exitMBB: 3822 // ... 3823 BB = exitMBB; 3824 3825 MI->eraseFromParent(); // The instruction is gone now. 3826 3827 return BB; 3828} 3829 3830MachineBasicBlock * 3831ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3832 MachineBasicBlock *BB) const { 3833 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3834 DebugLoc dl = MI->getDebugLoc(); 3835 bool isThumb2 = Subtarget->isThumb2(); 3836 switch (MI->getOpcode()) { 3837 default: 3838 MI->dump(); 3839 llvm_unreachable("Unexpected instr type to insert"); 3840 3841 case ARM::ATOMIC_LOAD_ADD_I8: 3842 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3843 case ARM::ATOMIC_LOAD_ADD_I16: 3844 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3845 case ARM::ATOMIC_LOAD_ADD_I32: 3846 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3847 3848 case ARM::ATOMIC_LOAD_AND_I8: 3849 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3850 case ARM::ATOMIC_LOAD_AND_I16: 3851 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3852 case ARM::ATOMIC_LOAD_AND_I32: 3853 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3854 3855 case ARM::ATOMIC_LOAD_OR_I8: 3856 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3857 case ARM::ATOMIC_LOAD_OR_I16: 3858 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3859 case ARM::ATOMIC_LOAD_OR_I32: 3860 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3861 3862 case ARM::ATOMIC_LOAD_XOR_I8: 3863 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3864 case ARM::ATOMIC_LOAD_XOR_I16: 3865 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3866 case ARM::ATOMIC_LOAD_XOR_I32: 3867 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3868 3869 case ARM::ATOMIC_LOAD_NAND_I8: 3870 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3871 case ARM::ATOMIC_LOAD_NAND_I16: 3872 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3873 case ARM::ATOMIC_LOAD_NAND_I32: 3874 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3875 3876 case ARM::ATOMIC_LOAD_SUB_I8: 3877 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3878 case ARM::ATOMIC_LOAD_SUB_I16: 3879 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3880 case ARM::ATOMIC_LOAD_SUB_I32: 3881 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3882 3883 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 3884 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 3885 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 3886 3887 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 3888 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 3889 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 3890 3891 case ARM::tMOVCCr_pseudo: { 3892 // To "insert" a SELECT_CC instruction, we actually have to insert the 3893 // diamond control-flow pattern. The incoming instruction knows the 3894 // destination vreg to set, the condition code register to branch on, the 3895 // true/false values to select between, and a branch opcode to use. 3896 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3897 MachineFunction::iterator It = BB; 3898 ++It; 3899 3900 // thisMBB: 3901 // ... 3902 // TrueVal = ... 3903 // cmpTY ccX, r1, r2 3904 // bCC copy1MBB 3905 // fallthrough --> copy0MBB 3906 MachineBasicBlock *thisMBB = BB; 3907 MachineFunction *F = BB->getParent(); 3908 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3909 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3910 F->insert(It, copy0MBB); 3911 F->insert(It, sinkMBB); 3912 3913 // Transfer the remainder of BB and its successor edges to sinkMBB. 3914 sinkMBB->splice(sinkMBB->begin(), BB, 3915 llvm::next(MachineBasicBlock::iterator(MI)), 3916 BB->end()); 3917 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3918 3919 BB->addSuccessor(copy0MBB); 3920 BB->addSuccessor(sinkMBB); 3921 3922 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 3923 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 3924 3925 // copy0MBB: 3926 // %FalseValue = ... 3927 // # fallthrough to sinkMBB 3928 BB = copy0MBB; 3929 3930 // Update machine-CFG edges 3931 BB->addSuccessor(sinkMBB); 3932 3933 // sinkMBB: 3934 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3935 // ... 3936 BB = sinkMBB; 3937 BuildMI(*BB, BB->begin(), dl, 3938 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 3939 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 3940 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3941 3942 MI->eraseFromParent(); // The pseudo instruction is gone now. 3943 return BB; 3944 } 3945 3946 case ARM::tANDsp: 3947 case ARM::tADDspr_: 3948 case ARM::tSUBspi_: 3949 case ARM::t2SUBrSPi_: 3950 case ARM::t2SUBrSPi12_: 3951 case ARM::t2SUBrSPs_: { 3952 MachineFunction *MF = BB->getParent(); 3953 unsigned DstReg = MI->getOperand(0).getReg(); 3954 unsigned SrcReg = MI->getOperand(1).getReg(); 3955 bool DstIsDead = MI->getOperand(0).isDead(); 3956 bool SrcIsKill = MI->getOperand(1).isKill(); 3957 3958 if (SrcReg != ARM::SP) { 3959 // Copy the source to SP from virtual register. 3960 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg); 3961 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 3962 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr; 3963 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP) 3964 .addReg(SrcReg, getKillRegState(SrcIsKill)); 3965 } 3966 3967 unsigned OpOpc = 0; 3968 bool NeedPred = false, NeedCC = false, NeedOp3 = false; 3969 switch (MI->getOpcode()) { 3970 default: 3971 llvm_unreachable("Unexpected pseudo instruction!"); 3972 case ARM::tANDsp: 3973 OpOpc = ARM::tAND; 3974 NeedPred = true; 3975 break; 3976 case ARM::tADDspr_: 3977 OpOpc = ARM::tADDspr; 3978 break; 3979 case ARM::tSUBspi_: 3980 OpOpc = ARM::tSUBspi; 3981 break; 3982 case ARM::t2SUBrSPi_: 3983 OpOpc = ARM::t2SUBrSPi; 3984 NeedPred = true; NeedCC = true; 3985 break; 3986 case ARM::t2SUBrSPi12_: 3987 OpOpc = ARM::t2SUBrSPi12; 3988 NeedPred = true; 3989 break; 3990 case ARM::t2SUBrSPs_: 3991 OpOpc = ARM::t2SUBrSPs; 3992 NeedPred = true; NeedCC = true; NeedOp3 = true; 3993 break; 3994 } 3995 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP); 3996 if (OpOpc == ARM::tAND) 3997 AddDefaultT1CC(MIB); 3998 MIB.addReg(ARM::SP); 3999 MIB.addOperand(MI->getOperand(2)); 4000 if (NeedOp3) 4001 MIB.addOperand(MI->getOperand(3)); 4002 if (NeedPred) 4003 AddDefaultPred(MIB); 4004 if (NeedCC) 4005 AddDefaultCC(MIB); 4006 4007 // Copy the result from SP to virtual register. 4008 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg); 4009 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 4010 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr; 4011 BuildMI(*BB, MI, dl, TII->get(CopyOpc)) 4012 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) 4013 .addReg(ARM::SP); 4014 MI->eraseFromParent(); // The pseudo instruction is gone now. 4015 return BB; 4016 } 4017 } 4018} 4019 4020//===----------------------------------------------------------------------===// 4021// ARM Optimization Hooks 4022//===----------------------------------------------------------------------===// 4023 4024static 4025SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 4026 TargetLowering::DAGCombinerInfo &DCI) { 4027 SelectionDAG &DAG = DCI.DAG; 4028 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4029 EVT VT = N->getValueType(0); 4030 unsigned Opc = N->getOpcode(); 4031 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 4032 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 4033 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 4034 ISD::CondCode CC = ISD::SETCC_INVALID; 4035 4036 if (isSlctCC) { 4037 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 4038 } else { 4039 SDValue CCOp = Slct.getOperand(0); 4040 if (CCOp.getOpcode() == ISD::SETCC) 4041 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 4042 } 4043 4044 bool DoXform = false; 4045 bool InvCC = false; 4046 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 4047 "Bad input!"); 4048 4049 if (LHS.getOpcode() == ISD::Constant && 4050 cast<ConstantSDNode>(LHS)->isNullValue()) { 4051 DoXform = true; 4052 } else if (CC != ISD::SETCC_INVALID && 4053 RHS.getOpcode() == ISD::Constant && 4054 cast<ConstantSDNode>(RHS)->isNullValue()) { 4055 std::swap(LHS, RHS); 4056 SDValue Op0 = Slct.getOperand(0); 4057 EVT OpVT = isSlctCC ? Op0.getValueType() : 4058 Op0.getOperand(0).getValueType(); 4059 bool isInt = OpVT.isInteger(); 4060 CC = ISD::getSetCCInverse(CC, isInt); 4061 4062 if (!TLI.isCondCodeLegal(CC, OpVT)) 4063 return SDValue(); // Inverse operator isn't legal. 4064 4065 DoXform = true; 4066 InvCC = true; 4067 } 4068 4069 if (DoXform) { 4070 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 4071 if (isSlctCC) 4072 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 4073 Slct.getOperand(0), Slct.getOperand(1), CC); 4074 SDValue CCOp = Slct.getOperand(0); 4075 if (InvCC) 4076 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 4077 CCOp.getOperand(0), CCOp.getOperand(1), CC); 4078 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4079 CCOp, OtherOp, Result); 4080 } 4081 return SDValue(); 4082} 4083 4084/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 4085static SDValue PerformADDCombine(SDNode *N, 4086 TargetLowering::DAGCombinerInfo &DCI) { 4087 // added by evan in r37685 with no testcase. 4088 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 4089 4090 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 4091 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 4092 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 4093 if (Result.getNode()) return Result; 4094 } 4095 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 4096 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 4097 if (Result.getNode()) return Result; 4098 } 4099 4100 return SDValue(); 4101} 4102 4103/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 4104static SDValue PerformSUBCombine(SDNode *N, 4105 TargetLowering::DAGCombinerInfo &DCI) { 4106 // added by evan in r37685 with no testcase. 4107 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 4108 4109 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 4110 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 4111 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 4112 if (Result.getNode()) return Result; 4113 } 4114 4115 return SDValue(); 4116} 4117 4118static SDValue PerformMULCombine(SDNode *N, 4119 TargetLowering::DAGCombinerInfo &DCI, 4120 const ARMSubtarget *Subtarget) { 4121 SelectionDAG &DAG = DCI.DAG; 4122 4123 if (Subtarget->isThumb1Only()) 4124 return SDValue(); 4125 4126 if (DAG.getMachineFunction(). 4127 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 4128 return SDValue(); 4129 4130 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 4131 return SDValue(); 4132 4133 EVT VT = N->getValueType(0); 4134 if (VT != MVT::i32) 4135 return SDValue(); 4136 4137 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 4138 if (!C) 4139 return SDValue(); 4140 4141 uint64_t MulAmt = C->getZExtValue(); 4142 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 4143 ShiftAmt = ShiftAmt & (32 - 1); 4144 SDValue V = N->getOperand(0); 4145 DebugLoc DL = N->getDebugLoc(); 4146 4147 SDValue Res; 4148 MulAmt >>= ShiftAmt; 4149 if (isPowerOf2_32(MulAmt - 1)) { 4150 // (mul x, 2^N + 1) => (add (shl x, N), x) 4151 Res = DAG.getNode(ISD::ADD, DL, VT, 4152 V, DAG.getNode(ISD::SHL, DL, VT, 4153 V, DAG.getConstant(Log2_32(MulAmt-1), 4154 MVT::i32))); 4155 } else if (isPowerOf2_32(MulAmt + 1)) { 4156 // (mul x, 2^N - 1) => (sub (shl x, N), x) 4157 Res = DAG.getNode(ISD::SUB, DL, VT, 4158 DAG.getNode(ISD::SHL, DL, VT, 4159 V, DAG.getConstant(Log2_32(MulAmt+1), 4160 MVT::i32)), 4161 V); 4162 } else 4163 return SDValue(); 4164 4165 if (ShiftAmt != 0) 4166 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 4167 DAG.getConstant(ShiftAmt, MVT::i32)); 4168 4169 // Do not add new nodes to DAG combiner worklist. 4170 DCI.CombineTo(N, Res, false); 4171 return SDValue(); 4172} 4173 4174/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 4175/// ARMISD::VMOVRRD. 4176static SDValue PerformVMOVRRDCombine(SDNode *N, 4177 TargetLowering::DAGCombinerInfo &DCI) { 4178 // fmrrd(fmdrr x, y) -> x,y 4179 SDValue InDouble = N->getOperand(0); 4180 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 4181 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 4182 return SDValue(); 4183} 4184 4185/// getVShiftImm - Check if this is a valid build_vector for the immediate 4186/// operand of a vector shift operation, where all the elements of the 4187/// build_vector must have the same constant integer value. 4188static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 4189 // Ignore bit_converts. 4190 while (Op.getOpcode() == ISD::BIT_CONVERT) 4191 Op = Op.getOperand(0); 4192 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4193 APInt SplatBits, SplatUndef; 4194 unsigned SplatBitSize; 4195 bool HasAnyUndefs; 4196 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 4197 HasAnyUndefs, ElementBits) || 4198 SplatBitSize > ElementBits) 4199 return false; 4200 Cnt = SplatBits.getSExtValue(); 4201 return true; 4202} 4203 4204/// isVShiftLImm - Check if this is a valid build_vector for the immediate 4205/// operand of a vector shift left operation. That value must be in the range: 4206/// 0 <= Value < ElementBits for a left shift; or 4207/// 0 <= Value <= ElementBits for a long left shift. 4208static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 4209 assert(VT.isVector() && "vector shift count is not a vector type"); 4210 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4211 if (! getVShiftImm(Op, ElementBits, Cnt)) 4212 return false; 4213 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 4214} 4215 4216/// isVShiftRImm - Check if this is a valid build_vector for the immediate 4217/// operand of a vector shift right operation. For a shift opcode, the value 4218/// is positive, but for an intrinsic the value count must be negative. The 4219/// absolute value must be in the range: 4220/// 1 <= |Value| <= ElementBits for a right shift; or 4221/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 4222static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 4223 int64_t &Cnt) { 4224 assert(VT.isVector() && "vector shift count is not a vector type"); 4225 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4226 if (! getVShiftImm(Op, ElementBits, Cnt)) 4227 return false; 4228 if (isIntrinsic) 4229 Cnt = -Cnt; 4230 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 4231} 4232 4233/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 4234static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 4235 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 4236 switch (IntNo) { 4237 default: 4238 // Don't do anything for most intrinsics. 4239 break; 4240 4241 // Vector shifts: check for immediate versions and lower them. 4242 // Note: This is done during DAG combining instead of DAG legalizing because 4243 // the build_vectors for 64-bit vector element shift counts are generally 4244 // not legal, and it is hard to see their values after they get legalized to 4245 // loads from a constant pool. 4246 case Intrinsic::arm_neon_vshifts: 4247 case Intrinsic::arm_neon_vshiftu: 4248 case Intrinsic::arm_neon_vshiftls: 4249 case Intrinsic::arm_neon_vshiftlu: 4250 case Intrinsic::arm_neon_vshiftn: 4251 case Intrinsic::arm_neon_vrshifts: 4252 case Intrinsic::arm_neon_vrshiftu: 4253 case Intrinsic::arm_neon_vrshiftn: 4254 case Intrinsic::arm_neon_vqshifts: 4255 case Intrinsic::arm_neon_vqshiftu: 4256 case Intrinsic::arm_neon_vqshiftsu: 4257 case Intrinsic::arm_neon_vqshiftns: 4258 case Intrinsic::arm_neon_vqshiftnu: 4259 case Intrinsic::arm_neon_vqshiftnsu: 4260 case Intrinsic::arm_neon_vqrshiftns: 4261 case Intrinsic::arm_neon_vqrshiftnu: 4262 case Intrinsic::arm_neon_vqrshiftnsu: { 4263 EVT VT = N->getOperand(1).getValueType(); 4264 int64_t Cnt; 4265 unsigned VShiftOpc = 0; 4266 4267 switch (IntNo) { 4268 case Intrinsic::arm_neon_vshifts: 4269 case Intrinsic::arm_neon_vshiftu: 4270 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 4271 VShiftOpc = ARMISD::VSHL; 4272 break; 4273 } 4274 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 4275 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 4276 ARMISD::VSHRs : ARMISD::VSHRu); 4277 break; 4278 } 4279 return SDValue(); 4280 4281 case Intrinsic::arm_neon_vshiftls: 4282 case Intrinsic::arm_neon_vshiftlu: 4283 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 4284 break; 4285 llvm_unreachable("invalid shift count for vshll intrinsic"); 4286 4287 case Intrinsic::arm_neon_vrshifts: 4288 case Intrinsic::arm_neon_vrshiftu: 4289 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 4290 break; 4291 return SDValue(); 4292 4293 case Intrinsic::arm_neon_vqshifts: 4294 case Intrinsic::arm_neon_vqshiftu: 4295 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4296 break; 4297 return SDValue(); 4298 4299 case Intrinsic::arm_neon_vqshiftsu: 4300 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4301 break; 4302 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 4303 4304 case Intrinsic::arm_neon_vshiftn: 4305 case Intrinsic::arm_neon_vrshiftn: 4306 case Intrinsic::arm_neon_vqshiftns: 4307 case Intrinsic::arm_neon_vqshiftnu: 4308 case Intrinsic::arm_neon_vqshiftnsu: 4309 case Intrinsic::arm_neon_vqrshiftns: 4310 case Intrinsic::arm_neon_vqrshiftnu: 4311 case Intrinsic::arm_neon_vqrshiftnsu: 4312 // Narrowing shifts require an immediate right shift. 4313 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 4314 break; 4315 llvm_unreachable("invalid shift count for narrowing vector shift " 4316 "intrinsic"); 4317 4318 default: 4319 llvm_unreachable("unhandled vector shift"); 4320 } 4321 4322 switch (IntNo) { 4323 case Intrinsic::arm_neon_vshifts: 4324 case Intrinsic::arm_neon_vshiftu: 4325 // Opcode already set above. 4326 break; 4327 case Intrinsic::arm_neon_vshiftls: 4328 case Intrinsic::arm_neon_vshiftlu: 4329 if (Cnt == VT.getVectorElementType().getSizeInBits()) 4330 VShiftOpc = ARMISD::VSHLLi; 4331 else 4332 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 4333 ARMISD::VSHLLs : ARMISD::VSHLLu); 4334 break; 4335 case Intrinsic::arm_neon_vshiftn: 4336 VShiftOpc = ARMISD::VSHRN; break; 4337 case Intrinsic::arm_neon_vrshifts: 4338 VShiftOpc = ARMISD::VRSHRs; break; 4339 case Intrinsic::arm_neon_vrshiftu: 4340 VShiftOpc = ARMISD::VRSHRu; break; 4341 case Intrinsic::arm_neon_vrshiftn: 4342 VShiftOpc = ARMISD::VRSHRN; break; 4343 case Intrinsic::arm_neon_vqshifts: 4344 VShiftOpc = ARMISD::VQSHLs; break; 4345 case Intrinsic::arm_neon_vqshiftu: 4346 VShiftOpc = ARMISD::VQSHLu; break; 4347 case Intrinsic::arm_neon_vqshiftsu: 4348 VShiftOpc = ARMISD::VQSHLsu; break; 4349 case Intrinsic::arm_neon_vqshiftns: 4350 VShiftOpc = ARMISD::VQSHRNs; break; 4351 case Intrinsic::arm_neon_vqshiftnu: 4352 VShiftOpc = ARMISD::VQSHRNu; break; 4353 case Intrinsic::arm_neon_vqshiftnsu: 4354 VShiftOpc = ARMISD::VQSHRNsu; break; 4355 case Intrinsic::arm_neon_vqrshiftns: 4356 VShiftOpc = ARMISD::VQRSHRNs; break; 4357 case Intrinsic::arm_neon_vqrshiftnu: 4358 VShiftOpc = ARMISD::VQRSHRNu; break; 4359 case Intrinsic::arm_neon_vqrshiftnsu: 4360 VShiftOpc = ARMISD::VQRSHRNsu; break; 4361 } 4362 4363 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4364 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 4365 } 4366 4367 case Intrinsic::arm_neon_vshiftins: { 4368 EVT VT = N->getOperand(1).getValueType(); 4369 int64_t Cnt; 4370 unsigned VShiftOpc = 0; 4371 4372 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 4373 VShiftOpc = ARMISD::VSLI; 4374 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 4375 VShiftOpc = ARMISD::VSRI; 4376 else { 4377 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 4378 } 4379 4380 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4381 N->getOperand(1), N->getOperand(2), 4382 DAG.getConstant(Cnt, MVT::i32)); 4383 } 4384 4385 case Intrinsic::arm_neon_vqrshifts: 4386 case Intrinsic::arm_neon_vqrshiftu: 4387 // No immediate versions of these to check for. 4388 break; 4389 } 4390 4391 return SDValue(); 4392} 4393 4394/// PerformShiftCombine - Checks for immediate versions of vector shifts and 4395/// lowers them. As with the vector shift intrinsics, this is done during DAG 4396/// combining instead of DAG legalizing because the build_vectors for 64-bit 4397/// vector element shift counts are generally not legal, and it is hard to see 4398/// their values after they get legalized to loads from a constant pool. 4399static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 4400 const ARMSubtarget *ST) { 4401 EVT VT = N->getValueType(0); 4402 4403 // Nothing to be done for scalar shifts. 4404 if (! VT.isVector()) 4405 return SDValue(); 4406 4407 assert(ST->hasNEON() && "unexpected vector shift"); 4408 int64_t Cnt; 4409 4410 switch (N->getOpcode()) { 4411 default: llvm_unreachable("unexpected shift opcode"); 4412 4413 case ISD::SHL: 4414 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 4415 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 4416 DAG.getConstant(Cnt, MVT::i32)); 4417 break; 4418 4419 case ISD::SRA: 4420 case ISD::SRL: 4421 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 4422 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 4423 ARMISD::VSHRs : ARMISD::VSHRu); 4424 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 4425 DAG.getConstant(Cnt, MVT::i32)); 4426 } 4427 } 4428 return SDValue(); 4429} 4430 4431/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 4432/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 4433static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 4434 const ARMSubtarget *ST) { 4435 SDValue N0 = N->getOperand(0); 4436 4437 // Check for sign- and zero-extensions of vector extract operations of 8- 4438 // and 16-bit vector elements. NEON supports these directly. They are 4439 // handled during DAG combining because type legalization will promote them 4440 // to 32-bit types and it is messy to recognize the operations after that. 4441 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 4442 SDValue Vec = N0.getOperand(0); 4443 SDValue Lane = N0.getOperand(1); 4444 EVT VT = N->getValueType(0); 4445 EVT EltVT = N0.getValueType(); 4446 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4447 4448 if (VT == MVT::i32 && 4449 (EltVT == MVT::i8 || EltVT == MVT::i16) && 4450 TLI.isTypeLegal(Vec.getValueType())) { 4451 4452 unsigned Opc = 0; 4453 switch (N->getOpcode()) { 4454 default: llvm_unreachable("unexpected opcode"); 4455 case ISD::SIGN_EXTEND: 4456 Opc = ARMISD::VGETLANEs; 4457 break; 4458 case ISD::ZERO_EXTEND: 4459 case ISD::ANY_EXTEND: 4460 Opc = ARMISD::VGETLANEu; 4461 break; 4462 } 4463 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 4464 } 4465 } 4466 4467 return SDValue(); 4468} 4469 4470/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 4471/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 4472static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 4473 const ARMSubtarget *ST) { 4474 // If the target supports NEON, try to use vmax/vmin instructions for f32 4475 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set, 4476 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 4477 // a NaN; only do the transformation when it matches that behavior. 4478 4479 // For now only do this when using NEON for FP operations; if using VFP, it 4480 // is not obvious that the benefit outweighs the cost of switching to the 4481 // NEON pipeline. 4482 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 4483 N->getValueType(0) != MVT::f32) 4484 return SDValue(); 4485 4486 SDValue CondLHS = N->getOperand(0); 4487 SDValue CondRHS = N->getOperand(1); 4488 SDValue LHS = N->getOperand(2); 4489 SDValue RHS = N->getOperand(3); 4490 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 4491 4492 unsigned Opcode = 0; 4493 bool IsReversed; 4494 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 4495 IsReversed = false; // x CC y ? x : y 4496 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 4497 IsReversed = true ; // x CC y ? y : x 4498 } else { 4499 return SDValue(); 4500 } 4501 4502 bool IsUnordered; 4503 switch (CC) { 4504 default: break; 4505 case ISD::SETOLT: 4506 case ISD::SETOLE: 4507 case ISD::SETLT: 4508 case ISD::SETLE: 4509 case ISD::SETULT: 4510 case ISD::SETULE: 4511 // If LHS is NaN, an ordered comparison will be false and the result will 4512 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 4513 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4514 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 4515 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4516 break; 4517 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 4518 // will return -0, so vmin can only be used for unsafe math or if one of 4519 // the operands is known to be nonzero. 4520 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 4521 !UnsafeFPMath && 4522 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4523 break; 4524 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 4525 break; 4526 4527 case ISD::SETOGT: 4528 case ISD::SETOGE: 4529 case ISD::SETGT: 4530 case ISD::SETGE: 4531 case ISD::SETUGT: 4532 case ISD::SETUGE: 4533 // If LHS is NaN, an ordered comparison will be false and the result will 4534 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 4535 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4536 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 4537 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4538 break; 4539 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 4540 // will return +0, so vmax can only be used for unsafe math or if one of 4541 // the operands is known to be nonzero. 4542 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 4543 !UnsafeFPMath && 4544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4545 break; 4546 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 4547 break; 4548 } 4549 4550 if (!Opcode) 4551 return SDValue(); 4552 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 4553} 4554 4555SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 4556 DAGCombinerInfo &DCI) const { 4557 switch (N->getOpcode()) { 4558 default: break; 4559 case ISD::ADD: return PerformADDCombine(N, DCI); 4560 case ISD::SUB: return PerformSUBCombine(N, DCI); 4561 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 4562 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 4563 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 4564 case ISD::SHL: 4565 case ISD::SRA: 4566 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 4567 case ISD::SIGN_EXTEND: 4568 case ISD::ZERO_EXTEND: 4569 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 4570 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 4571 } 4572 return SDValue(); 4573} 4574 4575bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 4576 if (!Subtarget->hasV6Ops()) 4577 // Pre-v6 does not support unaligned mem access. 4578 return false; 4579 4580 // v6+ may or may not support unaligned mem access depending on the system 4581 // configuration. 4582 // FIXME: This is pretty conservative. Should we provide cmdline option to 4583 // control the behaviour? 4584 if (!Subtarget->isTargetDarwin()) 4585 return false; 4586 4587 switch (VT.getSimpleVT().SimpleTy) { 4588 default: 4589 return false; 4590 case MVT::i8: 4591 case MVT::i16: 4592 case MVT::i32: 4593 return true; 4594 // FIXME: VLD1 etc with standard alignment is legal. 4595 } 4596} 4597 4598static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 4599 if (V < 0) 4600 return false; 4601 4602 unsigned Scale = 1; 4603 switch (VT.getSimpleVT().SimpleTy) { 4604 default: return false; 4605 case MVT::i1: 4606 case MVT::i8: 4607 // Scale == 1; 4608 break; 4609 case MVT::i16: 4610 // Scale == 2; 4611 Scale = 2; 4612 break; 4613 case MVT::i32: 4614 // Scale == 4; 4615 Scale = 4; 4616 break; 4617 } 4618 4619 if ((V & (Scale - 1)) != 0) 4620 return false; 4621 V /= Scale; 4622 return V == (V & ((1LL << 5) - 1)); 4623} 4624 4625static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 4626 const ARMSubtarget *Subtarget) { 4627 bool isNeg = false; 4628 if (V < 0) { 4629 isNeg = true; 4630 V = - V; 4631 } 4632 4633 switch (VT.getSimpleVT().SimpleTy) { 4634 default: return false; 4635 case MVT::i1: 4636 case MVT::i8: 4637 case MVT::i16: 4638 case MVT::i32: 4639 // + imm12 or - imm8 4640 if (isNeg) 4641 return V == (V & ((1LL << 8) - 1)); 4642 return V == (V & ((1LL << 12) - 1)); 4643 case MVT::f32: 4644 case MVT::f64: 4645 // Same as ARM mode. FIXME: NEON? 4646 if (!Subtarget->hasVFP2()) 4647 return false; 4648 if ((V & 3) != 0) 4649 return false; 4650 V >>= 2; 4651 return V == (V & ((1LL << 8) - 1)); 4652 } 4653} 4654 4655/// isLegalAddressImmediate - Return true if the integer value can be used 4656/// as the offset of the target addressing mode for load / store of the 4657/// given type. 4658static bool isLegalAddressImmediate(int64_t V, EVT VT, 4659 const ARMSubtarget *Subtarget) { 4660 if (V == 0) 4661 return true; 4662 4663 if (!VT.isSimple()) 4664 return false; 4665 4666 if (Subtarget->isThumb1Only()) 4667 return isLegalT1AddressImmediate(V, VT); 4668 else if (Subtarget->isThumb2()) 4669 return isLegalT2AddressImmediate(V, VT, Subtarget); 4670 4671 // ARM mode. 4672 if (V < 0) 4673 V = - V; 4674 switch (VT.getSimpleVT().SimpleTy) { 4675 default: return false; 4676 case MVT::i1: 4677 case MVT::i8: 4678 case MVT::i32: 4679 // +- imm12 4680 return V == (V & ((1LL << 12) - 1)); 4681 case MVT::i16: 4682 // +- imm8 4683 return V == (V & ((1LL << 8) - 1)); 4684 case MVT::f32: 4685 case MVT::f64: 4686 if (!Subtarget->hasVFP2()) // FIXME: NEON? 4687 return false; 4688 if ((V & 3) != 0) 4689 return false; 4690 V >>= 2; 4691 return V == (V & ((1LL << 8) - 1)); 4692 } 4693} 4694 4695bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 4696 EVT VT) const { 4697 int Scale = AM.Scale; 4698 if (Scale < 0) 4699 return false; 4700 4701 switch (VT.getSimpleVT().SimpleTy) { 4702 default: return false; 4703 case MVT::i1: 4704 case MVT::i8: 4705 case MVT::i16: 4706 case MVT::i32: 4707 if (Scale == 1) 4708 return true; 4709 // r + r << imm 4710 Scale = Scale & ~1; 4711 return Scale == 2 || Scale == 4 || Scale == 8; 4712 case MVT::i64: 4713 // r + r 4714 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 4715 return true; 4716 return false; 4717 case MVT::isVoid: 4718 // Note, we allow "void" uses (basically, uses that aren't loads or 4719 // stores), because arm allows folding a scale into many arithmetic 4720 // operations. This should be made more precise and revisited later. 4721 4722 // Allow r << imm, but the imm has to be a multiple of two. 4723 if (Scale & 1) return false; 4724 return isPowerOf2_32(Scale); 4725 } 4726} 4727 4728/// isLegalAddressingMode - Return true if the addressing mode represented 4729/// by AM is legal for this target, for a load/store of the specified type. 4730bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 4731 const Type *Ty) const { 4732 EVT VT = getValueType(Ty, true); 4733 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 4734 return false; 4735 4736 // Can never fold addr of global into load/store. 4737 if (AM.BaseGV) 4738 return false; 4739 4740 switch (AM.Scale) { 4741 case 0: // no scale reg, must be "r+i" or "r", or "i". 4742 break; 4743 case 1: 4744 if (Subtarget->isThumb1Only()) 4745 return false; 4746 // FALL THROUGH. 4747 default: 4748 // ARM doesn't support any R+R*scale+imm addr modes. 4749 if (AM.BaseOffs) 4750 return false; 4751 4752 if (!VT.isSimple()) 4753 return false; 4754 4755 if (Subtarget->isThumb2()) 4756 return isLegalT2ScaledAddressingMode(AM, VT); 4757 4758 int Scale = AM.Scale; 4759 switch (VT.getSimpleVT().SimpleTy) { 4760 default: return false; 4761 case MVT::i1: 4762 case MVT::i8: 4763 case MVT::i32: 4764 if (Scale < 0) Scale = -Scale; 4765 if (Scale == 1) 4766 return true; 4767 // r + r << imm 4768 return isPowerOf2_32(Scale & ~1); 4769 case MVT::i16: 4770 case MVT::i64: 4771 // r + r 4772 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 4773 return true; 4774 return false; 4775 4776 case MVT::isVoid: 4777 // Note, we allow "void" uses (basically, uses that aren't loads or 4778 // stores), because arm allows folding a scale into many arithmetic 4779 // operations. This should be made more precise and revisited later. 4780 4781 // Allow r << imm, but the imm has to be a multiple of two. 4782 if (Scale & 1) return false; 4783 return isPowerOf2_32(Scale); 4784 } 4785 break; 4786 } 4787 return true; 4788} 4789 4790/// isLegalICmpImmediate - Return true if the specified immediate is legal 4791/// icmp immediate, that is the target has icmp instructions which can compare 4792/// a register against the immediate without having to materialize the 4793/// immediate into a register. 4794bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 4795 if (!Subtarget->isThumb()) 4796 return ARM_AM::getSOImmVal(Imm) != -1; 4797 if (Subtarget->isThumb2()) 4798 return ARM_AM::getT2SOImmVal(Imm) != -1; 4799 return Imm >= 0 && Imm <= 255; 4800} 4801 4802static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 4803 bool isSEXTLoad, SDValue &Base, 4804 SDValue &Offset, bool &isInc, 4805 SelectionDAG &DAG) { 4806 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 4807 return false; 4808 4809 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 4810 // AddressingMode 3 4811 Base = Ptr->getOperand(0); 4812 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4813 int RHSC = (int)RHS->getZExtValue(); 4814 if (RHSC < 0 && RHSC > -256) { 4815 assert(Ptr->getOpcode() == ISD::ADD); 4816 isInc = false; 4817 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4818 return true; 4819 } 4820 } 4821 isInc = (Ptr->getOpcode() == ISD::ADD); 4822 Offset = Ptr->getOperand(1); 4823 return true; 4824 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 4825 // AddressingMode 2 4826 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4827 int RHSC = (int)RHS->getZExtValue(); 4828 if (RHSC < 0 && RHSC > -0x1000) { 4829 assert(Ptr->getOpcode() == ISD::ADD); 4830 isInc = false; 4831 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4832 Base = Ptr->getOperand(0); 4833 return true; 4834 } 4835 } 4836 4837 if (Ptr->getOpcode() == ISD::ADD) { 4838 isInc = true; 4839 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 4840 if (ShOpcVal != ARM_AM::no_shift) { 4841 Base = Ptr->getOperand(1); 4842 Offset = Ptr->getOperand(0); 4843 } else { 4844 Base = Ptr->getOperand(0); 4845 Offset = Ptr->getOperand(1); 4846 } 4847 return true; 4848 } 4849 4850 isInc = (Ptr->getOpcode() == ISD::ADD); 4851 Base = Ptr->getOperand(0); 4852 Offset = Ptr->getOperand(1); 4853 return true; 4854 } 4855 4856 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 4857 return false; 4858} 4859 4860static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 4861 bool isSEXTLoad, SDValue &Base, 4862 SDValue &Offset, bool &isInc, 4863 SelectionDAG &DAG) { 4864 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 4865 return false; 4866 4867 Base = Ptr->getOperand(0); 4868 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4869 int RHSC = (int)RHS->getZExtValue(); 4870 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 4871 assert(Ptr->getOpcode() == ISD::ADD); 4872 isInc = false; 4873 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4874 return true; 4875 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 4876 isInc = Ptr->getOpcode() == ISD::ADD; 4877 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 4878 return true; 4879 } 4880 } 4881 4882 return false; 4883} 4884 4885/// getPreIndexedAddressParts - returns true by value, base pointer and 4886/// offset pointer and addressing mode by reference if the node's address 4887/// can be legally represented as pre-indexed load / store address. 4888bool 4889ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 4890 SDValue &Offset, 4891 ISD::MemIndexedMode &AM, 4892 SelectionDAG &DAG) const { 4893 if (Subtarget->isThumb1Only()) 4894 return false; 4895 4896 EVT VT; 4897 SDValue Ptr; 4898 bool isSEXTLoad = false; 4899 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4900 Ptr = LD->getBasePtr(); 4901 VT = LD->getMemoryVT(); 4902 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 4903 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4904 Ptr = ST->getBasePtr(); 4905 VT = ST->getMemoryVT(); 4906 } else 4907 return false; 4908 4909 bool isInc; 4910 bool isLegal = false; 4911 if (Subtarget->isThumb2()) 4912 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 4913 Offset, isInc, DAG); 4914 else 4915 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 4916 Offset, isInc, DAG); 4917 if (!isLegal) 4918 return false; 4919 4920 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 4921 return true; 4922} 4923 4924/// getPostIndexedAddressParts - returns true by value, base pointer and 4925/// offset pointer and addressing mode by reference if this node can be 4926/// combined with a load / store to form a post-indexed load / store. 4927bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 4928 SDValue &Base, 4929 SDValue &Offset, 4930 ISD::MemIndexedMode &AM, 4931 SelectionDAG &DAG) const { 4932 if (Subtarget->isThumb1Only()) 4933 return false; 4934 4935 EVT VT; 4936 SDValue Ptr; 4937 bool isSEXTLoad = false; 4938 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4939 VT = LD->getMemoryVT(); 4940 Ptr = LD->getBasePtr(); 4941 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 4942 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4943 VT = ST->getMemoryVT(); 4944 Ptr = ST->getBasePtr(); 4945 } else 4946 return false; 4947 4948 bool isInc; 4949 bool isLegal = false; 4950 if (Subtarget->isThumb2()) 4951 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 4952 isInc, DAG); 4953 else 4954 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 4955 isInc, DAG); 4956 if (!isLegal) 4957 return false; 4958 4959 if (Ptr != Base) { 4960 // Swap base ptr and offset to catch more post-index load / store when 4961 // it's legal. In Thumb2 mode, offset must be an immediate. 4962 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 4963 !Subtarget->isThumb2()) 4964 std::swap(Base, Offset); 4965 4966 // Post-indexed load / store update the base pointer. 4967 if (Ptr != Base) 4968 return false; 4969 } 4970 4971 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 4972 return true; 4973} 4974 4975void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 4976 const APInt &Mask, 4977 APInt &KnownZero, 4978 APInt &KnownOne, 4979 const SelectionDAG &DAG, 4980 unsigned Depth) const { 4981 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 4982 switch (Op.getOpcode()) { 4983 default: break; 4984 case ARMISD::CMOV: { 4985 // Bits are known zero/one if known on the LHS and RHS. 4986 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 4987 if (KnownZero == 0 && KnownOne == 0) return; 4988 4989 APInt KnownZeroRHS, KnownOneRHS; 4990 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 4991 KnownZeroRHS, KnownOneRHS, Depth+1); 4992 KnownZero &= KnownZeroRHS; 4993 KnownOne &= KnownOneRHS; 4994 return; 4995 } 4996 } 4997} 4998 4999//===----------------------------------------------------------------------===// 5000// ARM Inline Assembly Support 5001//===----------------------------------------------------------------------===// 5002 5003/// getConstraintType - Given a constraint letter, return the type of 5004/// constraint it is for this target. 5005ARMTargetLowering::ConstraintType 5006ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 5007 if (Constraint.size() == 1) { 5008 switch (Constraint[0]) { 5009 default: break; 5010 case 'l': return C_RegisterClass; 5011 case 'w': return C_RegisterClass; 5012 } 5013 } 5014 return TargetLowering::getConstraintType(Constraint); 5015} 5016 5017std::pair<unsigned, const TargetRegisterClass*> 5018ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5019 EVT VT) const { 5020 if (Constraint.size() == 1) { 5021 // GCC ARM Constraint Letters 5022 switch (Constraint[0]) { 5023 case 'l': 5024 if (Subtarget->isThumb()) 5025 return std::make_pair(0U, ARM::tGPRRegisterClass); 5026 else 5027 return std::make_pair(0U, ARM::GPRRegisterClass); 5028 case 'r': 5029 return std::make_pair(0U, ARM::GPRRegisterClass); 5030 case 'w': 5031 if (VT == MVT::f32) 5032 return std::make_pair(0U, ARM::SPRRegisterClass); 5033 if (VT.getSizeInBits() == 64) 5034 return std::make_pair(0U, ARM::DPRRegisterClass); 5035 if (VT.getSizeInBits() == 128) 5036 return std::make_pair(0U, ARM::QPRRegisterClass); 5037 break; 5038 } 5039 } 5040 if (StringRef("{cc}").equals_lower(Constraint)) 5041 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 5042 5043 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5044} 5045 5046std::vector<unsigned> ARMTargetLowering:: 5047getRegClassForInlineAsmConstraint(const std::string &Constraint, 5048 EVT VT) const { 5049 if (Constraint.size() != 1) 5050 return std::vector<unsigned>(); 5051 5052 switch (Constraint[0]) { // GCC ARM Constraint Letters 5053 default: break; 5054 case 'l': 5055 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5056 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5057 0); 5058 case 'r': 5059 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5060 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5061 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 5062 ARM::R12, ARM::LR, 0); 5063 case 'w': 5064 if (VT == MVT::f32) 5065 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 5066 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 5067 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 5068 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 5069 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 5070 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 5071 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 5072 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 5073 if (VT.getSizeInBits() == 64) 5074 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 5075 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 5076 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 5077 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 5078 if (VT.getSizeInBits() == 128) 5079 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 5080 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0); 5081 break; 5082 } 5083 5084 return std::vector<unsigned>(); 5085} 5086 5087/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5088/// vector. If it is invalid, don't add anything to Ops. 5089void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5090 char Constraint, 5091 std::vector<SDValue>&Ops, 5092 SelectionDAG &DAG) const { 5093 SDValue Result(0, 0); 5094 5095 switch (Constraint) { 5096 default: break; 5097 case 'I': case 'J': case 'K': case 'L': 5098 case 'M': case 'N': case 'O': 5099 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 5100 if (!C) 5101 return; 5102 5103 int64_t CVal64 = C->getSExtValue(); 5104 int CVal = (int) CVal64; 5105 // None of these constraints allow values larger than 32 bits. Check 5106 // that the value fits in an int. 5107 if (CVal != CVal64) 5108 return; 5109 5110 switch (Constraint) { 5111 case 'I': 5112 if (Subtarget->isThumb1Only()) { 5113 // This must be a constant between 0 and 255, for ADD 5114 // immediates. 5115 if (CVal >= 0 && CVal <= 255) 5116 break; 5117 } else if (Subtarget->isThumb2()) { 5118 // A constant that can be used as an immediate value in a 5119 // data-processing instruction. 5120 if (ARM_AM::getT2SOImmVal(CVal) != -1) 5121 break; 5122 } else { 5123 // A constant that can be used as an immediate value in a 5124 // data-processing instruction. 5125 if (ARM_AM::getSOImmVal(CVal) != -1) 5126 break; 5127 } 5128 return; 5129 5130 case 'J': 5131 if (Subtarget->isThumb()) { // FIXME thumb2 5132 // This must be a constant between -255 and -1, for negated ADD 5133 // immediates. This can be used in GCC with an "n" modifier that 5134 // prints the negated value, for use with SUB instructions. It is 5135 // not useful otherwise but is implemented for compatibility. 5136 if (CVal >= -255 && CVal <= -1) 5137 break; 5138 } else { 5139 // This must be a constant between -4095 and 4095. It is not clear 5140 // what this constraint is intended for. Implemented for 5141 // compatibility with GCC. 5142 if (CVal >= -4095 && CVal <= 4095) 5143 break; 5144 } 5145 return; 5146 5147 case 'K': 5148 if (Subtarget->isThumb1Only()) { 5149 // A 32-bit value where only one byte has a nonzero value. Exclude 5150 // zero to match GCC. This constraint is used by GCC internally for 5151 // constants that can be loaded with a move/shift combination. 5152 // It is not useful otherwise but is implemented for compatibility. 5153 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 5154 break; 5155 } else if (Subtarget->isThumb2()) { 5156 // A constant whose bitwise inverse can be used as an immediate 5157 // value in a data-processing instruction. This can be used in GCC 5158 // with a "B" modifier that prints the inverted value, for use with 5159 // BIC and MVN instructions. It is not useful otherwise but is 5160 // implemented for compatibility. 5161 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 5162 break; 5163 } else { 5164 // A constant whose bitwise inverse can be used as an immediate 5165 // value in a data-processing instruction. This can be used in GCC 5166 // with a "B" modifier that prints the inverted value, for use with 5167 // BIC and MVN instructions. It is not useful otherwise but is 5168 // implemented for compatibility. 5169 if (ARM_AM::getSOImmVal(~CVal) != -1) 5170 break; 5171 } 5172 return; 5173 5174 case 'L': 5175 if (Subtarget->isThumb1Only()) { 5176 // This must be a constant between -7 and 7, 5177 // for 3-operand ADD/SUB immediate instructions. 5178 if (CVal >= -7 && CVal < 7) 5179 break; 5180 } else if (Subtarget->isThumb2()) { 5181 // A constant whose negation can be used as an immediate value in a 5182 // data-processing instruction. This can be used in GCC with an "n" 5183 // modifier that prints the negated value, for use with SUB 5184 // instructions. It is not useful otherwise but is implemented for 5185 // compatibility. 5186 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 5187 break; 5188 } else { 5189 // A constant whose negation can be used as an immediate value in a 5190 // data-processing instruction. This can be used in GCC with an "n" 5191 // modifier that prints the negated value, for use with SUB 5192 // instructions. It is not useful otherwise but is implemented for 5193 // compatibility. 5194 if (ARM_AM::getSOImmVal(-CVal) != -1) 5195 break; 5196 } 5197 return; 5198 5199 case 'M': 5200 if (Subtarget->isThumb()) { // FIXME thumb2 5201 // This must be a multiple of 4 between 0 and 1020, for 5202 // ADD sp + immediate. 5203 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 5204 break; 5205 } else { 5206 // A power of two or a constant between 0 and 32. This is used in 5207 // GCC for the shift amount on shifted register operands, but it is 5208 // useful in general for any shift amounts. 5209 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 5210 break; 5211 } 5212 return; 5213 5214 case 'N': 5215 if (Subtarget->isThumb()) { // FIXME thumb2 5216 // This must be a constant between 0 and 31, for shift amounts. 5217 if (CVal >= 0 && CVal <= 31) 5218 break; 5219 } 5220 return; 5221 5222 case 'O': 5223 if (Subtarget->isThumb()) { // FIXME thumb2 5224 // This must be a multiple of 4 between -508 and 508, for 5225 // ADD/SUB sp = sp + immediate. 5226 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 5227 break; 5228 } 5229 return; 5230 } 5231 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 5232 break; 5233 } 5234 5235 if (Result.getNode()) { 5236 Ops.push_back(Result); 5237 return; 5238 } 5239 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5240} 5241 5242bool 5243ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5244 // The ARM target isn't yet aware of offsets. 5245 return false; 5246} 5247 5248int ARM::getVFPf32Imm(const APFloat &FPImm) { 5249 APInt Imm = FPImm.bitcastToAPInt(); 5250 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 5251 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 5252 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 5253 5254 // We can handle 4 bits of mantissa. 5255 // mantissa = (16+UInt(e:f:g:h))/16. 5256 if (Mantissa & 0x7ffff) 5257 return -1; 5258 Mantissa >>= 19; 5259 if ((Mantissa & 0xf) != Mantissa) 5260 return -1; 5261 5262 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5263 if (Exp < -3 || Exp > 4) 5264 return -1; 5265 Exp = ((Exp+3) & 0x7) ^ 4; 5266 5267 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5268} 5269 5270int ARM::getVFPf64Imm(const APFloat &FPImm) { 5271 APInt Imm = FPImm.bitcastToAPInt(); 5272 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 5273 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 5274 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL; 5275 5276 // We can handle 4 bits of mantissa. 5277 // mantissa = (16+UInt(e:f:g:h))/16. 5278 if (Mantissa & 0xffffffffffffLL) 5279 return -1; 5280 Mantissa >>= 48; 5281 if ((Mantissa & 0xf) != Mantissa) 5282 return -1; 5283 5284 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5285 if (Exp < -3 || Exp > 4) 5286 return -1; 5287 Exp = ((Exp+3) & 0x7) ^ 4; 5288 5289 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5290} 5291 5292/// isFPImmLegal - Returns true if the target can instruction select the 5293/// specified FP immediate natively. If false, the legalizer will 5294/// materialize the FP immediate as a load from a constant pool. 5295bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 5296 if (!Subtarget->hasVFP3()) 5297 return false; 5298 if (VT == MVT::f32) 5299 return ARM::getVFPf32Imm(Imm) != -1; 5300 if (VT == MVT::f64) 5301 return ARM::getVFPf64Imm(Imm) != -1; 5302 return false; 5303} 5304