ARMISelLowering.cpp revision 36397f50343639ce9a25996f2d790c656791ab92
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/CodeGen/MachineBasicBlock.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/ADT/VectorExtras.h" 34#include "llvm/Support/MathExtras.h" 35using namespace llvm; 36 37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 38 : TargetLowering(TM), ARMPCLabelIndex(0) { 39 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 40 41 if (Subtarget->isTargetDarwin()) { 42 // Don't have these. 43 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 44 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 45 46 // Uses VFP for Thumb libfuncs if available. 47 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 48 // Single-precision floating-point arithmetic. 49 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 50 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 51 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 52 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 53 54 // Double-precision floating-point arithmetic. 55 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 56 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 57 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 58 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 59 60 // Single-precision comparisons. 61 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 62 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 63 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 64 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 65 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 66 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 67 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 68 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 69 70 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 71 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 72 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 78 79 // Double-precision comparisons. 80 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 81 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 82 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 83 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 84 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 85 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 86 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 87 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 88 89 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 97 98 // Floating-point to integer conversions. 99 // i64 conversions are done via library routines even when generating VFP 100 // instructions, so use the same ones. 101 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 102 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 103 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 105 106 // Conversions between floating types. 107 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 108 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 109 110 // Integer to floating-point conversions. 111 // i64 conversions are done via library routines even when generating VFP 112 // instructions, so use the same ones. 113 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 114 // __floatunsidf vs. __floatunssidfvfp. 115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 116 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 117 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 119 } 120 } 121 122 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 123 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 124 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 125 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 126 } 127 computeRegisterProperties(); 128 129 // ARM does not have f32 extending load. 130 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 131 132 // ARM supports all 4 flavors of integer indexed load / store. 133 for (unsigned im = (unsigned)ISD::PRE_INC; 134 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 135 setIndexedLoadAction(im, MVT::i1, Legal); 136 setIndexedLoadAction(im, MVT::i8, Legal); 137 setIndexedLoadAction(im, MVT::i16, Legal); 138 setIndexedLoadAction(im, MVT::i32, Legal); 139 setIndexedStoreAction(im, MVT::i1, Legal); 140 setIndexedStoreAction(im, MVT::i8, Legal); 141 setIndexedStoreAction(im, MVT::i16, Legal); 142 setIndexedStoreAction(im, MVT::i32, Legal); 143 } 144 145 // i64 operation support. 146 if (Subtarget->isThumb()) { 147 setOperationAction(ISD::MUL, MVT::i64, Expand); 148 setOperationAction(ISD::MULHU, MVT::i32, Expand); 149 setOperationAction(ISD::MULHS, MVT::i32, Expand); 150 } else { 151 setOperationAction(ISD::MUL, MVT::i64, Custom); 152 setOperationAction(ISD::MULHU, MVT::i32, Custom); 153 if (!Subtarget->hasV6Ops()) 154 setOperationAction(ISD::MULHS, MVT::i32, Custom); 155 } 156 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 157 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 158 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 159 setOperationAction(ISD::SRL, MVT::i64, Custom); 160 setOperationAction(ISD::SRA, MVT::i64, Custom); 161 162 // ARM does not have ROTL. 163 setOperationAction(ISD::ROTL, MVT::i32, Expand); 164 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 165 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 166 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 167 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 168 169 // Only ARMv6 has BSWAP. 170 if (!Subtarget->hasV6Ops()) 171 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 172 173 // These are expanded into libcalls. 174 setOperationAction(ISD::SDIV, MVT::i32, Expand); 175 setOperationAction(ISD::UDIV, MVT::i32, Expand); 176 setOperationAction(ISD::SREM, MVT::i32, Expand); 177 setOperationAction(ISD::UREM, MVT::i32, Expand); 178 179 // Support label based line numbers. 180 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 181 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 182 183 setOperationAction(ISD::RET, MVT::Other, Custom); 184 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 185 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 186 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 187 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 188 189 // Expand mem operations genericly. 190 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 191 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 192 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 193 194 if (Subtarget->isThumb()) 195 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Custom); 196 else 197 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand); 198 199 // Use the default implementation. 200 setOperationAction(ISD::VASTART , MVT::Other, Expand); 201 setOperationAction(ISD::VAARG , MVT::Other, Expand); 202 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 203 setOperationAction(ISD::VAEND , MVT::Other, Expand); 204 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 205 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 207 208 if (!Subtarget->hasV6Ops()) { 209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 211 } 212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 213 214 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 215 // Turn f64->i64 into FMRRD iff target supports vfp2. 216 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 217 218 setOperationAction(ISD::SETCC , MVT::i32, Expand); 219 setOperationAction(ISD::SETCC , MVT::f32, Expand); 220 setOperationAction(ISD::SETCC , MVT::f64, Expand); 221 setOperationAction(ISD::SELECT , MVT::i32, Expand); 222 setOperationAction(ISD::SELECT , MVT::f32, Expand); 223 setOperationAction(ISD::SELECT , MVT::f64, Expand); 224 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 225 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 226 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 227 228 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 229 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 230 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 231 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 232 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 233 234 setOperationAction(ISD::VASTART, MVT::Other, Custom); 235 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 236 setOperationAction(ISD::VAEND, MVT::Other, Expand); 237 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 238 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 239 240 // FP Constants can't be immediates. 241 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 242 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 243 244 // We don't support sin/cos/fmod/copysign 245 setOperationAction(ISD::FSIN , MVT::f64, Expand); 246 setOperationAction(ISD::FSIN , MVT::f32, Expand); 247 setOperationAction(ISD::FCOS , MVT::f32, Expand); 248 setOperationAction(ISD::FCOS , MVT::f64, Expand); 249 setOperationAction(ISD::FREM , MVT::f64, Expand); 250 setOperationAction(ISD::FREM , MVT::f32, Expand); 251 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 252 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 253 254 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 256 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 259 260 setStackPointerRegisterToSaveRestore(ARM::SP); 261 setSchedulingPreference(SchedulingForRegPressure); 262 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 263 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 264 265 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 266} 267 268 269const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 270 switch (Opcode) { 271 default: return 0; 272 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 273 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 274 case ARMISD::CALL: return "ARMISD::CALL"; 275 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 276 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 277 case ARMISD::tCALL: return "ARMISD::tCALL"; 278 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 279 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 280 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 281 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 282 case ARMISD::CMP: return "ARMISD::CMP"; 283 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 284 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 285 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 286 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 287 case ARMISD::CMOV: return "ARMISD::CMOV"; 288 case ARMISD::CNEG: return "ARMISD::CNEG"; 289 290 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 291 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 292 case ARMISD::SITOF: return "ARMISD::SITOF"; 293 case ARMISD::UITOF: return "ARMISD::UITOF"; 294 case ARMISD::MULHILOU: return "ARMISD::MULHILOU"; 295 case ARMISD::MULHILOS: return "ARMISD::MULHILOS"; 296 297 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 298 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 299 case ARMISD::RRX: return "ARMISD::RRX"; 300 301 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 302 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 303 304 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 305 } 306} 307 308//===----------------------------------------------------------------------===// 309// Lowering Code 310//===----------------------------------------------------------------------===// 311 312 313/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 314static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 315 switch (CC) { 316 default: assert(0 && "Unknown condition code!"); 317 case ISD::SETNE: return ARMCC::NE; 318 case ISD::SETEQ: return ARMCC::EQ; 319 case ISD::SETGT: return ARMCC::GT; 320 case ISD::SETGE: return ARMCC::GE; 321 case ISD::SETLT: return ARMCC::LT; 322 case ISD::SETLE: return ARMCC::LE; 323 case ISD::SETUGT: return ARMCC::HI; 324 case ISD::SETUGE: return ARMCC::HS; 325 case ISD::SETULT: return ARMCC::LO; 326 case ISD::SETULE: return ARMCC::LS; 327 } 328} 329 330/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 331/// returns true if the operands should be inverted to form the proper 332/// comparison. 333static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 334 ARMCC::CondCodes &CondCode2) { 335 bool Invert = false; 336 CondCode2 = ARMCC::AL; 337 switch (CC) { 338 default: assert(0 && "Unknown FP condition!"); 339 case ISD::SETEQ: 340 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 341 case ISD::SETGT: 342 case ISD::SETOGT: CondCode = ARMCC::GT; break; 343 case ISD::SETGE: 344 case ISD::SETOGE: CondCode = ARMCC::GE; break; 345 case ISD::SETOLT: CondCode = ARMCC::MI; break; 346 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 347 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 348 case ISD::SETO: CondCode = ARMCC::VC; break; 349 case ISD::SETUO: CondCode = ARMCC::VS; break; 350 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 351 case ISD::SETUGT: CondCode = ARMCC::HI; break; 352 case ISD::SETUGE: CondCode = ARMCC::PL; break; 353 case ISD::SETLT: 354 case ISD::SETULT: CondCode = ARMCC::LT; break; 355 case ISD::SETLE: 356 case ISD::SETULE: CondCode = ARMCC::LE; break; 357 case ISD::SETNE: 358 case ISD::SETUNE: CondCode = ARMCC::NE; break; 359 } 360 return Invert; 361} 362 363static void 364HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, 365 unsigned StackOffset, unsigned &NeededGPRs, 366 unsigned &NeededStackSize, unsigned &GPRPad, 367 unsigned &StackPad, unsigned Flags) { 368 NeededStackSize = 0; 369 NeededGPRs = 0; 370 StackPad = 0; 371 GPRPad = 0; 372 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); 373 GPRPad = NumGPRs % ((align + 3)/4); 374 StackPad = StackOffset % align; 375 unsigned firstGPR = NumGPRs + GPRPad; 376 switch (ObjectVT) { 377 default: assert(0 && "Unhandled argument type!"); 378 case MVT::i32: 379 case MVT::f32: 380 if (firstGPR < 4) 381 NeededGPRs = 1; 382 else 383 NeededStackSize = 4; 384 break; 385 case MVT::i64: 386 case MVT::f64: 387 if (firstGPR < 3) 388 NeededGPRs = 2; 389 else if (firstGPR == 3) { 390 NeededGPRs = 1; 391 NeededStackSize = 4; 392 } else 393 NeededStackSize = 8; 394 } 395} 396 397/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 398/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 399/// nodes. 400SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 401 MVT::ValueType RetVT= Op.Val->getValueType(0); 402 SDOperand Chain = Op.getOperand(0); 403 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 404 assert((CallConv == CallingConv::C || 405 CallConv == CallingConv::Fast) && "unknown calling convention"); 406 SDOperand Callee = Op.getOperand(4); 407 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 408 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 409 unsigned NumGPRs = 0; // GPRs used for parameter passing. 410 411 // Count how many bytes are to be pushed on the stack. 412 unsigned NumBytes = 0; 413 414 // Add up all the space actually used. 415 for (unsigned i = 0; i < NumOps; ++i) { 416 unsigned ObjSize; 417 unsigned ObjGPRs; 418 unsigned StackPad; 419 unsigned GPRPad; 420 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); 421 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 422 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 423 GPRPad, StackPad, Flags); 424 NumBytes += ObjSize + StackPad; 425 NumGPRs += ObjGPRs + GPRPad; 426 } 427 428 // Adjust the stack pointer for the new arguments... 429 // These operations are automatically eliminated by the prolog/epilog pass 430 Chain = DAG.getCALLSEQ_START(Chain, 431 DAG.getConstant(NumBytes, MVT::i32)); 432 433 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 434 435 static const unsigned GPRArgRegs[] = { 436 ARM::R0, ARM::R1, ARM::R2, ARM::R3 437 }; 438 439 NumGPRs = 0; 440 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 441 std::vector<SDOperand> MemOpChains; 442 for (unsigned i = 0; i != NumOps; ++i) { 443 SDOperand Arg = Op.getOperand(5+2*i); 444 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 445 MVT::ValueType ArgVT = Arg.getValueType(); 446 447 unsigned ObjSize; 448 unsigned ObjGPRs; 449 unsigned GPRPad; 450 unsigned StackPad; 451 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 452 ObjSize, GPRPad, StackPad, Flags); 453 NumGPRs += GPRPad; 454 ArgOffset += StackPad; 455 if (ObjGPRs > 0) { 456 switch (ArgVT) { 457 default: assert(0 && "Unexpected ValueType for argument!"); 458 case MVT::i32: 459 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 460 break; 461 case MVT::f32: 462 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 463 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 464 break; 465 case MVT::i64: { 466 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 467 DAG.getConstant(0, getPointerTy())); 468 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 469 DAG.getConstant(1, getPointerTy())); 470 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 471 if (ObjGPRs == 2) 472 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 473 else { 474 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 475 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 476 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 477 } 478 break; 479 } 480 case MVT::f64: { 481 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, 482 DAG.getVTList(MVT::i32, MVT::i32), 483 &Arg, 1); 484 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 485 if (ObjGPRs == 2) 486 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 487 Cvt.getValue(1))); 488 else { 489 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 490 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 491 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 492 NULL, 0)); 493 } 494 break; 495 } 496 } 497 } else { 498 assert(ObjSize != 0); 499 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 500 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 501 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 502 } 503 504 NumGPRs += ObjGPRs; 505 ArgOffset += ObjSize; 506 } 507 508 if (!MemOpChains.empty()) 509 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 510 &MemOpChains[0], MemOpChains.size()); 511 512 // Build a sequence of copy-to-reg nodes chained together with token chain 513 // and flag operands which copy the outgoing args into the appropriate regs. 514 SDOperand InFlag; 515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 516 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 517 InFlag); 518 InFlag = Chain.getValue(1); 519 } 520 521 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 522 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 523 // node so that legalize doesn't hack it. 524 bool isDirect = false; 525 bool isARMFunc = false; 526 bool isLocalARMFunc = false; 527 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 528 GlobalValue *GV = G->getGlobal(); 529 isDirect = true; 530 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 531 GV->hasLinkOnceLinkage()); 532 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 533 getTargetMachine().getRelocationModel() != Reloc::Static; 534 isARMFunc = !Subtarget->isThumb() || isStub; 535 // ARM call to a local ARM function is predicable. 536 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 537 // tBX takes a register source operand. 538 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 539 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 540 ARMCP::CPStub, 4); 541 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 542 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 543 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 544 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 545 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 546 } else 547 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 548 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 549 isDirect = true; 550 bool isStub = Subtarget->isTargetDarwin() && 551 getTargetMachine().getRelocationModel() != Reloc::Static; 552 isARMFunc = !Subtarget->isThumb() || isStub; 553 // tBX takes a register source operand. 554 const char *Sym = S->getSymbol(); 555 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 556 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 557 ARMCP::CPStub, 4); 558 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 559 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 560 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 561 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 562 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 563 } else 564 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 565 } 566 567 // FIXME: handle tail calls differently. 568 unsigned CallOpc; 569 if (Subtarget->isThumb()) { 570 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 571 CallOpc = ARMISD::CALL_NOLINK; 572 else 573 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 574 } else { 575 CallOpc = (isDirect || Subtarget->hasV5TOps()) 576 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 577 : ARMISD::CALL_NOLINK; 578 } 579 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 580 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 581 Chain = DAG.getCopyToReg(Chain, ARM::LR, 582 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 583 InFlag = Chain.getValue(1); 584 } 585 586 std::vector<MVT::ValueType> NodeTys; 587 NodeTys.push_back(MVT::Other); // Returns a chain 588 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 589 590 std::vector<SDOperand> Ops; 591 Ops.push_back(Chain); 592 Ops.push_back(Callee); 593 594 // Add argument registers to the end of the list so that they are known live 595 // into the call. 596 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 597 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 598 RegsToPass[i].second.getValueType())); 599 600 if (InFlag.Val) 601 Ops.push_back(InFlag); 602 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 603 InFlag = Chain.getValue(1); 604 605 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; 606 Chain = DAG.getNode(ISD::CALLSEQ_END, 607 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 608 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); 609 if (RetVT != MVT::Other) 610 InFlag = Chain.getValue(1); 611 612 std::vector<SDOperand> ResultVals; 613 NodeTys.clear(); 614 615 // If the call has results, copy the values out of the ret val registers. 616 switch (RetVT) { 617 default: assert(0 && "Unexpected ret value!"); 618 case MVT::Other: 619 break; 620 case MVT::i32: 621 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 622 ResultVals.push_back(Chain.getValue(0)); 623 if (Op.Val->getValueType(1) == MVT::i32) { 624 // Returns a i64 value. 625 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 626 Chain.getValue(2)).getValue(1); 627 ResultVals.push_back(Chain.getValue(0)); 628 NodeTys.push_back(MVT::i32); 629 } 630 NodeTys.push_back(MVT::i32); 631 break; 632 case MVT::f32: 633 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 634 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 635 Chain.getValue(0))); 636 NodeTys.push_back(MVT::f32); 637 break; 638 case MVT::f64: { 639 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 640 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 641 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 642 NodeTys.push_back(MVT::f64); 643 break; 644 } 645 } 646 647 NodeTys.push_back(MVT::Other); 648 649 if (ResultVals.empty()) 650 return Chain; 651 652 ResultVals.push_back(Chain); 653 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 654 ResultVals.size()); 655 return Res.getValue(Op.ResNo); 656} 657 658static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 659 SDOperand Copy; 660 SDOperand Chain = Op.getOperand(0); 661 switch(Op.getNumOperands()) { 662 default: 663 assert(0 && "Do not know how to return this many arguments!"); 664 abort(); 665 case 1: { 666 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); 667 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 668 } 669 case 3: 670 Op = Op.getOperand(1); 671 if (Op.getValueType() == MVT::f32) { 672 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 673 } else if (Op.getValueType() == MVT::f64) { 674 // Recursively legalize f64 -> i64. 675 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op); 676 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, 677 DAG.getConstant(0, MVT::i32)); 678 } 679 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); 680 if (DAG.getMachineFunction().liveout_empty()) 681 DAG.getMachineFunction().addLiveOut(ARM::R0); 682 break; 683 case 5: 684 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 685 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 686 // If we haven't noted the R0+R1 are live out, do so now. 687 if (DAG.getMachineFunction().liveout_empty()) { 688 DAG.getMachineFunction().addLiveOut(ARM::R0); 689 DAG.getMachineFunction().addLiveOut(ARM::R1); 690 } 691 break; 692 } 693 694 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 695 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 696} 697 698// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 699// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 700// one of the above mentioned nodes. It has to be wrapped because otherwise 701// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 702// be used to form addressing mode. These wrapped nodes will be selected 703// into MOVi. 704static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 705 MVT::ValueType PtrVT = Op.getValueType(); 706 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 707 SDOperand Res; 708 if (CP->isMachineConstantPoolEntry()) 709 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 710 CP->getAlignment()); 711 else 712 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 713 CP->getAlignment()); 714 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 715} 716 717// Lower ISD::GlobalTLSAddress using the "general dynamic" model 718SDOperand 719ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 720 SelectionDAG &DAG) { 721 MVT::ValueType PtrVT = getPointerTy(); 722 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 723 ARMConstantPoolValue *CPV = 724 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 725 PCAdj, "tlsgd", true); 726 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 727 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 728 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 729 SDOperand Chain = Argument.getValue(1); 730 731 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 732 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 733 734 // call __tls_get_addr. 735 ArgListTy Args; 736 ArgListEntry Entry; 737 Entry.Node = Argument; 738 Entry.Ty = (const Type *) Type::Int32Ty; 739 Args.push_back(Entry); 740 std::pair<SDOperand, SDOperand> CallResult = 741 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, 742 CallingConv::C, false, 743 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 744 return CallResult.first; 745} 746 747// Lower ISD::GlobalTLSAddress using the "initial exec" or 748// "local exec" model. 749SDOperand 750ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 751 SelectionDAG &DAG) { 752 GlobalValue *GV = GA->getGlobal(); 753 SDOperand Offset; 754 SDOperand Chain = DAG.getEntryNode(); 755 MVT::ValueType PtrVT = getPointerTy(); 756 // Get the Thread Pointer 757 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 758 759 if (GV->isDeclaration()){ 760 // initial exec model 761 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 762 ARMConstantPoolValue *CPV = 763 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 764 PCAdj, "gottpoff", true); 765 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 766 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 767 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 768 Chain = Offset.getValue(1); 769 770 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 771 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 772 773 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 774 } else { 775 // local exec model 776 ARMConstantPoolValue *CPV = 777 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 778 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 779 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 780 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 781 } 782 783 // The address of the thread local variable is the add of the thread 784 // pointer with the offset of the variable. 785 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 786} 787 788SDOperand 789ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 790 // TODO: implement the "local dynamic" model 791 assert(Subtarget->isTargetELF() && 792 "TLS not implemented for non-ELF targets"); 793 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 794 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 795 // otherwise use the "Local Exec" TLS Model 796 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 797 return LowerToTLSGeneralDynamicModel(GA, DAG); 798 else 799 return LowerToTLSExecModels(GA, DAG); 800} 801 802SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, 803 SelectionDAG &DAG) { 804 MVT::ValueType PtrVT = getPointerTy(); 805 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 806 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 807 if (RelocM == Reloc::PIC_) { 808 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 809 ARMConstantPoolValue *CPV = 810 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 811 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 812 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 813 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 814 SDOperand Chain = Result.getValue(1); 815 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 816 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 817 if (!UseGOTOFF) 818 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 819 return Result; 820 } else { 821 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 822 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 823 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 824 } 825} 826 827/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 828/// even in non-static mode. 829static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 830 return RelocM != Reloc::Static && 831 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 832 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 833} 834 835SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, 836 SelectionDAG &DAG) { 837 MVT::ValueType PtrVT = getPointerTy(); 838 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 839 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 840 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 841 SDOperand CPAddr; 842 if (RelocM == Reloc::Static) 843 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 844 else { 845 unsigned PCAdj = (RelocM != Reloc::PIC_) 846 ? 0 : (Subtarget->isThumb() ? 4 : 8); 847 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 848 : ARMCP::CPValue; 849 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 850 Kind, PCAdj); 851 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 852 } 853 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 854 855 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 856 SDOperand Chain = Result.getValue(1); 857 858 if (RelocM == Reloc::PIC_) { 859 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 860 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 861 } 862 if (IsIndirect) 863 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 864 865 return Result; 866} 867 868SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, 869 SelectionDAG &DAG){ 870 assert(Subtarget->isTargetELF() && 871 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 872 MVT::ValueType PtrVT = getPointerTy(); 873 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 874 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 875 ARMPCLabelIndex, 876 ARMCP::CPValue, PCAdj); 877 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 878 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 879 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 880 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 881 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 882} 883 884static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 885 unsigned VarArgsFrameIndex) { 886 // vastart just stores the address of the VarArgsFrameIndex slot into the 887 // memory location argument. 888 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 889 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 890 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 891 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 892 SV->getOffset()); 893} 894 895static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, 896 unsigned *vRegs, unsigned ArgNo, 897 unsigned &NumGPRs, unsigned &ArgOffset) { 898 MachineFunction &MF = DAG.getMachineFunction(); 899 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 900 SDOperand Root = Op.getOperand(0); 901 std::vector<SDOperand> ArgValues; 902 SSARegMap *RegMap = MF.getSSARegMap(); 903 904 static const unsigned GPRArgRegs[] = { 905 ARM::R0, ARM::R1, ARM::R2, ARM::R3 906 }; 907 908 unsigned ObjSize; 909 unsigned ObjGPRs; 910 unsigned GPRPad; 911 unsigned StackPad; 912 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3); 913 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 914 ObjSize, GPRPad, StackPad, Flags); 915 NumGPRs += GPRPad; 916 ArgOffset += StackPad; 917 918 SDOperand ArgValue; 919 if (ObjGPRs == 1) { 920 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 921 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 922 vRegs[NumGPRs] = VReg; 923 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 924 if (ObjectVT == MVT::f32) 925 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 926 } else if (ObjGPRs == 2) { 927 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 928 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 929 vRegs[NumGPRs] = VReg; 930 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 931 932 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 933 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 934 vRegs[NumGPRs+1] = VReg; 935 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 936 937 if (ObjectVT == MVT::i64) 938 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 939 else 940 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 941 } 942 NumGPRs += ObjGPRs; 943 944 if (ObjSize) { 945 // If the argument is actually used, emit a load from the right stack 946 // slot. 947 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 948 MachineFrameInfo *MFI = MF.getFrameInfo(); 949 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 950 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 951 if (ObjGPRs == 0) 952 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 953 else { 954 SDOperand ArgValue2 = 955 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 956 if (ObjectVT == MVT::i64) 957 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 958 else 959 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 960 } 961 } else { 962 // Don't emit a dead load. 963 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); 964 } 965 966 ArgOffset += ObjSize; // Move on to the next argument. 967 } 968 969 return ArgValue; 970} 971 972SDOperand 973ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 974 std::vector<SDOperand> ArgValues; 975 SDOperand Root = Op.getOperand(0); 976 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 977 unsigned NumGPRs = 0; // GPRs used for parameter passing. 978 unsigned VRegs[4]; 979 980 unsigned NumArgs = Op.Val->getNumValues()-1; 981 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 982 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, 983 NumGPRs, ArgOffset)); 984 985 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 986 if (isVarArg) { 987 static const unsigned GPRArgRegs[] = { 988 ARM::R0, ARM::R1, ARM::R2, ARM::R3 989 }; 990 991 MachineFunction &MF = DAG.getMachineFunction(); 992 SSARegMap *RegMap = MF.getSSARegMap(); 993 MachineFrameInfo *MFI = MF.getFrameInfo(); 994 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 995 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 996 unsigned VARegSize = (4 - NumGPRs) * 4; 997 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 998 if (VARegSaveSize) { 999 // If this function is vararg, store any remaining integer argument regs 1000 // to their spots on the stack so that they may be loaded by deferencing 1001 // the result of va_next. 1002 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1003 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1004 VARegSaveSize - VARegSize); 1005 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1006 1007 SmallVector<SDOperand, 4> MemOps; 1008 for (; NumGPRs < 4; ++NumGPRs) { 1009 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 1010 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1011 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1012 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1013 MemOps.push_back(Store); 1014 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1015 DAG.getConstant(4, getPointerTy())); 1016 } 1017 if (!MemOps.empty()) 1018 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1019 &MemOps[0], MemOps.size()); 1020 } else 1021 // This will point to the next argument passed via stack. 1022 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1023 } 1024 1025 ArgValues.push_back(Root); 1026 1027 // Return the new list of results. 1028 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1029 Op.Val->value_end()); 1030 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1031} 1032 1033/// isFloatingPointZero - Return true if this is +0.0. 1034static bool isFloatingPointZero(SDOperand Op) { 1035 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1036 return CFP->isExactlyValue(0.0); 1037 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 1038 // Maybe this has already been legalized into the constant pool? 1039 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1040 SDOperand WrapperOp = Op.getOperand(1).getOperand(0); 1041 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1042 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1043 return CFP->isExactlyValue(0.0); 1044 } 1045 } 1046 return false; 1047} 1048 1049static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1050 return ( isThumb && (C & ~255U) == 0) || 1051 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1052} 1053 1054/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1055/// the given operands. 1056static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, 1057 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { 1058 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { 1059 unsigned C = RHSC->getValue(); 1060 if (!isLegalCmpImmediate(C, isThumb)) { 1061 // Constant does not fit, try adjusting it by one? 1062 switch (CC) { 1063 default: break; 1064 case ISD::SETLT: 1065 case ISD::SETGE: 1066 if (isLegalCmpImmediate(C-1, isThumb)) { 1067 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1068 RHS = DAG.getConstant(C-1, MVT::i32); 1069 } 1070 break; 1071 case ISD::SETULT: 1072 case ISD::SETUGE: 1073 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1074 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1075 RHS = DAG.getConstant(C-1, MVT::i32); 1076 } 1077 break; 1078 case ISD::SETLE: 1079 case ISD::SETGT: 1080 if (isLegalCmpImmediate(C+1, isThumb)) { 1081 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1082 RHS = DAG.getConstant(C+1, MVT::i32); 1083 } 1084 break; 1085 case ISD::SETULE: 1086 case ISD::SETUGT: 1087 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1088 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1089 RHS = DAG.getConstant(C+1, MVT::i32); 1090 } 1091 break; 1092 } 1093 } 1094 } 1095 1096 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1097 ARMISD::NodeType CompareType; 1098 switch (CondCode) { 1099 default: 1100 CompareType = ARMISD::CMP; 1101 break; 1102 case ARMCC::EQ: 1103 case ARMCC::NE: 1104 case ARMCC::MI: 1105 case ARMCC::PL: 1106 // Uses only N and Z Flags 1107 CompareType = ARMISD::CMPNZ; 1108 break; 1109 } 1110 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1111 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1112} 1113 1114/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1115static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { 1116 SDOperand Cmp; 1117 if (!isFloatingPointZero(RHS)) 1118 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1119 else 1120 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1121 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1122} 1123 1124static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, 1125 const ARMSubtarget *ST) { 1126 MVT::ValueType VT = Op.getValueType(); 1127 SDOperand LHS = Op.getOperand(0); 1128 SDOperand RHS = Op.getOperand(1); 1129 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1130 SDOperand TrueVal = Op.getOperand(2); 1131 SDOperand FalseVal = Op.getOperand(3); 1132 1133 if (LHS.getValueType() == MVT::i32) { 1134 SDOperand ARMCC; 1135 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1136 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1137 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1138 } 1139 1140 ARMCC::CondCodes CondCode, CondCode2; 1141 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1142 std::swap(TrueVal, FalseVal); 1143 1144 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1145 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1146 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1147 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1148 ARMCC, CCR, Cmp); 1149 if (CondCode2 != ARMCC::AL) { 1150 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1151 // FIXME: Needs another CMP because flag can have but one use. 1152 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); 1153 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1154 } 1155 return Result; 1156} 1157 1158static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, 1159 const ARMSubtarget *ST) { 1160 SDOperand Chain = Op.getOperand(0); 1161 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1162 SDOperand LHS = Op.getOperand(2); 1163 SDOperand RHS = Op.getOperand(3); 1164 SDOperand Dest = Op.getOperand(4); 1165 1166 if (LHS.getValueType() == MVT::i32) { 1167 SDOperand ARMCC; 1168 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1169 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1170 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1171 } 1172 1173 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1174 ARMCC::CondCodes CondCode, CondCode2; 1175 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1176 // Swap the LHS/RHS of the comparison if needed. 1177 std::swap(LHS, RHS); 1178 1179 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1180 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1181 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1182 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1183 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1184 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1185 if (CondCode2 != ARMCC::AL) { 1186 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1187 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1188 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1189 } 1190 return Res; 1191} 1192 1193SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { 1194 SDOperand Chain = Op.getOperand(0); 1195 SDOperand Table = Op.getOperand(1); 1196 SDOperand Index = Op.getOperand(2); 1197 1198 MVT::ValueType PTy = getPointerTy(); 1199 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1200 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1201 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1202 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1203 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1204 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1205 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1206 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1207 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, 1208 Chain, Addr, NULL, 0); 1209 Chain = Addr.getValue(1); 1210 if (isPIC) 1211 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1212 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1213} 1214 1215static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { 1216 unsigned Opc = 1217 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1218 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1219 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1220} 1221 1222static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1223 MVT::ValueType VT = Op.getValueType(); 1224 unsigned Opc = 1225 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1226 1227 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1228 return DAG.getNode(Opc, VT, Op); 1229} 1230 1231static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 1232 // Implement fcopysign with a fabs and a conditional fneg. 1233 SDOperand Tmp0 = Op.getOperand(0); 1234 SDOperand Tmp1 = Op.getOperand(1); 1235 MVT::ValueType VT = Op.getValueType(); 1236 MVT::ValueType SrcVT = Tmp1.getValueType(); 1237 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1238 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1239 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1240 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1241 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1242} 1243 1244static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) { 1245 // Turn f64->i64 into FMRRD. 1246 assert(Op.getValueType() == MVT::i64 && 1247 Op.getOperand(0).getValueType() == MVT::f64); 1248 1249 Op = Op.getOperand(0); 1250 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1251 &Op, 1); 1252 1253 // Merge the pieces into a single i64 value. 1254 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); 1255} 1256 1257static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 1258 // FIXME: All this code is target-independent. Create a new target-indep 1259 // MULHILO node and move this code to the legalizer. 1260 // 1261 assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!"); 1262 1263 SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1264 DAG.getConstant(0, MVT::i32)); 1265 SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), 1266 DAG.getConstant(0, MVT::i32)); 1267 1268 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 1269 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 1270 1271 SDOperand Lo, Hi; 1272 // Figure out how to lower this multiply. 1273 if (LHSSB >= 33 && RHSSB >= 33) { 1274 // If the input values are both sign extended, we can emit a mulhs+mul. 1275 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); 1276 Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL); 1277 } else if (LHSSB == 32 && RHSSB == 32 && 1278 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 1279 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 1280 // If the inputs are zero extended, use mulhu. 1281 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); 1282 Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL); 1283 } else { 1284 SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1285 DAG.getConstant(1, MVT::i32)); 1286 SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), 1287 DAG.getConstant(1, MVT::i32)); 1288 1289 // Lo,Hi = umul LHS, RHS. 1290 SDOperand Ops[] = { LL, RL }; 1291 SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU, 1292 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2); 1293 Lo = UMul64; 1294 Hi = UMul64.getValue(1); 1295 RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH); 1296 LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL); 1297 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH); 1298 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH); 1299 } 1300 1301 // Merge the pieces into a single i64 value. 1302 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1303} 1304 1305static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) { 1306 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; 1307 return DAG.getNode(ARMISD::MULHILOU, 1308 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); 1309} 1310 1311static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) { 1312 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; 1313 return DAG.getNode(ARMISD::MULHILOS, 1314 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); 1315} 1316 1317static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG, 1318 const ARMSubtarget *ST) { 1319 assert(Op.getValueType() == MVT::i64 && 1320 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && 1321 "Unknown shift to lower!"); 1322 1323 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1324 if (!isa<ConstantSDNode>(Op.getOperand(1)) || 1325 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1) 1326 return SDOperand(); 1327 1328 // If we are in thumb mode, we don't have RRX. 1329 if (ST->isThumb()) return SDOperand(); 1330 1331 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1332 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1333 DAG.getConstant(0, MVT::i32)); 1334 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1335 DAG.getConstant(1, MVT::i32)); 1336 1337 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1338 // captures the result into a carry flag. 1339 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1340 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1341 1342 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1343 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1344 1345 // Merge the pieces into a single i64 value. 1346 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1347} 1348 1349SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 1350 SDOperand Chain = Op.getOperand(0); 1351 SDOperand Dest = Op.getOperand(1); 1352 SDOperand Src = Op.getOperand(2); 1353 SDOperand Count = Op.getOperand(3); 1354 unsigned Align = 1355 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 1356 if (Align == 0) Align = 1; 1357 1358 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Count); 1359 // Just call memcpy if: 1360 // not 4-byte aligned 1361 // size is unknown 1362 // size is >= the threshold. 1363 if ((Align & 3) != 0 || 1364 !I || 1365 I->getValue() >= 64 || 1366 (I->getValue() & 3) != 0) { 1367 MVT::ValueType IntPtr = getPointerTy(); 1368 TargetLowering::ArgListTy Args; 1369 TargetLowering::ArgListEntry Entry; 1370 Entry.Ty = getTargetData()->getIntPtrType(); 1371 Entry.Node = Op.getOperand(1); Args.push_back(Entry); 1372 Entry.Node = Op.getOperand(2); Args.push_back(Entry); 1373 Entry.Node = Op.getOperand(3); Args.push_back(Entry); 1374 std::pair<SDOperand,SDOperand> CallResult = 1375 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 1376 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 1377 return CallResult.second; 1378 } 1379 1380 // Otherwise do repeated 4-byte loads and stores. To be improved. 1381 assert((I->getValue() & 3) == 0); 1382 assert((Align & 3) == 0); 1383 unsigned NumMemOps = I->getValue() >> 2; 1384 unsigned EmittedNumMemOps = 0; 1385 unsigned SrcOff = 0, DstOff = 0; 1386 MVT::ValueType VT = MVT::i32; 1387 unsigned VTSize = 4; 1388 const unsigned MAX_LOADS_IN_LDM = 6; 1389 SDOperand LoadChains[MAX_LOADS_IN_LDM]; 1390 SDOperand Loads[MAX_LOADS_IN_LDM]; 1391 1392 // Emit up to 4 loads, then a TokenFactor barrier, then the same 1393 // number of stores. The loads and stores will get combined into 1394 // ldm/stm later on. 1395 while(EmittedNumMemOps < NumMemOps) { 1396 unsigned i; 1397 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) { 1398 Loads[i] = DAG.getLoad(VT, Chain, 1399 DAG.getNode(ISD::ADD, VT, Src, 1400 DAG.getConstant(SrcOff, VT)), 1401 NULL, 0); 1402 LoadChains[i] = Loads[i].getValue(1); 1403 SrcOff += VTSize; 1404 } 1405 1406 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &LoadChains[0], i); 1407 1408 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) { 1409 Chain = DAG.getStore(Chain, Loads[i], 1410 DAG.getNode(ISD::ADD, VT, Dest, 1411 DAG.getConstant(DstOff, VT)), 1412 NULL, 0); 1413 DstOff += VTSize; 1414 } 1415 EmittedNumMemOps += i; 1416 } 1417 1418 return Chain; 1419} 1420 1421SDOperand ARMTargetLowering::LowerADJUST_TRAMP(SDOperand Op, 1422 SelectionDAG &DAG) { 1423 // Thumb trampolines should be entered in thumb mode, so set the bottom bit 1424 // of the address. 1425 return DAG.getNode(ISD::OR, MVT::i32, Op.getOperand(0), 1426 DAG.getConstant(1, MVT::i32)); 1427} 1428 1429SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1430 switch (Op.getOpcode()) { 1431 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1432 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1433 case ISD::GlobalAddress: 1434 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1435 LowerGlobalAddressELF(Op, DAG); 1436 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1437 case ISD::CALL: return LowerCALL(Op, DAG); 1438 case ISD::RET: return LowerRET(Op, DAG); 1439 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1440 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1441 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1442 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1443 case ISD::SINT_TO_FP: 1444 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1445 case ISD::FP_TO_SINT: 1446 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1447 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1448 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 1449 case ISD::MUL: return LowerMUL(Op, DAG); 1450 case ISD::MULHU: return LowerMULHU(Op, DAG); 1451 case ISD::MULHS: return LowerMULHS(Op, DAG); 1452 case ISD::SRL: 1453 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); 1454 case ISD::FORMAL_ARGUMENTS: 1455 return LowerFORMAL_ARGUMENTS(Op, DAG); 1456 case ISD::RETURNADDR: break; 1457 case ISD::FRAMEADDR: break; 1458 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1459 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 1460 case ISD::ADJUST_TRAMP: return LowerADJUST_TRAMP(Op, DAG); 1461 } 1462 return SDOperand(); 1463} 1464 1465//===----------------------------------------------------------------------===// 1466// ARM Scheduler Hooks 1467//===----------------------------------------------------------------------===// 1468 1469MachineBasicBlock * 1470ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1471 MachineBasicBlock *BB) { 1472 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1473 switch (MI->getOpcode()) { 1474 default: assert(false && "Unexpected instr type to insert"); 1475 case ARM::tMOVCCr: { 1476 // To "insert" a SELECT_CC instruction, we actually have to insert the 1477 // diamond control-flow pattern. The incoming instruction knows the 1478 // destination vreg to set, the condition code register to branch on, the 1479 // true/false values to select between, and a branch opcode to use. 1480 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1481 ilist<MachineBasicBlock>::iterator It = BB; 1482 ++It; 1483 1484 // thisMBB: 1485 // ... 1486 // TrueVal = ... 1487 // cmpTY ccX, r1, r2 1488 // bCC copy1MBB 1489 // fallthrough --> copy0MBB 1490 MachineBasicBlock *thisMBB = BB; 1491 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1492 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1493 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1494 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1495 MachineFunction *F = BB->getParent(); 1496 F->getBasicBlockList().insert(It, copy0MBB); 1497 F->getBasicBlockList().insert(It, sinkMBB); 1498 // Update machine-CFG edges by first adding all successors of the current 1499 // block to the new block which will contain the Phi node for the select. 1500 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1501 e = BB->succ_end(); i != e; ++i) 1502 sinkMBB->addSuccessor(*i); 1503 // Next, remove all successors of the current block, and add the true 1504 // and fallthrough blocks as its successors. 1505 while(!BB->succ_empty()) 1506 BB->removeSuccessor(BB->succ_begin()); 1507 BB->addSuccessor(copy0MBB); 1508 BB->addSuccessor(sinkMBB); 1509 1510 // copy0MBB: 1511 // %FalseValue = ... 1512 // # fallthrough to sinkMBB 1513 BB = copy0MBB; 1514 1515 // Update machine-CFG edges 1516 BB->addSuccessor(sinkMBB); 1517 1518 // sinkMBB: 1519 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1520 // ... 1521 BB = sinkMBB; 1522 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1523 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1524 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1525 1526 delete MI; // The pseudo instruction is gone now. 1527 return BB; 1528 } 1529 } 1530} 1531 1532//===----------------------------------------------------------------------===// 1533// ARM Optimization Hooks 1534//===----------------------------------------------------------------------===// 1535 1536/// isLegalAddressImmediate - Return true if the integer value can be used 1537/// as the offset of the target addressing mode for load / store of the 1538/// given type. 1539static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, 1540 const ARMSubtarget *Subtarget) { 1541 if (V == 0) 1542 return true; 1543 1544 if (Subtarget->isThumb()) { 1545 if (V < 0) 1546 return false; 1547 1548 unsigned Scale = 1; 1549 switch (VT) { 1550 default: return false; 1551 case MVT::i1: 1552 case MVT::i8: 1553 // Scale == 1; 1554 break; 1555 case MVT::i16: 1556 // Scale == 2; 1557 Scale = 2; 1558 break; 1559 case MVT::i32: 1560 // Scale == 4; 1561 Scale = 4; 1562 break; 1563 } 1564 1565 if ((V & (Scale - 1)) != 0) 1566 return false; 1567 V /= Scale; 1568 return V == V & ((1LL << 5) - 1); 1569 } 1570 1571 if (V < 0) 1572 V = - V; 1573 switch (VT) { 1574 default: return false; 1575 case MVT::i1: 1576 case MVT::i8: 1577 case MVT::i32: 1578 // +- imm12 1579 return V == V & ((1LL << 12) - 1); 1580 case MVT::i16: 1581 // +- imm8 1582 return V == V & ((1LL << 8) - 1); 1583 case MVT::f32: 1584 case MVT::f64: 1585 if (!Subtarget->hasVFP2()) 1586 return false; 1587 if ((V & 3) != 0) 1588 return false; 1589 V >>= 2; 1590 return V == V & ((1LL << 8) - 1); 1591 } 1592} 1593 1594/// isLegalAddressingMode - Return true if the addressing mode represented 1595/// by AM is legal for this target, for a load/store of the specified type. 1596bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1597 const Type *Ty) const { 1598 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget)) 1599 return false; 1600 1601 // Can never fold addr of global into load/store. 1602 if (AM.BaseGV) 1603 return false; 1604 1605 switch (AM.Scale) { 1606 case 0: // no scale reg, must be "r+i" or "r", or "i". 1607 break; 1608 case 1: 1609 if (Subtarget->isThumb()) 1610 return false; 1611 // FALL THROUGH. 1612 default: 1613 // ARM doesn't support any R+R*scale+imm addr modes. 1614 if (AM.BaseOffs) 1615 return false; 1616 1617 int Scale = AM.Scale; 1618 switch (getValueType(Ty)) { 1619 default: return false; 1620 case MVT::i1: 1621 case MVT::i8: 1622 case MVT::i32: 1623 case MVT::i64: 1624 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1625 // ldrd / strd are used, then its address mode is same as i16. 1626 // r + r 1627 if (Scale < 0) Scale = -Scale; 1628 if (Scale == 1) 1629 return true; 1630 // r + r << imm 1631 return isPowerOf2_32(Scale & ~1); 1632 case MVT::i16: 1633 // r + r 1634 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1635 return true; 1636 return false; 1637 1638 case MVT::isVoid: 1639 // Note, we allow "void" uses (basically, uses that aren't loads or 1640 // stores), because arm allows folding a scale into many arithmetic 1641 // operations. This should be made more precise and revisited later. 1642 1643 // Allow r << imm, but the imm has to be a multiple of two. 1644 if (AM.Scale & 1) return false; 1645 return isPowerOf2_32(AM.Scale); 1646 } 1647 break; 1648 } 1649 return true; 1650} 1651 1652 1653static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, 1654 bool isSEXTLoad, SDOperand &Base, 1655 SDOperand &Offset, bool &isInc, 1656 SelectionDAG &DAG) { 1657 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1658 return false; 1659 1660 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1661 // AddressingMode 3 1662 Base = Ptr->getOperand(0); 1663 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1664 int RHSC = (int)RHS->getValue(); 1665 if (RHSC < 0 && RHSC > -256) { 1666 isInc = false; 1667 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1668 return true; 1669 } 1670 } 1671 isInc = (Ptr->getOpcode() == ISD::ADD); 1672 Offset = Ptr->getOperand(1); 1673 return true; 1674 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1675 // AddressingMode 2 1676 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1677 int RHSC = (int)RHS->getValue(); 1678 if (RHSC < 0 && RHSC > -0x1000) { 1679 isInc = false; 1680 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1681 Base = Ptr->getOperand(0); 1682 return true; 1683 } 1684 } 1685 1686 if (Ptr->getOpcode() == ISD::ADD) { 1687 isInc = true; 1688 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1689 if (ShOpcVal != ARM_AM::no_shift) { 1690 Base = Ptr->getOperand(1); 1691 Offset = Ptr->getOperand(0); 1692 } else { 1693 Base = Ptr->getOperand(0); 1694 Offset = Ptr->getOperand(1); 1695 } 1696 return true; 1697 } 1698 1699 isInc = (Ptr->getOpcode() == ISD::ADD); 1700 Base = Ptr->getOperand(0); 1701 Offset = Ptr->getOperand(1); 1702 return true; 1703 } 1704 1705 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1706 return false; 1707} 1708 1709/// getPreIndexedAddressParts - returns true by value, base pointer and 1710/// offset pointer and addressing mode by reference if the node's address 1711/// can be legally represented as pre-indexed load / store address. 1712bool 1713ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 1714 SDOperand &Offset, 1715 ISD::MemIndexedMode &AM, 1716 SelectionDAG &DAG) { 1717 if (Subtarget->isThumb()) 1718 return false; 1719 1720 MVT::ValueType VT; 1721 SDOperand Ptr; 1722 bool isSEXTLoad = false; 1723 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1724 Ptr = LD->getBasePtr(); 1725 VT = LD->getLoadedVT(); 1726 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1727 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1728 Ptr = ST->getBasePtr(); 1729 VT = ST->getStoredVT(); 1730 } else 1731 return false; 1732 1733 bool isInc; 1734 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, 1735 isInc, DAG); 1736 if (isLegal) { 1737 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1738 return true; 1739 } 1740 return false; 1741} 1742 1743/// getPostIndexedAddressParts - returns true by value, base pointer and 1744/// offset pointer and addressing mode by reference if this node can be 1745/// combined with a load / store to form a post-indexed load / store. 1746bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1747 SDOperand &Base, 1748 SDOperand &Offset, 1749 ISD::MemIndexedMode &AM, 1750 SelectionDAG &DAG) { 1751 if (Subtarget->isThumb()) 1752 return false; 1753 1754 MVT::ValueType VT; 1755 SDOperand Ptr; 1756 bool isSEXTLoad = false; 1757 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1758 VT = LD->getLoadedVT(); 1759 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1760 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1761 VT = ST->getStoredVT(); 1762 } else 1763 return false; 1764 1765 bool isInc; 1766 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1767 isInc, DAG); 1768 if (isLegal) { 1769 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1770 return true; 1771 } 1772 return false; 1773} 1774 1775void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1776 uint64_t Mask, 1777 uint64_t &KnownZero, 1778 uint64_t &KnownOne, 1779 const SelectionDAG &DAG, 1780 unsigned Depth) const { 1781 KnownZero = 0; 1782 KnownOne = 0; 1783 switch (Op.getOpcode()) { 1784 default: break; 1785 case ARMISD::CMOV: { 1786 // Bits are known zero/one if known on the LHS and RHS. 1787 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1788 if (KnownZero == 0 && KnownOne == 0) return; 1789 1790 uint64_t KnownZeroRHS, KnownOneRHS; 1791 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1792 KnownZeroRHS, KnownOneRHS, Depth+1); 1793 KnownZero &= KnownZeroRHS; 1794 KnownOne &= KnownOneRHS; 1795 return; 1796 } 1797 } 1798} 1799 1800//===----------------------------------------------------------------------===// 1801// ARM Inline Assembly Support 1802//===----------------------------------------------------------------------===// 1803 1804/// getConstraintType - Given a constraint letter, return the type of 1805/// constraint it is for this target. 1806ARMTargetLowering::ConstraintType 1807ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1808 if (Constraint.size() == 1) { 1809 switch (Constraint[0]) { 1810 default: break; 1811 case 'l': return C_RegisterClass; 1812 case 'w': return C_RegisterClass; 1813 } 1814 } 1815 return TargetLowering::getConstraintType(Constraint); 1816} 1817 1818std::pair<unsigned, const TargetRegisterClass*> 1819ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1820 MVT::ValueType VT) const { 1821 if (Constraint.size() == 1) { 1822 // GCC RS6000 Constraint Letters 1823 switch (Constraint[0]) { 1824 case 'l': 1825 // FIXME: in thumb mode, 'l' is only low-regs. 1826 // FALL THROUGH. 1827 case 'r': 1828 return std::make_pair(0U, ARM::GPRRegisterClass); 1829 case 'w': 1830 if (VT == MVT::f32) 1831 return std::make_pair(0U, ARM::SPRRegisterClass); 1832 if (VT == MVT::f64) 1833 return std::make_pair(0U, ARM::DPRRegisterClass); 1834 break; 1835 } 1836 } 1837 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1838} 1839 1840std::vector<unsigned> ARMTargetLowering:: 1841getRegClassForInlineAsmConstraint(const std::string &Constraint, 1842 MVT::ValueType VT) const { 1843 if (Constraint.size() != 1) 1844 return std::vector<unsigned>(); 1845 1846 switch (Constraint[0]) { // GCC ARM Constraint Letters 1847 default: break; 1848 case 'l': 1849 case 'r': 1850 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1851 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1852 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1853 ARM::R12, ARM::LR, 0); 1854 case 'w': 1855 if (VT == MVT::f32) 1856 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1857 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1858 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1859 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1860 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1861 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1862 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1863 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1864 if (VT == MVT::f64) 1865 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1866 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1867 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1868 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1869 break; 1870 } 1871 1872 return std::vector<unsigned>(); 1873} 1874