ARMISelLowering.cpp revision e0703c84ddeb1a1276de4e38210c1127ef5df130
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/CodeGen/MachineBasicBlock.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/ADT/VectorExtras.h" 34#include "llvm/Support/MathExtras.h" 35using namespace llvm; 36 37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 38 : TargetLowering(TM), ARMPCLabelIndex(0) { 39 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 40 41 if (Subtarget->isTargetDarwin()) { 42 // Don't have these. 43 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 44 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 45 46 // Uses VFP for Thumb libfuncs if available. 47 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 48 // Single-precision floating-point arithmetic. 49 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 50 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 51 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 52 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 53 54 // Double-precision floating-point arithmetic. 55 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 56 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 57 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 58 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 59 60 // Single-precision comparisons. 61 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 62 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 63 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 64 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 65 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 66 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 67 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 68 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 69 70 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 71 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 72 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 78 79 // Double-precision comparisons. 80 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 81 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 82 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 83 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 84 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 85 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 86 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 87 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 88 89 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 97 98 // Floating-point to integer conversions. 99 // i64 conversions are done via library routines even when generating VFP 100 // instructions, so use the same ones. 101 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 102 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 103 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 105 106 // Conversions between floating types. 107 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 108 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 109 110 // Integer to floating-point conversions. 111 // i64 conversions are done via library routines even when generating VFP 112 // instructions, so use the same ones. 113 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 114 // __floatunsidf vs. __floatunssidfvfp. 115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 116 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 117 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 119 } 120 } 121 122 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 123 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 124 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 125 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 126 } 127 computeRegisterProperties(); 128 129 // ARM does not have f32 extending load. 130 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 131 132 // ARM supports all 4 flavors of integer indexed load / store. 133 for (unsigned im = (unsigned)ISD::PRE_INC; 134 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 135 setIndexedLoadAction(im, MVT::i1, Legal); 136 setIndexedLoadAction(im, MVT::i8, Legal); 137 setIndexedLoadAction(im, MVT::i16, Legal); 138 setIndexedLoadAction(im, MVT::i32, Legal); 139 setIndexedStoreAction(im, MVT::i1, Legal); 140 setIndexedStoreAction(im, MVT::i8, Legal); 141 setIndexedStoreAction(im, MVT::i16, Legal); 142 setIndexedStoreAction(im, MVT::i32, Legal); 143 } 144 145 // i64 operation support. 146 if (Subtarget->isThumb()) { 147 setOperationAction(ISD::MUL, MVT::i64, Expand); 148 setOperationAction(ISD::MULHU, MVT::i32, Expand); 149 setOperationAction(ISD::MULHS, MVT::i32, Expand); 150 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 151 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 152 } else { 153 setOperationAction(ISD::MUL, MVT::i64, Expand); 154 setOperationAction(ISD::MULHU, MVT::i32, Expand); 155 if (!Subtarget->hasV6Ops()) 156 setOperationAction(ISD::MULHS, MVT::i32, Expand); 157 } 158 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 159 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 160 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 161 setOperationAction(ISD::SRL, MVT::i64, Custom); 162 setOperationAction(ISD::SRA, MVT::i64, Custom); 163 164 // ARM does not have ROTL. 165 setOperationAction(ISD::ROTL, MVT::i32, Expand); 166 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 167 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 168 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 169 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 170 171 // Only ARMv6 has BSWAP. 172 if (!Subtarget->hasV6Ops()) 173 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 174 175 // These are expanded into libcalls. 176 setOperationAction(ISD::SDIV, MVT::i32, Expand); 177 setOperationAction(ISD::UDIV, MVT::i32, Expand); 178 setOperationAction(ISD::SREM, MVT::i32, Expand); 179 setOperationAction(ISD::UREM, MVT::i32, Expand); 180 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 181 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 182 183 // Support label based line numbers. 184 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 185 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 186 187 setOperationAction(ISD::RET, MVT::Other, Custom); 188 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 189 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 190 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 191 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 192 193 // Expand mem operations genericly. 194 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 195 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 196 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 197 198 // Use the default implementation. 199 setOperationAction(ISD::VASTART , MVT::Other, Expand); 200 setOperationAction(ISD::VAARG , MVT::Other, Expand); 201 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 202 setOperationAction(ISD::VAEND , MVT::Other, Expand); 203 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 204 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 206 207 if (!Subtarget->hasV6Ops()) { 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 210 } 211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 212 213 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 214 // Turn f64->i64 into FMRRD iff target supports vfp2. 215 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 216 217 setOperationAction(ISD::SETCC , MVT::i32, Expand); 218 setOperationAction(ISD::SETCC , MVT::f32, Expand); 219 setOperationAction(ISD::SETCC , MVT::f64, Expand); 220 setOperationAction(ISD::SELECT , MVT::i32, Expand); 221 setOperationAction(ISD::SELECT , MVT::f32, Expand); 222 setOperationAction(ISD::SELECT , MVT::f64, Expand); 223 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 224 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 225 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 226 227 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 228 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 229 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 230 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 231 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 232 233 setOperationAction(ISD::VASTART, MVT::Other, Custom); 234 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 235 setOperationAction(ISD::VAEND, MVT::Other, Expand); 236 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 237 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 238 239 // FP Constants can't be immediates. 240 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 241 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 242 243 // We don't support sin/cos/fmod/copysign/pow 244 setOperationAction(ISD::FSIN , MVT::f64, Expand); 245 setOperationAction(ISD::FSIN , MVT::f32, Expand); 246 setOperationAction(ISD::FCOS , MVT::f32, Expand); 247 setOperationAction(ISD::FCOS , MVT::f64, Expand); 248 setOperationAction(ISD::FREM , MVT::f64, Expand); 249 setOperationAction(ISD::FREM , MVT::f32, Expand); 250 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 251 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 252 setOperationAction(ISD::FPOW , MVT::f64, Expand); 253 setOperationAction(ISD::FPOW , MVT::f32, Expand); 254 255 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 258 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 259 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 260 261 setStackPointerRegisterToSaveRestore(ARM::SP); 262 setSchedulingPreference(SchedulingForRegPressure); 263 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 264 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 265 266 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 267} 268 269 270const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 271 switch (Opcode) { 272 default: return 0; 273 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 274 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 275 case ARMISD::CALL: return "ARMISD::CALL"; 276 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 277 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 278 case ARMISD::tCALL: return "ARMISD::tCALL"; 279 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 280 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 281 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 282 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 283 case ARMISD::CMP: return "ARMISD::CMP"; 284 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 285 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 286 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 287 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 288 case ARMISD::CMOV: return "ARMISD::CMOV"; 289 case ARMISD::CNEG: return "ARMISD::CNEG"; 290 291 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 292 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 293 case ARMISD::SITOF: return "ARMISD::SITOF"; 294 case ARMISD::UITOF: return "ARMISD::UITOF"; 295 296 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 297 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 298 case ARMISD::RRX: return "ARMISD::RRX"; 299 300 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 301 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 302 303 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 304 } 305} 306 307//===----------------------------------------------------------------------===// 308// Lowering Code 309//===----------------------------------------------------------------------===// 310 311 312/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 313static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 314 switch (CC) { 315 default: assert(0 && "Unknown condition code!"); 316 case ISD::SETNE: return ARMCC::NE; 317 case ISD::SETEQ: return ARMCC::EQ; 318 case ISD::SETGT: return ARMCC::GT; 319 case ISD::SETGE: return ARMCC::GE; 320 case ISD::SETLT: return ARMCC::LT; 321 case ISD::SETLE: return ARMCC::LE; 322 case ISD::SETUGT: return ARMCC::HI; 323 case ISD::SETUGE: return ARMCC::HS; 324 case ISD::SETULT: return ARMCC::LO; 325 case ISD::SETULE: return ARMCC::LS; 326 } 327} 328 329/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 330/// returns true if the operands should be inverted to form the proper 331/// comparison. 332static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 333 ARMCC::CondCodes &CondCode2) { 334 bool Invert = false; 335 CondCode2 = ARMCC::AL; 336 switch (CC) { 337 default: assert(0 && "Unknown FP condition!"); 338 case ISD::SETEQ: 339 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 340 case ISD::SETGT: 341 case ISD::SETOGT: CondCode = ARMCC::GT; break; 342 case ISD::SETGE: 343 case ISD::SETOGE: CondCode = ARMCC::GE; break; 344 case ISD::SETOLT: CondCode = ARMCC::MI; break; 345 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 346 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 347 case ISD::SETO: CondCode = ARMCC::VC; break; 348 case ISD::SETUO: CondCode = ARMCC::VS; break; 349 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 350 case ISD::SETUGT: CondCode = ARMCC::HI; break; 351 case ISD::SETUGE: CondCode = ARMCC::PL; break; 352 case ISD::SETLT: 353 case ISD::SETULT: CondCode = ARMCC::LT; break; 354 case ISD::SETLE: 355 case ISD::SETULE: CondCode = ARMCC::LE; break; 356 case ISD::SETNE: 357 case ISD::SETUNE: CondCode = ARMCC::NE; break; 358 } 359 return Invert; 360} 361 362static void 363HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, 364 unsigned StackOffset, unsigned &NeededGPRs, 365 unsigned &NeededStackSize, unsigned &GPRPad, 366 unsigned &StackPad, unsigned Flags) { 367 NeededStackSize = 0; 368 NeededGPRs = 0; 369 StackPad = 0; 370 GPRPad = 0; 371 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); 372 GPRPad = NumGPRs % ((align + 3)/4); 373 StackPad = StackOffset % align; 374 unsigned firstGPR = NumGPRs + GPRPad; 375 switch (ObjectVT) { 376 default: assert(0 && "Unhandled argument type!"); 377 case MVT::i32: 378 case MVT::f32: 379 if (firstGPR < 4) 380 NeededGPRs = 1; 381 else 382 NeededStackSize = 4; 383 break; 384 case MVT::i64: 385 case MVT::f64: 386 if (firstGPR < 3) 387 NeededGPRs = 2; 388 else if (firstGPR == 3) { 389 NeededGPRs = 1; 390 NeededStackSize = 4; 391 } else 392 NeededStackSize = 8; 393 } 394} 395 396/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 397/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 398/// nodes. 399SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 400 MVT::ValueType RetVT= Op.Val->getValueType(0); 401 SDOperand Chain = Op.getOperand(0); 402 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 403 assert((CallConv == CallingConv::C || 404 CallConv == CallingConv::Fast) && "unknown calling convention"); 405 SDOperand Callee = Op.getOperand(4); 406 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 407 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 408 unsigned NumGPRs = 0; // GPRs used for parameter passing. 409 410 // Count how many bytes are to be pushed on the stack. 411 unsigned NumBytes = 0; 412 413 // Add up all the space actually used. 414 for (unsigned i = 0; i < NumOps; ++i) { 415 unsigned ObjSize; 416 unsigned ObjGPRs; 417 unsigned StackPad; 418 unsigned GPRPad; 419 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); 420 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 421 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 422 GPRPad, StackPad, Flags); 423 NumBytes += ObjSize + StackPad; 424 NumGPRs += ObjGPRs + GPRPad; 425 } 426 427 // Adjust the stack pointer for the new arguments... 428 // These operations are automatically eliminated by the prolog/epilog pass 429 Chain = DAG.getCALLSEQ_START(Chain, 430 DAG.getConstant(NumBytes, MVT::i32)); 431 432 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 433 434 static const unsigned GPRArgRegs[] = { 435 ARM::R0, ARM::R1, ARM::R2, ARM::R3 436 }; 437 438 NumGPRs = 0; 439 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 440 std::vector<SDOperand> MemOpChains; 441 for (unsigned i = 0; i != NumOps; ++i) { 442 SDOperand Arg = Op.getOperand(5+2*i); 443 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 444 MVT::ValueType ArgVT = Arg.getValueType(); 445 446 unsigned ObjSize; 447 unsigned ObjGPRs; 448 unsigned GPRPad; 449 unsigned StackPad; 450 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 451 ObjSize, GPRPad, StackPad, Flags); 452 NumGPRs += GPRPad; 453 ArgOffset += StackPad; 454 if (ObjGPRs > 0) { 455 switch (ArgVT) { 456 default: assert(0 && "Unexpected ValueType for argument!"); 457 case MVT::i32: 458 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 459 break; 460 case MVT::f32: 461 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 462 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 463 break; 464 case MVT::i64: { 465 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 466 DAG.getConstant(0, getPointerTy())); 467 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 468 DAG.getConstant(1, getPointerTy())); 469 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 470 if (ObjGPRs == 2) 471 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 472 else { 473 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 474 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 475 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 476 } 477 break; 478 } 479 case MVT::f64: { 480 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, 481 DAG.getVTList(MVT::i32, MVT::i32), 482 &Arg, 1); 483 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 484 if (ObjGPRs == 2) 485 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 486 Cvt.getValue(1))); 487 else { 488 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 489 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 490 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 491 NULL, 0)); 492 } 493 break; 494 } 495 } 496 } else { 497 assert(ObjSize != 0); 498 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 499 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 500 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 501 } 502 503 NumGPRs += ObjGPRs; 504 ArgOffset += ObjSize; 505 } 506 507 if (!MemOpChains.empty()) 508 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 509 &MemOpChains[0], MemOpChains.size()); 510 511 // Build a sequence of copy-to-reg nodes chained together with token chain 512 // and flag operands which copy the outgoing args into the appropriate regs. 513 SDOperand InFlag; 514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 515 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 516 InFlag); 517 InFlag = Chain.getValue(1); 518 } 519 520 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 521 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 522 // node so that legalize doesn't hack it. 523 bool isDirect = false; 524 bool isARMFunc = false; 525 bool isLocalARMFunc = false; 526 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 527 GlobalValue *GV = G->getGlobal(); 528 isDirect = true; 529 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 530 GV->hasLinkOnceLinkage()); 531 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 532 getTargetMachine().getRelocationModel() != Reloc::Static; 533 isARMFunc = !Subtarget->isThumb() || isStub; 534 // ARM call to a local ARM function is predicable. 535 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 536 // tBX takes a register source operand. 537 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 538 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 539 ARMCP::CPStub, 4); 540 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 541 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 542 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 543 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 544 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 545 } else 546 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 547 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 548 isDirect = true; 549 bool isStub = Subtarget->isTargetDarwin() && 550 getTargetMachine().getRelocationModel() != Reloc::Static; 551 isARMFunc = !Subtarget->isThumb() || isStub; 552 // tBX takes a register source operand. 553 const char *Sym = S->getSymbol(); 554 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 555 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 556 ARMCP::CPStub, 4); 557 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 558 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 559 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 560 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 561 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 562 } else 563 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 564 } 565 566 // FIXME: handle tail calls differently. 567 unsigned CallOpc; 568 if (Subtarget->isThumb()) { 569 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 570 CallOpc = ARMISD::CALL_NOLINK; 571 else 572 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 573 } else { 574 CallOpc = (isDirect || Subtarget->hasV5TOps()) 575 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 576 : ARMISD::CALL_NOLINK; 577 } 578 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 579 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 580 Chain = DAG.getCopyToReg(Chain, ARM::LR, 581 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 582 InFlag = Chain.getValue(1); 583 } 584 585 std::vector<MVT::ValueType> NodeTys; 586 NodeTys.push_back(MVT::Other); // Returns a chain 587 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 588 589 std::vector<SDOperand> Ops; 590 Ops.push_back(Chain); 591 Ops.push_back(Callee); 592 593 // Add argument registers to the end of the list so that they are known live 594 // into the call. 595 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 596 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 597 RegsToPass[i].second.getValueType())); 598 599 if (InFlag.Val) 600 Ops.push_back(InFlag); 601 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 602 InFlag = Chain.getValue(1); 603 604 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; 605 Chain = DAG.getNode(ISD::CALLSEQ_END, 606 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 607 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); 608 if (RetVT != MVT::Other) 609 InFlag = Chain.getValue(1); 610 611 std::vector<SDOperand> ResultVals; 612 NodeTys.clear(); 613 614 // If the call has results, copy the values out of the ret val registers. 615 switch (RetVT) { 616 default: assert(0 && "Unexpected ret value!"); 617 case MVT::Other: 618 break; 619 case MVT::i32: 620 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 621 ResultVals.push_back(Chain.getValue(0)); 622 if (Op.Val->getValueType(1) == MVT::i32) { 623 // Returns a i64 value. 624 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 625 Chain.getValue(2)).getValue(1); 626 ResultVals.push_back(Chain.getValue(0)); 627 NodeTys.push_back(MVT::i32); 628 } 629 NodeTys.push_back(MVT::i32); 630 break; 631 case MVT::f32: 632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 633 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 634 Chain.getValue(0))); 635 NodeTys.push_back(MVT::f32); 636 break; 637 case MVT::f64: { 638 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 639 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 640 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 641 NodeTys.push_back(MVT::f64); 642 break; 643 } 644 } 645 646 NodeTys.push_back(MVT::Other); 647 648 if (ResultVals.empty()) 649 return Chain; 650 651 ResultVals.push_back(Chain); 652 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 653 ResultVals.size()); 654 return Res.getValue(Op.ResNo); 655} 656 657static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 658 SDOperand Copy; 659 SDOperand Chain = Op.getOperand(0); 660 switch(Op.getNumOperands()) { 661 default: 662 assert(0 && "Do not know how to return this many arguments!"); 663 abort(); 664 case 1: { 665 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); 666 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 667 } 668 case 3: 669 Op = Op.getOperand(1); 670 if (Op.getValueType() == MVT::f32) { 671 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 672 } else if (Op.getValueType() == MVT::f64) { 673 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 674 // available. 675 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); 676 SDOperand Sign = DAG.getConstant(0, MVT::i32); 677 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 678 Op.getValue(1), Sign); 679 } 680 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); 681 if (DAG.getMachineFunction().liveout_empty()) 682 DAG.getMachineFunction().addLiveOut(ARM::R0); 683 break; 684 case 5: 685 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 686 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 687 // If we haven't noted the R0+R1 are live out, do so now. 688 if (DAG.getMachineFunction().liveout_empty()) { 689 DAG.getMachineFunction().addLiveOut(ARM::R0); 690 DAG.getMachineFunction().addLiveOut(ARM::R1); 691 } 692 break; 693 } 694 695 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 696 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 697} 698 699// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 700// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 701// one of the above mentioned nodes. It has to be wrapped because otherwise 702// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 703// be used to form addressing mode. These wrapped nodes will be selected 704// into MOVi. 705static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 706 MVT::ValueType PtrVT = Op.getValueType(); 707 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 708 SDOperand Res; 709 if (CP->isMachineConstantPoolEntry()) 710 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 711 CP->getAlignment()); 712 else 713 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 714 CP->getAlignment()); 715 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 716} 717 718// Lower ISD::GlobalTLSAddress using the "general dynamic" model 719SDOperand 720ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 721 SelectionDAG &DAG) { 722 MVT::ValueType PtrVT = getPointerTy(); 723 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 724 ARMConstantPoolValue *CPV = 725 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 726 PCAdj, "tlsgd", true); 727 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 728 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 729 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 730 SDOperand Chain = Argument.getValue(1); 731 732 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 733 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 734 735 // call __tls_get_addr. 736 ArgListTy Args; 737 ArgListEntry Entry; 738 Entry.Node = Argument; 739 Entry.Ty = (const Type *) Type::Int32Ty; 740 Args.push_back(Entry); 741 std::pair<SDOperand, SDOperand> CallResult = 742 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, 743 CallingConv::C, false, 744 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 745 return CallResult.first; 746} 747 748// Lower ISD::GlobalTLSAddress using the "initial exec" or 749// "local exec" model. 750SDOperand 751ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 752 SelectionDAG &DAG) { 753 GlobalValue *GV = GA->getGlobal(); 754 SDOperand Offset; 755 SDOperand Chain = DAG.getEntryNode(); 756 MVT::ValueType PtrVT = getPointerTy(); 757 // Get the Thread Pointer 758 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 759 760 if (GV->isDeclaration()){ 761 // initial exec model 762 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 763 ARMConstantPoolValue *CPV = 764 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 765 PCAdj, "gottpoff", true); 766 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 767 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 768 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 769 Chain = Offset.getValue(1); 770 771 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 772 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 773 774 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 775 } else { 776 // local exec model 777 ARMConstantPoolValue *CPV = 778 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 779 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 780 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 781 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 782 } 783 784 // The address of the thread local variable is the add of the thread 785 // pointer with the offset of the variable. 786 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 787} 788 789SDOperand 790ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 791 // TODO: implement the "local dynamic" model 792 assert(Subtarget->isTargetELF() && 793 "TLS not implemented for non-ELF targets"); 794 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 795 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 796 // otherwise use the "Local Exec" TLS Model 797 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 798 return LowerToTLSGeneralDynamicModel(GA, DAG); 799 else 800 return LowerToTLSExecModels(GA, DAG); 801} 802 803SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, 804 SelectionDAG &DAG) { 805 MVT::ValueType PtrVT = getPointerTy(); 806 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 807 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 808 if (RelocM == Reloc::PIC_) { 809 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 810 ARMConstantPoolValue *CPV = 811 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 812 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 813 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 814 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 815 SDOperand Chain = Result.getValue(1); 816 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 817 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 818 if (!UseGOTOFF) 819 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 820 return Result; 821 } else { 822 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 823 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 824 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 825 } 826} 827 828/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 829/// even in non-static mode. 830static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 831 return RelocM != Reloc::Static && 832 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 833 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 834} 835 836SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, 837 SelectionDAG &DAG) { 838 MVT::ValueType PtrVT = getPointerTy(); 839 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 840 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 841 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 842 SDOperand CPAddr; 843 if (RelocM == Reloc::Static) 844 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 845 else { 846 unsigned PCAdj = (RelocM != Reloc::PIC_) 847 ? 0 : (Subtarget->isThumb() ? 4 : 8); 848 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 849 : ARMCP::CPValue; 850 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 851 Kind, PCAdj); 852 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 853 } 854 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 855 856 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 857 SDOperand Chain = Result.getValue(1); 858 859 if (RelocM == Reloc::PIC_) { 860 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 861 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 862 } 863 if (IsIndirect) 864 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 865 866 return Result; 867} 868 869SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, 870 SelectionDAG &DAG){ 871 assert(Subtarget->isTargetELF() && 872 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 873 MVT::ValueType PtrVT = getPointerTy(); 874 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 875 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 876 ARMPCLabelIndex, 877 ARMCP::CPValue, PCAdj); 878 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 879 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 880 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 881 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 882 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 883} 884 885static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 886 unsigned VarArgsFrameIndex) { 887 // vastart just stores the address of the VarArgsFrameIndex slot into the 888 // memory location argument. 889 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 890 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 891 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 892 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 893 SV->getOffset()); 894} 895 896static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, 897 unsigned *vRegs, unsigned ArgNo, 898 unsigned &NumGPRs, unsigned &ArgOffset) { 899 MachineFunction &MF = DAG.getMachineFunction(); 900 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 901 SDOperand Root = Op.getOperand(0); 902 std::vector<SDOperand> ArgValues; 903 SSARegMap *RegMap = MF.getSSARegMap(); 904 905 static const unsigned GPRArgRegs[] = { 906 ARM::R0, ARM::R1, ARM::R2, ARM::R3 907 }; 908 909 unsigned ObjSize; 910 unsigned ObjGPRs; 911 unsigned GPRPad; 912 unsigned StackPad; 913 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3); 914 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 915 ObjSize, GPRPad, StackPad, Flags); 916 NumGPRs += GPRPad; 917 ArgOffset += StackPad; 918 919 SDOperand ArgValue; 920 if (ObjGPRs == 1) { 921 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 922 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 923 vRegs[NumGPRs] = VReg; 924 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 925 if (ObjectVT == MVT::f32) 926 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 927 } else if (ObjGPRs == 2) { 928 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 929 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 930 vRegs[NumGPRs] = VReg; 931 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 932 933 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 934 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 935 vRegs[NumGPRs+1] = VReg; 936 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 937 938 if (ObjectVT == MVT::i64) 939 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 940 else 941 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 942 } 943 NumGPRs += ObjGPRs; 944 945 if (ObjSize) { 946 // If the argument is actually used, emit a load from the right stack 947 // slot. 948 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 949 MachineFrameInfo *MFI = MF.getFrameInfo(); 950 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 951 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 952 if (ObjGPRs == 0) 953 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 954 else { 955 SDOperand ArgValue2 = 956 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 957 if (ObjectVT == MVT::i64) 958 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 959 else 960 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 961 } 962 } else { 963 // Don't emit a dead load. 964 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); 965 } 966 967 ArgOffset += ObjSize; // Move on to the next argument. 968 } 969 970 return ArgValue; 971} 972 973SDOperand 974ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 975 std::vector<SDOperand> ArgValues; 976 SDOperand Root = Op.getOperand(0); 977 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 978 unsigned NumGPRs = 0; // GPRs used for parameter passing. 979 unsigned VRegs[4]; 980 981 unsigned NumArgs = Op.Val->getNumValues()-1; 982 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 983 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, 984 NumGPRs, ArgOffset)); 985 986 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 987 if (isVarArg) { 988 static const unsigned GPRArgRegs[] = { 989 ARM::R0, ARM::R1, ARM::R2, ARM::R3 990 }; 991 992 MachineFunction &MF = DAG.getMachineFunction(); 993 SSARegMap *RegMap = MF.getSSARegMap(); 994 MachineFrameInfo *MFI = MF.getFrameInfo(); 995 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 996 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 997 unsigned VARegSize = (4 - NumGPRs) * 4; 998 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 999 if (VARegSaveSize) { 1000 // If this function is vararg, store any remaining integer argument regs 1001 // to their spots on the stack so that they may be loaded by deferencing 1002 // the result of va_next. 1003 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1004 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1005 VARegSaveSize - VARegSize); 1006 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1007 1008 SmallVector<SDOperand, 4> MemOps; 1009 for (; NumGPRs < 4; ++NumGPRs) { 1010 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 1011 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1012 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1013 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1014 MemOps.push_back(Store); 1015 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1016 DAG.getConstant(4, getPointerTy())); 1017 } 1018 if (!MemOps.empty()) 1019 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1020 &MemOps[0], MemOps.size()); 1021 } else 1022 // This will point to the next argument passed via stack. 1023 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1024 } 1025 1026 ArgValues.push_back(Root); 1027 1028 // Return the new list of results. 1029 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1030 Op.Val->value_end()); 1031 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1032} 1033 1034/// isFloatingPointZero - Return true if this is +0.0. 1035static bool isFloatingPointZero(SDOperand Op) { 1036 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1037 return CFP->getValueAPF().isPosZero(); 1038 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 1039 // Maybe this has already been legalized into the constant pool? 1040 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1041 SDOperand WrapperOp = Op.getOperand(1).getOperand(0); 1042 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1043 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1044 return CFP->getValueAPF().isPosZero(); 1045 } 1046 } 1047 return false; 1048} 1049 1050static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1051 return ( isThumb && (C & ~255U) == 0) || 1052 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1053} 1054 1055/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1056/// the given operands. 1057static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, 1058 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { 1059 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { 1060 unsigned C = RHSC->getValue(); 1061 if (!isLegalCmpImmediate(C, isThumb)) { 1062 // Constant does not fit, try adjusting it by one? 1063 switch (CC) { 1064 default: break; 1065 case ISD::SETLT: 1066 case ISD::SETGE: 1067 if (isLegalCmpImmediate(C-1, isThumb)) { 1068 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1069 RHS = DAG.getConstant(C-1, MVT::i32); 1070 } 1071 break; 1072 case ISD::SETULT: 1073 case ISD::SETUGE: 1074 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1075 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1076 RHS = DAG.getConstant(C-1, MVT::i32); 1077 } 1078 break; 1079 case ISD::SETLE: 1080 case ISD::SETGT: 1081 if (isLegalCmpImmediate(C+1, isThumb)) { 1082 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1083 RHS = DAG.getConstant(C+1, MVT::i32); 1084 } 1085 break; 1086 case ISD::SETULE: 1087 case ISD::SETUGT: 1088 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1089 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1090 RHS = DAG.getConstant(C+1, MVT::i32); 1091 } 1092 break; 1093 } 1094 } 1095 } 1096 1097 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1098 ARMISD::NodeType CompareType; 1099 switch (CondCode) { 1100 default: 1101 CompareType = ARMISD::CMP; 1102 break; 1103 case ARMCC::EQ: 1104 case ARMCC::NE: 1105 case ARMCC::MI: 1106 case ARMCC::PL: 1107 // Uses only N and Z Flags 1108 CompareType = ARMISD::CMPNZ; 1109 break; 1110 } 1111 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1112 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1113} 1114 1115/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1116static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { 1117 SDOperand Cmp; 1118 if (!isFloatingPointZero(RHS)) 1119 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1120 else 1121 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1122 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1123} 1124 1125static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, 1126 const ARMSubtarget *ST) { 1127 MVT::ValueType VT = Op.getValueType(); 1128 SDOperand LHS = Op.getOperand(0); 1129 SDOperand RHS = Op.getOperand(1); 1130 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1131 SDOperand TrueVal = Op.getOperand(2); 1132 SDOperand FalseVal = Op.getOperand(3); 1133 1134 if (LHS.getValueType() == MVT::i32) { 1135 SDOperand ARMCC; 1136 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1137 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1138 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1139 } 1140 1141 ARMCC::CondCodes CondCode, CondCode2; 1142 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1143 std::swap(TrueVal, FalseVal); 1144 1145 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1146 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1147 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1148 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1149 ARMCC, CCR, Cmp); 1150 if (CondCode2 != ARMCC::AL) { 1151 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1152 // FIXME: Needs another CMP because flag can have but one use. 1153 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); 1154 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1155 } 1156 return Result; 1157} 1158 1159static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, 1160 const ARMSubtarget *ST) { 1161 SDOperand Chain = Op.getOperand(0); 1162 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1163 SDOperand LHS = Op.getOperand(2); 1164 SDOperand RHS = Op.getOperand(3); 1165 SDOperand Dest = Op.getOperand(4); 1166 1167 if (LHS.getValueType() == MVT::i32) { 1168 SDOperand ARMCC; 1169 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1170 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1171 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1172 } 1173 1174 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1175 ARMCC::CondCodes CondCode, CondCode2; 1176 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1177 // Swap the LHS/RHS of the comparison if needed. 1178 std::swap(LHS, RHS); 1179 1180 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1181 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1182 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1183 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1184 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1185 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1186 if (CondCode2 != ARMCC::AL) { 1187 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1188 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1189 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1190 } 1191 return Res; 1192} 1193 1194SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { 1195 SDOperand Chain = Op.getOperand(0); 1196 SDOperand Table = Op.getOperand(1); 1197 SDOperand Index = Op.getOperand(2); 1198 1199 MVT::ValueType PTy = getPointerTy(); 1200 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1201 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1202 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1203 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1204 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1205 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1206 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1207 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1208 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, 1209 Chain, Addr, NULL, 0); 1210 Chain = Addr.getValue(1); 1211 if (isPIC) 1212 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1213 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1214} 1215 1216static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { 1217 unsigned Opc = 1218 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1219 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1220 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1221} 1222 1223static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1224 MVT::ValueType VT = Op.getValueType(); 1225 unsigned Opc = 1226 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1227 1228 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1229 return DAG.getNode(Opc, VT, Op); 1230} 1231 1232static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 1233 // Implement fcopysign with a fabs and a conditional fneg. 1234 SDOperand Tmp0 = Op.getOperand(0); 1235 SDOperand Tmp1 = Op.getOperand(1); 1236 MVT::ValueType VT = Op.getValueType(); 1237 MVT::ValueType SrcVT = Tmp1.getValueType(); 1238 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1239 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1240 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1241 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1242 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1243} 1244 1245static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) { 1246 // Turn f64->i64 into FMRRD. 1247 assert(Op.getValueType() == MVT::i64 && 1248 Op.getOperand(0).getValueType() == MVT::f64); 1249 1250 Op = Op.getOperand(0); 1251 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1252 &Op, 1); 1253 1254 // Merge the pieces into a single i64 value. 1255 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); 1256} 1257 1258static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG, 1259 const ARMSubtarget *ST) { 1260 assert(Op.getValueType() == MVT::i64 && 1261 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && 1262 "Unknown shift to lower!"); 1263 1264 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1265 if (!isa<ConstantSDNode>(Op.getOperand(1)) || 1266 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1) 1267 return SDOperand(); 1268 1269 // If we are in thumb mode, we don't have RRX. 1270 if (ST->isThumb()) return SDOperand(); 1271 1272 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1273 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1274 DAG.getConstant(0, MVT::i32)); 1275 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1276 DAG.getConstant(1, MVT::i32)); 1277 1278 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1279 // captures the result into a carry flag. 1280 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1281 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1282 1283 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1284 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1285 1286 // Merge the pieces into a single i64 value. 1287 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1288} 1289 1290SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 1291 SDOperand ChainOp = Op.getOperand(0); 1292 SDOperand DestOp = Op.getOperand(1); 1293 SDOperand SourceOp = Op.getOperand(2); 1294 SDOperand CountOp = Op.getOperand(3); 1295 SDOperand AlignOp = Op.getOperand(4); 1296 SDOperand AlwaysInlineOp = Op.getOperand(5); 1297 1298 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 1299 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 1300 if (Align == 0) Align = 1; 1301 1302 // If size is unknown, call memcpy. 1303 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 1304 if (!I) { 1305 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 1306 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 1307 } 1308 1309 // If not DWORD aligned or if size is more than threshold, then call memcpy. 1310 // The libc version is likely to be faster for the these cases. It can 1311 // use the address value and run time information about the CPU. 1312 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 1313 unsigned Size = I->getValue(); 1314 if (AlwaysInline || 1315 (Size <= Subtarget->getMaxInlineSizeThreshold() && 1316 (Align & 3) == 0)) 1317 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 1318 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 1319} 1320 1321SDOperand ARMTargetLowering::LowerMEMCPYCall(SDOperand Chain, 1322 SDOperand Dest, 1323 SDOperand Source, 1324 SDOperand Count, 1325 SelectionDAG &DAG) { 1326 MVT::ValueType IntPtr = getPointerTy(); 1327 TargetLowering::ArgListTy Args; 1328 TargetLowering::ArgListEntry Entry; 1329 Entry.Ty = getTargetData()->getIntPtrType(); 1330 Entry.Node = Dest; Args.push_back(Entry); 1331 Entry.Node = Source; Args.push_back(Entry); 1332 Entry.Node = Count; Args.push_back(Entry); 1333 std::pair<SDOperand,SDOperand> CallResult = 1334 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 1335 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 1336 return CallResult.second; 1337} 1338 1339SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain, 1340 SDOperand Dest, 1341 SDOperand Source, 1342 unsigned Size, 1343 unsigned Align, 1344 SelectionDAG &DAG) { 1345 // Do repeated 4-byte loads and stores. To be improved. 1346 assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!"); 1347 unsigned BytesLeft = Size & 3; 1348 unsigned NumMemOps = Size >> 2; 1349 unsigned EmittedNumMemOps = 0; 1350 unsigned SrcOff = 0, DstOff = 0; 1351 MVT::ValueType VT = MVT::i32; 1352 unsigned VTSize = 4; 1353 unsigned i = 0; 1354 const unsigned MAX_LOADS_IN_LDM = 6; 1355 SDOperand TFOps[MAX_LOADS_IN_LDM]; 1356 SDOperand Loads[MAX_LOADS_IN_LDM]; 1357 1358 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1359 // same number of stores. The loads and stores will get combined into 1360 // ldm/stm later on. 1361 while (EmittedNumMemOps < NumMemOps) { 1362 for (i = 0; 1363 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1364 Loads[i] = DAG.getLoad(VT, Chain, 1365 DAG.getNode(ISD::ADD, MVT::i32, Source, 1366 DAG.getConstant(SrcOff, MVT::i32)), 1367 NULL, 0); 1368 TFOps[i] = Loads[i].getValue(1); 1369 SrcOff += VTSize; 1370 } 1371 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1372 1373 for (i = 0; 1374 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1375 TFOps[i] = DAG.getStore(Chain, Loads[i], 1376 DAG.getNode(ISD::ADD, MVT::i32, Dest, 1377 DAG.getConstant(DstOff, MVT::i32)), 1378 NULL, 0); 1379 DstOff += VTSize; 1380 } 1381 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1382 1383 EmittedNumMemOps += i; 1384 } 1385 1386 if (BytesLeft == 0) 1387 return Chain; 1388 1389 // Issue loads / stores for the trailing (1 - 3) bytes. 1390 unsigned BytesLeftSave = BytesLeft; 1391 i = 0; 1392 while (BytesLeft) { 1393 if (BytesLeft >= 2) { 1394 VT = MVT::i16; 1395 VTSize = 2; 1396 } else { 1397 VT = MVT::i8; 1398 VTSize = 1; 1399 } 1400 1401 Loads[i] = DAG.getLoad(VT, Chain, 1402 DAG.getNode(ISD::ADD, MVT::i32, Source, 1403 DAG.getConstant(SrcOff, MVT::i32)), 1404 NULL, 0); 1405 TFOps[i] = Loads[i].getValue(1); 1406 ++i; 1407 SrcOff += VTSize; 1408 BytesLeft -= VTSize; 1409 } 1410 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1411 1412 i = 0; 1413 BytesLeft = BytesLeftSave; 1414 while (BytesLeft) { 1415 if (BytesLeft >= 2) { 1416 VT = MVT::i16; 1417 VTSize = 2; 1418 } else { 1419 VT = MVT::i8; 1420 VTSize = 1; 1421 } 1422 1423 TFOps[i] = DAG.getStore(Chain, Loads[i], 1424 DAG.getNode(ISD::ADD, MVT::i32, Dest, 1425 DAG.getConstant(DstOff, MVT::i32)), 1426 NULL, 0); 1427 ++i; 1428 DstOff += VTSize; 1429 BytesLeft -= VTSize; 1430 } 1431 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1432} 1433 1434SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1435 switch (Op.getOpcode()) { 1436 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1437 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1438 case ISD::GlobalAddress: 1439 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1440 LowerGlobalAddressELF(Op, DAG); 1441 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1442 case ISD::CALL: return LowerCALL(Op, DAG); 1443 case ISD::RET: return LowerRET(Op, DAG); 1444 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1445 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1446 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1447 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1448 case ISD::SINT_TO_FP: 1449 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1450 case ISD::FP_TO_SINT: 1451 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1452 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1453 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 1454 case ISD::SRL: 1455 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); 1456 case ISD::FORMAL_ARGUMENTS: 1457 return LowerFORMAL_ARGUMENTS(Op, DAG); 1458 case ISD::RETURNADDR: break; 1459 case ISD::FRAMEADDR: break; 1460 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1461 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 1462 } 1463 return SDOperand(); 1464} 1465 1466//===----------------------------------------------------------------------===// 1467// ARM Scheduler Hooks 1468//===----------------------------------------------------------------------===// 1469 1470MachineBasicBlock * 1471ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1472 MachineBasicBlock *BB) { 1473 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1474 switch (MI->getOpcode()) { 1475 default: assert(false && "Unexpected instr type to insert"); 1476 case ARM::tMOVCCr: { 1477 // To "insert" a SELECT_CC instruction, we actually have to insert the 1478 // diamond control-flow pattern. The incoming instruction knows the 1479 // destination vreg to set, the condition code register to branch on, the 1480 // true/false values to select between, and a branch opcode to use. 1481 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1482 ilist<MachineBasicBlock>::iterator It = BB; 1483 ++It; 1484 1485 // thisMBB: 1486 // ... 1487 // TrueVal = ... 1488 // cmpTY ccX, r1, r2 1489 // bCC copy1MBB 1490 // fallthrough --> copy0MBB 1491 MachineBasicBlock *thisMBB = BB; 1492 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1493 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1494 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1495 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1496 MachineFunction *F = BB->getParent(); 1497 F->getBasicBlockList().insert(It, copy0MBB); 1498 F->getBasicBlockList().insert(It, sinkMBB); 1499 // Update machine-CFG edges by first adding all successors of the current 1500 // block to the new block which will contain the Phi node for the select. 1501 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1502 e = BB->succ_end(); i != e; ++i) 1503 sinkMBB->addSuccessor(*i); 1504 // Next, remove all successors of the current block, and add the true 1505 // and fallthrough blocks as its successors. 1506 while(!BB->succ_empty()) 1507 BB->removeSuccessor(BB->succ_begin()); 1508 BB->addSuccessor(copy0MBB); 1509 BB->addSuccessor(sinkMBB); 1510 1511 // copy0MBB: 1512 // %FalseValue = ... 1513 // # fallthrough to sinkMBB 1514 BB = copy0MBB; 1515 1516 // Update machine-CFG edges 1517 BB->addSuccessor(sinkMBB); 1518 1519 // sinkMBB: 1520 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1521 // ... 1522 BB = sinkMBB; 1523 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1524 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1525 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1526 1527 delete MI; // The pseudo instruction is gone now. 1528 return BB; 1529 } 1530 } 1531} 1532 1533//===----------------------------------------------------------------------===// 1534// ARM Optimization Hooks 1535//===----------------------------------------------------------------------===// 1536 1537/// isLegalAddressImmediate - Return true if the integer value can be used 1538/// as the offset of the target addressing mode for load / store of the 1539/// given type. 1540static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, 1541 const ARMSubtarget *Subtarget) { 1542 if (V == 0) 1543 return true; 1544 1545 if (Subtarget->isThumb()) { 1546 if (V < 0) 1547 return false; 1548 1549 unsigned Scale = 1; 1550 switch (VT) { 1551 default: return false; 1552 case MVT::i1: 1553 case MVT::i8: 1554 // Scale == 1; 1555 break; 1556 case MVT::i16: 1557 // Scale == 2; 1558 Scale = 2; 1559 break; 1560 case MVT::i32: 1561 // Scale == 4; 1562 Scale = 4; 1563 break; 1564 } 1565 1566 if ((V & (Scale - 1)) != 0) 1567 return false; 1568 V /= Scale; 1569 return V == V & ((1LL << 5) - 1); 1570 } 1571 1572 if (V < 0) 1573 V = - V; 1574 switch (VT) { 1575 default: return false; 1576 case MVT::i1: 1577 case MVT::i8: 1578 case MVT::i32: 1579 // +- imm12 1580 return V == V & ((1LL << 12) - 1); 1581 case MVT::i16: 1582 // +- imm8 1583 return V == V & ((1LL << 8) - 1); 1584 case MVT::f32: 1585 case MVT::f64: 1586 if (!Subtarget->hasVFP2()) 1587 return false; 1588 if ((V & 3) != 0) 1589 return false; 1590 V >>= 2; 1591 return V == V & ((1LL << 8) - 1); 1592 } 1593} 1594 1595/// isLegalAddressingMode - Return true if the addressing mode represented 1596/// by AM is legal for this target, for a load/store of the specified type. 1597bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1598 const Type *Ty) const { 1599 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget)) 1600 return false; 1601 1602 // Can never fold addr of global into load/store. 1603 if (AM.BaseGV) 1604 return false; 1605 1606 switch (AM.Scale) { 1607 case 0: // no scale reg, must be "r+i" or "r", or "i". 1608 break; 1609 case 1: 1610 if (Subtarget->isThumb()) 1611 return false; 1612 // FALL THROUGH. 1613 default: 1614 // ARM doesn't support any R+R*scale+imm addr modes. 1615 if (AM.BaseOffs) 1616 return false; 1617 1618 int Scale = AM.Scale; 1619 switch (getValueType(Ty)) { 1620 default: return false; 1621 case MVT::i1: 1622 case MVT::i8: 1623 case MVT::i32: 1624 case MVT::i64: 1625 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1626 // ldrd / strd are used, then its address mode is same as i16. 1627 // r + r 1628 if (Scale < 0) Scale = -Scale; 1629 if (Scale == 1) 1630 return true; 1631 // r + r << imm 1632 return isPowerOf2_32(Scale & ~1); 1633 case MVT::i16: 1634 // r + r 1635 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1636 return true; 1637 return false; 1638 1639 case MVT::isVoid: 1640 // Note, we allow "void" uses (basically, uses that aren't loads or 1641 // stores), because arm allows folding a scale into many arithmetic 1642 // operations. This should be made more precise and revisited later. 1643 1644 // Allow r << imm, but the imm has to be a multiple of two. 1645 if (AM.Scale & 1) return false; 1646 return isPowerOf2_32(AM.Scale); 1647 } 1648 break; 1649 } 1650 return true; 1651} 1652 1653 1654static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, 1655 bool isSEXTLoad, SDOperand &Base, 1656 SDOperand &Offset, bool &isInc, 1657 SelectionDAG &DAG) { 1658 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1659 return false; 1660 1661 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1662 // AddressingMode 3 1663 Base = Ptr->getOperand(0); 1664 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1665 int RHSC = (int)RHS->getValue(); 1666 if (RHSC < 0 && RHSC > -256) { 1667 isInc = false; 1668 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1669 return true; 1670 } 1671 } 1672 isInc = (Ptr->getOpcode() == ISD::ADD); 1673 Offset = Ptr->getOperand(1); 1674 return true; 1675 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1676 // AddressingMode 2 1677 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1678 int RHSC = (int)RHS->getValue(); 1679 if (RHSC < 0 && RHSC > -0x1000) { 1680 isInc = false; 1681 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1682 Base = Ptr->getOperand(0); 1683 return true; 1684 } 1685 } 1686 1687 if (Ptr->getOpcode() == ISD::ADD) { 1688 isInc = true; 1689 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1690 if (ShOpcVal != ARM_AM::no_shift) { 1691 Base = Ptr->getOperand(1); 1692 Offset = Ptr->getOperand(0); 1693 } else { 1694 Base = Ptr->getOperand(0); 1695 Offset = Ptr->getOperand(1); 1696 } 1697 return true; 1698 } 1699 1700 isInc = (Ptr->getOpcode() == ISD::ADD); 1701 Base = Ptr->getOperand(0); 1702 Offset = Ptr->getOperand(1); 1703 return true; 1704 } 1705 1706 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1707 return false; 1708} 1709 1710/// getPreIndexedAddressParts - returns true by value, base pointer and 1711/// offset pointer and addressing mode by reference if the node's address 1712/// can be legally represented as pre-indexed load / store address. 1713bool 1714ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 1715 SDOperand &Offset, 1716 ISD::MemIndexedMode &AM, 1717 SelectionDAG &DAG) { 1718 if (Subtarget->isThumb()) 1719 return false; 1720 1721 MVT::ValueType VT; 1722 SDOperand Ptr; 1723 bool isSEXTLoad = false; 1724 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1725 Ptr = LD->getBasePtr(); 1726 VT = LD->getLoadedVT(); 1727 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1728 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1729 Ptr = ST->getBasePtr(); 1730 VT = ST->getStoredVT(); 1731 } else 1732 return false; 1733 1734 bool isInc; 1735 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, 1736 isInc, DAG); 1737 if (isLegal) { 1738 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1739 return true; 1740 } 1741 return false; 1742} 1743 1744/// getPostIndexedAddressParts - returns true by value, base pointer and 1745/// offset pointer and addressing mode by reference if this node can be 1746/// combined with a load / store to form a post-indexed load / store. 1747bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1748 SDOperand &Base, 1749 SDOperand &Offset, 1750 ISD::MemIndexedMode &AM, 1751 SelectionDAG &DAG) { 1752 if (Subtarget->isThumb()) 1753 return false; 1754 1755 MVT::ValueType VT; 1756 SDOperand Ptr; 1757 bool isSEXTLoad = false; 1758 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1759 VT = LD->getLoadedVT(); 1760 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1761 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1762 VT = ST->getStoredVT(); 1763 } else 1764 return false; 1765 1766 bool isInc; 1767 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1768 isInc, DAG); 1769 if (isLegal) { 1770 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1771 return true; 1772 } 1773 return false; 1774} 1775 1776void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1777 uint64_t Mask, 1778 uint64_t &KnownZero, 1779 uint64_t &KnownOne, 1780 const SelectionDAG &DAG, 1781 unsigned Depth) const { 1782 KnownZero = 0; 1783 KnownOne = 0; 1784 switch (Op.getOpcode()) { 1785 default: break; 1786 case ARMISD::CMOV: { 1787 // Bits are known zero/one if known on the LHS and RHS. 1788 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1789 if (KnownZero == 0 && KnownOne == 0) return; 1790 1791 uint64_t KnownZeroRHS, KnownOneRHS; 1792 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1793 KnownZeroRHS, KnownOneRHS, Depth+1); 1794 KnownZero &= KnownZeroRHS; 1795 KnownOne &= KnownOneRHS; 1796 return; 1797 } 1798 } 1799} 1800 1801//===----------------------------------------------------------------------===// 1802// ARM Inline Assembly Support 1803//===----------------------------------------------------------------------===// 1804 1805/// getConstraintType - Given a constraint letter, return the type of 1806/// constraint it is for this target. 1807ARMTargetLowering::ConstraintType 1808ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1809 if (Constraint.size() == 1) { 1810 switch (Constraint[0]) { 1811 default: break; 1812 case 'l': return C_RegisterClass; 1813 case 'w': return C_RegisterClass; 1814 } 1815 } 1816 return TargetLowering::getConstraintType(Constraint); 1817} 1818 1819std::pair<unsigned, const TargetRegisterClass*> 1820ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1821 MVT::ValueType VT) const { 1822 if (Constraint.size() == 1) { 1823 // GCC RS6000 Constraint Letters 1824 switch (Constraint[0]) { 1825 case 'l': 1826 // FIXME: in thumb mode, 'l' is only low-regs. 1827 // FALL THROUGH. 1828 case 'r': 1829 return std::make_pair(0U, ARM::GPRRegisterClass); 1830 case 'w': 1831 if (VT == MVT::f32) 1832 return std::make_pair(0U, ARM::SPRRegisterClass); 1833 if (VT == MVT::f64) 1834 return std::make_pair(0U, ARM::DPRRegisterClass); 1835 break; 1836 } 1837 } 1838 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1839} 1840 1841std::vector<unsigned> ARMTargetLowering:: 1842getRegClassForInlineAsmConstraint(const std::string &Constraint, 1843 MVT::ValueType VT) const { 1844 if (Constraint.size() != 1) 1845 return std::vector<unsigned>(); 1846 1847 switch (Constraint[0]) { // GCC ARM Constraint Letters 1848 default: break; 1849 case 'l': 1850 case 'r': 1851 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1852 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1853 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1854 ARM::R12, ARM::LR, 0); 1855 case 'w': 1856 if (VT == MVT::f32) 1857 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1858 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1859 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1860 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1861 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1862 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1863 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1864 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1865 if (VT == MVT::f64) 1866 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1867 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1868 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1869 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1870 break; 1871 } 1872 1873 return std::vector<unsigned>(); 1874} 1875