ARMISelLowering.cpp revision c9403659a98bf6487ab6fbf40b81628b5695c02e
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/Function.h" 29#include "llvm/GlobalValue.h" 30#include "llvm/Instruction.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Type.h" 33#include "llvm/CodeGen/CallingConvLower.h" 34#include "llvm/CodeGen/MachineBasicBlock.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineFunction.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineRegisterInfo.h" 39#include "llvm/CodeGen/PseudoSourceValue.h" 40#include "llvm/CodeGen/SelectionDAG.h" 41#include "llvm/MC/MCSectionMachO.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/ADT/VectorExtras.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/Support/CommandLine.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/raw_ostream.h" 49#include <sstream> 50using namespace llvm; 51 52STATISTIC(NumTailCalls, "Number of tail calls"); 53 54// This option should go away when tail calls fully work. 55static cl::opt<bool> 56EnableARMTailCalls("arm-tail-calls", cl::Hidden, 57 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 58 cl::init(true)); 59 60static cl::opt<bool> 61EnableARMLongCalls("arm-long-calls", cl::Hidden, 62 cl::desc("Generate calls via indirect call instructions."), 63 cl::init(false)); 64 65static cl::opt<bool> 66ARMInterworking("arm-interworking", cl::Hidden, 67 cl::desc("Enable / disable ARM interworking (for debugging only)"), 68 cl::init(true)); 69 70static cl::opt<bool> 71EnableARMCodePlacement("arm-code-placement", cl::Hidden, 72 cl::desc("Enable code placement pass for ARM."), 73 cl::init(false)); 74 75static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 76 CCValAssign::LocInfo &LocInfo, 77 ISD::ArgFlagsTy &ArgFlags, 78 CCState &State); 79static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 80 CCValAssign::LocInfo &LocInfo, 81 ISD::ArgFlagsTy &ArgFlags, 82 CCState &State); 83static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 84 CCValAssign::LocInfo &LocInfo, 85 ISD::ArgFlagsTy &ArgFlags, 86 CCState &State); 87static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 88 CCValAssign::LocInfo &LocInfo, 89 ISD::ArgFlagsTy &ArgFlags, 90 CCState &State); 91 92void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 93 EVT PromotedBitwiseVT) { 94 if (VT != PromotedLdStVT) { 95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 97 PromotedLdStVT.getSimpleVT()); 98 99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 } 103 104 EVT ElemTy = VT.getVectorElementType(); 105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); 107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) 108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 109 if (ElemTy != MVT::i32) { 110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 114 } 115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); 119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 121 if (VT.isInteger()) { 122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 125 } 126 127 // Promote all bit-wise operations. 128 if (VT.isInteger() && VT != PromotedBitwiseVT) { 129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 130 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 131 PromotedBitwiseVT.getSimpleVT()); 132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 133 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 134 PromotedBitwiseVT.getSimpleVT()); 135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 137 PromotedBitwiseVT.getSimpleVT()); 138 } 139 140 // Neon does not support vector divide/remainder operations. 141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 147} 148 149void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 150 addRegisterClass(VT, ARM::DPRRegisterClass); 151 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 152} 153 154void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 155 addRegisterClass(VT, ARM::QPRRegisterClass); 156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 157} 158 159static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 161 return new TargetLoweringObjectFileMachO(); 162 163 return new ARMElfTargetObjectFile(); 164} 165 166ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 167 : TargetLowering(TM, createTLOF(TM)) { 168 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 169 170 if (Subtarget->isTargetDarwin()) { 171 // Uses VFP for Thumb libfuncs if available. 172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 173 // Single-precision floating-point arithmetic. 174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 178 179 // Double-precision floating-point arithmetic. 180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 184 185 // Single-precision comparisons. 186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 194 195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 203 204 // Double-precision comparisons. 205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 213 214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 222 223 // Floating-point to integer conversions. 224 // i64 conversions are done via library routines even when generating VFP 225 // instructions, so use the same ones. 226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 230 231 // Conversions between floating types. 232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 234 235 // Integer to floating-point conversions. 236 // i64 conversions are done via library routines even when generating VFP 237 // instructions, so use the same ones. 238 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 239 // e.g., __floatunsidf vs. __floatunssidfvfp. 240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 244 } 245 } 246 247 // These libcalls are not available in 32-bit. 248 setLibcallName(RTLIB::SHL_I128, 0); 249 setLibcallName(RTLIB::SRL_I128, 0); 250 setLibcallName(RTLIB::SRA_I128, 0); 251 252 // Libcalls should use the AAPCS base standard ABI, even if hard float 253 // is in effect, as per the ARM RTABI specification, section 4.1.2. 254 if (Subtarget->isAAPCS_ABI()) { 255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i), 257 CallingConv::ARM_AAPCS); 258 } 259 } 260 261 if (Subtarget->isThumb1Only()) 262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 263 else 264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 268 269 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 270 } 271 272 if (Subtarget->hasNEON()) { 273 addDRTypeForNEON(MVT::v2f32); 274 addDRTypeForNEON(MVT::v8i8); 275 addDRTypeForNEON(MVT::v4i16); 276 addDRTypeForNEON(MVT::v2i32); 277 addDRTypeForNEON(MVT::v1i64); 278 279 addQRTypeForNEON(MVT::v4f32); 280 addQRTypeForNEON(MVT::v2f64); 281 addQRTypeForNEON(MVT::v16i8); 282 addQRTypeForNEON(MVT::v8i16); 283 addQRTypeForNEON(MVT::v4i32); 284 addQRTypeForNEON(MVT::v2i64); 285 286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 287 // neither Neon nor VFP support any arithmetic operations on it. 288 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 292 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand); 295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 296 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 312 313 // Neon does not support some operations on v1i64 and v2i64 types. 314 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 315 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); 317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); 318 319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 320 setTargetDAGCombine(ISD::SHL); 321 setTargetDAGCombine(ISD::SRL); 322 setTargetDAGCombine(ISD::SRA); 323 setTargetDAGCombine(ISD::SIGN_EXTEND); 324 setTargetDAGCombine(ISD::ZERO_EXTEND); 325 setTargetDAGCombine(ISD::ANY_EXTEND); 326 setTargetDAGCombine(ISD::SELECT_CC); 327 } 328 329 computeRegisterProperties(); 330 331 // ARM does not have f32 extending load. 332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 333 334 // ARM does not have i1 sign extending load. 335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 336 337 // ARM supports all 4 flavors of integer indexed load / store. 338 if (!Subtarget->isThumb1Only()) { 339 for (unsigned im = (unsigned)ISD::PRE_INC; 340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 341 setIndexedLoadAction(im, MVT::i1, Legal); 342 setIndexedLoadAction(im, MVT::i8, Legal); 343 setIndexedLoadAction(im, MVT::i16, Legal); 344 setIndexedLoadAction(im, MVT::i32, Legal); 345 setIndexedStoreAction(im, MVT::i1, Legal); 346 setIndexedStoreAction(im, MVT::i8, Legal); 347 setIndexedStoreAction(im, MVT::i16, Legal); 348 setIndexedStoreAction(im, MVT::i32, Legal); 349 } 350 } 351 352 // i64 operation support. 353 if (Subtarget->isThumb1Only()) { 354 setOperationAction(ISD::MUL, MVT::i64, Expand); 355 setOperationAction(ISD::MULHU, MVT::i32, Expand); 356 setOperationAction(ISD::MULHS, MVT::i32, Expand); 357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 359 } else { 360 setOperationAction(ISD::MUL, MVT::i64, Expand); 361 setOperationAction(ISD::MULHU, MVT::i32, Expand); 362 if (!Subtarget->hasV6Ops()) 363 setOperationAction(ISD::MULHS, MVT::i32, Expand); 364 } 365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 368 setOperationAction(ISD::SRL, MVT::i64, Custom); 369 setOperationAction(ISD::SRA, MVT::i64, Custom); 370 371 // ARM does not have ROTL. 372 setOperationAction(ISD::ROTL, MVT::i32, Expand); 373 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 374 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 376 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 377 378 // Only ARMv6 has BSWAP. 379 if (!Subtarget->hasV6Ops()) 380 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 381 382 // These are expanded into libcalls. 383 if (!Subtarget->hasDivide()) { 384 // v7M has a hardware divider 385 setOperationAction(ISD::SDIV, MVT::i32, Expand); 386 setOperationAction(ISD::UDIV, MVT::i32, Expand); 387 } 388 setOperationAction(ISD::SREM, MVT::i32, Expand); 389 setOperationAction(ISD::UREM, MVT::i32, Expand); 390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 392 393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 398 399 setOperationAction(ISD::TRAP, MVT::Other, Legal); 400 401 // Use the default implementation. 402 setOperationAction(ISD::VASTART, MVT::Other, Custom); 403 setOperationAction(ISD::VAARG, MVT::Other, Expand); 404 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 405 setOperationAction(ISD::VAEND, MVT::Other, Expand); 406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 409 // FIXME: Shouldn't need this, since no register is used, but the legalizer 410 // doesn't yet know how to not do that for SjLj. 411 setExceptionSelectorRegister(ARM::R0); 412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise 414 // use the default expansion. 415 bool canHandleAtomics = 416 (Subtarget->hasV7Ops() || 417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())); 418 if (canHandleAtomics) { 419 // membarrier needs custom lowering; the rest are legal and handled 420 // normally. 421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 422 } else { 423 // Set them all for expansion, which will force libcalls. 424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand); 426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand); 427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand); 429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand); 430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand); 432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand); 433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand); 435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand); 436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand); 438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand); 439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand); 441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand); 442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand); 444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand); 445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand); 447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand); 448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 449 // Since the libcalls include locking, fold in the fences 450 setShouldFoldAtomicFences(true); 451 } 452 // 64-bit versions are always libcalls (for now) 453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand); 454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand); 455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand); 456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand); 457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand); 458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand); 459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); 460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); 461 462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 463 if (!Subtarget->hasV6Ops()) { 464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 466 } 467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 468 469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) 470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 471 // iff target supports vfp2. 472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 473 474 // We want to custom lower some of our intrinsics. 475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 476 if (Subtarget->isTargetDarwin()) { 477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 479 } 480 481 setOperationAction(ISD::SETCC, MVT::i32, Expand); 482 setOperationAction(ISD::SETCC, MVT::f32, Expand); 483 setOperationAction(ISD::SETCC, MVT::f64, Expand); 484 setOperationAction(ISD::SELECT, MVT::i32, Expand); 485 setOperationAction(ISD::SELECT, MVT::f32, Expand); 486 setOperationAction(ISD::SELECT, MVT::f64, Expand); 487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 490 491 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 492 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 493 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 494 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 495 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 496 497 // We don't support sin/cos/fmod/copysign/pow 498 setOperationAction(ISD::FSIN, MVT::f64, Expand); 499 setOperationAction(ISD::FSIN, MVT::f32, Expand); 500 setOperationAction(ISD::FCOS, MVT::f32, Expand); 501 setOperationAction(ISD::FCOS, MVT::f64, Expand); 502 setOperationAction(ISD::FREM, MVT::f64, Expand); 503 setOperationAction(ISD::FREM, MVT::f32, Expand); 504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 507 } 508 setOperationAction(ISD::FPOW, MVT::f64, Expand); 509 setOperationAction(ISD::FPOW, MVT::f32, Expand); 510 511 // Various VFP goodness 512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 513 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 514 if (Subtarget->hasVFP2()) { 515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 519 } 520 // Special handling for half-precision FP. 521 if (!Subtarget->hasFP16()) { 522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 524 } 525 } 526 527 // We have target-specific dag combine patterns for the following nodes: 528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 529 setTargetDAGCombine(ISD::ADD); 530 setTargetDAGCombine(ISD::SUB); 531 setTargetDAGCombine(ISD::MUL); 532 533 setStackPointerRegisterToSaveRestore(ARM::SP); 534 535 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 536 setSchedulingPreference(Sched::RegPressure); 537 else 538 setSchedulingPreference(Sched::Hybrid); 539 540 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 541 542 if (EnableARMCodePlacement) 543 benefitFromCodePlacementOpt = true; 544} 545 546const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 547 switch (Opcode) { 548 default: return 0; 549 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 550 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 551 case ARMISD::CALL: return "ARMISD::CALL"; 552 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 553 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 554 case ARMISD::tCALL: return "ARMISD::tCALL"; 555 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 556 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 557 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 558 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 559 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 560 case ARMISD::CMP: return "ARMISD::CMP"; 561 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 562 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 563 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 564 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 565 case ARMISD::CMOV: return "ARMISD::CMOV"; 566 case ARMISD::CNEG: return "ARMISD::CNEG"; 567 568 case ARMISD::RBIT: return "ARMISD::RBIT"; 569 570 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 571 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 572 case ARMISD::SITOF: return "ARMISD::SITOF"; 573 case ARMISD::UITOF: return "ARMISD::UITOF"; 574 575 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 576 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 577 case ARMISD::RRX: return "ARMISD::RRX"; 578 579 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 580 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 581 582 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 583 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 584 585 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 586 587 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 588 589 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 590 591 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 592 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER"; 593 594 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 595 case ARMISD::VCGE: return "ARMISD::VCGE"; 596 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 597 case ARMISD::VCGT: return "ARMISD::VCGT"; 598 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 599 case ARMISD::VTST: return "ARMISD::VTST"; 600 601 case ARMISD::VSHL: return "ARMISD::VSHL"; 602 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 603 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 604 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 605 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 606 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 607 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 608 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 609 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 610 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 611 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 612 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 613 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 614 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 615 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 616 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 617 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 618 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 619 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 620 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 621 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 622 case ARMISD::VDUP: return "ARMISD::VDUP"; 623 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 624 case ARMISD::VEXT: return "ARMISD::VEXT"; 625 case ARMISD::VREV64: return "ARMISD::VREV64"; 626 case ARMISD::VREV32: return "ARMISD::VREV32"; 627 case ARMISD::VREV16: return "ARMISD::VREV16"; 628 case ARMISD::VZIP: return "ARMISD::VZIP"; 629 case ARMISD::VUZP: return "ARMISD::VUZP"; 630 case ARMISD::VTRN: return "ARMISD::VTRN"; 631 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 632 case ARMISD::FMAX: return "ARMISD::FMAX"; 633 case ARMISD::FMIN: return "ARMISD::FMIN"; 634 } 635} 636 637/// getRegClassFor - Return the register class that should be used for the 638/// specified value type. 639TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 640 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 641 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 642 // load / store 4 to 8 consecutive D registers. 643 if (Subtarget->hasNEON()) { 644 if (VT == MVT::v4i64) 645 return ARM::QQPRRegisterClass; 646 else if (VT == MVT::v8i64) 647 return ARM::QQQQPRRegisterClass; 648 } 649 return TargetLowering::getRegClassFor(VT); 650} 651 652/// getFunctionAlignment - Return the Log2 alignment of this function. 653unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { 654 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2; 655} 656 657Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 658 unsigned NumVals = N->getNumValues(); 659 if (!NumVals) 660 return Sched::RegPressure; 661 662 for (unsigned i = 0; i != NumVals; ++i) { 663 EVT VT = N->getValueType(i); 664 if (VT.isFloatingPoint() || VT.isVector()) 665 return Sched::Latency; 666 } 667 668 if (!N->isMachineOpcode()) 669 return Sched::RegPressure; 670 671 // Load are scheduled for latency even if there instruction itinerary 672 // is not available. 673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 674 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 675 if (TID.mayLoad()) 676 return Sched::Latency; 677 678 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData(); 679 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2) 680 return Sched::Latency; 681 return Sched::RegPressure; 682} 683 684//===----------------------------------------------------------------------===// 685// Lowering Code 686//===----------------------------------------------------------------------===// 687 688/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 689static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 690 switch (CC) { 691 default: llvm_unreachable("Unknown condition code!"); 692 case ISD::SETNE: return ARMCC::NE; 693 case ISD::SETEQ: return ARMCC::EQ; 694 case ISD::SETGT: return ARMCC::GT; 695 case ISD::SETGE: return ARMCC::GE; 696 case ISD::SETLT: return ARMCC::LT; 697 case ISD::SETLE: return ARMCC::LE; 698 case ISD::SETUGT: return ARMCC::HI; 699 case ISD::SETUGE: return ARMCC::HS; 700 case ISD::SETULT: return ARMCC::LO; 701 case ISD::SETULE: return ARMCC::LS; 702 } 703} 704 705/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 706static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 707 ARMCC::CondCodes &CondCode2) { 708 CondCode2 = ARMCC::AL; 709 switch (CC) { 710 default: llvm_unreachable("Unknown FP condition!"); 711 case ISD::SETEQ: 712 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 713 case ISD::SETGT: 714 case ISD::SETOGT: CondCode = ARMCC::GT; break; 715 case ISD::SETGE: 716 case ISD::SETOGE: CondCode = ARMCC::GE; break; 717 case ISD::SETOLT: CondCode = ARMCC::MI; break; 718 case ISD::SETOLE: CondCode = ARMCC::LS; break; 719 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 720 case ISD::SETO: CondCode = ARMCC::VC; break; 721 case ISD::SETUO: CondCode = ARMCC::VS; break; 722 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 723 case ISD::SETUGT: CondCode = ARMCC::HI; break; 724 case ISD::SETUGE: CondCode = ARMCC::PL; break; 725 case ISD::SETLT: 726 case ISD::SETULT: CondCode = ARMCC::LT; break; 727 case ISD::SETLE: 728 case ISD::SETULE: CondCode = ARMCC::LE; break; 729 case ISD::SETNE: 730 case ISD::SETUNE: CondCode = ARMCC::NE; break; 731 } 732} 733 734//===----------------------------------------------------------------------===// 735// Calling Convention Implementation 736//===----------------------------------------------------------------------===// 737 738#include "ARMGenCallingConv.inc" 739 740// APCS f64 is in register pairs, possibly split to stack 741static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 742 CCValAssign::LocInfo &LocInfo, 743 CCState &State, bool CanFail) { 744 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 745 746 // Try to get the first register. 747 if (unsigned Reg = State.AllocateReg(RegList, 4)) 748 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 749 else { 750 // For the 2nd half of a v2f64, do not fail. 751 if (CanFail) 752 return false; 753 754 // Put the whole thing on the stack. 755 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 756 State.AllocateStack(8, 4), 757 LocVT, LocInfo)); 758 return true; 759 } 760 761 // Try to get the second register. 762 if (unsigned Reg = State.AllocateReg(RegList, 4)) 763 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 764 else 765 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 766 State.AllocateStack(4, 4), 767 LocVT, LocInfo)); 768 return true; 769} 770 771static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 772 CCValAssign::LocInfo &LocInfo, 773 ISD::ArgFlagsTy &ArgFlags, 774 CCState &State) { 775 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 776 return false; 777 if (LocVT == MVT::v2f64 && 778 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 779 return false; 780 return true; // we handled it 781} 782 783// AAPCS f64 is in aligned register pairs 784static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 785 CCValAssign::LocInfo &LocInfo, 786 CCState &State, bool CanFail) { 787 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 788 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 789 790 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 791 if (Reg == 0) { 792 // For the 2nd half of a v2f64, do not just fail. 793 if (CanFail) 794 return false; 795 796 // Put the whole thing on the stack. 797 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 798 State.AllocateStack(8, 8), 799 LocVT, LocInfo)); 800 return true; 801 } 802 803 unsigned i; 804 for (i = 0; i < 2; ++i) 805 if (HiRegList[i] == Reg) 806 break; 807 808 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 809 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 810 LocVT, LocInfo)); 811 return true; 812} 813 814static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 815 CCValAssign::LocInfo &LocInfo, 816 ISD::ArgFlagsTy &ArgFlags, 817 CCState &State) { 818 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 819 return false; 820 if (LocVT == MVT::v2f64 && 821 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 822 return false; 823 return true; // we handled it 824} 825 826static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 827 CCValAssign::LocInfo &LocInfo, CCState &State) { 828 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 829 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 830 831 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 832 if (Reg == 0) 833 return false; // we didn't handle it 834 835 unsigned i; 836 for (i = 0; i < 2; ++i) 837 if (HiRegList[i] == Reg) 838 break; 839 840 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 841 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 842 LocVT, LocInfo)); 843 return true; 844} 845 846static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 847 CCValAssign::LocInfo &LocInfo, 848 ISD::ArgFlagsTy &ArgFlags, 849 CCState &State) { 850 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 851 return false; 852 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 853 return false; 854 return true; // we handled it 855} 856 857static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 858 CCValAssign::LocInfo &LocInfo, 859 ISD::ArgFlagsTy &ArgFlags, 860 CCState &State) { 861 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, 862 State); 863} 864 865/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 866/// given CallingConvention value. 867CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 868 bool Return, 869 bool isVarArg) const { 870 switch (CC) { 871 default: 872 llvm_unreachable("Unsupported calling convention"); 873 case CallingConv::C: 874 case CallingConv::Fast: 875 // Use target triple & subtarget features to do actual dispatch. 876 if (Subtarget->isAAPCS_ABI()) { 877 if (Subtarget->hasVFP2() && 878 FloatABIType == FloatABI::Hard && !isVarArg) 879 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 880 else 881 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 882 } else 883 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 884 case CallingConv::ARM_AAPCS_VFP: 885 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 886 case CallingConv::ARM_AAPCS: 887 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 888 case CallingConv::ARM_APCS: 889 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 890 } 891} 892 893/// LowerCallResult - Lower the result values of a call into the 894/// appropriate copies out of appropriate physical registers. 895SDValue 896ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 897 CallingConv::ID CallConv, bool isVarArg, 898 const SmallVectorImpl<ISD::InputArg> &Ins, 899 DebugLoc dl, SelectionDAG &DAG, 900 SmallVectorImpl<SDValue> &InVals) const { 901 902 // Assign locations to each value returned by this call. 903 SmallVector<CCValAssign, 16> RVLocs; 904 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 905 RVLocs, *DAG.getContext()); 906 CCInfo.AnalyzeCallResult(Ins, 907 CCAssignFnForNode(CallConv, /* Return*/ true, 908 isVarArg)); 909 910 // Copy all of the result registers out of their specified physreg. 911 for (unsigned i = 0; i != RVLocs.size(); ++i) { 912 CCValAssign VA = RVLocs[i]; 913 914 SDValue Val; 915 if (VA.needsCustom()) { 916 // Handle f64 or half of a v2f64. 917 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 918 InFlag); 919 Chain = Lo.getValue(1); 920 InFlag = Lo.getValue(2); 921 VA = RVLocs[++i]; // skip ahead to next loc 922 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 923 InFlag); 924 Chain = Hi.getValue(1); 925 InFlag = Hi.getValue(2); 926 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 927 928 if (VA.getLocVT() == MVT::v2f64) { 929 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 930 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 931 DAG.getConstant(0, MVT::i32)); 932 933 VA = RVLocs[++i]; // skip ahead to next loc 934 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 935 Chain = Lo.getValue(1); 936 InFlag = Lo.getValue(2); 937 VA = RVLocs[++i]; // skip ahead to next loc 938 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 939 Chain = Hi.getValue(1); 940 InFlag = Hi.getValue(2); 941 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 942 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 943 DAG.getConstant(1, MVT::i32)); 944 } 945 } else { 946 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 947 InFlag); 948 Chain = Val.getValue(1); 949 InFlag = Val.getValue(2); 950 } 951 952 switch (VA.getLocInfo()) { 953 default: llvm_unreachable("Unknown loc info!"); 954 case CCValAssign::Full: break; 955 case CCValAssign::BCvt: 956 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); 957 break; 958 } 959 960 InVals.push_back(Val); 961 } 962 963 return Chain; 964} 965 966/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 967/// by "Src" to address "Dst" of size "Size". Alignment information is 968/// specified by the specific parameter attribute. The copy will be passed as 969/// a byval function parameter. 970/// Sometimes what we are copying is the end of a larger object, the part that 971/// does not fit in registers. 972static SDValue 973CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 974 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 975 DebugLoc dl) { 976 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 977 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 978 /*isVolatile=*/false, /*AlwaysInline=*/false, 979 NULL, 0, NULL, 0); 980} 981 982/// LowerMemOpCallTo - Store the argument to the stack. 983SDValue 984ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 985 SDValue StackPtr, SDValue Arg, 986 DebugLoc dl, SelectionDAG &DAG, 987 const CCValAssign &VA, 988 ISD::ArgFlagsTy Flags) const { 989 unsigned LocMemOffset = VA.getLocMemOffset(); 990 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 991 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 992 if (Flags.isByVal()) { 993 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 994 } 995 return DAG.getStore(Chain, dl, Arg, PtrOff, 996 PseudoSourceValue::getStack(), LocMemOffset, 997 false, false, 0); 998} 999 1000void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1001 SDValue Chain, SDValue &Arg, 1002 RegsToPassVector &RegsToPass, 1003 CCValAssign &VA, CCValAssign &NextVA, 1004 SDValue &StackPtr, 1005 SmallVector<SDValue, 8> &MemOpChains, 1006 ISD::ArgFlagsTy Flags) const { 1007 1008 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1009 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1010 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1011 1012 if (NextVA.isRegLoc()) 1013 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1014 else { 1015 assert(NextVA.isMemLoc()); 1016 if (StackPtr.getNode() == 0) 1017 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1018 1019 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1020 dl, DAG, NextVA, 1021 Flags)); 1022 } 1023} 1024 1025/// LowerCall - Lowering a call into a callseq_start <- 1026/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1027/// nodes. 1028SDValue 1029ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1030 CallingConv::ID CallConv, bool isVarArg, 1031 bool &isTailCall, 1032 const SmallVectorImpl<ISD::OutputArg> &Outs, 1033 const SmallVectorImpl<SDValue> &OutVals, 1034 const SmallVectorImpl<ISD::InputArg> &Ins, 1035 DebugLoc dl, SelectionDAG &DAG, 1036 SmallVectorImpl<SDValue> &InVals) const { 1037 MachineFunction &MF = DAG.getMachineFunction(); 1038 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1039 bool IsSibCall = false; 1040 // Temporarily disable tail calls so things don't break. 1041 if (!EnableARMTailCalls) 1042 isTailCall = false; 1043 if (isTailCall) { 1044 // Check if it's really possible to do a tail call. 1045 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1046 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1047 Outs, OutVals, Ins, DAG); 1048 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1049 // detected sibcalls. 1050 if (isTailCall) { 1051 ++NumTailCalls; 1052 IsSibCall = true; 1053 } 1054 } 1055 1056 // Analyze operands of the call, assigning locations to each operand. 1057 SmallVector<CCValAssign, 16> ArgLocs; 1058 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1059 *DAG.getContext()); 1060 CCInfo.AnalyzeCallOperands(Outs, 1061 CCAssignFnForNode(CallConv, /* Return*/ false, 1062 isVarArg)); 1063 1064 // Get a count of how many bytes are to be pushed on the stack. 1065 unsigned NumBytes = CCInfo.getNextStackOffset(); 1066 1067 // For tail calls, memory operands are available in our caller's stack. 1068 if (IsSibCall) 1069 NumBytes = 0; 1070 1071 // Adjust the stack pointer for the new arguments... 1072 // These operations are automatically eliminated by the prolog/epilog pass 1073 if (!IsSibCall) 1074 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1075 1076 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1077 1078 RegsToPassVector RegsToPass; 1079 SmallVector<SDValue, 8> MemOpChains; 1080 1081 // Walk the register/memloc assignments, inserting copies/loads. In the case 1082 // of tail call optimization, arguments are handled later. 1083 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1084 i != e; 1085 ++i, ++realArgIdx) { 1086 CCValAssign &VA = ArgLocs[i]; 1087 SDValue Arg = OutVals[realArgIdx]; 1088 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1089 1090 // Promote the value if needed. 1091 switch (VA.getLocInfo()) { 1092 default: llvm_unreachable("Unknown loc info!"); 1093 case CCValAssign::Full: break; 1094 case CCValAssign::SExt: 1095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1096 break; 1097 case CCValAssign::ZExt: 1098 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1099 break; 1100 case CCValAssign::AExt: 1101 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1102 break; 1103 case CCValAssign::BCvt: 1104 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1105 break; 1106 } 1107 1108 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1109 if (VA.needsCustom()) { 1110 if (VA.getLocVT() == MVT::v2f64) { 1111 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1112 DAG.getConstant(0, MVT::i32)); 1113 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1114 DAG.getConstant(1, MVT::i32)); 1115 1116 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1117 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1118 1119 VA = ArgLocs[++i]; // skip ahead to next loc 1120 if (VA.isRegLoc()) { 1121 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1122 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1123 } else { 1124 assert(VA.isMemLoc()); 1125 1126 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1127 dl, DAG, VA, Flags)); 1128 } 1129 } else { 1130 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1131 StackPtr, MemOpChains, Flags); 1132 } 1133 } else if (VA.isRegLoc()) { 1134 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1135 } else if (!IsSibCall) { 1136 assert(VA.isMemLoc()); 1137 1138 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1139 dl, DAG, VA, Flags)); 1140 } 1141 } 1142 1143 if (!MemOpChains.empty()) 1144 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1145 &MemOpChains[0], MemOpChains.size()); 1146 1147 // Build a sequence of copy-to-reg nodes chained together with token chain 1148 // and flag operands which copy the outgoing args into the appropriate regs. 1149 SDValue InFlag; 1150 // Tail call byval lowering might overwrite argument registers so in case of 1151 // tail call optimization the copies to registers are lowered later. 1152 if (!isTailCall) 1153 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1154 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1155 RegsToPass[i].second, InFlag); 1156 InFlag = Chain.getValue(1); 1157 } 1158 1159 // For tail calls lower the arguments to the 'real' stack slot. 1160 if (isTailCall) { 1161 // Force all the incoming stack arguments to be loaded from the stack 1162 // before any new outgoing arguments are stored to the stack, because the 1163 // outgoing stack slots may alias the incoming argument stack slots, and 1164 // the alias isn't otherwise explicit. This is slightly more conservative 1165 // than necessary, because it means that each store effectively depends 1166 // on every argument instead of just those arguments it would clobber. 1167 1168 // Do not flag preceeding copytoreg stuff together with the following stuff. 1169 InFlag = SDValue(); 1170 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1171 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1172 RegsToPass[i].second, InFlag); 1173 InFlag = Chain.getValue(1); 1174 } 1175 InFlag =SDValue(); 1176 } 1177 1178 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1179 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1180 // node so that legalize doesn't hack it. 1181 bool isDirect = false; 1182 bool isARMFunc = false; 1183 bool isLocalARMFunc = false; 1184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1185 1186 if (EnableARMLongCalls) { 1187 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1188 && "long-calls with non-static relocation model!"); 1189 // Handle a global address or an external symbol. If it's not one of 1190 // those, the target's already in a register, so we don't need to do 1191 // anything extra. 1192 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1193 const GlobalValue *GV = G->getGlobal(); 1194 // Create a constant pool entry for the callee address 1195 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1196 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1197 ARMPCLabelIndex, 1198 ARMCP::CPValue, 0); 1199 // Get the address of the callee into a register 1200 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1201 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1202 Callee = DAG.getLoad(getPointerTy(), dl, 1203 DAG.getEntryNode(), CPAddr, 1204 PseudoSourceValue::getConstantPool(), 0, 1205 false, false, 0); 1206 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1207 const char *Sym = S->getSymbol(); 1208 1209 // Create a constant pool entry for the callee address 1210 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1211 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1212 Sym, ARMPCLabelIndex, 0); 1213 // Get the address of the callee into a register 1214 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1215 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1216 Callee = DAG.getLoad(getPointerTy(), dl, 1217 DAG.getEntryNode(), CPAddr, 1218 PseudoSourceValue::getConstantPool(), 0, 1219 false, false, 0); 1220 } 1221 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1222 const GlobalValue *GV = G->getGlobal(); 1223 isDirect = true; 1224 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1225 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1226 getTargetMachine().getRelocationModel() != Reloc::Static; 1227 isARMFunc = !Subtarget->isThumb() || isStub; 1228 // ARM call to a local ARM function is predicable. 1229 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1230 // tBX takes a register source operand. 1231 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1232 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1233 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1234 ARMPCLabelIndex, 1235 ARMCP::CPValue, 4); 1236 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1237 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1238 Callee = DAG.getLoad(getPointerTy(), dl, 1239 DAG.getEntryNode(), CPAddr, 1240 PseudoSourceValue::getConstantPool(), 0, 1241 false, false, 0); 1242 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1243 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1244 getPointerTy(), Callee, PICLabel); 1245 } else 1246 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 1247 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1248 isDirect = true; 1249 bool isStub = Subtarget->isTargetDarwin() && 1250 getTargetMachine().getRelocationModel() != Reloc::Static; 1251 isARMFunc = !Subtarget->isThumb() || isStub; 1252 // tBX takes a register source operand. 1253 const char *Sym = S->getSymbol(); 1254 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1255 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1256 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1257 Sym, ARMPCLabelIndex, 4); 1258 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1259 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1260 Callee = DAG.getLoad(getPointerTy(), dl, 1261 DAG.getEntryNode(), CPAddr, 1262 PseudoSourceValue::getConstantPool(), 0, 1263 false, false, 0); 1264 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1265 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1266 getPointerTy(), Callee, PICLabel); 1267 } else 1268 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 1269 } 1270 1271 // FIXME: handle tail calls differently. 1272 unsigned CallOpc; 1273 if (Subtarget->isThumb()) { 1274 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1275 CallOpc = ARMISD::CALL_NOLINK; 1276 else 1277 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1278 } else { 1279 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1280 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1281 : ARMISD::CALL_NOLINK; 1282 } 1283 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) { 1284 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 1285 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); 1286 InFlag = Chain.getValue(1); 1287 } 1288 1289 std::vector<SDValue> Ops; 1290 Ops.push_back(Chain); 1291 Ops.push_back(Callee); 1292 1293 // Add argument registers to the end of the list so that they are known live 1294 // into the call. 1295 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1296 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1297 RegsToPass[i].second.getValueType())); 1298 1299 if (InFlag.getNode()) 1300 Ops.push_back(InFlag); 1301 1302 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1303 if (isTailCall) 1304 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1305 1306 // Returns a chain and a flag for retval copy to use. 1307 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1308 InFlag = Chain.getValue(1); 1309 1310 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1311 DAG.getIntPtrConstant(0, true), InFlag); 1312 if (!Ins.empty()) 1313 InFlag = Chain.getValue(1); 1314 1315 // Handle result values, copying them out of physregs into vregs that we 1316 // return. 1317 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1318 dl, DAG, InVals); 1319} 1320 1321/// MatchingStackOffset - Return true if the given stack call argument is 1322/// already available in the same position (relatively) of the caller's 1323/// incoming argument stack. 1324static 1325bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1326 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1327 const ARMInstrInfo *TII) { 1328 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1329 int FI = INT_MAX; 1330 if (Arg.getOpcode() == ISD::CopyFromReg) { 1331 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1332 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 1333 return false; 1334 MachineInstr *Def = MRI->getVRegDef(VR); 1335 if (!Def) 1336 return false; 1337 if (!Flags.isByVal()) { 1338 if (!TII->isLoadFromStackSlot(Def, FI)) 1339 return false; 1340 } else { 1341// unsigned Opcode = Def->getOpcode(); 1342// if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 1343// Def->getOperand(1).isFI()) { 1344// FI = Def->getOperand(1).getIndex(); 1345// Bytes = Flags.getByValSize(); 1346// } else 1347 return false; 1348 } 1349 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1350 if (Flags.isByVal()) 1351 // ByVal argument is passed in as a pointer but it's now being 1352 // dereferenced. e.g. 1353 // define @foo(%struct.X* %A) { 1354 // tail call @bar(%struct.X* byval %A) 1355 // } 1356 return false; 1357 SDValue Ptr = Ld->getBasePtr(); 1358 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1359 if (!FINode) 1360 return false; 1361 FI = FINode->getIndex(); 1362 } else 1363 return false; 1364 1365 assert(FI != INT_MAX); 1366 if (!MFI->isFixedObjectIndex(FI)) 1367 return false; 1368 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1369} 1370 1371/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1372/// for tail call optimization. Targets which want to do tail call 1373/// optimization should implement this function. 1374bool 1375ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1376 CallingConv::ID CalleeCC, 1377 bool isVarArg, 1378 bool isCalleeStructRet, 1379 bool isCallerStructRet, 1380 const SmallVectorImpl<ISD::OutputArg> &Outs, 1381 const SmallVectorImpl<SDValue> &OutVals, 1382 const SmallVectorImpl<ISD::InputArg> &Ins, 1383 SelectionDAG& DAG) const { 1384 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1385 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1386 bool CCMatch = CallerCC == CalleeCC; 1387 1388 // Look for obvious safe cases to perform tail call optimization that do not 1389 // require ABI changes. This is what gcc calls sibcall. 1390 1391 // Do not sibcall optimize vararg calls unless the call site is not passing 1392 // any arguments. 1393 if (isVarArg && !Outs.empty()) 1394 return false; 1395 1396 // Also avoid sibcall optimization if either caller or callee uses struct 1397 // return semantics. 1398 if (isCalleeStructRet || isCallerStructRet) 1399 return false; 1400 1401 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1402 // emitEpilogue is not ready for them. 1403 if (Subtarget->isThumb1Only()) 1404 return false; 1405 1406 // For the moment, we can only do this to functions defined in this 1407 // compilation, or to indirect calls. A Thumb B to an ARM function, 1408 // or vice versa, is not easily fixed up in the linker unlike BL. 1409 // (We could do this by loading the address of the callee into a register; 1410 // that is an extra instruction over the direct call and burns a register 1411 // as well, so is not likely to be a win.) 1412 if (isa<ExternalSymbolSDNode>(Callee)) 1413 return false; 1414 1415 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1416 const GlobalValue *GV = G->getGlobal(); 1417 if (GV->isDeclaration() || GV->isWeakForLinker()) 1418 return false; 1419 } 1420 1421 // If the calling conventions do not match, then we'd better make sure the 1422 // results are returned in the same way as what the caller expects. 1423 if (!CCMatch) { 1424 SmallVector<CCValAssign, 16> RVLocs1; 1425 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 1426 RVLocs1, *DAG.getContext()); 1427 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1428 1429 SmallVector<CCValAssign, 16> RVLocs2; 1430 CCState CCInfo2(CallerCC, false, getTargetMachine(), 1431 RVLocs2, *DAG.getContext()); 1432 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1433 1434 if (RVLocs1.size() != RVLocs2.size()) 1435 return false; 1436 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1437 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1438 return false; 1439 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1440 return false; 1441 if (RVLocs1[i].isRegLoc()) { 1442 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1443 return false; 1444 } else { 1445 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1446 return false; 1447 } 1448 } 1449 } 1450 1451 // If the callee takes no arguments then go on to check the results of the 1452 // call. 1453 if (!Outs.empty()) { 1454 // Check if stack adjustment is needed. For now, do not do this if any 1455 // argument is passed on the stack. 1456 SmallVector<CCValAssign, 16> ArgLocs; 1457 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 1458 ArgLocs, *DAG.getContext()); 1459 CCInfo.AnalyzeCallOperands(Outs, 1460 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1461 if (CCInfo.getNextStackOffset()) { 1462 MachineFunction &MF = DAG.getMachineFunction(); 1463 1464 // Check if the arguments are already laid out in the right way as 1465 // the caller's fixed stack objects. 1466 MachineFrameInfo *MFI = MF.getFrameInfo(); 1467 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1468 const ARMInstrInfo *TII = 1469 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1470 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1471 i != e; 1472 ++i, ++realArgIdx) { 1473 CCValAssign &VA = ArgLocs[i]; 1474 EVT RegVT = VA.getLocVT(); 1475 SDValue Arg = OutVals[realArgIdx]; 1476 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1477 if (VA.getLocInfo() == CCValAssign::Indirect) 1478 return false; 1479 if (VA.needsCustom()) { 1480 // f64 and vector types are split into multiple registers or 1481 // register/stack-slot combinations. The types will not match 1482 // the registers; give up on memory f64 refs until we figure 1483 // out what to do about this. 1484 if (!VA.isRegLoc()) 1485 return false; 1486 if (!ArgLocs[++i].isRegLoc()) 1487 return false; 1488 if (RegVT == MVT::v2f64) { 1489 if (!ArgLocs[++i].isRegLoc()) 1490 return false; 1491 if (!ArgLocs[++i].isRegLoc()) 1492 return false; 1493 } 1494 } else if (!VA.isRegLoc()) { 1495 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1496 MFI, MRI, TII)) 1497 return false; 1498 } 1499 } 1500 } 1501 } 1502 1503 return true; 1504} 1505 1506SDValue 1507ARMTargetLowering::LowerReturn(SDValue Chain, 1508 CallingConv::ID CallConv, bool isVarArg, 1509 const SmallVectorImpl<ISD::OutputArg> &Outs, 1510 const SmallVectorImpl<SDValue> &OutVals, 1511 DebugLoc dl, SelectionDAG &DAG) const { 1512 1513 // CCValAssign - represent the assignment of the return value to a location. 1514 SmallVector<CCValAssign, 16> RVLocs; 1515 1516 // CCState - Info about the registers and stack slots. 1517 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 1518 *DAG.getContext()); 1519 1520 // Analyze outgoing return values. 1521 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1522 isVarArg)); 1523 1524 // If this is the first return lowered for this function, add 1525 // the regs to the liveout set for the function. 1526 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1527 for (unsigned i = 0; i != RVLocs.size(); ++i) 1528 if (RVLocs[i].isRegLoc()) 1529 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1530 } 1531 1532 SDValue Flag; 1533 1534 // Copy the result values into the output registers. 1535 for (unsigned i = 0, realRVLocIdx = 0; 1536 i != RVLocs.size(); 1537 ++i, ++realRVLocIdx) { 1538 CCValAssign &VA = RVLocs[i]; 1539 assert(VA.isRegLoc() && "Can only return in registers!"); 1540 1541 SDValue Arg = OutVals[realRVLocIdx]; 1542 1543 switch (VA.getLocInfo()) { 1544 default: llvm_unreachable("Unknown loc info!"); 1545 case CCValAssign::Full: break; 1546 case CCValAssign::BCvt: 1547 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1548 break; 1549 } 1550 1551 if (VA.needsCustom()) { 1552 if (VA.getLocVT() == MVT::v2f64) { 1553 // Extract the first half and return it in two registers. 1554 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1555 DAG.getConstant(0, MVT::i32)); 1556 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1557 DAG.getVTList(MVT::i32, MVT::i32), Half); 1558 1559 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1560 Flag = Chain.getValue(1); 1561 VA = RVLocs[++i]; // skip ahead to next loc 1562 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1563 HalfGPRs.getValue(1), Flag); 1564 Flag = Chain.getValue(1); 1565 VA = RVLocs[++i]; // skip ahead to next loc 1566 1567 // Extract the 2nd half and fall through to handle it as an f64 value. 1568 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1569 DAG.getConstant(1, MVT::i32)); 1570 } 1571 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1572 // available. 1573 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1574 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1575 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1576 Flag = Chain.getValue(1); 1577 VA = RVLocs[++i]; // skip ahead to next loc 1578 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1579 Flag); 1580 } else 1581 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1582 1583 // Guarantee that all emitted copies are 1584 // stuck together, avoiding something bad. 1585 Flag = Chain.getValue(1); 1586 } 1587 1588 SDValue result; 1589 if (Flag.getNode()) 1590 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1591 else // Return Void 1592 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1593 1594 return result; 1595} 1596 1597// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1598// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1599// one of the above mentioned nodes. It has to be wrapped because otherwise 1600// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1601// be used to form addressing mode. These wrapped nodes will be selected 1602// into MOVi. 1603static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1604 EVT PtrVT = Op.getValueType(); 1605 // FIXME there is no actual debug info here 1606 DebugLoc dl = Op.getDebugLoc(); 1607 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1608 SDValue Res; 1609 if (CP->isMachineConstantPoolEntry()) 1610 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1611 CP->getAlignment()); 1612 else 1613 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1614 CP->getAlignment()); 1615 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1616} 1617 1618SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1619 SelectionDAG &DAG) const { 1620 MachineFunction &MF = DAG.getMachineFunction(); 1621 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1622 unsigned ARMPCLabelIndex = 0; 1623 DebugLoc DL = Op.getDebugLoc(); 1624 EVT PtrVT = getPointerTy(); 1625 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1626 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1627 SDValue CPAddr; 1628 if (RelocM == Reloc::Static) { 1629 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1630 } else { 1631 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1632 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1633 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex, 1634 ARMCP::CPBlockAddress, 1635 PCAdj); 1636 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1637 } 1638 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1639 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1640 PseudoSourceValue::getConstantPool(), 0, 1641 false, false, 0); 1642 if (RelocM == Reloc::Static) 1643 return Result; 1644 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1645 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1646} 1647 1648// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1649SDValue 1650ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1651 SelectionDAG &DAG) const { 1652 DebugLoc dl = GA->getDebugLoc(); 1653 EVT PtrVT = getPointerTy(); 1654 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1655 MachineFunction &MF = DAG.getMachineFunction(); 1656 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1657 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1658 ARMConstantPoolValue *CPV = 1659 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1660 ARMCP::CPValue, PCAdj, "tlsgd", true); 1661 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1662 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1663 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1664 PseudoSourceValue::getConstantPool(), 0, 1665 false, false, 0); 1666 SDValue Chain = Argument.getValue(1); 1667 1668 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1669 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1670 1671 // call __tls_get_addr. 1672 ArgListTy Args; 1673 ArgListEntry Entry; 1674 Entry.Node = Argument; 1675 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext()); 1676 Args.push_back(Entry); 1677 // FIXME: is there useful debug info available here? 1678 std::pair<SDValue, SDValue> CallResult = 1679 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()), 1680 false, false, false, false, 1681 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 1682 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 1683 return CallResult.first; 1684} 1685 1686// Lower ISD::GlobalTLSAddress using the "initial exec" or 1687// "local exec" model. 1688SDValue 1689ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 1690 SelectionDAG &DAG) const { 1691 const GlobalValue *GV = GA->getGlobal(); 1692 DebugLoc dl = GA->getDebugLoc(); 1693 SDValue Offset; 1694 SDValue Chain = DAG.getEntryNode(); 1695 EVT PtrVT = getPointerTy(); 1696 // Get the Thread Pointer 1697 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1698 1699 if (GV->isDeclaration()) { 1700 MachineFunction &MF = DAG.getMachineFunction(); 1701 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1702 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1703 // Initial exec model. 1704 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1705 ARMConstantPoolValue *CPV = 1706 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1707 ARMCP::CPValue, PCAdj, "gottpoff", true); 1708 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1709 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1710 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1711 PseudoSourceValue::getConstantPool(), 0, 1712 false, false, 0); 1713 Chain = Offset.getValue(1); 1714 1715 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1716 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 1717 1718 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1719 PseudoSourceValue::getConstantPool(), 0, 1720 false, false, 0); 1721 } else { 1722 // local exec model 1723 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff"); 1724 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1725 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1726 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1727 PseudoSourceValue::getConstantPool(), 0, 1728 false, false, 0); 1729 } 1730 1731 // The address of the thread local variable is the add of the thread 1732 // pointer with the offset of the variable. 1733 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1734} 1735 1736SDValue 1737ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 1738 // TODO: implement the "local dynamic" model 1739 assert(Subtarget->isTargetELF() && 1740 "TLS not implemented for non-ELF targets"); 1741 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1742 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 1743 // otherwise use the "Local Exec" TLS Model 1744 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 1745 return LowerToTLSGeneralDynamicModel(GA, DAG); 1746 else 1747 return LowerToTLSExecModels(GA, DAG); 1748} 1749 1750SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 1751 SelectionDAG &DAG) const { 1752 EVT PtrVT = getPointerTy(); 1753 DebugLoc dl = Op.getDebugLoc(); 1754 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1755 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1756 if (RelocM == Reloc::PIC_) { 1757 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 1758 ARMConstantPoolValue *CPV = 1759 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT"); 1760 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1761 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1762 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1763 CPAddr, 1764 PseudoSourceValue::getConstantPool(), 0, 1765 false, false, 0); 1766 SDValue Chain = Result.getValue(1); 1767 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 1768 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 1769 if (!UseGOTOFF) 1770 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1771 PseudoSourceValue::getGOT(), 0, 1772 false, false, 0); 1773 return Result; 1774 } else { 1775 // If we have T2 ops, we can materialize the address directly via movt/movw 1776 // pair. This is always cheaper. 1777 if (Subtarget->useMovt()) { 1778 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 1779 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 1780 } else { 1781 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1782 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1783 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1784 PseudoSourceValue::getConstantPool(), 0, 1785 false, false, 0); 1786 } 1787 } 1788} 1789 1790SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 1791 SelectionDAG &DAG) const { 1792 MachineFunction &MF = DAG.getMachineFunction(); 1793 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1794 unsigned ARMPCLabelIndex = 0; 1795 EVT PtrVT = getPointerTy(); 1796 DebugLoc dl = Op.getDebugLoc(); 1797 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1798 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1799 SDValue CPAddr; 1800 if (RelocM == Reloc::Static) 1801 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1802 else { 1803 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1804 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 1805 ARMConstantPoolValue *CPV = 1806 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj); 1807 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1808 } 1809 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1810 1811 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1812 PseudoSourceValue::getConstantPool(), 0, 1813 false, false, 0); 1814 SDValue Chain = Result.getValue(1); 1815 1816 if (RelocM == Reloc::PIC_) { 1817 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1818 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1819 } 1820 1821 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 1822 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1823 PseudoSourceValue::getGOT(), 0, 1824 false, false, 0); 1825 1826 return Result; 1827} 1828 1829SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 1830 SelectionDAG &DAG) const { 1831 assert(Subtarget->isTargetELF() && 1832 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 1833 MachineFunction &MF = DAG.getMachineFunction(); 1834 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1835 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1836 EVT PtrVT = getPointerTy(); 1837 DebugLoc dl = Op.getDebugLoc(); 1838 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1839 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1840 "_GLOBAL_OFFSET_TABLE_", 1841 ARMPCLabelIndex, PCAdj); 1842 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1843 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1844 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1845 PseudoSourceValue::getConstantPool(), 0, 1846 false, false, 0); 1847 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1848 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1849} 1850 1851SDValue 1852ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 1853 DebugLoc dl = Op.getDebugLoc(); 1854 SDValue Val = DAG.getConstant(0, MVT::i32); 1855 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), 1856 Op.getOperand(1), Val); 1857} 1858 1859SDValue 1860ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 1861 DebugLoc dl = Op.getDebugLoc(); 1862 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 1863 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 1864} 1865 1866SDValue 1867ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 1868 const ARMSubtarget *Subtarget) const { 1869 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1870 DebugLoc dl = Op.getDebugLoc(); 1871 switch (IntNo) { 1872 default: return SDValue(); // Don't custom lower most intrinsics. 1873 case Intrinsic::arm_thread_pointer: { 1874 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1875 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1876 } 1877 case Intrinsic::eh_sjlj_lsda: { 1878 MachineFunction &MF = DAG.getMachineFunction(); 1879 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1880 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1881 EVT PtrVT = getPointerTy(); 1882 DebugLoc dl = Op.getDebugLoc(); 1883 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1884 SDValue CPAddr; 1885 unsigned PCAdj = (RelocM != Reloc::PIC_) 1886 ? 0 : (Subtarget->isThumb() ? 4 : 8); 1887 ARMConstantPoolValue *CPV = 1888 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex, 1889 ARMCP::CPLSDA, PCAdj); 1890 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1891 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1892 SDValue Result = 1893 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1894 PseudoSourceValue::getConstantPool(), 0, 1895 false, false, 0); 1896 1897 if (RelocM == Reloc::PIC_) { 1898 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1899 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1900 } 1901 return Result; 1902 } 1903 } 1904} 1905 1906static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 1907 const ARMSubtarget *Subtarget) { 1908 DebugLoc dl = Op.getDebugLoc(); 1909 SDValue Op5 = Op.getOperand(5); 1910 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue(); 1911 // v6 and v7 can both handle barriers directly, but need handled a bit 1912 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should 1913 // never get here. 1914 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER; 1915 if (Subtarget->hasV7Ops()) 1916 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0)); 1917 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()) 1918 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0), 1919 DAG.getConstant(0, MVT::i32)); 1920 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 1921 return SDValue(); 1922} 1923 1924static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 1925 MachineFunction &MF = DAG.getMachineFunction(); 1926 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 1927 1928 // vastart just stores the address of the VarArgsFrameIndex slot into the 1929 // memory location argument. 1930 DebugLoc dl = Op.getDebugLoc(); 1931 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1932 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1933 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1934 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 1935 false, false, 0); 1936} 1937 1938SDValue 1939ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 1940 SelectionDAG &DAG) const { 1941 SDNode *Node = Op.getNode(); 1942 DebugLoc dl = Node->getDebugLoc(); 1943 EVT VT = Node->getValueType(0); 1944 SDValue Chain = Op.getOperand(0); 1945 SDValue Size = Op.getOperand(1); 1946 SDValue Align = Op.getOperand(2); 1947 1948 // Chain the dynamic stack allocation so that it doesn't modify the stack 1949 // pointer when other instructions are using the stack. 1950 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1951 1952 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue(); 1953 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment(); 1954 if (AlignVal > StackAlign) 1955 // Do this now since selection pass cannot introduce new target 1956 // independent node. 1957 Align = DAG.getConstant(-(uint64_t)AlignVal, VT); 1958 1959 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up 1960 // using a "add r, sp, r" instead. Negate the size now so we don't have to 1961 // do even more horrible hack later. 1962 MachineFunction &MF = DAG.getMachineFunction(); 1963 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1964 if (AFI->isThumb1OnlyFunction()) { 1965 bool Negate = true; 1966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size); 1967 if (C) { 1968 uint32_t Val = C->getZExtValue(); 1969 if (Val <= 508 && ((Val & 3) == 0)) 1970 Negate = false; 1971 } 1972 if (Negate) 1973 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size); 1974 } 1975 1976 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1977 SDValue Ops1[] = { Chain, Size, Align }; 1978 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3); 1979 Chain = Res.getValue(1); 1980 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1981 DAG.getIntPtrConstant(0, true), SDValue()); 1982 SDValue Ops2[] = { Res, Chain }; 1983 return DAG.getMergeValues(Ops2, 2, dl); 1984} 1985 1986SDValue 1987ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 1988 SDValue &Root, SelectionDAG &DAG, 1989 DebugLoc dl) const { 1990 MachineFunction &MF = DAG.getMachineFunction(); 1991 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1992 1993 TargetRegisterClass *RC; 1994 if (AFI->isThumb1OnlyFunction()) 1995 RC = ARM::tGPRRegisterClass; 1996 else 1997 RC = ARM::GPRRegisterClass; 1998 1999 // Transform the arguments stored in physical registers into virtual ones. 2000 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2001 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2002 2003 SDValue ArgValue2; 2004 if (NextVA.isMemLoc()) { 2005 MachineFrameInfo *MFI = MF.getFrameInfo(); 2006 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2007 2008 // Create load node to retrieve arguments from the stack. 2009 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2010 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2011 PseudoSourceValue::getFixedStack(FI), 0, 2012 false, false, 0); 2013 } else { 2014 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2015 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2016 } 2017 2018 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2019} 2020 2021SDValue 2022ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2023 CallingConv::ID CallConv, bool isVarArg, 2024 const SmallVectorImpl<ISD::InputArg> 2025 &Ins, 2026 DebugLoc dl, SelectionDAG &DAG, 2027 SmallVectorImpl<SDValue> &InVals) 2028 const { 2029 2030 MachineFunction &MF = DAG.getMachineFunction(); 2031 MachineFrameInfo *MFI = MF.getFrameInfo(); 2032 2033 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2034 2035 // Assign locations to all of the incoming arguments. 2036 SmallVector<CCValAssign, 16> ArgLocs; 2037 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 2038 *DAG.getContext()); 2039 CCInfo.AnalyzeFormalArguments(Ins, 2040 CCAssignFnForNode(CallConv, /* Return*/ false, 2041 isVarArg)); 2042 2043 SmallVector<SDValue, 16> ArgValues; 2044 2045 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2046 CCValAssign &VA = ArgLocs[i]; 2047 2048 // Arguments stored in registers. 2049 if (VA.isRegLoc()) { 2050 EVT RegVT = VA.getLocVT(); 2051 2052 SDValue ArgValue; 2053 if (VA.needsCustom()) { 2054 // f64 and vector types are split up into multiple registers or 2055 // combinations of registers and stack slots. 2056 if (VA.getLocVT() == MVT::v2f64) { 2057 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2058 Chain, DAG, dl); 2059 VA = ArgLocs[++i]; // skip ahead to next loc 2060 SDValue ArgValue2; 2061 if (VA.isMemLoc()) { 2062 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2063 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2064 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2065 PseudoSourceValue::getFixedStack(FI), 0, 2066 false, false, 0); 2067 } else { 2068 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2069 Chain, DAG, dl); 2070 } 2071 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2072 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2073 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2074 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2075 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2076 } else 2077 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2078 2079 } else { 2080 TargetRegisterClass *RC; 2081 2082 if (RegVT == MVT::f32) 2083 RC = ARM::SPRRegisterClass; 2084 else if (RegVT == MVT::f64) 2085 RC = ARM::DPRRegisterClass; 2086 else if (RegVT == MVT::v2f64) 2087 RC = ARM::QPRRegisterClass; 2088 else if (RegVT == MVT::i32) 2089 RC = (AFI->isThumb1OnlyFunction() ? 2090 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2091 else 2092 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2093 2094 // Transform the arguments in physical registers into virtual ones. 2095 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2096 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2097 } 2098 2099 // If this is an 8 or 16-bit value, it is really passed promoted 2100 // to 32 bits. Insert an assert[sz]ext to capture this, then 2101 // truncate to the right size. 2102 switch (VA.getLocInfo()) { 2103 default: llvm_unreachable("Unknown loc info!"); 2104 case CCValAssign::Full: break; 2105 case CCValAssign::BCvt: 2106 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 2107 break; 2108 case CCValAssign::SExt: 2109 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2110 DAG.getValueType(VA.getValVT())); 2111 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2112 break; 2113 case CCValAssign::ZExt: 2114 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2115 DAG.getValueType(VA.getValVT())); 2116 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2117 break; 2118 } 2119 2120 InVals.push_back(ArgValue); 2121 2122 } else { // VA.isRegLoc() 2123 2124 // sanity check 2125 assert(VA.isMemLoc()); 2126 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2127 2128 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 2129 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true); 2130 2131 // Create load nodes to retrieve arguments from the stack. 2132 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2133 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2134 PseudoSourceValue::getFixedStack(FI), 0, 2135 false, false, 0)); 2136 } 2137 } 2138 2139 // varargs 2140 if (isVarArg) { 2141 static const unsigned GPRArgRegs[] = { 2142 ARM::R0, ARM::R1, ARM::R2, ARM::R3 2143 }; 2144 2145 unsigned NumGPRs = CCInfo.getFirstUnallocated 2146 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2147 2148 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 2149 unsigned VARegSize = (4 - NumGPRs) * 4; 2150 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2151 unsigned ArgOffset = CCInfo.getNextStackOffset(); 2152 if (VARegSaveSize) { 2153 // If this function is vararg, store any remaining integer argument regs 2154 // to their spots on the stack so that they may be loaded by deferencing 2155 // the result of va_next. 2156 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2157 AFI->setVarArgsFrameIndex( 2158 MFI->CreateFixedObject(VARegSaveSize, 2159 ArgOffset + VARegSaveSize - VARegSize, 2160 true)); 2161 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2162 getPointerTy()); 2163 2164 SmallVector<SDValue, 4> MemOps; 2165 for (; NumGPRs < 4; ++NumGPRs) { 2166 TargetRegisterClass *RC; 2167 if (AFI->isThumb1OnlyFunction()) 2168 RC = ARM::tGPRRegisterClass; 2169 else 2170 RC = ARM::GPRRegisterClass; 2171 2172 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); 2173 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2174 SDValue Store = 2175 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2176 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()), 2177 0, false, false, 0); 2178 MemOps.push_back(Store); 2179 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2180 DAG.getConstant(4, getPointerTy())); 2181 } 2182 if (!MemOps.empty()) 2183 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2184 &MemOps[0], MemOps.size()); 2185 } else 2186 // This will point to the next argument passed via stack. 2187 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2188 } 2189 2190 return Chain; 2191} 2192 2193/// isFloatingPointZero - Return true if this is +0.0. 2194static bool isFloatingPointZero(SDValue Op) { 2195 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2196 return CFP->getValueAPF().isPosZero(); 2197 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2198 // Maybe this has already been legalized into the constant pool? 2199 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2200 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2201 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2202 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2203 return CFP->getValueAPF().isPosZero(); 2204 } 2205 } 2206 return false; 2207} 2208 2209/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2210/// the given operands. 2211SDValue 2212ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2213 SDValue &ARMCC, SelectionDAG &DAG, 2214 DebugLoc dl) const { 2215 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2216 unsigned C = RHSC->getZExtValue(); 2217 if (!isLegalICmpImmediate(C)) { 2218 // Constant does not fit, try adjusting it by one? 2219 switch (CC) { 2220 default: break; 2221 case ISD::SETLT: 2222 case ISD::SETGE: 2223 if (isLegalICmpImmediate(C-1)) { 2224 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2225 RHS = DAG.getConstant(C-1, MVT::i32); 2226 } 2227 break; 2228 case ISD::SETULT: 2229 case ISD::SETUGE: 2230 if (C > 0 && isLegalICmpImmediate(C-1)) { 2231 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2232 RHS = DAG.getConstant(C-1, MVT::i32); 2233 } 2234 break; 2235 case ISD::SETLE: 2236 case ISD::SETGT: 2237 if (isLegalICmpImmediate(C+1)) { 2238 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2239 RHS = DAG.getConstant(C+1, MVT::i32); 2240 } 2241 break; 2242 case ISD::SETULE: 2243 case ISD::SETUGT: 2244 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) { 2245 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2246 RHS = DAG.getConstant(C+1, MVT::i32); 2247 } 2248 break; 2249 } 2250 } 2251 } 2252 2253 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2254 ARMISD::NodeType CompareType; 2255 switch (CondCode) { 2256 default: 2257 CompareType = ARMISD::CMP; 2258 break; 2259 case ARMCC::EQ: 2260 case ARMCC::NE: 2261 // Uses only Z Flag 2262 CompareType = ARMISD::CMPZ; 2263 break; 2264 } 2265 ARMCC = DAG.getConstant(CondCode, MVT::i32); 2266 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); 2267} 2268 2269/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2270static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2271 DebugLoc dl) { 2272 SDValue Cmp; 2273 if (!isFloatingPointZero(RHS)) 2274 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); 2275 else 2276 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); 2277 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); 2278} 2279 2280SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2281 EVT VT = Op.getValueType(); 2282 SDValue LHS = Op.getOperand(0); 2283 SDValue RHS = Op.getOperand(1); 2284 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2285 SDValue TrueVal = Op.getOperand(2); 2286 SDValue FalseVal = Op.getOperand(3); 2287 DebugLoc dl = Op.getDebugLoc(); 2288 2289 if (LHS.getValueType() == MVT::i32) { 2290 SDValue ARMCC; 2291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2292 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2293 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); 2294 } 2295 2296 ARMCC::CondCodes CondCode, CondCode2; 2297 FPCCToARMCC(CC, CondCode, CondCode2); 2298 2299 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 2300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2301 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2302 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2303 ARMCC, CCR, Cmp); 2304 if (CondCode2 != ARMCC::AL) { 2305 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 2306 // FIXME: Needs another CMP because flag can have but one use. 2307 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2308 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2309 Result, TrueVal, ARMCC2, CCR, Cmp2); 2310 } 2311 return Result; 2312} 2313 2314SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2315 SDValue Chain = Op.getOperand(0); 2316 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2317 SDValue LHS = Op.getOperand(2); 2318 SDValue RHS = Op.getOperand(3); 2319 SDValue Dest = Op.getOperand(4); 2320 DebugLoc dl = Op.getDebugLoc(); 2321 2322 if (LHS.getValueType() == MVT::i32) { 2323 SDValue ARMCC; 2324 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2325 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); 2326 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2327 Chain, Dest, ARMCC, CCR,Cmp); 2328 } 2329 2330 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2331 ARMCC::CondCodes CondCode, CondCode2; 2332 FPCCToARMCC(CC, CondCode, CondCode2); 2333 2334 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2335 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 2336 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2337 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 2338 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 2339 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2340 if (CondCode2 != ARMCC::AL) { 2341 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 2342 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 2343 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2344 } 2345 return Res; 2346} 2347 2348SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2349 SDValue Chain = Op.getOperand(0); 2350 SDValue Table = Op.getOperand(1); 2351 SDValue Index = Op.getOperand(2); 2352 DebugLoc dl = Op.getDebugLoc(); 2353 2354 EVT PTy = getPointerTy(); 2355 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2356 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2357 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2358 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2359 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2360 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2361 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2362 if (Subtarget->isThumb2()) { 2363 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2364 // which does another jump to the destination. This also makes it easier 2365 // to translate it to TBB / TBH later. 2366 // FIXME: This might not work if the function is extremely large. 2367 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2368 Addr, Op.getOperand(2), JTI, UId); 2369 } 2370 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2371 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 2372 PseudoSourceValue::getJumpTable(), 0, 2373 false, false, 0); 2374 Chain = Addr.getValue(1); 2375 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 2376 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2377 } else { 2378 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 2379 PseudoSourceValue::getJumpTable(), 0, false, false, 0); 2380 Chain = Addr.getValue(1); 2381 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2382 } 2383} 2384 2385static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 2386 DebugLoc dl = Op.getDebugLoc(); 2387 unsigned Opc; 2388 2389 switch (Op.getOpcode()) { 2390 default: 2391 assert(0 && "Invalid opcode!"); 2392 case ISD::FP_TO_SINT: 2393 Opc = ARMISD::FTOSI; 2394 break; 2395 case ISD::FP_TO_UINT: 2396 Opc = ARMISD::FTOUI; 2397 break; 2398 } 2399 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 2400 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 2401} 2402 2403static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2404 EVT VT = Op.getValueType(); 2405 DebugLoc dl = Op.getDebugLoc(); 2406 unsigned Opc; 2407 2408 switch (Op.getOpcode()) { 2409 default: 2410 assert(0 && "Invalid opcode!"); 2411 case ISD::SINT_TO_FP: 2412 Opc = ARMISD::SITOF; 2413 break; 2414 case ISD::UINT_TO_FP: 2415 Opc = ARMISD::UITOF; 2416 break; 2417 } 2418 2419 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 2420 return DAG.getNode(Opc, dl, VT, Op); 2421} 2422 2423static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 2424 // Implement fcopysign with a fabs and a conditional fneg. 2425 SDValue Tmp0 = Op.getOperand(0); 2426 SDValue Tmp1 = Op.getOperand(1); 2427 DebugLoc dl = Op.getDebugLoc(); 2428 EVT VT = Op.getValueType(); 2429 EVT SrcVT = Tmp1.getValueType(); 2430 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); 2431 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); 2432 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 2433 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2434 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 2435} 2436 2437SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 2438 MachineFunction &MF = DAG.getMachineFunction(); 2439 MachineFrameInfo *MFI = MF.getFrameInfo(); 2440 MFI->setReturnAddressIsTaken(true); 2441 2442 EVT VT = Op.getValueType(); 2443 DebugLoc dl = Op.getDebugLoc(); 2444 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2445 if (Depth) { 2446 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 2447 SDValue Offset = DAG.getConstant(4, MVT::i32); 2448 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 2449 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 2450 NULL, 0, false, false, 0); 2451 } 2452 2453 // Return LR, which contains the return address. Mark it an implicit live-in. 2454 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass); 2455 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 2456} 2457 2458SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2459 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2460 MFI->setFrameAddressIsTaken(true); 2461 2462 EVT VT = Op.getValueType(); 2463 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 2464 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2465 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 2466 ? ARM::R7 : ARM::R11; 2467 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2468 while (Depth--) 2469 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 2470 false, false, 0); 2471 return FrameAddr; 2472} 2473 2474/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to 2475/// expand a bit convert where either the source or destination type is i64 to 2476/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 2477/// operand type is illegal (e.g., v2f32 for a target that doesn't support 2478/// vectors), since the legalizer won't know what to do with that. 2479static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 2480 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2481 DebugLoc dl = N->getDebugLoc(); 2482 SDValue Op = N->getOperand(0); 2483 2484 // This function is only supposed to be called for i64 types, either as the 2485 // source or destination of the bit convert. 2486 EVT SrcVT = Op.getValueType(); 2487 EVT DstVT = N->getValueType(0); 2488 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 2489 "ExpandBIT_CONVERT called for non-i64 type"); 2490 2491 // Turn i64->f64 into VMOVDRR. 2492 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 2493 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2494 DAG.getConstant(0, MVT::i32)); 2495 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2496 DAG.getConstant(1, MVT::i32)); 2497 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT, 2498 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 2499 } 2500 2501 // Turn f64->i64 into VMOVRRD. 2502 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 2503 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 2504 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 2505 // Merge the pieces into a single i64 value. 2506 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 2507 } 2508 2509 return SDValue(); 2510} 2511 2512/// getZeroVector - Returns a vector of specified type with all zero elements. 2513/// 2514static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2515 assert(VT.isVector() && "Expected a vector type"); 2516 2517 // Zero vectors are used to represent vector negation and in those cases 2518 // will be implemented with the NEON VNEG instruction. However, VNEG does 2519 // not support i64 elements, so sometimes the zero vectors will need to be 2520 // explicitly constructed. For those cases, and potentially other uses in 2521 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted 2522 // to their dest type. This ensures they get CSE'd. 2523 SDValue Vec; 2524 SDValue Cst = DAG.getTargetConstant(0, MVT::i8); 2525 SmallVector<SDValue, 8> Ops; 2526 MVT TVT; 2527 2528 if (VT.getSizeInBits() == 64) { 2529 Ops.assign(8, Cst); TVT = MVT::v8i8; 2530 } else { 2531 Ops.assign(16, Cst); TVT = MVT::v16i8; 2532 } 2533 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2534 2535 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2536} 2537 2538/// getOnesVector - Returns a vector of specified type with all bits set. 2539/// 2540static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2541 assert(VT.isVector() && "Expected a vector type"); 2542 2543 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their 2544 // dest type. This ensures they get CSE'd. 2545 SDValue Vec; 2546 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8); 2547 SmallVector<SDValue, 8> Ops; 2548 MVT TVT; 2549 2550 if (VT.getSizeInBits() == 64) { 2551 Ops.assign(8, Cst); TVT = MVT::v8i8; 2552 } else { 2553 Ops.assign(16, Cst); TVT = MVT::v16i8; 2554 } 2555 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2556 2557 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2558} 2559 2560/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 2561/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2562SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 2563 SelectionDAG &DAG) const { 2564 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2565 EVT VT = Op.getValueType(); 2566 unsigned VTBits = VT.getSizeInBits(); 2567 DebugLoc dl = Op.getDebugLoc(); 2568 SDValue ShOpLo = Op.getOperand(0); 2569 SDValue ShOpHi = Op.getOperand(1); 2570 SDValue ShAmt = Op.getOperand(2); 2571 SDValue ARMCC; 2572 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 2573 2574 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 2575 2576 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2577 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2578 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 2579 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2580 DAG.getConstant(VTBits, MVT::i32)); 2581 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 2582 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2583 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 2584 2585 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2586 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2587 ARMCC, DAG, dl); 2588 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 2589 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, 2590 CCR, Cmp); 2591 2592 SDValue Ops[2] = { Lo, Hi }; 2593 return DAG.getMergeValues(Ops, 2, dl); 2594} 2595 2596/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 2597/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2598SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 2599 SelectionDAG &DAG) const { 2600 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2601 EVT VT = Op.getValueType(); 2602 unsigned VTBits = VT.getSizeInBits(); 2603 DebugLoc dl = Op.getDebugLoc(); 2604 SDValue ShOpLo = Op.getOperand(0); 2605 SDValue ShOpHi = Op.getOperand(1); 2606 SDValue ShAmt = Op.getOperand(2); 2607 SDValue ARMCC; 2608 2609 assert(Op.getOpcode() == ISD::SHL_PARTS); 2610 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2611 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2612 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 2613 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2614 DAG.getConstant(VTBits, MVT::i32)); 2615 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 2616 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 2617 2618 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2619 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2620 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2621 ARMCC, DAG, dl); 2622 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 2623 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC, 2624 CCR, Cmp); 2625 2626 SDValue Ops[2] = { Lo, Hi }; 2627 return DAG.getMergeValues(Ops, 2, dl); 2628} 2629 2630static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 2631 const ARMSubtarget *ST) { 2632 EVT VT = N->getValueType(0); 2633 DebugLoc dl = N->getDebugLoc(); 2634 2635 if (!ST->hasV6T2Ops()) 2636 return SDValue(); 2637 2638 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 2639 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 2640} 2641 2642static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 2643 const ARMSubtarget *ST) { 2644 EVT VT = N->getValueType(0); 2645 DebugLoc dl = N->getDebugLoc(); 2646 2647 // Lower vector shifts on NEON to use VSHL. 2648 if (VT.isVector()) { 2649 assert(ST->hasNEON() && "unexpected vector shift"); 2650 2651 // Left shifts translate directly to the vshiftu intrinsic. 2652 if (N->getOpcode() == ISD::SHL) 2653 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2654 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 2655 N->getOperand(0), N->getOperand(1)); 2656 2657 assert((N->getOpcode() == ISD::SRA || 2658 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 2659 2660 // NEON uses the same intrinsics for both left and right shifts. For 2661 // right shifts, the shift amounts are negative, so negate the vector of 2662 // shift amounts. 2663 EVT ShiftVT = N->getOperand(1).getValueType(); 2664 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 2665 getZeroVector(ShiftVT, DAG, dl), 2666 N->getOperand(1)); 2667 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 2668 Intrinsic::arm_neon_vshifts : 2669 Intrinsic::arm_neon_vshiftu); 2670 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2671 DAG.getConstant(vshiftInt, MVT::i32), 2672 N->getOperand(0), NegatedCount); 2673 } 2674 2675 // We can get here for a node like i32 = ISD::SHL i32, i64 2676 if (VT != MVT::i64) 2677 return SDValue(); 2678 2679 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 2680 "Unknown shift to lower!"); 2681 2682 // We only lower SRA, SRL of 1 here, all others use generic lowering. 2683 if (!isa<ConstantSDNode>(N->getOperand(1)) || 2684 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 2685 return SDValue(); 2686 2687 // If we are in thumb mode, we don't have RRX. 2688 if (ST->isThumb1Only()) return SDValue(); 2689 2690 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 2691 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2692 DAG.getConstant(0, MVT::i32)); 2693 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2694 DAG.getConstant(1, MVT::i32)); 2695 2696 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 2697 // captures the result into a carry flag. 2698 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 2699 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 2700 2701 // The low part is an ARMISD::RRX operand, which shifts the carry in. 2702 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 2703 2704 // Merge the pieces into a single i64 value. 2705 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 2706} 2707 2708static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 2709 SDValue TmpOp0, TmpOp1; 2710 bool Invert = false; 2711 bool Swap = false; 2712 unsigned Opc = 0; 2713 2714 SDValue Op0 = Op.getOperand(0); 2715 SDValue Op1 = Op.getOperand(1); 2716 SDValue CC = Op.getOperand(2); 2717 EVT VT = Op.getValueType(); 2718 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 2719 DebugLoc dl = Op.getDebugLoc(); 2720 2721 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 2722 switch (SetCCOpcode) { 2723 default: llvm_unreachable("Illegal FP comparison"); break; 2724 case ISD::SETUNE: 2725 case ISD::SETNE: Invert = true; // Fallthrough 2726 case ISD::SETOEQ: 2727 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2728 case ISD::SETOLT: 2729 case ISD::SETLT: Swap = true; // Fallthrough 2730 case ISD::SETOGT: 2731 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2732 case ISD::SETOLE: 2733 case ISD::SETLE: Swap = true; // Fallthrough 2734 case ISD::SETOGE: 2735 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2736 case ISD::SETUGE: Swap = true; // Fallthrough 2737 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 2738 case ISD::SETUGT: Swap = true; // Fallthrough 2739 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 2740 case ISD::SETUEQ: Invert = true; // Fallthrough 2741 case ISD::SETONE: 2742 // Expand this to (OLT | OGT). 2743 TmpOp0 = Op0; 2744 TmpOp1 = Op1; 2745 Opc = ISD::OR; 2746 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2747 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 2748 break; 2749 case ISD::SETUO: Invert = true; // Fallthrough 2750 case ISD::SETO: 2751 // Expand this to (OLT | OGE). 2752 TmpOp0 = Op0; 2753 TmpOp1 = Op1; 2754 Opc = ISD::OR; 2755 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2756 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 2757 break; 2758 } 2759 } else { 2760 // Integer comparisons. 2761 switch (SetCCOpcode) { 2762 default: llvm_unreachable("Illegal integer comparison"); break; 2763 case ISD::SETNE: Invert = true; 2764 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2765 case ISD::SETLT: Swap = true; 2766 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2767 case ISD::SETLE: Swap = true; 2768 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2769 case ISD::SETULT: Swap = true; 2770 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 2771 case ISD::SETULE: Swap = true; 2772 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 2773 } 2774 2775 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 2776 if (Opc == ARMISD::VCEQ) { 2777 2778 SDValue AndOp; 2779 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 2780 AndOp = Op0; 2781 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 2782 AndOp = Op1; 2783 2784 // Ignore bitconvert. 2785 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) 2786 AndOp = AndOp.getOperand(0); 2787 2788 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 2789 Opc = ARMISD::VTST; 2790 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); 2791 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); 2792 Invert = !Invert; 2793 } 2794 } 2795 } 2796 2797 if (Swap) 2798 std::swap(Op0, Op1); 2799 2800 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 2801 2802 if (Invert) 2803 Result = DAG.getNOT(dl, Result, VT); 2804 2805 return Result; 2806} 2807 2808/// isNEONModifiedImm - Check if the specified splat value corresponds to a 2809/// valid vector constant for a NEON instruction with a "modified immediate" 2810/// operand (e.g., VMOV). If so, return either the constant being 2811/// splatted or the encoded value, depending on the DoEncode parameter. The 2812/// format of the encoded value is: bit12=Op, bits11-8=Cmode, 2813/// bits7-0=Immediate. 2814static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 2815 unsigned SplatBitSize, SelectionDAG &DAG, 2816 bool isVMOV, bool DoEncode) { 2817 unsigned Op, Cmode, Imm; 2818 EVT VT; 2819 2820 // SplatBitSize is set to the smallest size that splats the vector, so a 2821 // zero vector will always have SplatBitSize == 8. However, NEON modified 2822 // immediate instructions others than VMOV do not support the 8-bit encoding 2823 // of a zero vector, and the default encoding of zero is supposed to be the 2824 // 32-bit version. 2825 if (SplatBits == 0) 2826 SplatBitSize = 32; 2827 2828 Op = 0; 2829 switch (SplatBitSize) { 2830 case 8: 2831 // Any 1-byte value is OK. Op=0, Cmode=1110. 2832 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 2833 Cmode = 0xe; 2834 Imm = SplatBits; 2835 VT = MVT::i8; 2836 break; 2837 2838 case 16: 2839 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 2840 VT = MVT::i16; 2841 if ((SplatBits & ~0xff) == 0) { 2842 // Value = 0x00nn: Op=x, Cmode=100x. 2843 Cmode = 0x8; 2844 Imm = SplatBits; 2845 break; 2846 } 2847 if ((SplatBits & ~0xff00) == 0) { 2848 // Value = 0xnn00: Op=x, Cmode=101x. 2849 Cmode = 0xa; 2850 Imm = SplatBits >> 8; 2851 break; 2852 } 2853 return SDValue(); 2854 2855 case 32: 2856 // NEON's 32-bit VMOV supports splat values where: 2857 // * only one byte is nonzero, or 2858 // * the least significant byte is 0xff and the second byte is nonzero, or 2859 // * the least significant 2 bytes are 0xff and the third is nonzero. 2860 VT = MVT::i32; 2861 if ((SplatBits & ~0xff) == 0) { 2862 // Value = 0x000000nn: Op=x, Cmode=000x. 2863 Cmode = 0; 2864 Imm = SplatBits; 2865 break; 2866 } 2867 if ((SplatBits & ~0xff00) == 0) { 2868 // Value = 0x0000nn00: Op=x, Cmode=001x. 2869 Cmode = 0x2; 2870 Imm = SplatBits >> 8; 2871 break; 2872 } 2873 if ((SplatBits & ~0xff0000) == 0) { 2874 // Value = 0x00nn0000: Op=x, Cmode=010x. 2875 Cmode = 0x4; 2876 Imm = SplatBits >> 16; 2877 break; 2878 } 2879 if ((SplatBits & ~0xff000000) == 0) { 2880 // Value = 0xnn000000: Op=x, Cmode=011x. 2881 Cmode = 0x6; 2882 Imm = SplatBits >> 24; 2883 break; 2884 } 2885 2886 if ((SplatBits & ~0xffff) == 0 && 2887 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 2888 // Value = 0x0000nnff: Op=x, Cmode=1100. 2889 Cmode = 0xc; 2890 Imm = SplatBits >> 8; 2891 SplatBits |= 0xff; 2892 break; 2893 } 2894 2895 if ((SplatBits & ~0xffffff) == 0 && 2896 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 2897 // Value = 0x00nnffff: Op=x, Cmode=1101. 2898 Cmode = 0xd; 2899 Imm = SplatBits >> 16; 2900 SplatBits |= 0xffff; 2901 break; 2902 } 2903 2904 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 2905 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 2906 // VMOV.I32. A (very) minor optimization would be to replicate the value 2907 // and fall through here to test for a valid 64-bit splat. But, then the 2908 // caller would also need to check and handle the change in size. 2909 return SDValue(); 2910 2911 case 64: { 2912 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 2913 if (!isVMOV) 2914 return SDValue(); 2915 uint64_t BitMask = 0xff; 2916 uint64_t Val = 0; 2917 unsigned ImmMask = 1; 2918 Imm = 0; 2919 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 2920 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 2921 Val |= BitMask; 2922 Imm |= ImmMask; 2923 } else if ((SplatBits & BitMask) != 0) { 2924 return SDValue(); 2925 } 2926 BitMask <<= 8; 2927 ImmMask <<= 1; 2928 } 2929 // Op=1, Cmode=1110. 2930 Op = 1; 2931 Cmode = 0xe; 2932 SplatBits = Val; 2933 VT = MVT::i64; 2934 break; 2935 } 2936 2937 default: 2938 llvm_unreachable("unexpected size for isNEONModifiedImm"); 2939 return SDValue(); 2940 } 2941 2942 if (DoEncode) 2943 return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32); 2944 return DAG.getTargetConstant(SplatBits, VT); 2945} 2946 2947 2948/// getNEONModImm - If this is a valid vector constant for a NEON instruction 2949/// with a "modified immediate" operand (e.g., VMOV) of the specified element 2950/// size, return the encoded value for that immediate. The ByteSize field 2951/// indicates the number of bytes of each element [1248]. 2952SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, 2953 SelectionDAG &DAG) { 2954 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 2955 APInt SplatBits, SplatUndef; 2956 unsigned SplatBitSize; 2957 bool HasAnyUndefs; 2958 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 2959 HasAnyUndefs, ByteSize * 8)) 2960 return SDValue(); 2961 2962 if (SplatBitSize > ByteSize * 8) 2963 return SDValue(); 2964 2965 return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), 2966 SplatBitSize, DAG, isVMOV, true); 2967} 2968 2969static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 2970 bool &ReverseVEXT, unsigned &Imm) { 2971 unsigned NumElts = VT.getVectorNumElements(); 2972 ReverseVEXT = false; 2973 Imm = M[0]; 2974 2975 // If this is a VEXT shuffle, the immediate value is the index of the first 2976 // element. The other shuffle indices must be the successive elements after 2977 // the first one. 2978 unsigned ExpectedElt = Imm; 2979 for (unsigned i = 1; i < NumElts; ++i) { 2980 // Increment the expected index. If it wraps around, it may still be 2981 // a VEXT but the source vectors must be swapped. 2982 ExpectedElt += 1; 2983 if (ExpectedElt == NumElts * 2) { 2984 ExpectedElt = 0; 2985 ReverseVEXT = true; 2986 } 2987 2988 if (ExpectedElt != static_cast<unsigned>(M[i])) 2989 return false; 2990 } 2991 2992 // Adjust the index value if the source operands will be swapped. 2993 if (ReverseVEXT) 2994 Imm -= NumElts; 2995 2996 return true; 2997} 2998 2999/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3000/// instruction with the specified blocksize. (The order of the elements 3001/// within each block of the vector is reversed.) 3002static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3003 unsigned BlockSize) { 3004 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3005 "Only possible block sizes for VREV are: 16, 32, 64"); 3006 3007 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3008 if (EltSz == 64) 3009 return false; 3010 3011 unsigned NumElts = VT.getVectorNumElements(); 3012 unsigned BlockElts = M[0] + 1; 3013 3014 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3015 return false; 3016 3017 for (unsigned i = 0; i < NumElts; ++i) { 3018 if ((unsigned) M[i] != 3019 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3020 return false; 3021 } 3022 3023 return true; 3024} 3025 3026static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3027 unsigned &WhichResult) { 3028 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3029 if (EltSz == 64) 3030 return false; 3031 3032 unsigned NumElts = VT.getVectorNumElements(); 3033 WhichResult = (M[0] == 0 ? 0 : 1); 3034 for (unsigned i = 0; i < NumElts; i += 2) { 3035 if ((unsigned) M[i] != i + WhichResult || 3036 (unsigned) M[i+1] != i + NumElts + WhichResult) 3037 return false; 3038 } 3039 return true; 3040} 3041 3042/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3043/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3044/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3045static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3046 unsigned &WhichResult) { 3047 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3048 if (EltSz == 64) 3049 return false; 3050 3051 unsigned NumElts = VT.getVectorNumElements(); 3052 WhichResult = (M[0] == 0 ? 0 : 1); 3053 for (unsigned i = 0; i < NumElts; i += 2) { 3054 if ((unsigned) M[i] != i + WhichResult || 3055 (unsigned) M[i+1] != i + WhichResult) 3056 return false; 3057 } 3058 return true; 3059} 3060 3061static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3062 unsigned &WhichResult) { 3063 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3064 if (EltSz == 64) 3065 return false; 3066 3067 unsigned NumElts = VT.getVectorNumElements(); 3068 WhichResult = (M[0] == 0 ? 0 : 1); 3069 for (unsigned i = 0; i != NumElts; ++i) { 3070 if ((unsigned) M[i] != 2 * i + WhichResult) 3071 return false; 3072 } 3073 3074 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3075 if (VT.is64BitVector() && EltSz == 32) 3076 return false; 3077 3078 return true; 3079} 3080 3081/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3082/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3083/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3084static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3085 unsigned &WhichResult) { 3086 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3087 if (EltSz == 64) 3088 return false; 3089 3090 unsigned Half = VT.getVectorNumElements() / 2; 3091 WhichResult = (M[0] == 0 ? 0 : 1); 3092 for (unsigned j = 0; j != 2; ++j) { 3093 unsigned Idx = WhichResult; 3094 for (unsigned i = 0; i != Half; ++i) { 3095 if ((unsigned) M[i + j * Half] != Idx) 3096 return false; 3097 Idx += 2; 3098 } 3099 } 3100 3101 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3102 if (VT.is64BitVector() && EltSz == 32) 3103 return false; 3104 3105 return true; 3106} 3107 3108static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3109 unsigned &WhichResult) { 3110 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3111 if (EltSz == 64) 3112 return false; 3113 3114 unsigned NumElts = VT.getVectorNumElements(); 3115 WhichResult = (M[0] == 0 ? 0 : 1); 3116 unsigned Idx = WhichResult * NumElts / 2; 3117 for (unsigned i = 0; i != NumElts; i += 2) { 3118 if ((unsigned) M[i] != Idx || 3119 (unsigned) M[i+1] != Idx + NumElts) 3120 return false; 3121 Idx += 1; 3122 } 3123 3124 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3125 if (VT.is64BitVector() && EltSz == 32) 3126 return false; 3127 3128 return true; 3129} 3130 3131/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3132/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3133/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3134static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3135 unsigned &WhichResult) { 3136 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3137 if (EltSz == 64) 3138 return false; 3139 3140 unsigned NumElts = VT.getVectorNumElements(); 3141 WhichResult = (M[0] == 0 ? 0 : 1); 3142 unsigned Idx = WhichResult * NumElts / 2; 3143 for (unsigned i = 0; i != NumElts; i += 2) { 3144 if ((unsigned) M[i] != Idx || 3145 (unsigned) M[i+1] != Idx) 3146 return false; 3147 Idx += 1; 3148 } 3149 3150 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3151 if (VT.is64BitVector() && EltSz == 32) 3152 return false; 3153 3154 return true; 3155} 3156 3157 3158static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3159 // Canonicalize all-zeros and all-ones vectors. 3160 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode()); 3161 if (ConstVal->isNullValue()) 3162 return getZeroVector(VT, DAG, dl); 3163 if (ConstVal->isAllOnesValue()) 3164 return getOnesVector(VT, DAG, dl); 3165 3166 EVT CanonicalVT; 3167 if (VT.is64BitVector()) { 3168 switch (Val.getValueType().getSizeInBits()) { 3169 case 8: CanonicalVT = MVT::v8i8; break; 3170 case 16: CanonicalVT = MVT::v4i16; break; 3171 case 32: CanonicalVT = MVT::v2i32; break; 3172 case 64: CanonicalVT = MVT::v1i64; break; 3173 default: llvm_unreachable("unexpected splat element type"); break; 3174 } 3175 } else { 3176 assert(VT.is128BitVector() && "unknown splat vector size"); 3177 switch (Val.getValueType().getSizeInBits()) { 3178 case 8: CanonicalVT = MVT::v16i8; break; 3179 case 16: CanonicalVT = MVT::v8i16; break; 3180 case 32: CanonicalVT = MVT::v4i32; break; 3181 case 64: CanonicalVT = MVT::v2i64; break; 3182 default: llvm_unreachable("unexpected splat element type"); break; 3183 } 3184 } 3185 3186 // Build a canonical splat for this value. 3187 SmallVector<SDValue, 8> Ops; 3188 Ops.assign(CanonicalVT.getVectorNumElements(), Val); 3189 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], 3190 Ops.size()); 3191 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res); 3192} 3193 3194// If this is a case we can't handle, return null and let the default 3195// expansion code take care of it. 3196static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3197 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3198 DebugLoc dl = Op.getDebugLoc(); 3199 EVT VT = Op.getValueType(); 3200 3201 APInt SplatBits, SplatUndef; 3202 unsigned SplatBitSize; 3203 bool HasAnyUndefs; 3204 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3205 if (SplatBitSize <= 64) { 3206 // Check if an immediate VMOV works. 3207 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3208 SplatUndef.getZExtValue(), 3209 SplatBitSize, DAG, true, false); 3210 if (Val.getNode()) 3211 return BuildSplat(Val, VT, DAG, dl); 3212 } 3213 } 3214 3215 // Scan through the operands to see if only one value is used. 3216 unsigned NumElts = VT.getVectorNumElements(); 3217 bool isOnlyLowElement = true; 3218 bool usesOnlyOneValue = true; 3219 bool isConstant = true; 3220 SDValue Value; 3221 for (unsigned i = 0; i < NumElts; ++i) { 3222 SDValue V = Op.getOperand(i); 3223 if (V.getOpcode() == ISD::UNDEF) 3224 continue; 3225 if (i > 0) 3226 isOnlyLowElement = false; 3227 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3228 isConstant = false; 3229 3230 if (!Value.getNode()) 3231 Value = V; 3232 else if (V != Value) 3233 usesOnlyOneValue = false; 3234 } 3235 3236 if (!Value.getNode()) 3237 return DAG.getUNDEF(VT); 3238 3239 if (isOnlyLowElement) 3240 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3241 3242 // If all elements are constants, fall back to the default expansion, which 3243 // will generate a load from the constant pool. 3244 if (isConstant) 3245 return SDValue(); 3246 3247 // Use VDUP for non-constant splats. 3248 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3249 if (usesOnlyOneValue && EltSize <= 32) 3250 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3251 3252 // Vectors with 32- or 64-bit elements can be built by directly assigning 3253 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 3254 // will be legalized. 3255 if (EltSize >= 32) { 3256 // Do the expansion with floating-point types, since that is what the VFP 3257 // registers are defined to use, and since i64 is not legal. 3258 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3259 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3260 SmallVector<SDValue, 8> Ops; 3261 for (unsigned i = 0; i < NumElts; ++i) 3262 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i))); 3263 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3264 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3265 } 3266 3267 return SDValue(); 3268} 3269 3270/// isShuffleMaskLegal - Targets can use this to indicate that they only 3271/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 3272/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 3273/// are assumed to be legal. 3274bool 3275ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 3276 EVT VT) const { 3277 if (VT.getVectorNumElements() == 4 && 3278 (VT.is128BitVector() || VT.is64BitVector())) { 3279 unsigned PFIndexes[4]; 3280 for (unsigned i = 0; i != 4; ++i) { 3281 if (M[i] < 0) 3282 PFIndexes[i] = 8; 3283 else 3284 PFIndexes[i] = M[i]; 3285 } 3286 3287 // Compute the index in the perfect shuffle table. 3288 unsigned PFTableIndex = 3289 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3290 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3291 unsigned Cost = (PFEntry >> 30); 3292 3293 if (Cost <= 4) 3294 return true; 3295 } 3296 3297 bool ReverseVEXT; 3298 unsigned Imm, WhichResult; 3299 3300 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3301 return (EltSize >= 32 || 3302 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 3303 isVREVMask(M, VT, 64) || 3304 isVREVMask(M, VT, 32) || 3305 isVREVMask(M, VT, 16) || 3306 isVEXTMask(M, VT, ReverseVEXT, Imm) || 3307 isVTRNMask(M, VT, WhichResult) || 3308 isVUZPMask(M, VT, WhichResult) || 3309 isVZIPMask(M, VT, WhichResult) || 3310 isVTRN_v_undef_Mask(M, VT, WhichResult) || 3311 isVUZP_v_undef_Mask(M, VT, WhichResult) || 3312 isVZIP_v_undef_Mask(M, VT, WhichResult)); 3313} 3314 3315/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3316/// the specified operations to build the shuffle. 3317static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3318 SDValue RHS, SelectionDAG &DAG, 3319 DebugLoc dl) { 3320 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3321 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3322 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3323 3324 enum { 3325 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3326 OP_VREV, 3327 OP_VDUP0, 3328 OP_VDUP1, 3329 OP_VDUP2, 3330 OP_VDUP3, 3331 OP_VEXT1, 3332 OP_VEXT2, 3333 OP_VEXT3, 3334 OP_VUZPL, // VUZP, left result 3335 OP_VUZPR, // VUZP, right result 3336 OP_VZIPL, // VZIP, left result 3337 OP_VZIPR, // VZIP, right result 3338 OP_VTRNL, // VTRN, left result 3339 OP_VTRNR // VTRN, right result 3340 }; 3341 3342 if (OpNum == OP_COPY) { 3343 if (LHSID == (1*9+2)*9+3) return LHS; 3344 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3345 return RHS; 3346 } 3347 3348 SDValue OpLHS, OpRHS; 3349 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 3350 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 3351 EVT VT = OpLHS.getValueType(); 3352 3353 switch (OpNum) { 3354 default: llvm_unreachable("Unknown shuffle opcode!"); 3355 case OP_VREV: 3356 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 3357 case OP_VDUP0: 3358 case OP_VDUP1: 3359 case OP_VDUP2: 3360 case OP_VDUP3: 3361 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 3362 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 3363 case OP_VEXT1: 3364 case OP_VEXT2: 3365 case OP_VEXT3: 3366 return DAG.getNode(ARMISD::VEXT, dl, VT, 3367 OpLHS, OpRHS, 3368 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 3369 case OP_VUZPL: 3370 case OP_VUZPR: 3371 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3372 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 3373 case OP_VZIPL: 3374 case OP_VZIPR: 3375 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3376 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 3377 case OP_VTRNL: 3378 case OP_VTRNR: 3379 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3380 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 3381 } 3382} 3383 3384static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 3385 SDValue V1 = Op.getOperand(0); 3386 SDValue V2 = Op.getOperand(1); 3387 DebugLoc dl = Op.getDebugLoc(); 3388 EVT VT = Op.getValueType(); 3389 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 3390 SmallVector<int, 8> ShuffleMask; 3391 3392 // Convert shuffles that are directly supported on NEON to target-specific 3393 // DAG nodes, instead of keeping them as shuffles and matching them again 3394 // during code selection. This is more efficient and avoids the possibility 3395 // of inconsistencies between legalization and selection. 3396 // FIXME: floating-point vectors should be canonicalized to integer vectors 3397 // of the same time so that they get CSEd properly. 3398 SVN->getMask(ShuffleMask); 3399 3400 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3401 if (EltSize <= 32) { 3402 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 3403 int Lane = SVN->getSplatIndex(); 3404 // If this is undef splat, generate it via "just" vdup, if possible. 3405 if (Lane == -1) Lane = 0; 3406 3407 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3408 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 3409 } 3410 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 3411 DAG.getConstant(Lane, MVT::i32)); 3412 } 3413 3414 bool ReverseVEXT; 3415 unsigned Imm; 3416 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 3417 if (ReverseVEXT) 3418 std::swap(V1, V2); 3419 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 3420 DAG.getConstant(Imm, MVT::i32)); 3421 } 3422 3423 if (isVREVMask(ShuffleMask, VT, 64)) 3424 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 3425 if (isVREVMask(ShuffleMask, VT, 32)) 3426 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 3427 if (isVREVMask(ShuffleMask, VT, 16)) 3428 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 3429 3430 // Check for Neon shuffles that modify both input vectors in place. 3431 // If both results are used, i.e., if there are two shuffles with the same 3432 // source operands and with masks corresponding to both results of one of 3433 // these operations, DAG memoization will ensure that a single node is 3434 // used for both shuffles. 3435 unsigned WhichResult; 3436 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 3437 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3438 V1, V2).getValue(WhichResult); 3439 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 3440 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3441 V1, V2).getValue(WhichResult); 3442 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 3443 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3444 V1, V2).getValue(WhichResult); 3445 3446 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3447 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3448 V1, V1).getValue(WhichResult); 3449 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3450 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3451 V1, V1).getValue(WhichResult); 3452 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3453 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3454 V1, V1).getValue(WhichResult); 3455 } 3456 3457 // If the shuffle is not directly supported and it has 4 elements, use 3458 // the PerfectShuffle-generated table to synthesize it from other shuffles. 3459 unsigned NumElts = VT.getVectorNumElements(); 3460 if (NumElts == 4) { 3461 unsigned PFIndexes[4]; 3462 for (unsigned i = 0; i != 4; ++i) { 3463 if (ShuffleMask[i] < 0) 3464 PFIndexes[i] = 8; 3465 else 3466 PFIndexes[i] = ShuffleMask[i]; 3467 } 3468 3469 // Compute the index in the perfect shuffle table. 3470 unsigned PFTableIndex = 3471 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3472 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3473 unsigned Cost = (PFEntry >> 30); 3474 3475 if (Cost <= 4) 3476 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 3477 } 3478 3479 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 3480 if (EltSize >= 32) { 3481 // Do the expansion with floating-point types, since that is what the VFP 3482 // registers are defined to use, and since i64 is not legal. 3483 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3484 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3485 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1); 3486 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2); 3487 SmallVector<SDValue, 8> Ops; 3488 for (unsigned i = 0; i < NumElts; ++i) { 3489 if (ShuffleMask[i] < 0) 3490 Ops.push_back(DAG.getUNDEF(EltVT)); 3491 else 3492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3493 ShuffleMask[i] < (int)NumElts ? V1 : V2, 3494 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 3495 MVT::i32))); 3496 } 3497 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3498 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3499 } 3500 3501 return SDValue(); 3502} 3503 3504static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 3505 EVT VT = Op.getValueType(); 3506 DebugLoc dl = Op.getDebugLoc(); 3507 SDValue Vec = Op.getOperand(0); 3508 SDValue Lane = Op.getOperand(1); 3509 assert(VT == MVT::i32 && 3510 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && 3511 "unexpected type for custom-lowering vector extract"); 3512 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 3513} 3514 3515static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3516 // The only time a CONCAT_VECTORS operation can have legal types is when 3517 // two 64-bit vectors are concatenated to a 128-bit vector. 3518 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 3519 "unexpected CONCAT_VECTORS"); 3520 DebugLoc dl = Op.getDebugLoc(); 3521 SDValue Val = DAG.getUNDEF(MVT::v2f64); 3522 SDValue Op0 = Op.getOperand(0); 3523 SDValue Op1 = Op.getOperand(1); 3524 if (Op0.getOpcode() != ISD::UNDEF) 3525 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3526 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), 3527 DAG.getIntPtrConstant(0)); 3528 if (Op1.getOpcode() != ISD::UNDEF) 3529 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3530 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), 3531 DAG.getIntPtrConstant(1)); 3532 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); 3533} 3534 3535SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 3536 switch (Op.getOpcode()) { 3537 default: llvm_unreachable("Don't know how to custom lower this!"); 3538 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3539 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 3540 case ISD::GlobalAddress: 3541 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 3542 LowerGlobalAddressELF(Op, DAG); 3543 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3544 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3545 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 3546 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 3547 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 3548 case ISD::VASTART: return LowerVASTART(Op, DAG); 3549 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 3550 case ISD::SINT_TO_FP: 3551 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 3552 case ISD::FP_TO_SINT: 3553 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 3554 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 3555 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3556 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3557 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 3558 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 3559 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 3560 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 3561 Subtarget); 3562 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 3563 case ISD::SHL: 3564 case ISD::SRL: 3565 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 3566 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 3567 case ISD::SRL_PARTS: 3568 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 3569 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 3570 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 3571 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3572 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3573 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 3574 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 3575 } 3576 return SDValue(); 3577} 3578 3579/// ReplaceNodeResults - Replace the results of node with an illegal result 3580/// type with new values built out of custom code. 3581void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 3582 SmallVectorImpl<SDValue>&Results, 3583 SelectionDAG &DAG) const { 3584 SDValue Res; 3585 switch (N->getOpcode()) { 3586 default: 3587 llvm_unreachable("Don't know how to custom expand this!"); 3588 break; 3589 case ISD::BIT_CONVERT: 3590 Res = ExpandBIT_CONVERT(N, DAG); 3591 break; 3592 case ISD::SRL: 3593 case ISD::SRA: 3594 Res = LowerShift(N, DAG, Subtarget); 3595 break; 3596 } 3597 if (Res.getNode()) 3598 Results.push_back(Res); 3599} 3600 3601//===----------------------------------------------------------------------===// 3602// ARM Scheduler Hooks 3603//===----------------------------------------------------------------------===// 3604 3605MachineBasicBlock * 3606ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 3607 MachineBasicBlock *BB, 3608 unsigned Size) const { 3609 unsigned dest = MI->getOperand(0).getReg(); 3610 unsigned ptr = MI->getOperand(1).getReg(); 3611 unsigned oldval = MI->getOperand(2).getReg(); 3612 unsigned newval = MI->getOperand(3).getReg(); 3613 unsigned scratch = BB->getParent()->getRegInfo() 3614 .createVirtualRegister(ARM::GPRRegisterClass); 3615 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3616 DebugLoc dl = MI->getDebugLoc(); 3617 bool isThumb2 = Subtarget->isThumb2(); 3618 3619 unsigned ldrOpc, strOpc; 3620 switch (Size) { 3621 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3622 case 1: 3623 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3624 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB; 3625 break; 3626 case 2: 3627 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3628 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3629 break; 3630 case 4: 3631 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3632 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3633 break; 3634 } 3635 3636 MachineFunction *MF = BB->getParent(); 3637 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3638 MachineFunction::iterator It = BB; 3639 ++It; // insert the new blocks after the current block 3640 3641 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3642 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3643 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3644 MF->insert(It, loop1MBB); 3645 MF->insert(It, loop2MBB); 3646 MF->insert(It, exitMBB); 3647 3648 // Transfer the remainder of BB and its successor edges to exitMBB. 3649 exitMBB->splice(exitMBB->begin(), BB, 3650 llvm::next(MachineBasicBlock::iterator(MI)), 3651 BB->end()); 3652 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3653 3654 // thisMBB: 3655 // ... 3656 // fallthrough --> loop1MBB 3657 BB->addSuccessor(loop1MBB); 3658 3659 // loop1MBB: 3660 // ldrex dest, [ptr] 3661 // cmp dest, oldval 3662 // bne exitMBB 3663 BB = loop1MBB; 3664 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 3665 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 3666 .addReg(dest).addReg(oldval)); 3667 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3668 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3669 BB->addSuccessor(loop2MBB); 3670 BB->addSuccessor(exitMBB); 3671 3672 // loop2MBB: 3673 // strex scratch, newval, [ptr] 3674 // cmp scratch, #0 3675 // bne loop1MBB 3676 BB = loop2MBB; 3677 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval) 3678 .addReg(ptr)); 3679 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 3680 .addReg(scratch).addImm(0)); 3681 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3682 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3683 BB->addSuccessor(loop1MBB); 3684 BB->addSuccessor(exitMBB); 3685 3686 // exitMBB: 3687 // ... 3688 BB = exitMBB; 3689 3690 MI->eraseFromParent(); // The instruction is gone now. 3691 3692 return BB; 3693} 3694 3695MachineBasicBlock * 3696ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 3697 unsigned Size, unsigned BinOpcode) const { 3698 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3699 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3700 3701 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3702 MachineFunction *MF = BB->getParent(); 3703 MachineFunction::iterator It = BB; 3704 ++It; 3705 3706 unsigned dest = MI->getOperand(0).getReg(); 3707 unsigned ptr = MI->getOperand(1).getReg(); 3708 unsigned incr = MI->getOperand(2).getReg(); 3709 DebugLoc dl = MI->getDebugLoc(); 3710 3711 bool isThumb2 = Subtarget->isThumb2(); 3712 unsigned ldrOpc, strOpc; 3713 switch (Size) { 3714 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3715 case 1: 3716 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3717 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 3718 break; 3719 case 2: 3720 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3721 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3722 break; 3723 case 4: 3724 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3725 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3726 break; 3727 } 3728 3729 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3730 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3731 MF->insert(It, loopMBB); 3732 MF->insert(It, exitMBB); 3733 3734 // Transfer the remainder of BB and its successor edges to exitMBB. 3735 exitMBB->splice(exitMBB->begin(), BB, 3736 llvm::next(MachineBasicBlock::iterator(MI)), 3737 BB->end()); 3738 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3739 3740 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3741 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 3742 unsigned scratch2 = (!BinOpcode) ? incr : 3743 RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 3744 3745 // thisMBB: 3746 // ... 3747 // fallthrough --> loopMBB 3748 BB->addSuccessor(loopMBB); 3749 3750 // loopMBB: 3751 // ldrex dest, ptr 3752 // <binop> scratch2, dest, incr 3753 // strex scratch, scratch2, ptr 3754 // cmp scratch, #0 3755 // bne- loopMBB 3756 // fallthrough --> exitMBB 3757 BB = loopMBB; 3758 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 3759 if (BinOpcode) { 3760 // operand order needs to go the other way for NAND 3761 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 3762 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 3763 addReg(incr).addReg(dest)).addReg(0); 3764 else 3765 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 3766 addReg(dest).addReg(incr)).addReg(0); 3767 } 3768 3769 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2) 3770 .addReg(ptr)); 3771 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 3772 .addReg(scratch).addImm(0)); 3773 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3774 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3775 3776 BB->addSuccessor(loopMBB); 3777 BB->addSuccessor(exitMBB); 3778 3779 // exitMBB: 3780 // ... 3781 BB = exitMBB; 3782 3783 MI->eraseFromParent(); // The instruction is gone now. 3784 3785 return BB; 3786} 3787 3788MachineBasicBlock * 3789ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3790 MachineBasicBlock *BB) const { 3791 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3792 DebugLoc dl = MI->getDebugLoc(); 3793 bool isThumb2 = Subtarget->isThumb2(); 3794 switch (MI->getOpcode()) { 3795 default: 3796 MI->dump(); 3797 llvm_unreachable("Unexpected instr type to insert"); 3798 3799 case ARM::ATOMIC_LOAD_ADD_I8: 3800 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3801 case ARM::ATOMIC_LOAD_ADD_I16: 3802 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3803 case ARM::ATOMIC_LOAD_ADD_I32: 3804 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 3805 3806 case ARM::ATOMIC_LOAD_AND_I8: 3807 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3808 case ARM::ATOMIC_LOAD_AND_I16: 3809 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3810 case ARM::ATOMIC_LOAD_AND_I32: 3811 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 3812 3813 case ARM::ATOMIC_LOAD_OR_I8: 3814 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3815 case ARM::ATOMIC_LOAD_OR_I16: 3816 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3817 case ARM::ATOMIC_LOAD_OR_I32: 3818 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 3819 3820 case ARM::ATOMIC_LOAD_XOR_I8: 3821 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3822 case ARM::ATOMIC_LOAD_XOR_I16: 3823 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3824 case ARM::ATOMIC_LOAD_XOR_I32: 3825 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 3826 3827 case ARM::ATOMIC_LOAD_NAND_I8: 3828 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3829 case ARM::ATOMIC_LOAD_NAND_I16: 3830 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3831 case ARM::ATOMIC_LOAD_NAND_I32: 3832 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 3833 3834 case ARM::ATOMIC_LOAD_SUB_I8: 3835 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3836 case ARM::ATOMIC_LOAD_SUB_I16: 3837 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3838 case ARM::ATOMIC_LOAD_SUB_I32: 3839 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 3840 3841 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 3842 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 3843 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 3844 3845 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 3846 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 3847 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 3848 3849 case ARM::tMOVCCr_pseudo: { 3850 // To "insert" a SELECT_CC instruction, we actually have to insert the 3851 // diamond control-flow pattern. The incoming instruction knows the 3852 // destination vreg to set, the condition code register to branch on, the 3853 // true/false values to select between, and a branch opcode to use. 3854 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3855 MachineFunction::iterator It = BB; 3856 ++It; 3857 3858 // thisMBB: 3859 // ... 3860 // TrueVal = ... 3861 // cmpTY ccX, r1, r2 3862 // bCC copy1MBB 3863 // fallthrough --> copy0MBB 3864 MachineBasicBlock *thisMBB = BB; 3865 MachineFunction *F = BB->getParent(); 3866 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3867 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3868 F->insert(It, copy0MBB); 3869 F->insert(It, sinkMBB); 3870 3871 // Transfer the remainder of BB and its successor edges to sinkMBB. 3872 sinkMBB->splice(sinkMBB->begin(), BB, 3873 llvm::next(MachineBasicBlock::iterator(MI)), 3874 BB->end()); 3875 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3876 3877 BB->addSuccessor(copy0MBB); 3878 BB->addSuccessor(sinkMBB); 3879 3880 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 3881 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 3882 3883 // copy0MBB: 3884 // %FalseValue = ... 3885 // # fallthrough to sinkMBB 3886 BB = copy0MBB; 3887 3888 // Update machine-CFG edges 3889 BB->addSuccessor(sinkMBB); 3890 3891 // sinkMBB: 3892 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3893 // ... 3894 BB = sinkMBB; 3895 BuildMI(*BB, BB->begin(), dl, 3896 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 3897 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 3898 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3899 3900 MI->eraseFromParent(); // The pseudo instruction is gone now. 3901 return BB; 3902 } 3903 3904 case ARM::tANDsp: 3905 case ARM::tADDspr_: 3906 case ARM::tSUBspi_: 3907 case ARM::t2SUBrSPi_: 3908 case ARM::t2SUBrSPi12_: 3909 case ARM::t2SUBrSPs_: { 3910 MachineFunction *MF = BB->getParent(); 3911 unsigned DstReg = MI->getOperand(0).getReg(); 3912 unsigned SrcReg = MI->getOperand(1).getReg(); 3913 bool DstIsDead = MI->getOperand(0).isDead(); 3914 bool SrcIsKill = MI->getOperand(1).isKill(); 3915 3916 if (SrcReg != ARM::SP) { 3917 // Copy the source to SP from virtual register. 3918 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg); 3919 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 3920 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr; 3921 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP) 3922 .addReg(SrcReg, getKillRegState(SrcIsKill)); 3923 } 3924 3925 unsigned OpOpc = 0; 3926 bool NeedPred = false, NeedCC = false, NeedOp3 = false; 3927 switch (MI->getOpcode()) { 3928 default: 3929 llvm_unreachable("Unexpected pseudo instruction!"); 3930 case ARM::tANDsp: 3931 OpOpc = ARM::tAND; 3932 NeedPred = true; 3933 break; 3934 case ARM::tADDspr_: 3935 OpOpc = ARM::tADDspr; 3936 break; 3937 case ARM::tSUBspi_: 3938 OpOpc = ARM::tSUBspi; 3939 break; 3940 case ARM::t2SUBrSPi_: 3941 OpOpc = ARM::t2SUBrSPi; 3942 NeedPred = true; NeedCC = true; 3943 break; 3944 case ARM::t2SUBrSPi12_: 3945 OpOpc = ARM::t2SUBrSPi12; 3946 NeedPred = true; 3947 break; 3948 case ARM::t2SUBrSPs_: 3949 OpOpc = ARM::t2SUBrSPs; 3950 NeedPred = true; NeedCC = true; NeedOp3 = true; 3951 break; 3952 } 3953 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP); 3954 if (OpOpc == ARM::tAND) 3955 AddDefaultT1CC(MIB); 3956 MIB.addReg(ARM::SP); 3957 MIB.addOperand(MI->getOperand(2)); 3958 if (NeedOp3) 3959 MIB.addOperand(MI->getOperand(3)); 3960 if (NeedPred) 3961 AddDefaultPred(MIB); 3962 if (NeedCC) 3963 AddDefaultCC(MIB); 3964 3965 // Copy the result from SP to virtual register. 3966 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg); 3967 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 3968 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr; 3969 BuildMI(*BB, MI, dl, TII->get(CopyOpc)) 3970 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) 3971 .addReg(ARM::SP); 3972 MI->eraseFromParent(); // The pseudo instruction is gone now. 3973 return BB; 3974 } 3975 } 3976} 3977 3978//===----------------------------------------------------------------------===// 3979// ARM Optimization Hooks 3980//===----------------------------------------------------------------------===// 3981 3982static 3983SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 3984 TargetLowering::DAGCombinerInfo &DCI) { 3985 SelectionDAG &DAG = DCI.DAG; 3986 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3987 EVT VT = N->getValueType(0); 3988 unsigned Opc = N->getOpcode(); 3989 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 3990 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 3991 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 3992 ISD::CondCode CC = ISD::SETCC_INVALID; 3993 3994 if (isSlctCC) { 3995 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 3996 } else { 3997 SDValue CCOp = Slct.getOperand(0); 3998 if (CCOp.getOpcode() == ISD::SETCC) 3999 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 4000 } 4001 4002 bool DoXform = false; 4003 bool InvCC = false; 4004 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 4005 "Bad input!"); 4006 4007 if (LHS.getOpcode() == ISD::Constant && 4008 cast<ConstantSDNode>(LHS)->isNullValue()) { 4009 DoXform = true; 4010 } else if (CC != ISD::SETCC_INVALID && 4011 RHS.getOpcode() == ISD::Constant && 4012 cast<ConstantSDNode>(RHS)->isNullValue()) { 4013 std::swap(LHS, RHS); 4014 SDValue Op0 = Slct.getOperand(0); 4015 EVT OpVT = isSlctCC ? Op0.getValueType() : 4016 Op0.getOperand(0).getValueType(); 4017 bool isInt = OpVT.isInteger(); 4018 CC = ISD::getSetCCInverse(CC, isInt); 4019 4020 if (!TLI.isCondCodeLegal(CC, OpVT)) 4021 return SDValue(); // Inverse operator isn't legal. 4022 4023 DoXform = true; 4024 InvCC = true; 4025 } 4026 4027 if (DoXform) { 4028 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 4029 if (isSlctCC) 4030 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 4031 Slct.getOperand(0), Slct.getOperand(1), CC); 4032 SDValue CCOp = Slct.getOperand(0); 4033 if (InvCC) 4034 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 4035 CCOp.getOperand(0), CCOp.getOperand(1), CC); 4036 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4037 CCOp, OtherOp, Result); 4038 } 4039 return SDValue(); 4040} 4041 4042/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 4043static SDValue PerformADDCombine(SDNode *N, 4044 TargetLowering::DAGCombinerInfo &DCI) { 4045 // added by evan in r37685 with no testcase. 4046 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 4047 4048 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 4049 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 4050 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 4051 if (Result.getNode()) return Result; 4052 } 4053 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 4054 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 4055 if (Result.getNode()) return Result; 4056 } 4057 4058 return SDValue(); 4059} 4060 4061/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 4062static SDValue PerformSUBCombine(SDNode *N, 4063 TargetLowering::DAGCombinerInfo &DCI) { 4064 // added by evan in r37685 with no testcase. 4065 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 4066 4067 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 4068 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 4069 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 4070 if (Result.getNode()) return Result; 4071 } 4072 4073 return SDValue(); 4074} 4075 4076static SDValue PerformMULCombine(SDNode *N, 4077 TargetLowering::DAGCombinerInfo &DCI, 4078 const ARMSubtarget *Subtarget) { 4079 SelectionDAG &DAG = DCI.DAG; 4080 4081 if (Subtarget->isThumb1Only()) 4082 return SDValue(); 4083 4084 if (DAG.getMachineFunction(). 4085 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 4086 return SDValue(); 4087 4088 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 4089 return SDValue(); 4090 4091 EVT VT = N->getValueType(0); 4092 if (VT != MVT::i32) 4093 return SDValue(); 4094 4095 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 4096 if (!C) 4097 return SDValue(); 4098 4099 uint64_t MulAmt = C->getZExtValue(); 4100 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 4101 ShiftAmt = ShiftAmt & (32 - 1); 4102 SDValue V = N->getOperand(0); 4103 DebugLoc DL = N->getDebugLoc(); 4104 4105 SDValue Res; 4106 MulAmt >>= ShiftAmt; 4107 if (isPowerOf2_32(MulAmt - 1)) { 4108 // (mul x, 2^N + 1) => (add (shl x, N), x) 4109 Res = DAG.getNode(ISD::ADD, DL, VT, 4110 V, DAG.getNode(ISD::SHL, DL, VT, 4111 V, DAG.getConstant(Log2_32(MulAmt-1), 4112 MVT::i32))); 4113 } else if (isPowerOf2_32(MulAmt + 1)) { 4114 // (mul x, 2^N - 1) => (sub (shl x, N), x) 4115 Res = DAG.getNode(ISD::SUB, DL, VT, 4116 DAG.getNode(ISD::SHL, DL, VT, 4117 V, DAG.getConstant(Log2_32(MulAmt+1), 4118 MVT::i32)), 4119 V); 4120 } else 4121 return SDValue(); 4122 4123 if (ShiftAmt != 0) 4124 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 4125 DAG.getConstant(ShiftAmt, MVT::i32)); 4126 4127 // Do not add new nodes to DAG combiner worklist. 4128 DCI.CombineTo(N, Res, false); 4129 return SDValue(); 4130} 4131 4132/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 4133/// ARMISD::VMOVRRD. 4134static SDValue PerformVMOVRRDCombine(SDNode *N, 4135 TargetLowering::DAGCombinerInfo &DCI) { 4136 // fmrrd(fmdrr x, y) -> x,y 4137 SDValue InDouble = N->getOperand(0); 4138 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 4139 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 4140 return SDValue(); 4141} 4142 4143/// getVShiftImm - Check if this is a valid build_vector for the immediate 4144/// operand of a vector shift operation, where all the elements of the 4145/// build_vector must have the same constant integer value. 4146static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 4147 // Ignore bit_converts. 4148 while (Op.getOpcode() == ISD::BIT_CONVERT) 4149 Op = Op.getOperand(0); 4150 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4151 APInt SplatBits, SplatUndef; 4152 unsigned SplatBitSize; 4153 bool HasAnyUndefs; 4154 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 4155 HasAnyUndefs, ElementBits) || 4156 SplatBitSize > ElementBits) 4157 return false; 4158 Cnt = SplatBits.getSExtValue(); 4159 return true; 4160} 4161 4162/// isVShiftLImm - Check if this is a valid build_vector for the immediate 4163/// operand of a vector shift left operation. That value must be in the range: 4164/// 0 <= Value < ElementBits for a left shift; or 4165/// 0 <= Value <= ElementBits for a long left shift. 4166static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 4167 assert(VT.isVector() && "vector shift count is not a vector type"); 4168 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4169 if (! getVShiftImm(Op, ElementBits, Cnt)) 4170 return false; 4171 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 4172} 4173 4174/// isVShiftRImm - Check if this is a valid build_vector for the immediate 4175/// operand of a vector shift right operation. For a shift opcode, the value 4176/// is positive, but for an intrinsic the value count must be negative. The 4177/// absolute value must be in the range: 4178/// 1 <= |Value| <= ElementBits for a right shift; or 4179/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 4180static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 4181 int64_t &Cnt) { 4182 assert(VT.isVector() && "vector shift count is not a vector type"); 4183 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4184 if (! getVShiftImm(Op, ElementBits, Cnt)) 4185 return false; 4186 if (isIntrinsic) 4187 Cnt = -Cnt; 4188 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 4189} 4190 4191/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 4192static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 4193 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 4194 switch (IntNo) { 4195 default: 4196 // Don't do anything for most intrinsics. 4197 break; 4198 4199 // Vector shifts: check for immediate versions and lower them. 4200 // Note: This is done during DAG combining instead of DAG legalizing because 4201 // the build_vectors for 64-bit vector element shift counts are generally 4202 // not legal, and it is hard to see their values after they get legalized to 4203 // loads from a constant pool. 4204 case Intrinsic::arm_neon_vshifts: 4205 case Intrinsic::arm_neon_vshiftu: 4206 case Intrinsic::arm_neon_vshiftls: 4207 case Intrinsic::arm_neon_vshiftlu: 4208 case Intrinsic::arm_neon_vshiftn: 4209 case Intrinsic::arm_neon_vrshifts: 4210 case Intrinsic::arm_neon_vrshiftu: 4211 case Intrinsic::arm_neon_vrshiftn: 4212 case Intrinsic::arm_neon_vqshifts: 4213 case Intrinsic::arm_neon_vqshiftu: 4214 case Intrinsic::arm_neon_vqshiftsu: 4215 case Intrinsic::arm_neon_vqshiftns: 4216 case Intrinsic::arm_neon_vqshiftnu: 4217 case Intrinsic::arm_neon_vqshiftnsu: 4218 case Intrinsic::arm_neon_vqrshiftns: 4219 case Intrinsic::arm_neon_vqrshiftnu: 4220 case Intrinsic::arm_neon_vqrshiftnsu: { 4221 EVT VT = N->getOperand(1).getValueType(); 4222 int64_t Cnt; 4223 unsigned VShiftOpc = 0; 4224 4225 switch (IntNo) { 4226 case Intrinsic::arm_neon_vshifts: 4227 case Intrinsic::arm_neon_vshiftu: 4228 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 4229 VShiftOpc = ARMISD::VSHL; 4230 break; 4231 } 4232 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 4233 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 4234 ARMISD::VSHRs : ARMISD::VSHRu); 4235 break; 4236 } 4237 return SDValue(); 4238 4239 case Intrinsic::arm_neon_vshiftls: 4240 case Intrinsic::arm_neon_vshiftlu: 4241 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 4242 break; 4243 llvm_unreachable("invalid shift count for vshll intrinsic"); 4244 4245 case Intrinsic::arm_neon_vrshifts: 4246 case Intrinsic::arm_neon_vrshiftu: 4247 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 4248 break; 4249 return SDValue(); 4250 4251 case Intrinsic::arm_neon_vqshifts: 4252 case Intrinsic::arm_neon_vqshiftu: 4253 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4254 break; 4255 return SDValue(); 4256 4257 case Intrinsic::arm_neon_vqshiftsu: 4258 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4259 break; 4260 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 4261 4262 case Intrinsic::arm_neon_vshiftn: 4263 case Intrinsic::arm_neon_vrshiftn: 4264 case Intrinsic::arm_neon_vqshiftns: 4265 case Intrinsic::arm_neon_vqshiftnu: 4266 case Intrinsic::arm_neon_vqshiftnsu: 4267 case Intrinsic::arm_neon_vqrshiftns: 4268 case Intrinsic::arm_neon_vqrshiftnu: 4269 case Intrinsic::arm_neon_vqrshiftnsu: 4270 // Narrowing shifts require an immediate right shift. 4271 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 4272 break; 4273 llvm_unreachable("invalid shift count for narrowing vector shift " 4274 "intrinsic"); 4275 4276 default: 4277 llvm_unreachable("unhandled vector shift"); 4278 } 4279 4280 switch (IntNo) { 4281 case Intrinsic::arm_neon_vshifts: 4282 case Intrinsic::arm_neon_vshiftu: 4283 // Opcode already set above. 4284 break; 4285 case Intrinsic::arm_neon_vshiftls: 4286 case Intrinsic::arm_neon_vshiftlu: 4287 if (Cnt == VT.getVectorElementType().getSizeInBits()) 4288 VShiftOpc = ARMISD::VSHLLi; 4289 else 4290 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 4291 ARMISD::VSHLLs : ARMISD::VSHLLu); 4292 break; 4293 case Intrinsic::arm_neon_vshiftn: 4294 VShiftOpc = ARMISD::VSHRN; break; 4295 case Intrinsic::arm_neon_vrshifts: 4296 VShiftOpc = ARMISD::VRSHRs; break; 4297 case Intrinsic::arm_neon_vrshiftu: 4298 VShiftOpc = ARMISD::VRSHRu; break; 4299 case Intrinsic::arm_neon_vrshiftn: 4300 VShiftOpc = ARMISD::VRSHRN; break; 4301 case Intrinsic::arm_neon_vqshifts: 4302 VShiftOpc = ARMISD::VQSHLs; break; 4303 case Intrinsic::arm_neon_vqshiftu: 4304 VShiftOpc = ARMISD::VQSHLu; break; 4305 case Intrinsic::arm_neon_vqshiftsu: 4306 VShiftOpc = ARMISD::VQSHLsu; break; 4307 case Intrinsic::arm_neon_vqshiftns: 4308 VShiftOpc = ARMISD::VQSHRNs; break; 4309 case Intrinsic::arm_neon_vqshiftnu: 4310 VShiftOpc = ARMISD::VQSHRNu; break; 4311 case Intrinsic::arm_neon_vqshiftnsu: 4312 VShiftOpc = ARMISD::VQSHRNsu; break; 4313 case Intrinsic::arm_neon_vqrshiftns: 4314 VShiftOpc = ARMISD::VQRSHRNs; break; 4315 case Intrinsic::arm_neon_vqrshiftnu: 4316 VShiftOpc = ARMISD::VQRSHRNu; break; 4317 case Intrinsic::arm_neon_vqrshiftnsu: 4318 VShiftOpc = ARMISD::VQRSHRNsu; break; 4319 } 4320 4321 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4322 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 4323 } 4324 4325 case Intrinsic::arm_neon_vshiftins: { 4326 EVT VT = N->getOperand(1).getValueType(); 4327 int64_t Cnt; 4328 unsigned VShiftOpc = 0; 4329 4330 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 4331 VShiftOpc = ARMISD::VSLI; 4332 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 4333 VShiftOpc = ARMISD::VSRI; 4334 else { 4335 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 4336 } 4337 4338 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4339 N->getOperand(1), N->getOperand(2), 4340 DAG.getConstant(Cnt, MVT::i32)); 4341 } 4342 4343 case Intrinsic::arm_neon_vqrshifts: 4344 case Intrinsic::arm_neon_vqrshiftu: 4345 // No immediate versions of these to check for. 4346 break; 4347 } 4348 4349 return SDValue(); 4350} 4351 4352/// PerformShiftCombine - Checks for immediate versions of vector shifts and 4353/// lowers them. As with the vector shift intrinsics, this is done during DAG 4354/// combining instead of DAG legalizing because the build_vectors for 64-bit 4355/// vector element shift counts are generally not legal, and it is hard to see 4356/// their values after they get legalized to loads from a constant pool. 4357static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 4358 const ARMSubtarget *ST) { 4359 EVT VT = N->getValueType(0); 4360 4361 // Nothing to be done for scalar shifts. 4362 if (! VT.isVector()) 4363 return SDValue(); 4364 4365 assert(ST->hasNEON() && "unexpected vector shift"); 4366 int64_t Cnt; 4367 4368 switch (N->getOpcode()) { 4369 default: llvm_unreachable("unexpected shift opcode"); 4370 4371 case ISD::SHL: 4372 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 4373 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 4374 DAG.getConstant(Cnt, MVT::i32)); 4375 break; 4376 4377 case ISD::SRA: 4378 case ISD::SRL: 4379 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 4380 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 4381 ARMISD::VSHRs : ARMISD::VSHRu); 4382 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 4383 DAG.getConstant(Cnt, MVT::i32)); 4384 } 4385 } 4386 return SDValue(); 4387} 4388 4389/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 4390/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 4391static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 4392 const ARMSubtarget *ST) { 4393 SDValue N0 = N->getOperand(0); 4394 4395 // Check for sign- and zero-extensions of vector extract operations of 8- 4396 // and 16-bit vector elements. NEON supports these directly. They are 4397 // handled during DAG combining because type legalization will promote them 4398 // to 32-bit types and it is messy to recognize the operations after that. 4399 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 4400 SDValue Vec = N0.getOperand(0); 4401 SDValue Lane = N0.getOperand(1); 4402 EVT VT = N->getValueType(0); 4403 EVT EltVT = N0.getValueType(); 4404 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4405 4406 if (VT == MVT::i32 && 4407 (EltVT == MVT::i8 || EltVT == MVT::i16) && 4408 TLI.isTypeLegal(Vec.getValueType())) { 4409 4410 unsigned Opc = 0; 4411 switch (N->getOpcode()) { 4412 default: llvm_unreachable("unexpected opcode"); 4413 case ISD::SIGN_EXTEND: 4414 Opc = ARMISD::VGETLANEs; 4415 break; 4416 case ISD::ZERO_EXTEND: 4417 case ISD::ANY_EXTEND: 4418 Opc = ARMISD::VGETLANEu; 4419 break; 4420 } 4421 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 4422 } 4423 } 4424 4425 return SDValue(); 4426} 4427 4428/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 4429/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 4430static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 4431 const ARMSubtarget *ST) { 4432 // If the target supports NEON, try to use vmax/vmin instructions for f32 4433 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set, 4434 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 4435 // a NaN; only do the transformation when it matches that behavior. 4436 4437 // For now only do this when using NEON for FP operations; if using VFP, it 4438 // is not obvious that the benefit outweighs the cost of switching to the 4439 // NEON pipeline. 4440 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 4441 N->getValueType(0) != MVT::f32) 4442 return SDValue(); 4443 4444 SDValue CondLHS = N->getOperand(0); 4445 SDValue CondRHS = N->getOperand(1); 4446 SDValue LHS = N->getOperand(2); 4447 SDValue RHS = N->getOperand(3); 4448 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 4449 4450 unsigned Opcode = 0; 4451 bool IsReversed; 4452 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 4453 IsReversed = false; // x CC y ? x : y 4454 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 4455 IsReversed = true ; // x CC y ? y : x 4456 } else { 4457 return SDValue(); 4458 } 4459 4460 bool IsUnordered; 4461 switch (CC) { 4462 default: break; 4463 case ISD::SETOLT: 4464 case ISD::SETOLE: 4465 case ISD::SETLT: 4466 case ISD::SETLE: 4467 case ISD::SETULT: 4468 case ISD::SETULE: 4469 // If LHS is NaN, an ordered comparison will be false and the result will 4470 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 4471 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4472 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 4473 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4474 break; 4475 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 4476 // will return -0, so vmin can only be used for unsafe math or if one of 4477 // the operands is known to be nonzero. 4478 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 4479 !UnsafeFPMath && 4480 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4481 break; 4482 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 4483 break; 4484 4485 case ISD::SETOGT: 4486 case ISD::SETOGE: 4487 case ISD::SETGT: 4488 case ISD::SETGE: 4489 case ISD::SETUGT: 4490 case ISD::SETUGE: 4491 // If LHS is NaN, an ordered comparison will be false and the result will 4492 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 4493 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4494 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 4495 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4496 break; 4497 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 4498 // will return +0, so vmax can only be used for unsafe math or if one of 4499 // the operands is known to be nonzero. 4500 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 4501 !UnsafeFPMath && 4502 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4503 break; 4504 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 4505 break; 4506 } 4507 4508 if (!Opcode) 4509 return SDValue(); 4510 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 4511} 4512 4513SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 4514 DAGCombinerInfo &DCI) const { 4515 switch (N->getOpcode()) { 4516 default: break; 4517 case ISD::ADD: return PerformADDCombine(N, DCI); 4518 case ISD::SUB: return PerformSUBCombine(N, DCI); 4519 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 4520 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 4521 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 4522 case ISD::SHL: 4523 case ISD::SRA: 4524 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 4525 case ISD::SIGN_EXTEND: 4526 case ISD::ZERO_EXTEND: 4527 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 4528 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 4529 } 4530 return SDValue(); 4531} 4532 4533bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 4534 if (!Subtarget->hasV6Ops()) 4535 // Pre-v6 does not support unaligned mem access. 4536 return false; 4537 4538 // v6+ may or may not support unaligned mem access depending on the system 4539 // configuration. 4540 // FIXME: This is pretty conservative. Should we provide cmdline option to 4541 // control the behaviour? 4542 if (!Subtarget->isTargetDarwin()) 4543 return false; 4544 4545 switch (VT.getSimpleVT().SimpleTy) { 4546 default: 4547 return false; 4548 case MVT::i8: 4549 case MVT::i16: 4550 case MVT::i32: 4551 return true; 4552 // FIXME: VLD1 etc with standard alignment is legal. 4553 } 4554} 4555 4556static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 4557 if (V < 0) 4558 return false; 4559 4560 unsigned Scale = 1; 4561 switch (VT.getSimpleVT().SimpleTy) { 4562 default: return false; 4563 case MVT::i1: 4564 case MVT::i8: 4565 // Scale == 1; 4566 break; 4567 case MVT::i16: 4568 // Scale == 2; 4569 Scale = 2; 4570 break; 4571 case MVT::i32: 4572 // Scale == 4; 4573 Scale = 4; 4574 break; 4575 } 4576 4577 if ((V & (Scale - 1)) != 0) 4578 return false; 4579 V /= Scale; 4580 return V == (V & ((1LL << 5) - 1)); 4581} 4582 4583static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 4584 const ARMSubtarget *Subtarget) { 4585 bool isNeg = false; 4586 if (V < 0) { 4587 isNeg = true; 4588 V = - V; 4589 } 4590 4591 switch (VT.getSimpleVT().SimpleTy) { 4592 default: return false; 4593 case MVT::i1: 4594 case MVT::i8: 4595 case MVT::i16: 4596 case MVT::i32: 4597 // + imm12 or - imm8 4598 if (isNeg) 4599 return V == (V & ((1LL << 8) - 1)); 4600 return V == (V & ((1LL << 12) - 1)); 4601 case MVT::f32: 4602 case MVT::f64: 4603 // Same as ARM mode. FIXME: NEON? 4604 if (!Subtarget->hasVFP2()) 4605 return false; 4606 if ((V & 3) != 0) 4607 return false; 4608 V >>= 2; 4609 return V == (V & ((1LL << 8) - 1)); 4610 } 4611} 4612 4613/// isLegalAddressImmediate - Return true if the integer value can be used 4614/// as the offset of the target addressing mode for load / store of the 4615/// given type. 4616static bool isLegalAddressImmediate(int64_t V, EVT VT, 4617 const ARMSubtarget *Subtarget) { 4618 if (V == 0) 4619 return true; 4620 4621 if (!VT.isSimple()) 4622 return false; 4623 4624 if (Subtarget->isThumb1Only()) 4625 return isLegalT1AddressImmediate(V, VT); 4626 else if (Subtarget->isThumb2()) 4627 return isLegalT2AddressImmediate(V, VT, Subtarget); 4628 4629 // ARM mode. 4630 if (V < 0) 4631 V = - V; 4632 switch (VT.getSimpleVT().SimpleTy) { 4633 default: return false; 4634 case MVT::i1: 4635 case MVT::i8: 4636 case MVT::i32: 4637 // +- imm12 4638 return V == (V & ((1LL << 12) - 1)); 4639 case MVT::i16: 4640 // +- imm8 4641 return V == (V & ((1LL << 8) - 1)); 4642 case MVT::f32: 4643 case MVT::f64: 4644 if (!Subtarget->hasVFP2()) // FIXME: NEON? 4645 return false; 4646 if ((V & 3) != 0) 4647 return false; 4648 V >>= 2; 4649 return V == (V & ((1LL << 8) - 1)); 4650 } 4651} 4652 4653bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 4654 EVT VT) const { 4655 int Scale = AM.Scale; 4656 if (Scale < 0) 4657 return false; 4658 4659 switch (VT.getSimpleVT().SimpleTy) { 4660 default: return false; 4661 case MVT::i1: 4662 case MVT::i8: 4663 case MVT::i16: 4664 case MVT::i32: 4665 if (Scale == 1) 4666 return true; 4667 // r + r << imm 4668 Scale = Scale & ~1; 4669 return Scale == 2 || Scale == 4 || Scale == 8; 4670 case MVT::i64: 4671 // r + r 4672 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 4673 return true; 4674 return false; 4675 case MVT::isVoid: 4676 // Note, we allow "void" uses (basically, uses that aren't loads or 4677 // stores), because arm allows folding a scale into many arithmetic 4678 // operations. This should be made more precise and revisited later. 4679 4680 // Allow r << imm, but the imm has to be a multiple of two. 4681 if (Scale & 1) return false; 4682 return isPowerOf2_32(Scale); 4683 } 4684} 4685 4686/// isLegalAddressingMode - Return true if the addressing mode represented 4687/// by AM is legal for this target, for a load/store of the specified type. 4688bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 4689 const Type *Ty) const { 4690 EVT VT = getValueType(Ty, true); 4691 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 4692 return false; 4693 4694 // Can never fold addr of global into load/store. 4695 if (AM.BaseGV) 4696 return false; 4697 4698 switch (AM.Scale) { 4699 case 0: // no scale reg, must be "r+i" or "r", or "i". 4700 break; 4701 case 1: 4702 if (Subtarget->isThumb1Only()) 4703 return false; 4704 // FALL THROUGH. 4705 default: 4706 // ARM doesn't support any R+R*scale+imm addr modes. 4707 if (AM.BaseOffs) 4708 return false; 4709 4710 if (!VT.isSimple()) 4711 return false; 4712 4713 if (Subtarget->isThumb2()) 4714 return isLegalT2ScaledAddressingMode(AM, VT); 4715 4716 int Scale = AM.Scale; 4717 switch (VT.getSimpleVT().SimpleTy) { 4718 default: return false; 4719 case MVT::i1: 4720 case MVT::i8: 4721 case MVT::i32: 4722 if (Scale < 0) Scale = -Scale; 4723 if (Scale == 1) 4724 return true; 4725 // r + r << imm 4726 return isPowerOf2_32(Scale & ~1); 4727 case MVT::i16: 4728 case MVT::i64: 4729 // r + r 4730 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 4731 return true; 4732 return false; 4733 4734 case MVT::isVoid: 4735 // Note, we allow "void" uses (basically, uses that aren't loads or 4736 // stores), because arm allows folding a scale into many arithmetic 4737 // operations. This should be made more precise and revisited later. 4738 4739 // Allow r << imm, but the imm has to be a multiple of two. 4740 if (Scale & 1) return false; 4741 return isPowerOf2_32(Scale); 4742 } 4743 break; 4744 } 4745 return true; 4746} 4747 4748/// isLegalICmpImmediate - Return true if the specified immediate is legal 4749/// icmp immediate, that is the target has icmp instructions which can compare 4750/// a register against the immediate without having to materialize the 4751/// immediate into a register. 4752bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 4753 if (!Subtarget->isThumb()) 4754 return ARM_AM::getSOImmVal(Imm) != -1; 4755 if (Subtarget->isThumb2()) 4756 return ARM_AM::getT2SOImmVal(Imm) != -1; 4757 return Imm >= 0 && Imm <= 255; 4758} 4759 4760static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 4761 bool isSEXTLoad, SDValue &Base, 4762 SDValue &Offset, bool &isInc, 4763 SelectionDAG &DAG) { 4764 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 4765 return false; 4766 4767 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 4768 // AddressingMode 3 4769 Base = Ptr->getOperand(0); 4770 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4771 int RHSC = (int)RHS->getZExtValue(); 4772 if (RHSC < 0 && RHSC > -256) { 4773 assert(Ptr->getOpcode() == ISD::ADD); 4774 isInc = false; 4775 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4776 return true; 4777 } 4778 } 4779 isInc = (Ptr->getOpcode() == ISD::ADD); 4780 Offset = Ptr->getOperand(1); 4781 return true; 4782 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 4783 // AddressingMode 2 4784 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4785 int RHSC = (int)RHS->getZExtValue(); 4786 if (RHSC < 0 && RHSC > -0x1000) { 4787 assert(Ptr->getOpcode() == ISD::ADD); 4788 isInc = false; 4789 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4790 Base = Ptr->getOperand(0); 4791 return true; 4792 } 4793 } 4794 4795 if (Ptr->getOpcode() == ISD::ADD) { 4796 isInc = true; 4797 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 4798 if (ShOpcVal != ARM_AM::no_shift) { 4799 Base = Ptr->getOperand(1); 4800 Offset = Ptr->getOperand(0); 4801 } else { 4802 Base = Ptr->getOperand(0); 4803 Offset = Ptr->getOperand(1); 4804 } 4805 return true; 4806 } 4807 4808 isInc = (Ptr->getOpcode() == ISD::ADD); 4809 Base = Ptr->getOperand(0); 4810 Offset = Ptr->getOperand(1); 4811 return true; 4812 } 4813 4814 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 4815 return false; 4816} 4817 4818static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 4819 bool isSEXTLoad, SDValue &Base, 4820 SDValue &Offset, bool &isInc, 4821 SelectionDAG &DAG) { 4822 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 4823 return false; 4824 4825 Base = Ptr->getOperand(0); 4826 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 4827 int RHSC = (int)RHS->getZExtValue(); 4828 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 4829 assert(Ptr->getOpcode() == ISD::ADD); 4830 isInc = false; 4831 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 4832 return true; 4833 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 4834 isInc = Ptr->getOpcode() == ISD::ADD; 4835 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 4836 return true; 4837 } 4838 } 4839 4840 return false; 4841} 4842 4843/// getPreIndexedAddressParts - returns true by value, base pointer and 4844/// offset pointer and addressing mode by reference if the node's address 4845/// can be legally represented as pre-indexed load / store address. 4846bool 4847ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 4848 SDValue &Offset, 4849 ISD::MemIndexedMode &AM, 4850 SelectionDAG &DAG) const { 4851 if (Subtarget->isThumb1Only()) 4852 return false; 4853 4854 EVT VT; 4855 SDValue Ptr; 4856 bool isSEXTLoad = false; 4857 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4858 Ptr = LD->getBasePtr(); 4859 VT = LD->getMemoryVT(); 4860 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 4861 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4862 Ptr = ST->getBasePtr(); 4863 VT = ST->getMemoryVT(); 4864 } else 4865 return false; 4866 4867 bool isInc; 4868 bool isLegal = false; 4869 if (Subtarget->isThumb2()) 4870 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 4871 Offset, isInc, DAG); 4872 else 4873 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 4874 Offset, isInc, DAG); 4875 if (!isLegal) 4876 return false; 4877 4878 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 4879 return true; 4880} 4881 4882/// getPostIndexedAddressParts - returns true by value, base pointer and 4883/// offset pointer and addressing mode by reference if this node can be 4884/// combined with a load / store to form a post-indexed load / store. 4885bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 4886 SDValue &Base, 4887 SDValue &Offset, 4888 ISD::MemIndexedMode &AM, 4889 SelectionDAG &DAG) const { 4890 if (Subtarget->isThumb1Only()) 4891 return false; 4892 4893 EVT VT; 4894 SDValue Ptr; 4895 bool isSEXTLoad = false; 4896 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4897 VT = LD->getMemoryVT(); 4898 Ptr = LD->getBasePtr(); 4899 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 4900 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4901 VT = ST->getMemoryVT(); 4902 Ptr = ST->getBasePtr(); 4903 } else 4904 return false; 4905 4906 bool isInc; 4907 bool isLegal = false; 4908 if (Subtarget->isThumb2()) 4909 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 4910 isInc, DAG); 4911 else 4912 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 4913 isInc, DAG); 4914 if (!isLegal) 4915 return false; 4916 4917 if (Ptr != Base) { 4918 // Swap base ptr and offset to catch more post-index load / store when 4919 // it's legal. In Thumb2 mode, offset must be an immediate. 4920 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 4921 !Subtarget->isThumb2()) 4922 std::swap(Base, Offset); 4923 4924 // Post-indexed load / store update the base pointer. 4925 if (Ptr != Base) 4926 return false; 4927 } 4928 4929 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 4930 return true; 4931} 4932 4933void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 4934 const APInt &Mask, 4935 APInt &KnownZero, 4936 APInt &KnownOne, 4937 const SelectionDAG &DAG, 4938 unsigned Depth) const { 4939 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 4940 switch (Op.getOpcode()) { 4941 default: break; 4942 case ARMISD::CMOV: { 4943 // Bits are known zero/one if known on the LHS and RHS. 4944 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 4945 if (KnownZero == 0 && KnownOne == 0) return; 4946 4947 APInt KnownZeroRHS, KnownOneRHS; 4948 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 4949 KnownZeroRHS, KnownOneRHS, Depth+1); 4950 KnownZero &= KnownZeroRHS; 4951 KnownOne &= KnownOneRHS; 4952 return; 4953 } 4954 } 4955} 4956 4957//===----------------------------------------------------------------------===// 4958// ARM Inline Assembly Support 4959//===----------------------------------------------------------------------===// 4960 4961/// getConstraintType - Given a constraint letter, return the type of 4962/// constraint it is for this target. 4963ARMTargetLowering::ConstraintType 4964ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 4965 if (Constraint.size() == 1) { 4966 switch (Constraint[0]) { 4967 default: break; 4968 case 'l': return C_RegisterClass; 4969 case 'w': return C_RegisterClass; 4970 } 4971 } 4972 return TargetLowering::getConstraintType(Constraint); 4973} 4974 4975std::pair<unsigned, const TargetRegisterClass*> 4976ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 4977 EVT VT) const { 4978 if (Constraint.size() == 1) { 4979 // GCC ARM Constraint Letters 4980 switch (Constraint[0]) { 4981 case 'l': 4982 if (Subtarget->isThumb()) 4983 return std::make_pair(0U, ARM::tGPRRegisterClass); 4984 else 4985 return std::make_pair(0U, ARM::GPRRegisterClass); 4986 case 'r': 4987 return std::make_pair(0U, ARM::GPRRegisterClass); 4988 case 'w': 4989 if (VT == MVT::f32) 4990 return std::make_pair(0U, ARM::SPRRegisterClass); 4991 if (VT.getSizeInBits() == 64) 4992 return std::make_pair(0U, ARM::DPRRegisterClass); 4993 if (VT.getSizeInBits() == 128) 4994 return std::make_pair(0U, ARM::QPRRegisterClass); 4995 break; 4996 } 4997 } 4998 if (StringRef("{cc}").equals_lower(Constraint)) 4999 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 5000 5001 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5002} 5003 5004std::vector<unsigned> ARMTargetLowering:: 5005getRegClassForInlineAsmConstraint(const std::string &Constraint, 5006 EVT VT) const { 5007 if (Constraint.size() != 1) 5008 return std::vector<unsigned>(); 5009 5010 switch (Constraint[0]) { // GCC ARM Constraint Letters 5011 default: break; 5012 case 'l': 5013 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5014 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5015 0); 5016 case 'r': 5017 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5018 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5019 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 5020 ARM::R12, ARM::LR, 0); 5021 case 'w': 5022 if (VT == MVT::f32) 5023 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 5024 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 5025 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 5026 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 5027 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 5028 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 5029 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 5030 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 5031 if (VT.getSizeInBits() == 64) 5032 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 5033 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 5034 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 5035 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 5036 if (VT.getSizeInBits() == 128) 5037 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 5038 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0); 5039 break; 5040 } 5041 5042 return std::vector<unsigned>(); 5043} 5044 5045/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5046/// vector. If it is invalid, don't add anything to Ops. 5047void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5048 char Constraint, 5049 std::vector<SDValue>&Ops, 5050 SelectionDAG &DAG) const { 5051 SDValue Result(0, 0); 5052 5053 switch (Constraint) { 5054 default: break; 5055 case 'I': case 'J': case 'K': case 'L': 5056 case 'M': case 'N': case 'O': 5057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 5058 if (!C) 5059 return; 5060 5061 int64_t CVal64 = C->getSExtValue(); 5062 int CVal = (int) CVal64; 5063 // None of these constraints allow values larger than 32 bits. Check 5064 // that the value fits in an int. 5065 if (CVal != CVal64) 5066 return; 5067 5068 switch (Constraint) { 5069 case 'I': 5070 if (Subtarget->isThumb1Only()) { 5071 // This must be a constant between 0 and 255, for ADD 5072 // immediates. 5073 if (CVal >= 0 && CVal <= 255) 5074 break; 5075 } else if (Subtarget->isThumb2()) { 5076 // A constant that can be used as an immediate value in a 5077 // data-processing instruction. 5078 if (ARM_AM::getT2SOImmVal(CVal) != -1) 5079 break; 5080 } else { 5081 // A constant that can be used as an immediate value in a 5082 // data-processing instruction. 5083 if (ARM_AM::getSOImmVal(CVal) != -1) 5084 break; 5085 } 5086 return; 5087 5088 case 'J': 5089 if (Subtarget->isThumb()) { // FIXME thumb2 5090 // This must be a constant between -255 and -1, for negated ADD 5091 // immediates. This can be used in GCC with an "n" modifier that 5092 // prints the negated value, for use with SUB instructions. It is 5093 // not useful otherwise but is implemented for compatibility. 5094 if (CVal >= -255 && CVal <= -1) 5095 break; 5096 } else { 5097 // This must be a constant between -4095 and 4095. It is not clear 5098 // what this constraint is intended for. Implemented for 5099 // compatibility with GCC. 5100 if (CVal >= -4095 && CVal <= 4095) 5101 break; 5102 } 5103 return; 5104 5105 case 'K': 5106 if (Subtarget->isThumb1Only()) { 5107 // A 32-bit value where only one byte has a nonzero value. Exclude 5108 // zero to match GCC. This constraint is used by GCC internally for 5109 // constants that can be loaded with a move/shift combination. 5110 // It is not useful otherwise but is implemented for compatibility. 5111 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 5112 break; 5113 } else if (Subtarget->isThumb2()) { 5114 // A constant whose bitwise inverse can be used as an immediate 5115 // value in a data-processing instruction. This can be used in GCC 5116 // with a "B" modifier that prints the inverted value, for use with 5117 // BIC and MVN instructions. It is not useful otherwise but is 5118 // implemented for compatibility. 5119 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 5120 break; 5121 } else { 5122 // A constant whose bitwise inverse can be used as an immediate 5123 // value in a data-processing instruction. This can be used in GCC 5124 // with a "B" modifier that prints the inverted value, for use with 5125 // BIC and MVN instructions. It is not useful otherwise but is 5126 // implemented for compatibility. 5127 if (ARM_AM::getSOImmVal(~CVal) != -1) 5128 break; 5129 } 5130 return; 5131 5132 case 'L': 5133 if (Subtarget->isThumb1Only()) { 5134 // This must be a constant between -7 and 7, 5135 // for 3-operand ADD/SUB immediate instructions. 5136 if (CVal >= -7 && CVal < 7) 5137 break; 5138 } else if (Subtarget->isThumb2()) { 5139 // A constant whose negation can be used as an immediate value in a 5140 // data-processing instruction. This can be used in GCC with an "n" 5141 // modifier that prints the negated value, for use with SUB 5142 // instructions. It is not useful otherwise but is implemented for 5143 // compatibility. 5144 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 5145 break; 5146 } else { 5147 // A constant whose negation can be used as an immediate value in a 5148 // data-processing instruction. This can be used in GCC with an "n" 5149 // modifier that prints the negated value, for use with SUB 5150 // instructions. It is not useful otherwise but is implemented for 5151 // compatibility. 5152 if (ARM_AM::getSOImmVal(-CVal) != -1) 5153 break; 5154 } 5155 return; 5156 5157 case 'M': 5158 if (Subtarget->isThumb()) { // FIXME thumb2 5159 // This must be a multiple of 4 between 0 and 1020, for 5160 // ADD sp + immediate. 5161 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 5162 break; 5163 } else { 5164 // A power of two or a constant between 0 and 32. This is used in 5165 // GCC for the shift amount on shifted register operands, but it is 5166 // useful in general for any shift amounts. 5167 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 5168 break; 5169 } 5170 return; 5171 5172 case 'N': 5173 if (Subtarget->isThumb()) { // FIXME thumb2 5174 // This must be a constant between 0 and 31, for shift amounts. 5175 if (CVal >= 0 && CVal <= 31) 5176 break; 5177 } 5178 return; 5179 5180 case 'O': 5181 if (Subtarget->isThumb()) { // FIXME thumb2 5182 // This must be a multiple of 4 between -508 and 508, for 5183 // ADD/SUB sp = sp + immediate. 5184 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 5185 break; 5186 } 5187 return; 5188 } 5189 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 5190 break; 5191 } 5192 5193 if (Result.getNode()) { 5194 Ops.push_back(Result); 5195 return; 5196 } 5197 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5198} 5199 5200bool 5201ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5202 // The ARM target isn't yet aware of offsets. 5203 return false; 5204} 5205 5206int ARM::getVFPf32Imm(const APFloat &FPImm) { 5207 APInt Imm = FPImm.bitcastToAPInt(); 5208 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 5209 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 5210 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 5211 5212 // We can handle 4 bits of mantissa. 5213 // mantissa = (16+UInt(e:f:g:h))/16. 5214 if (Mantissa & 0x7ffff) 5215 return -1; 5216 Mantissa >>= 19; 5217 if ((Mantissa & 0xf) != Mantissa) 5218 return -1; 5219 5220 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5221 if (Exp < -3 || Exp > 4) 5222 return -1; 5223 Exp = ((Exp+3) & 0x7) ^ 4; 5224 5225 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5226} 5227 5228int ARM::getVFPf64Imm(const APFloat &FPImm) { 5229 APInt Imm = FPImm.bitcastToAPInt(); 5230 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 5231 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 5232 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL; 5233 5234 // We can handle 4 bits of mantissa. 5235 // mantissa = (16+UInt(e:f:g:h))/16. 5236 if (Mantissa & 0xffffffffffffLL) 5237 return -1; 5238 Mantissa >>= 48; 5239 if ((Mantissa & 0xf) != Mantissa) 5240 return -1; 5241 5242 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5243 if (Exp < -3 || Exp > 4) 5244 return -1; 5245 Exp = ((Exp+3) & 0x7) ^ 4; 5246 5247 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5248} 5249 5250/// isFPImmLegal - Returns true if the target can instruction select the 5251/// specified FP immediate natively. If false, the legalizer will 5252/// materialize the FP immediate as a load from a constant pool. 5253bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 5254 if (!Subtarget->hasVFP3()) 5255 return false; 5256 if (VT == MVT::f32) 5257 return ARM::getVFPf32Imm(Imm) != -1; 5258 if (VT == MVT::f64) 5259 return ARM::getVFPf64Imm(Imm) != -1; 5260 return false; 5261} 5262