ARMISelLowering.cpp revision ba36cb5242eb02b12b277f82b9efe497f7da4d7f
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/GlobalValue.h" 28#include "llvm/CodeGen/MachineBasicBlock.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/ADT/VectorExtras.h" 36#include "llvm/Support/MathExtras.h" 37using namespace llvm; 38 39ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 40 : TargetLowering(TM), ARMPCLabelIndex(0) { 41 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 42 43 if (Subtarget->isTargetDarwin()) { 44 // Don't have these. 45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 47 48 // Uses VFP for Thumb libfuncs if available. 49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 50 // Single-precision floating-point arithmetic. 51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 55 56 // Double-precision floating-point arithmetic. 57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 61 62 // Single-precision comparisons. 63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 71 72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 80 81 // Double-precision comparisons. 82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 90 91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 99 100 // Floating-point to integer conversions. 101 // i64 conversions are done via library routines even when generating VFP 102 // instructions, so use the same ones. 103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 107 108 // Conversions between floating types. 109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 111 112 // Integer to floating-point conversions. 113 // i64 conversions are done via library routines even when generating VFP 114 // instructions, so use the same ones. 115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 116 // __floatunsidf vs. __floatunssidfvfp. 117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 121 } 122 } 123 124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 128 129 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 130 } 131 computeRegisterProperties(); 132 133 // ARM does not have f32 extending load. 134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 135 136 // ARM does not have i1 sign extending load. 137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 138 139 // ARM supports all 4 flavors of integer indexed load / store. 140 for (unsigned im = (unsigned)ISD::PRE_INC; 141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 142 setIndexedLoadAction(im, MVT::i1, Legal); 143 setIndexedLoadAction(im, MVT::i8, Legal); 144 setIndexedLoadAction(im, MVT::i16, Legal); 145 setIndexedLoadAction(im, MVT::i32, Legal); 146 setIndexedStoreAction(im, MVT::i1, Legal); 147 setIndexedStoreAction(im, MVT::i8, Legal); 148 setIndexedStoreAction(im, MVT::i16, Legal); 149 setIndexedStoreAction(im, MVT::i32, Legal); 150 } 151 152 // i64 operation support. 153 if (Subtarget->isThumb()) { 154 setOperationAction(ISD::MUL, MVT::i64, Expand); 155 setOperationAction(ISD::MULHU, MVT::i32, Expand); 156 setOperationAction(ISD::MULHS, MVT::i32, Expand); 157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 159 } else { 160 setOperationAction(ISD::MUL, MVT::i64, Expand); 161 setOperationAction(ISD::MULHU, MVT::i32, Expand); 162 if (!Subtarget->hasV6Ops()) 163 setOperationAction(ISD::MULHS, MVT::i32, Expand); 164 } 165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::SRL, MVT::i64, Custom); 169 setOperationAction(ISD::SRA, MVT::i64, Custom); 170 171 // ARM does not have ROTL. 172 setOperationAction(ISD::ROTL, MVT::i32, Expand); 173 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 174 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 176 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 177 178 // Only ARMv6 has BSWAP. 179 if (!Subtarget->hasV6Ops()) 180 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 181 182 // These are expanded into libcalls. 183 setOperationAction(ISD::SDIV, MVT::i32, Expand); 184 setOperationAction(ISD::UDIV, MVT::i32, Expand); 185 setOperationAction(ISD::SREM, MVT::i32, Expand); 186 setOperationAction(ISD::UREM, MVT::i32, Expand); 187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 189 190 // Support label based line numbers. 191 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 193 194 setOperationAction(ISD::RET, MVT::Other, Custom); 195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 200 // Use the default implementation. 201 setOperationAction(ISD::VASTART , MVT::Other, Custom); 202 setOperationAction(ISD::VAARG , MVT::Other, Expand); 203 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 204 setOperationAction(ISD::VAEND , MVT::Other, Expand); 205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 208 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 209 210 if (!Subtarget->hasV6Ops()) { 211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 213 } 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 215 216 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 217 // Turn f64->i64 into FMRRD iff target supports vfp2. 218 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 219 220 // We want to custom lower some of our intrinsics. 221 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 222 223 setOperationAction(ISD::SETCC , MVT::i32, Expand); 224 setOperationAction(ISD::SETCC , MVT::f32, Expand); 225 setOperationAction(ISD::SETCC , MVT::f64, Expand); 226 setOperationAction(ISD::SELECT , MVT::i32, Expand); 227 setOperationAction(ISD::SELECT , MVT::f32, Expand); 228 setOperationAction(ISD::SELECT , MVT::f64, Expand); 229 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 230 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 231 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 232 233 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 234 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 235 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 236 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 237 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 238 239 // We don't support sin/cos/fmod/copysign/pow 240 setOperationAction(ISD::FSIN , MVT::f64, Expand); 241 setOperationAction(ISD::FSIN , MVT::f32, Expand); 242 setOperationAction(ISD::FCOS , MVT::f32, Expand); 243 setOperationAction(ISD::FCOS , MVT::f64, Expand); 244 setOperationAction(ISD::FREM , MVT::f64, Expand); 245 setOperationAction(ISD::FREM , MVT::f32, Expand); 246 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 247 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 248 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 249 } 250 setOperationAction(ISD::FPOW , MVT::f64, Expand); 251 setOperationAction(ISD::FPOW , MVT::f32, Expand); 252 253 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 254 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 256 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 259 } 260 261 // We have target-specific dag combine patterns for the following nodes: 262 // ARMISD::FMRRD - No need to call setTargetDAGCombine 263 264 setStackPointerRegisterToSaveRestore(ARM::SP); 265 setSchedulingPreference(SchedulingForRegPressure); 266 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 267 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 268 269 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 270} 271 272 273const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 274 switch (Opcode) { 275 default: return 0; 276 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 277 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 278 case ARMISD::CALL: return "ARMISD::CALL"; 279 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 280 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 281 case ARMISD::tCALL: return "ARMISD::tCALL"; 282 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 283 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 284 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 285 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 286 case ARMISD::CMP: return "ARMISD::CMP"; 287 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 288 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 289 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 290 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 291 case ARMISD::CMOV: return "ARMISD::CMOV"; 292 case ARMISD::CNEG: return "ARMISD::CNEG"; 293 294 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 295 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 296 case ARMISD::SITOF: return "ARMISD::SITOF"; 297 case ARMISD::UITOF: return "ARMISD::UITOF"; 298 299 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 300 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 301 case ARMISD::RRX: return "ARMISD::RRX"; 302 303 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 304 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 305 306 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 307 } 308} 309 310//===----------------------------------------------------------------------===// 311// Lowering Code 312//===----------------------------------------------------------------------===// 313 314 315/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 316static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 317 switch (CC) { 318 default: assert(0 && "Unknown condition code!"); 319 case ISD::SETNE: return ARMCC::NE; 320 case ISD::SETEQ: return ARMCC::EQ; 321 case ISD::SETGT: return ARMCC::GT; 322 case ISD::SETGE: return ARMCC::GE; 323 case ISD::SETLT: return ARMCC::LT; 324 case ISD::SETLE: return ARMCC::LE; 325 case ISD::SETUGT: return ARMCC::HI; 326 case ISD::SETUGE: return ARMCC::HS; 327 case ISD::SETULT: return ARMCC::LO; 328 case ISD::SETULE: return ARMCC::LS; 329 } 330} 331 332/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 333/// returns true if the operands should be inverted to form the proper 334/// comparison. 335static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 336 ARMCC::CondCodes &CondCode2) { 337 bool Invert = false; 338 CondCode2 = ARMCC::AL; 339 switch (CC) { 340 default: assert(0 && "Unknown FP condition!"); 341 case ISD::SETEQ: 342 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 343 case ISD::SETGT: 344 case ISD::SETOGT: CondCode = ARMCC::GT; break; 345 case ISD::SETGE: 346 case ISD::SETOGE: CondCode = ARMCC::GE; break; 347 case ISD::SETOLT: CondCode = ARMCC::MI; break; 348 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 349 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 350 case ISD::SETO: CondCode = ARMCC::VC; break; 351 case ISD::SETUO: CondCode = ARMCC::VS; break; 352 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 353 case ISD::SETUGT: CondCode = ARMCC::HI; break; 354 case ISD::SETUGE: CondCode = ARMCC::PL; break; 355 case ISD::SETLT: 356 case ISD::SETULT: CondCode = ARMCC::LT; break; 357 case ISD::SETLE: 358 case ISD::SETULE: CondCode = ARMCC::LE; break; 359 case ISD::SETNE: 360 case ISD::SETUNE: CondCode = ARMCC::NE; break; 361 } 362 return Invert; 363} 364 365static void 366HowToPassArgument(MVT ObjectVT, unsigned NumGPRs, 367 unsigned StackOffset, unsigned &NeededGPRs, 368 unsigned &NeededStackSize, unsigned &GPRPad, 369 unsigned &StackPad, ISD::ArgFlagsTy Flags) { 370 NeededStackSize = 0; 371 NeededGPRs = 0; 372 StackPad = 0; 373 GPRPad = 0; 374 unsigned align = Flags.getOrigAlign(); 375 GPRPad = NumGPRs % ((align + 3)/4); 376 StackPad = StackOffset % align; 377 unsigned firstGPR = NumGPRs + GPRPad; 378 switch (ObjectVT.getSimpleVT()) { 379 default: assert(0 && "Unhandled argument type!"); 380 case MVT::i32: 381 case MVT::f32: 382 if (firstGPR < 4) 383 NeededGPRs = 1; 384 else 385 NeededStackSize = 4; 386 break; 387 case MVT::i64: 388 case MVT::f64: 389 if (firstGPR < 3) 390 NeededGPRs = 2; 391 else if (firstGPR == 3) { 392 NeededGPRs = 1; 393 NeededStackSize = 4; 394 } else 395 NeededStackSize = 8; 396 } 397} 398 399/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 400/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 401/// nodes. 402SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 403 MVT RetVT= Op.getNode()->getValueType(0); 404 SDValue Chain = Op.getOperand(0); 405 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 406 assert((CallConv == CallingConv::C || 407 CallConv == CallingConv::Fast) && "unknown calling convention"); 408 SDValue Callee = Op.getOperand(4); 409 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 410 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 411 unsigned NumGPRs = 0; // GPRs used for parameter passing. 412 413 // Count how many bytes are to be pushed on the stack. 414 unsigned NumBytes = 0; 415 416 // Add up all the space actually used. 417 for (unsigned i = 0; i < NumOps; ++i) { 418 unsigned ObjSize; 419 unsigned ObjGPRs; 420 unsigned StackPad; 421 unsigned GPRPad; 422 MVT ObjectVT = Op.getOperand(5+2*i).getValueType(); 423 ISD::ArgFlagsTy Flags = 424 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); 425 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 426 GPRPad, StackPad, Flags); 427 NumBytes += ObjSize + StackPad; 428 NumGPRs += ObjGPRs + GPRPad; 429 } 430 431 // Adjust the stack pointer for the new arguments... 432 // These operations are automatically eliminated by the prolog/epilog pass 433 Chain = DAG.getCALLSEQ_START(Chain, 434 DAG.getConstant(NumBytes, MVT::i32)); 435 436 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 437 438 static const unsigned GPRArgRegs[] = { 439 ARM::R0, ARM::R1, ARM::R2, ARM::R3 440 }; 441 442 NumGPRs = 0; 443 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 444 std::vector<SDValue> MemOpChains; 445 for (unsigned i = 0; i != NumOps; ++i) { 446 SDValue Arg = Op.getOperand(5+2*i); 447 ISD::ArgFlagsTy Flags = 448 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); 449 MVT ArgVT = Arg.getValueType(); 450 451 unsigned ObjSize; 452 unsigned ObjGPRs; 453 unsigned GPRPad; 454 unsigned StackPad; 455 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 456 ObjSize, GPRPad, StackPad, Flags); 457 NumGPRs += GPRPad; 458 ArgOffset += StackPad; 459 if (ObjGPRs > 0) { 460 switch (ArgVT.getSimpleVT()) { 461 default: assert(0 && "Unexpected ValueType for argument!"); 462 case MVT::i32: 463 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 464 break; 465 case MVT::f32: 466 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 467 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 468 break; 469 case MVT::i64: { 470 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 471 DAG.getConstant(0, getPointerTy())); 472 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 473 DAG.getConstant(1, getPointerTy())); 474 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 475 if (ObjGPRs == 2) 476 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 477 else { 478 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 479 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 480 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 481 } 482 break; 483 } 484 case MVT::f64: { 485 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, 486 DAG.getVTList(MVT::i32, MVT::i32), 487 &Arg, 1); 488 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 489 if (ObjGPRs == 2) 490 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 491 Cvt.getValue(1))); 492 else { 493 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 494 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 495 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 496 NULL, 0)); 497 } 498 break; 499 } 500 } 501 } else { 502 assert(ObjSize != 0); 503 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 504 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 505 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 506 } 507 508 NumGPRs += ObjGPRs; 509 ArgOffset += ObjSize; 510 } 511 512 if (!MemOpChains.empty()) 513 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 514 &MemOpChains[0], MemOpChains.size()); 515 516 // Build a sequence of copy-to-reg nodes chained together with token chain 517 // and flag operands which copy the outgoing args into the appropriate regs. 518 SDValue InFlag; 519 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 520 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 521 InFlag); 522 InFlag = Chain.getValue(1); 523 } 524 525 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 526 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 527 // node so that legalize doesn't hack it. 528 bool isDirect = false; 529 bool isARMFunc = false; 530 bool isLocalARMFunc = false; 531 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 532 GlobalValue *GV = G->getGlobal(); 533 isDirect = true; 534 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 535 GV->hasLinkOnceLinkage()); 536 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 537 getTargetMachine().getRelocationModel() != Reloc::Static; 538 isARMFunc = !Subtarget->isThumb() || isStub; 539 // ARM call to a local ARM function is predicable. 540 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 541 // tBX takes a register source operand. 542 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 543 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 544 ARMCP::CPStub, 4); 545 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 546 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 547 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 548 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 549 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 550 } else 551 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 552 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 553 isDirect = true; 554 bool isStub = Subtarget->isTargetDarwin() && 555 getTargetMachine().getRelocationModel() != Reloc::Static; 556 isARMFunc = !Subtarget->isThumb() || isStub; 557 // tBX takes a register source operand. 558 const char *Sym = S->getSymbol(); 559 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 560 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 561 ARMCP::CPStub, 4); 562 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 563 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 564 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 565 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 566 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 567 } else 568 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 569 } 570 571 // FIXME: handle tail calls differently. 572 unsigned CallOpc; 573 if (Subtarget->isThumb()) { 574 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 575 CallOpc = ARMISD::CALL_NOLINK; 576 else 577 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 578 } else { 579 CallOpc = (isDirect || Subtarget->hasV5TOps()) 580 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 581 : ARMISD::CALL_NOLINK; 582 } 583 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 584 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 585 Chain = DAG.getCopyToReg(Chain, ARM::LR, 586 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 587 InFlag = Chain.getValue(1); 588 } 589 590 std::vector<SDValue> Ops; 591 Ops.push_back(Chain); 592 Ops.push_back(Callee); 593 594 // Add argument registers to the end of the list so that they are known live 595 // into the call. 596 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 597 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 598 RegsToPass[i].second.getValueType())); 599 600 if (InFlag.getNode()) 601 Ops.push_back(InFlag); 602 // Returns a chain and a flag for retval copy to use. 603 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), 604 &Ops[0], Ops.size()); 605 InFlag = Chain.getValue(1); 606 607 Chain = DAG.getCALLSEQ_END(Chain, 608 DAG.getConstant(NumBytes, MVT::i32), 609 DAG.getConstant(0, MVT::i32), 610 InFlag); 611 if (RetVT != MVT::Other) 612 InFlag = Chain.getValue(1); 613 614 std::vector<SDValue> ResultVals; 615 616 // If the call has results, copy the values out of the ret val registers. 617 switch (RetVT.getSimpleVT()) { 618 default: assert(0 && "Unexpected ret value!"); 619 case MVT::Other: 620 break; 621 case MVT::i32: 622 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 623 ResultVals.push_back(Chain.getValue(0)); 624 if (Op.getNode()->getValueType(1) == MVT::i32) { 625 // Returns a i64 value. 626 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 627 Chain.getValue(2)).getValue(1); 628 ResultVals.push_back(Chain.getValue(0)); 629 } 630 break; 631 case MVT::f32: 632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 633 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 634 Chain.getValue(0))); 635 break; 636 case MVT::f64: { 637 SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 638 SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 639 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 640 break; 641 } 642 } 643 644 if (ResultVals.empty()) 645 return Chain; 646 647 ResultVals.push_back(Chain); 648 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); 649 return Res.getValue(Op.getResNo()); 650} 651 652static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { 653 SDValue Copy; 654 SDValue Chain = Op.getOperand(0); 655 switch(Op.getNumOperands()) { 656 default: 657 assert(0 && "Do not know how to return this many arguments!"); 658 abort(); 659 case 1: { 660 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); 661 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 662 } 663 case 3: 664 Op = Op.getOperand(1); 665 if (Op.getValueType() == MVT::f32) { 666 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 667 } else if (Op.getValueType() == MVT::f64) { 668 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 669 // available. 670 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); 671 SDValue Sign = DAG.getConstant(0, MVT::i32); 672 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 673 Op.getValue(1), Sign); 674 } 675 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); 676 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) 677 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 678 break; 679 case 5: 680 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); 681 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 682 // If we haven't noted the R0+R1 are live out, do so now. 683 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 684 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 685 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 686 } 687 break; 688 case 9: // i128 -> 4 regs 689 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); 690 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); 691 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); 692 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); 693 // If we haven't noted the R0+R1 are live out, do so now. 694 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 696 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 697 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2); 698 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3); 699 } 700 break; 701 702 } 703 704 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 705 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 706} 707 708// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 709// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 710// one of the above mentioned nodes. It has to be wrapped because otherwise 711// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 712// be used to form addressing mode. These wrapped nodes will be selected 713// into MOVi. 714static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 715 MVT PtrVT = Op.getValueType(); 716 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 717 SDValue Res; 718 if (CP->isMachineConstantPoolEntry()) 719 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 720 CP->getAlignment()); 721 else 722 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 723 CP->getAlignment()); 724 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 725} 726 727// Lower ISD::GlobalTLSAddress using the "general dynamic" model 728SDValue 729ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 730 SelectionDAG &DAG) { 731 MVT PtrVT = getPointerTy(); 732 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 733 ARMConstantPoolValue *CPV = 734 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 735 PCAdj, "tlsgd", true); 736 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 737 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 738 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 739 SDValue Chain = Argument.getValue(1); 740 741 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 742 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 743 744 // call __tls_get_addr. 745 ArgListTy Args; 746 ArgListEntry Entry; 747 Entry.Node = Argument; 748 Entry.Ty = (const Type *) Type::Int32Ty; 749 Args.push_back(Entry); 750 std::pair<SDValue, SDValue> CallResult = 751 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, 752 CallingConv::C, false, 753 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 754 return CallResult.first; 755} 756 757// Lower ISD::GlobalTLSAddress using the "initial exec" or 758// "local exec" model. 759SDValue 760ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 761 SelectionDAG &DAG) { 762 GlobalValue *GV = GA->getGlobal(); 763 SDValue Offset; 764 SDValue Chain = DAG.getEntryNode(); 765 MVT PtrVT = getPointerTy(); 766 // Get the Thread Pointer 767 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 768 769 if (GV->isDeclaration()){ 770 // initial exec model 771 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 772 ARMConstantPoolValue *CPV = 773 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 774 PCAdj, "gottpoff", true); 775 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 776 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 777 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 778 Chain = Offset.getValue(1); 779 780 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 781 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 782 783 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 784 } else { 785 // local exec model 786 ARMConstantPoolValue *CPV = 787 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 788 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 789 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 790 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 791 } 792 793 // The address of the thread local variable is the add of the thread 794 // pointer with the offset of the variable. 795 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 796} 797 798SDValue 799ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 800 // TODO: implement the "local dynamic" model 801 assert(Subtarget->isTargetELF() && 802 "TLS not implemented for non-ELF targets"); 803 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 804 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 805 // otherwise use the "Local Exec" TLS Model 806 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 807 return LowerToTLSGeneralDynamicModel(GA, DAG); 808 else 809 return LowerToTLSExecModels(GA, DAG); 810} 811 812SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 813 SelectionDAG &DAG) { 814 MVT PtrVT = getPointerTy(); 815 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 816 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 817 if (RelocM == Reloc::PIC_) { 818 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 819 ARMConstantPoolValue *CPV = 820 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 821 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 822 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 823 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 824 SDValue Chain = Result.getValue(1); 825 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 826 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 827 if (!UseGOTOFF) 828 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 829 return Result; 830 } else { 831 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 832 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 833 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 834 } 835} 836 837/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 838/// even in non-static mode. 839static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 840 return RelocM != Reloc::Static && 841 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 842 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 843} 844 845SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 846 SelectionDAG &DAG) { 847 MVT PtrVT = getPointerTy(); 848 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 849 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 850 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 851 SDValue CPAddr; 852 if (RelocM == Reloc::Static) 853 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 854 else { 855 unsigned PCAdj = (RelocM != Reloc::PIC_) 856 ? 0 : (Subtarget->isThumb() ? 4 : 8); 857 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 858 : ARMCP::CPValue; 859 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 860 Kind, PCAdj); 861 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 862 } 863 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 864 865 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 866 SDValue Chain = Result.getValue(1); 867 868 if (RelocM == Reloc::PIC_) { 869 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 870 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 871 } 872 if (IsIndirect) 873 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 874 875 return Result; 876} 877 878SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 879 SelectionDAG &DAG){ 880 assert(Subtarget->isTargetELF() && 881 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 882 MVT PtrVT = getPointerTy(); 883 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 884 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 885 ARMPCLabelIndex, 886 ARMCP::CPValue, PCAdj); 887 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 888 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 889 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 890 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 891 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 892} 893 894static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 895 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 896 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 897 switch (IntNo) { 898 default: return SDValue(); // Don't custom lower most intrinsics. 899 case Intrinsic::arm_thread_pointer: 900 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 901 } 902} 903 904static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 905 unsigned VarArgsFrameIndex) { 906 // vastart just stores the address of the VarArgsFrameIndex slot into the 907 // memory location argument. 908 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 909 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 910 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 911 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 912} 913 914static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, 915 unsigned ArgNo, unsigned &NumGPRs, 916 unsigned &ArgOffset) { 917 MachineFunction &MF = DAG.getMachineFunction(); 918 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 919 SDValue Root = Op.getOperand(0); 920 std::vector<SDValue> ArgValues; 921 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 922 923 static const unsigned GPRArgRegs[] = { 924 ARM::R0, ARM::R1, ARM::R2, ARM::R3 925 }; 926 927 unsigned ObjSize; 928 unsigned ObjGPRs; 929 unsigned GPRPad; 930 unsigned StackPad; 931 ISD::ArgFlagsTy Flags = 932 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags(); 933 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 934 ObjSize, GPRPad, StackPad, Flags); 935 NumGPRs += GPRPad; 936 ArgOffset += StackPad; 937 938 SDValue ArgValue; 939 if (ObjGPRs == 1) { 940 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 941 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 942 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 943 if (ObjectVT == MVT::f32) 944 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 945 } else if (ObjGPRs == 2) { 946 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 947 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 948 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 949 950 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 951 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 952 SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 953 954 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 955 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 956 } 957 NumGPRs += ObjGPRs; 958 959 if (ObjSize) { 960 MachineFrameInfo *MFI = MF.getFrameInfo(); 961 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 962 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 963 if (ObjGPRs == 0) 964 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 965 else { 966 SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 967 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 968 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 969 } 970 971 ArgOffset += ObjSize; // Move on to the next argument. 972 } 973 974 return ArgValue; 975} 976 977SDValue 978ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 979 std::vector<SDValue> ArgValues; 980 SDValue Root = Op.getOperand(0); 981 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 982 unsigned NumGPRs = 0; // GPRs used for parameter passing. 983 984 unsigned NumArgs = Op.getNode()->getNumValues()-1; 985 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 986 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, 987 NumGPRs, ArgOffset)); 988 989 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 990 if (isVarArg) { 991 static const unsigned GPRArgRegs[] = { 992 ARM::R0, ARM::R1, ARM::R2, ARM::R3 993 }; 994 995 MachineFunction &MF = DAG.getMachineFunction(); 996 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 997 MachineFrameInfo *MFI = MF.getFrameInfo(); 998 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 999 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1000 unsigned VARegSize = (4 - NumGPRs) * 4; 1001 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 1002 if (VARegSaveSize) { 1003 // If this function is vararg, store any remaining integer argument regs 1004 // to their spots on the stack so that they may be loaded by deferencing 1005 // the result of va_next. 1006 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1007 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1008 VARegSaveSize - VARegSize); 1009 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1010 1011 SmallVector<SDValue, 4> MemOps; 1012 for (; NumGPRs < 4; ++NumGPRs) { 1013 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 1014 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1015 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1016 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1017 MemOps.push_back(Store); 1018 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1019 DAG.getConstant(4, getPointerTy())); 1020 } 1021 if (!MemOps.empty()) 1022 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1023 &MemOps[0], MemOps.size()); 1024 } else 1025 // This will point to the next argument passed via stack. 1026 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1027 } 1028 1029 ArgValues.push_back(Root); 1030 1031 // Return the new list of results. 1032 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], 1033 ArgValues.size()); 1034} 1035 1036/// isFloatingPointZero - Return true if this is +0.0. 1037static bool isFloatingPointZero(SDValue Op) { 1038 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1039 return CFP->getValueAPF().isPosZero(); 1040 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 1041 // Maybe this has already been legalized into the constant pool? 1042 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1043 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 1044 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1045 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1046 return CFP->getValueAPF().isPosZero(); 1047 } 1048 } 1049 return false; 1050} 1051 1052static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1053 return ( isThumb && (C & ~255U) == 0) || 1054 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1055} 1056 1057/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1058/// the given operands. 1059static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1060 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { 1061 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1062 unsigned C = RHSC->getValue(); 1063 if (!isLegalCmpImmediate(C, isThumb)) { 1064 // Constant does not fit, try adjusting it by one? 1065 switch (CC) { 1066 default: break; 1067 case ISD::SETLT: 1068 case ISD::SETGE: 1069 if (isLegalCmpImmediate(C-1, isThumb)) { 1070 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1071 RHS = DAG.getConstant(C-1, MVT::i32); 1072 } 1073 break; 1074 case ISD::SETULT: 1075 case ISD::SETUGE: 1076 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1077 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1078 RHS = DAG.getConstant(C-1, MVT::i32); 1079 } 1080 break; 1081 case ISD::SETLE: 1082 case ISD::SETGT: 1083 if (isLegalCmpImmediate(C+1, isThumb)) { 1084 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1085 RHS = DAG.getConstant(C+1, MVT::i32); 1086 } 1087 break; 1088 case ISD::SETULE: 1089 case ISD::SETUGT: 1090 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1091 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1092 RHS = DAG.getConstant(C+1, MVT::i32); 1093 } 1094 break; 1095 } 1096 } 1097 } 1098 1099 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1100 ARMISD::NodeType CompareType; 1101 switch (CondCode) { 1102 default: 1103 CompareType = ARMISD::CMP; 1104 break; 1105 case ARMCC::EQ: 1106 case ARMCC::NE: 1107 case ARMCC::MI: 1108 case ARMCC::PL: 1109 // Uses only N and Z Flags 1110 CompareType = ARMISD::CMPNZ; 1111 break; 1112 } 1113 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1114 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1115} 1116 1117/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1118static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { 1119 SDValue Cmp; 1120 if (!isFloatingPointZero(RHS)) 1121 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1122 else 1123 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1124 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1125} 1126 1127static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 1128 const ARMSubtarget *ST) { 1129 MVT VT = Op.getValueType(); 1130 SDValue LHS = Op.getOperand(0); 1131 SDValue RHS = Op.getOperand(1); 1132 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1133 SDValue TrueVal = Op.getOperand(2); 1134 SDValue FalseVal = Op.getOperand(3); 1135 1136 if (LHS.getValueType() == MVT::i32) { 1137 SDValue ARMCC; 1138 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1139 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1140 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1141 } 1142 1143 ARMCC::CondCodes CondCode, CondCode2; 1144 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1145 std::swap(TrueVal, FalseVal); 1146 1147 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1148 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1149 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1150 SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1151 ARMCC, CCR, Cmp); 1152 if (CondCode2 != ARMCC::AL) { 1153 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1154 // FIXME: Needs another CMP because flag can have but one use. 1155 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); 1156 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1157 } 1158 return Result; 1159} 1160 1161static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 1162 const ARMSubtarget *ST) { 1163 SDValue Chain = Op.getOperand(0); 1164 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1165 SDValue LHS = Op.getOperand(2); 1166 SDValue RHS = Op.getOperand(3); 1167 SDValue Dest = Op.getOperand(4); 1168 1169 if (LHS.getValueType() == MVT::i32) { 1170 SDValue ARMCC; 1171 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1172 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1173 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1174 } 1175 1176 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1177 ARMCC::CondCodes CondCode, CondCode2; 1178 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1179 // Swap the LHS/RHS of the comparison if needed. 1180 std::swap(LHS, RHS); 1181 1182 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1183 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1184 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1185 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1186 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1187 SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1188 if (CondCode2 != ARMCC::AL) { 1189 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1190 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1191 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1192 } 1193 return Res; 1194} 1195 1196SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { 1197 SDValue Chain = Op.getOperand(0); 1198 SDValue Table = Op.getOperand(1); 1199 SDValue Index = Op.getOperand(2); 1200 1201 MVT PTy = getPointerTy(); 1202 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1203 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1204 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1205 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1206 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1207 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1208 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1209 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1210 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, 1211 Chain, Addr, NULL, 0); 1212 Chain = Addr.getValue(1); 1213 if (isPIC) 1214 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1215 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1216} 1217 1218static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1219 unsigned Opc = 1220 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1221 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1222 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1223} 1224 1225static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1226 MVT VT = Op.getValueType(); 1227 unsigned Opc = 1228 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1229 1230 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1231 return DAG.getNode(Opc, VT, Op); 1232} 1233 1234static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 1235 // Implement fcopysign with a fabs and a conditional fneg. 1236 SDValue Tmp0 = Op.getOperand(0); 1237 SDValue Tmp1 = Op.getOperand(1); 1238 MVT VT = Op.getValueType(); 1239 MVT SrcVT = Tmp1.getValueType(); 1240 SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1241 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1242 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1243 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1244 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1245} 1246 1247SDValue 1248ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1249 SDValue Chain, 1250 SDValue Dst, SDValue Src, 1251 SDValue Size, unsigned Align, 1252 bool AlwaysInline, 1253 const Value *DstSV, uint64_t DstSVOff, 1254 const Value *SrcSV, uint64_t SrcSVOff){ 1255 // Do repeated 4-byte loads and stores. To be improved. 1256 // This requires 4-byte alignment. 1257 if ((Align & 3) != 0) 1258 return SDValue(); 1259 // This requires the copy size to be a constant, preferrably 1260 // within a subtarget-specific limit. 1261 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 1262 if (!ConstantSize) 1263 return SDValue(); 1264 uint64_t SizeVal = ConstantSize->getValue(); 1265 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 1266 return SDValue(); 1267 1268 unsigned BytesLeft = SizeVal & 3; 1269 unsigned NumMemOps = SizeVal >> 2; 1270 unsigned EmittedNumMemOps = 0; 1271 MVT VT = MVT::i32; 1272 unsigned VTSize = 4; 1273 unsigned i = 0; 1274 const unsigned MAX_LOADS_IN_LDM = 6; 1275 SDValue TFOps[MAX_LOADS_IN_LDM]; 1276 SDValue Loads[MAX_LOADS_IN_LDM]; 1277 uint64_t SrcOff = 0, DstOff = 0; 1278 1279 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1280 // same number of stores. The loads and stores will get combined into 1281 // ldm/stm later on. 1282 while (EmittedNumMemOps < NumMemOps) { 1283 for (i = 0; 1284 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1285 Loads[i] = DAG.getLoad(VT, Chain, 1286 DAG.getNode(ISD::ADD, MVT::i32, Src, 1287 DAG.getConstant(SrcOff, MVT::i32)), 1288 SrcSV, SrcSVOff + SrcOff); 1289 TFOps[i] = Loads[i].getValue(1); 1290 SrcOff += VTSize; 1291 } 1292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1293 1294 for (i = 0; 1295 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1296 TFOps[i] = DAG.getStore(Chain, Loads[i], 1297 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1298 DAG.getConstant(DstOff, MVT::i32)), 1299 DstSV, DstSVOff + DstOff); 1300 DstOff += VTSize; 1301 } 1302 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1303 1304 EmittedNumMemOps += i; 1305 } 1306 1307 if (BytesLeft == 0) 1308 return Chain; 1309 1310 // Issue loads / stores for the trailing (1 - 3) bytes. 1311 unsigned BytesLeftSave = BytesLeft; 1312 i = 0; 1313 while (BytesLeft) { 1314 if (BytesLeft >= 2) { 1315 VT = MVT::i16; 1316 VTSize = 2; 1317 } else { 1318 VT = MVT::i8; 1319 VTSize = 1; 1320 } 1321 1322 Loads[i] = DAG.getLoad(VT, Chain, 1323 DAG.getNode(ISD::ADD, MVT::i32, Src, 1324 DAG.getConstant(SrcOff, MVT::i32)), 1325 SrcSV, SrcSVOff + SrcOff); 1326 TFOps[i] = Loads[i].getValue(1); 1327 ++i; 1328 SrcOff += VTSize; 1329 BytesLeft -= VTSize; 1330 } 1331 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1332 1333 i = 0; 1334 BytesLeft = BytesLeftSave; 1335 while (BytesLeft) { 1336 if (BytesLeft >= 2) { 1337 VT = MVT::i16; 1338 VTSize = 2; 1339 } else { 1340 VT = MVT::i8; 1341 VTSize = 1; 1342 } 1343 1344 TFOps[i] = DAG.getStore(Chain, Loads[i], 1345 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1346 DAG.getConstant(DstOff, MVT::i32)), 1347 DstSV, DstSVOff + DstOff); 1348 ++i; 1349 DstOff += VTSize; 1350 BytesLeft -= VTSize; 1351 } 1352 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1353} 1354 1355static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 1356 // Turn f64->i64 into FMRRD. 1357 assert(N->getValueType(0) == MVT::i64 && 1358 N->getOperand(0).getValueType() == MVT::f64); 1359 1360 SDValue Op = N->getOperand(0); 1361 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1362 &Op, 1); 1363 1364 // Merge the pieces into a single i64 value. 1365 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode(); 1366} 1367 1368static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { 1369 assert(N->getValueType(0) == MVT::i64 && 1370 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 1371 "Unknown shift to lower!"); 1372 1373 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1374 if (!isa<ConstantSDNode>(N->getOperand(1)) || 1375 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1) 1376 return 0; 1377 1378 // If we are in thumb mode, we don't have RRX. 1379 if (ST->isThumb()) return 0; 1380 1381 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1382 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1383 DAG.getConstant(0, MVT::i32)); 1384 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1385 DAG.getConstant(1, MVT::i32)); 1386 1387 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1388 // captures the result into a carry flag. 1389 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1390 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1391 1392 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1393 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1394 1395 // Merge the pieces into a single i64 value. 1396 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode(); 1397} 1398 1399 1400SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 1401 switch (Op.getOpcode()) { 1402 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1403 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1404 case ISD::GlobalAddress: 1405 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1406 LowerGlobalAddressELF(Op, DAG); 1407 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1408 case ISD::CALL: return LowerCALL(Op, DAG); 1409 case ISD::RET: return LowerRET(Op, DAG); 1410 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1411 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1412 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1413 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1414 case ISD::SINT_TO_FP: 1415 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1416 case ISD::FP_TO_SINT: 1417 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1418 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1419 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 1420 case ISD::RETURNADDR: break; 1421 case ISD::FRAMEADDR: break; 1422 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1423 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1424 1425 1426 // FIXME: Remove these when LegalizeDAGTypes lands. 1427 case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0); 1428 case ISD::SRL: 1429 case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0); 1430 } 1431 return SDValue(); 1432} 1433 1434 1435/// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal 1436/// result types. 1437SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 1438 switch (N->getOpcode()) { 1439 default: assert(0 && "Don't know how to custom expand this!"); abort(); 1440 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG); 1441 case ISD::SRL: 1442 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget); 1443 } 1444} 1445 1446 1447//===----------------------------------------------------------------------===// 1448// ARM Scheduler Hooks 1449//===----------------------------------------------------------------------===// 1450 1451MachineBasicBlock * 1452ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1453 MachineBasicBlock *BB) { 1454 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1455 switch (MI->getOpcode()) { 1456 default: assert(false && "Unexpected instr type to insert"); 1457 case ARM::tMOVCCr: { 1458 // To "insert" a SELECT_CC instruction, we actually have to insert the 1459 // diamond control-flow pattern. The incoming instruction knows the 1460 // destination vreg to set, the condition code register to branch on, the 1461 // true/false values to select between, and a branch opcode to use. 1462 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1463 MachineFunction::iterator It = BB; 1464 ++It; 1465 1466 // thisMBB: 1467 // ... 1468 // TrueVal = ... 1469 // cmpTY ccX, r1, r2 1470 // bCC copy1MBB 1471 // fallthrough --> copy0MBB 1472 MachineBasicBlock *thisMBB = BB; 1473 MachineFunction *F = BB->getParent(); 1474 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1475 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1476 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1477 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1478 F->insert(It, copy0MBB); 1479 F->insert(It, sinkMBB); 1480 // Update machine-CFG edges by first adding all successors of the current 1481 // block to the new block which will contain the Phi node for the select. 1482 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1483 e = BB->succ_end(); i != e; ++i) 1484 sinkMBB->addSuccessor(*i); 1485 // Next, remove all successors of the current block, and add the true 1486 // and fallthrough blocks as its successors. 1487 while(!BB->succ_empty()) 1488 BB->removeSuccessor(BB->succ_begin()); 1489 BB->addSuccessor(copy0MBB); 1490 BB->addSuccessor(sinkMBB); 1491 1492 // copy0MBB: 1493 // %FalseValue = ... 1494 // # fallthrough to sinkMBB 1495 BB = copy0MBB; 1496 1497 // Update machine-CFG edges 1498 BB->addSuccessor(sinkMBB); 1499 1500 // sinkMBB: 1501 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1502 // ... 1503 BB = sinkMBB; 1504 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1505 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1506 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1507 1508 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1509 return BB; 1510 } 1511 } 1512} 1513 1514//===----------------------------------------------------------------------===// 1515// ARM Optimization Hooks 1516//===----------------------------------------------------------------------===// 1517 1518/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 1519static SDValue PerformFMRRDCombine(SDNode *N, 1520 TargetLowering::DAGCombinerInfo &DCI) { 1521 // fmrrd(fmdrr x, y) -> x,y 1522 SDValue InDouble = N->getOperand(0); 1523 if (InDouble.getOpcode() == ARMISD::FMDRR) 1524 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 1525 return SDValue(); 1526} 1527 1528SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 1529 DAGCombinerInfo &DCI) const { 1530 switch (N->getOpcode()) { 1531 default: break; 1532 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 1533 } 1534 1535 return SDValue(); 1536} 1537 1538 1539/// isLegalAddressImmediate - Return true if the integer value can be used 1540/// as the offset of the target addressing mode for load / store of the 1541/// given type. 1542static bool isLegalAddressImmediate(int64_t V, MVT VT, 1543 const ARMSubtarget *Subtarget) { 1544 if (V == 0) 1545 return true; 1546 1547 if (Subtarget->isThumb()) { 1548 if (V < 0) 1549 return false; 1550 1551 unsigned Scale = 1; 1552 switch (VT.getSimpleVT()) { 1553 default: return false; 1554 case MVT::i1: 1555 case MVT::i8: 1556 // Scale == 1; 1557 break; 1558 case MVT::i16: 1559 // Scale == 2; 1560 Scale = 2; 1561 break; 1562 case MVT::i32: 1563 // Scale == 4; 1564 Scale = 4; 1565 break; 1566 } 1567 1568 if ((V & (Scale - 1)) != 0) 1569 return false; 1570 V /= Scale; 1571 return V == (V & ((1LL << 5) - 1)); 1572 } 1573 1574 if (V < 0) 1575 V = - V; 1576 switch (VT.getSimpleVT()) { 1577 default: return false; 1578 case MVT::i1: 1579 case MVT::i8: 1580 case MVT::i32: 1581 // +- imm12 1582 return V == (V & ((1LL << 12) - 1)); 1583 case MVT::i16: 1584 // +- imm8 1585 return V == (V & ((1LL << 8) - 1)); 1586 case MVT::f32: 1587 case MVT::f64: 1588 if (!Subtarget->hasVFP2()) 1589 return false; 1590 if ((V & 3) != 0) 1591 return false; 1592 V >>= 2; 1593 return V == (V & ((1LL << 8) - 1)); 1594 } 1595} 1596 1597/// isLegalAddressingMode - Return true if the addressing mode represented 1598/// by AM is legal for this target, for a load/store of the specified type. 1599bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1600 const Type *Ty) const { 1601 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget)) 1602 return false; 1603 1604 // Can never fold addr of global into load/store. 1605 if (AM.BaseGV) 1606 return false; 1607 1608 switch (AM.Scale) { 1609 case 0: // no scale reg, must be "r+i" or "r", or "i". 1610 break; 1611 case 1: 1612 if (Subtarget->isThumb()) 1613 return false; 1614 // FALL THROUGH. 1615 default: 1616 // ARM doesn't support any R+R*scale+imm addr modes. 1617 if (AM.BaseOffs) 1618 return false; 1619 1620 int Scale = AM.Scale; 1621 switch (getValueType(Ty).getSimpleVT()) { 1622 default: return false; 1623 case MVT::i1: 1624 case MVT::i8: 1625 case MVT::i32: 1626 case MVT::i64: 1627 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1628 // ldrd / strd are used, then its address mode is same as i16. 1629 // r + r 1630 if (Scale < 0) Scale = -Scale; 1631 if (Scale == 1) 1632 return true; 1633 // r + r << imm 1634 return isPowerOf2_32(Scale & ~1); 1635 case MVT::i16: 1636 // r + r 1637 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1638 return true; 1639 return false; 1640 1641 case MVT::isVoid: 1642 // Note, we allow "void" uses (basically, uses that aren't loads or 1643 // stores), because arm allows folding a scale into many arithmetic 1644 // operations. This should be made more precise and revisited later. 1645 1646 // Allow r << imm, but the imm has to be a multiple of two. 1647 if (AM.Scale & 1) return false; 1648 return isPowerOf2_32(AM.Scale); 1649 } 1650 break; 1651 } 1652 return true; 1653} 1654 1655 1656static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, 1657 bool isSEXTLoad, SDValue &Base, 1658 SDValue &Offset, bool &isInc, 1659 SelectionDAG &DAG) { 1660 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1661 return false; 1662 1663 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1664 // AddressingMode 3 1665 Base = Ptr->getOperand(0); 1666 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1667 int RHSC = (int)RHS->getValue(); 1668 if (RHSC < 0 && RHSC > -256) { 1669 isInc = false; 1670 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1671 return true; 1672 } 1673 } 1674 isInc = (Ptr->getOpcode() == ISD::ADD); 1675 Offset = Ptr->getOperand(1); 1676 return true; 1677 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1678 // AddressingMode 2 1679 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1680 int RHSC = (int)RHS->getValue(); 1681 if (RHSC < 0 && RHSC > -0x1000) { 1682 isInc = false; 1683 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1684 Base = Ptr->getOperand(0); 1685 return true; 1686 } 1687 } 1688 1689 if (Ptr->getOpcode() == ISD::ADD) { 1690 isInc = true; 1691 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1692 if (ShOpcVal != ARM_AM::no_shift) { 1693 Base = Ptr->getOperand(1); 1694 Offset = Ptr->getOperand(0); 1695 } else { 1696 Base = Ptr->getOperand(0); 1697 Offset = Ptr->getOperand(1); 1698 } 1699 return true; 1700 } 1701 1702 isInc = (Ptr->getOpcode() == ISD::ADD); 1703 Base = Ptr->getOperand(0); 1704 Offset = Ptr->getOperand(1); 1705 return true; 1706 } 1707 1708 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1709 return false; 1710} 1711 1712/// getPreIndexedAddressParts - returns true by value, base pointer and 1713/// offset pointer and addressing mode by reference if the node's address 1714/// can be legally represented as pre-indexed load / store address. 1715bool 1716ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1717 SDValue &Offset, 1718 ISD::MemIndexedMode &AM, 1719 SelectionDAG &DAG) { 1720 if (Subtarget->isThumb()) 1721 return false; 1722 1723 MVT VT; 1724 SDValue Ptr; 1725 bool isSEXTLoad = false; 1726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1727 Ptr = LD->getBasePtr(); 1728 VT = LD->getMemoryVT(); 1729 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1730 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1731 Ptr = ST->getBasePtr(); 1732 VT = ST->getMemoryVT(); 1733 } else 1734 return false; 1735 1736 bool isInc; 1737 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset, 1738 isInc, DAG); 1739 if (isLegal) { 1740 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1741 return true; 1742 } 1743 return false; 1744} 1745 1746/// getPostIndexedAddressParts - returns true by value, base pointer and 1747/// offset pointer and addressing mode by reference if this node can be 1748/// combined with a load / store to form a post-indexed load / store. 1749bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1750 SDValue &Base, 1751 SDValue &Offset, 1752 ISD::MemIndexedMode &AM, 1753 SelectionDAG &DAG) { 1754 if (Subtarget->isThumb()) 1755 return false; 1756 1757 MVT VT; 1758 SDValue Ptr; 1759 bool isSEXTLoad = false; 1760 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1761 VT = LD->getMemoryVT(); 1762 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1763 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1764 VT = ST->getMemoryVT(); 1765 } else 1766 return false; 1767 1768 bool isInc; 1769 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1770 isInc, DAG); 1771 if (isLegal) { 1772 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1773 return true; 1774 } 1775 return false; 1776} 1777 1778void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1779 const APInt &Mask, 1780 APInt &KnownZero, 1781 APInt &KnownOne, 1782 const SelectionDAG &DAG, 1783 unsigned Depth) const { 1784 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1785 switch (Op.getOpcode()) { 1786 default: break; 1787 case ARMISD::CMOV: { 1788 // Bits are known zero/one if known on the LHS and RHS. 1789 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1790 if (KnownZero == 0 && KnownOne == 0) return; 1791 1792 APInt KnownZeroRHS, KnownOneRHS; 1793 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1794 KnownZeroRHS, KnownOneRHS, Depth+1); 1795 KnownZero &= KnownZeroRHS; 1796 KnownOne &= KnownOneRHS; 1797 return; 1798 } 1799 } 1800} 1801 1802//===----------------------------------------------------------------------===// 1803// ARM Inline Assembly Support 1804//===----------------------------------------------------------------------===// 1805 1806/// getConstraintType - Given a constraint letter, return the type of 1807/// constraint it is for this target. 1808ARMTargetLowering::ConstraintType 1809ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1810 if (Constraint.size() == 1) { 1811 switch (Constraint[0]) { 1812 default: break; 1813 case 'l': return C_RegisterClass; 1814 case 'w': return C_RegisterClass; 1815 } 1816 } 1817 return TargetLowering::getConstraintType(Constraint); 1818} 1819 1820std::pair<unsigned, const TargetRegisterClass*> 1821ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1822 MVT VT) const { 1823 if (Constraint.size() == 1) { 1824 // GCC RS6000 Constraint Letters 1825 switch (Constraint[0]) { 1826 case 'l': 1827 // FIXME: in thumb mode, 'l' is only low-regs. 1828 // FALL THROUGH. 1829 case 'r': 1830 return std::make_pair(0U, ARM::GPRRegisterClass); 1831 case 'w': 1832 if (VT == MVT::f32) 1833 return std::make_pair(0U, ARM::SPRRegisterClass); 1834 if (VT == MVT::f64) 1835 return std::make_pair(0U, ARM::DPRRegisterClass); 1836 break; 1837 } 1838 } 1839 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1840} 1841 1842std::vector<unsigned> ARMTargetLowering:: 1843getRegClassForInlineAsmConstraint(const std::string &Constraint, 1844 MVT VT) const { 1845 if (Constraint.size() != 1) 1846 return std::vector<unsigned>(); 1847 1848 switch (Constraint[0]) { // GCC ARM Constraint Letters 1849 default: break; 1850 case 'l': 1851 case 'r': 1852 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1853 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1854 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1855 ARM::R12, ARM::LR, 0); 1856 case 'w': 1857 if (VT == MVT::f32) 1858 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1859 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1860 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1861 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1862 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1863 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1864 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1865 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1866 if (VT == MVT::f64) 1867 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1868 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1869 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1870 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1871 break; 1872 } 1873 1874 return std::vector<unsigned>(); 1875} 1876