ARMISelLowering.cpp revision b1df8f2750cb8df55f7e15985ef5c86f9092cbe1 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/CallingConv.h"
24#include "llvm/Constants.h"
25#include "llvm/Instruction.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/CodeGen/SSARegMap.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/ADT/VectorExtras.h"
34#include "llvm/Support/MathExtras.h"
35using namespace llvm;
36
37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
38    : TargetLowering(TM), ARMPCLabelIndex(0) {
39  Subtarget = &TM.getSubtarget<ARMSubtarget>();
40
41  if (Subtarget->isTargetDarwin()) {
42    // Don't have these.
43    setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
44    setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
45
46    // Uses VFP for Thumb libfuncs if available.
47    if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
48      // Single-precision floating-point arithmetic.
49      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
50      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
51      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
52      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
53
54      // Double-precision floating-point arithmetic.
55      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
56      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
57      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
58      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
59
60      // Single-precision comparisons.
61      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
62      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
63      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
64      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
65      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
66      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
67      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
68      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
69
70      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
71      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
72      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
73      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
74      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
75      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
76      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
77      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
78
79      // Double-precision comparisons.
80      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
81      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
82      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
83      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
84      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
85      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
86      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
87      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
88
89      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
90      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
91      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
92      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
93      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
94      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
95      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
96      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
97
98      // Floating-point to integer conversions.
99      // i64 conversions are done via library routines even when generating VFP
100      // instructions, so use the same ones.
101      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
102      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
103      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
104      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
105
106      // Conversions between floating types.
107      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
108      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
109
110      // Integer to floating-point conversions.
111      // i64 conversions are done via library routines even when generating VFP
112      // instructions, so use the same ones.
113      // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
114      // __floatunsidf vs. __floatunssidfvfp.
115      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
116      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
117      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
118      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
119    }
120  }
121
122  addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
123  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
124    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
125    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
126  }
127
128  // ARM does not have f32 extending load.
129  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
130
131  // ARM supports all 4 flavors of integer indexed load / store.
132  for (unsigned im = (unsigned)ISD::PRE_INC;
133       im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
134    setIndexedLoadAction(im,  MVT::i1,  Legal);
135    setIndexedLoadAction(im,  MVT::i8,  Legal);
136    setIndexedLoadAction(im,  MVT::i16, Legal);
137    setIndexedLoadAction(im,  MVT::i32, Legal);
138    setIndexedStoreAction(im, MVT::i1,  Legal);
139    setIndexedStoreAction(im, MVT::i8,  Legal);
140    setIndexedStoreAction(im, MVT::i16, Legal);
141    setIndexedStoreAction(im, MVT::i32, Legal);
142  }
143
144  // i64 operation support.
145  if (Subtarget->isThumb()) {
146    setOperationAction(ISD::MUL,     MVT::i64, Expand);
147    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
148    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
149  } else {
150    setOperationAction(ISD::MUL,     MVT::i64, Custom);
151    setOperationAction(ISD::MULHU,   MVT::i32, Custom);
152    if (!Subtarget->hasV6Ops())
153      setOperationAction(ISD::MULHS, MVT::i32, Custom);
154  }
155  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158  setOperationAction(ISD::SRL,       MVT::i64, Custom);
159  setOperationAction(ISD::SRA,       MVT::i64, Custom);
160
161  // ARM does not have ROTL.
162  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
163  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
164  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
165  if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
166    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
167
168  // Only ARMv6 has BSWAP.
169  if (!Subtarget->hasV6Ops())
170    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
171
172  // These are expanded into libcalls.
173  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
174  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
175  setOperationAction(ISD::SREM,  MVT::i32, Expand);
176  setOperationAction(ISD::UREM,  MVT::i32, Expand);
177
178  // Support label based line numbers.
179  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
180  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
181  // FIXME - use subtarget debug flags
182  if (!Subtarget->isTargetDarwin())
183    setOperationAction(ISD::LABEL, MVT::Other, Expand);
184
185  setOperationAction(ISD::RET,           MVT::Other, Custom);
186  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
187  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
188  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
189
190  // Expand mem operations genericly.
191  setOperationAction(ISD::MEMSET          , MVT::Other, Expand);
192  setOperationAction(ISD::MEMCPY          , MVT::Other, Expand);
193  setOperationAction(ISD::MEMMOVE         , MVT::Other, Expand);
194
195  // Use the default implementation.
196  setOperationAction(ISD::VASTART           , MVT::Other, Expand);
197  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
198  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
199  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
200  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
201  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
202  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
203
204  if (!Subtarget->hasV6Ops()) {
205    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
206    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
207  }
208  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
209
210  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
211    // Turn f64->i64 into FMRRD iff target supports vfp2.
212    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
213
214  setOperationAction(ISD::SETCC    , MVT::i32, Expand);
215  setOperationAction(ISD::SETCC    , MVT::f32, Expand);
216  setOperationAction(ISD::SETCC    , MVT::f64, Expand);
217  setOperationAction(ISD::SELECT   , MVT::i32, Expand);
218  setOperationAction(ISD::SELECT   , MVT::f32, Expand);
219  setOperationAction(ISD::SELECT   , MVT::f64, Expand);
220  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
221  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
222  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
223
224  setOperationAction(ISD::BRCOND   , MVT::Other, Expand);
225  setOperationAction(ISD::BR_CC    , MVT::i32,   Custom);
226  setOperationAction(ISD::BR_CC    , MVT::f32,   Custom);
227  setOperationAction(ISD::BR_CC    , MVT::f64,   Custom);
228  setOperationAction(ISD::BR_JT    , MVT::Other, Custom);
229
230  setOperationAction(ISD::VASTART,       MVT::Other, Custom);
231  setOperationAction(ISD::VACOPY,        MVT::Other, Expand);
232  setOperationAction(ISD::VAEND,         MVT::Other, Expand);
233  setOperationAction(ISD::STACKSAVE,     MVT::Other, Expand);
234  setOperationAction(ISD::STACKRESTORE,  MVT::Other, Expand);
235
236  // FP Constants can't be immediates.
237  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
238  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
239
240  // We don't support sin/cos/fmod/copysign
241  setOperationAction(ISD::FSIN     , MVT::f64, Expand);
242  setOperationAction(ISD::FSIN     , MVT::f32, Expand);
243  setOperationAction(ISD::FCOS     , MVT::f32, Expand);
244  setOperationAction(ISD::FCOS     , MVT::f64, Expand);
245  setOperationAction(ISD::FREM     , MVT::f64, Expand);
246  setOperationAction(ISD::FREM     , MVT::f32, Expand);
247  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
248  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
249
250  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
251  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
252  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
253  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
254  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255
256  setStackPointerRegisterToSaveRestore(ARM::SP);
257
258  setSchedulingPreference(SchedulingForRegPressure);
259  computeRegisterProperties();
260}
261
262
263const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
264  switch (Opcode) {
265  default: return 0;
266  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
267  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
268  case ARMISD::CALL:          return "ARMISD::CALL";
269  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
270  case ARMISD::tCALL:         return "ARMISD::tCALL";
271  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
272  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
273  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
274  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
275  case ARMISD::CMP:           return "ARMISD::CMP";
276  case ARMISD::CMPNZ:         return "ARMISD::CMPNZ";
277  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
278  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
279  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
280  case ARMISD::CMOV:          return "ARMISD::CMOV";
281  case ARMISD::CNEG:          return "ARMISD::CNEG";
282
283  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
284  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
285  case ARMISD::SITOF:         return "ARMISD::SITOF";
286  case ARMISD::UITOF:         return "ARMISD::UITOF";
287  case ARMISD::MULHILOU:      return "ARMISD::MULHILOU";
288  case ARMISD::MULHILOS:      return "ARMISD::MULHILOS";
289
290  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
291  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
292  case ARMISD::RRX:           return "ARMISD::RRX";
293
294  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
295  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
296  }
297}
298
299//===----------------------------------------------------------------------===//
300// Lowering Code
301//===----------------------------------------------------------------------===//
302
303
304/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
305static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
306  switch (CC) {
307  default: assert(0 && "Unknown condition code!");
308  case ISD::SETNE:  return ARMCC::NE;
309  case ISD::SETEQ:  return ARMCC::EQ;
310  case ISD::SETGT:  return ARMCC::GT;
311  case ISD::SETGE:  return ARMCC::GE;
312  case ISD::SETLT:  return ARMCC::LT;
313  case ISD::SETLE:  return ARMCC::LE;
314  case ISD::SETUGT: return ARMCC::HI;
315  case ISD::SETUGE: return ARMCC::HS;
316  case ISD::SETULT: return ARMCC::LO;
317  case ISD::SETULE: return ARMCC::LS;
318  }
319}
320
321/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
322/// returns true if the operands should be inverted to form the proper
323/// comparison.
324static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
325                        ARMCC::CondCodes &CondCode2) {
326  bool Invert = false;
327  CondCode2 = ARMCC::AL;
328  switch (CC) {
329  default: assert(0 && "Unknown FP condition!");
330  case ISD::SETEQ:
331  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
332  case ISD::SETGT:
333  case ISD::SETOGT: CondCode = ARMCC::GT; break;
334  case ISD::SETGE:
335  case ISD::SETOGE: CondCode = ARMCC::GE; break;
336  case ISD::SETOLT: CondCode = ARMCC::MI; break;
337  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
338  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
339  case ISD::SETO:   CondCode = ARMCC::VC; break;
340  case ISD::SETUO:  CondCode = ARMCC::VS; break;
341  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
342  case ISD::SETUGT: CondCode = ARMCC::HI; break;
343  case ISD::SETUGE: CondCode = ARMCC::PL; break;
344  case ISD::SETLT:
345  case ISD::SETULT: CondCode = ARMCC::LT; break;
346  case ISD::SETLE:
347  case ISD::SETULE: CondCode = ARMCC::LE; break;
348  case ISD::SETNE:
349  case ISD::SETUNE: CondCode = ARMCC::NE; break;
350  }
351  return Invert;
352}
353
354static void
355HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
356                  unsigned StackOffset, unsigned &NeededGPRs,
357                  unsigned &NeededStackSize, unsigned &GPRPad,
358                  unsigned &StackPad, unsigned Flags) {
359  NeededStackSize = 0;
360  NeededGPRs = 0;
361  StackPad = 0;
362  GPRPad = 0;
363  unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
364  GPRPad = NumGPRs % ((align + 3)/4);
365  StackPad = StackOffset % align;
366  unsigned firstGPR = NumGPRs + GPRPad;
367  switch (ObjectVT) {
368  default: assert(0 && "Unhandled argument type!");
369  case MVT::i32:
370  case MVT::f32:
371    if (firstGPR < 4)
372      NeededGPRs = 1;
373    else
374      NeededStackSize = 4;
375    break;
376  case MVT::i64:
377  case MVT::f64:
378    if (firstGPR < 3)
379      NeededGPRs = 2;
380    else if (firstGPR == 3) {
381      NeededGPRs = 1;
382      NeededStackSize = 4;
383    } else
384      NeededStackSize = 8;
385  }
386}
387
388/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
389/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
390/// nodes.
391SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
392  MVT::ValueType RetVT= Op.Val->getValueType(0);
393  SDOperand Chain    = Op.getOperand(0);
394  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
395  assert((CallConv == CallingConv::C ||
396          CallConv == CallingConv::Fast) && "unknown calling convention");
397  SDOperand Callee   = Op.getOperand(4);
398  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
399  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
400  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
401
402  // Count how many bytes are to be pushed on the stack.
403  unsigned NumBytes = 0;
404
405  // Add up all the space actually used.
406  for (unsigned i = 0; i < NumOps; ++i) {
407    unsigned ObjSize;
408    unsigned ObjGPRs;
409    unsigned StackPad;
410    unsigned GPRPad;
411    MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
412    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
413    HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
414                      GPRPad, StackPad, Flags);
415    NumBytes += ObjSize + StackPad;
416    NumGPRs += ObjGPRs + GPRPad;
417  }
418
419  // Adjust the stack pointer for the new arguments...
420  // These operations are automatically eliminated by the prolog/epilog pass
421  Chain = DAG.getCALLSEQ_START(Chain,
422                               DAG.getConstant(NumBytes, MVT::i32));
423
424  SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
425
426  static const unsigned GPRArgRegs[] = {
427    ARM::R0, ARM::R1, ARM::R2, ARM::R3
428  };
429
430  NumGPRs = 0;
431  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
432  std::vector<SDOperand> MemOpChains;
433  for (unsigned i = 0; i != NumOps; ++i) {
434    SDOperand Arg = Op.getOperand(5+2*i);
435    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
436    MVT::ValueType ArgVT = Arg.getValueType();
437
438    unsigned ObjSize;
439    unsigned ObjGPRs;
440    unsigned GPRPad;
441    unsigned StackPad;
442    HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
443                      ObjSize, GPRPad, StackPad, Flags);
444    NumGPRs += GPRPad;
445    ArgOffset += StackPad;
446    if (ObjGPRs > 0) {
447      switch (ArgVT) {
448      default: assert(0 && "Unexpected ValueType for argument!");
449      case MVT::i32:
450        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
451        break;
452      case MVT::f32:
453        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
454                                 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
455        break;
456      case MVT::i64: {
457        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
458                                   DAG.getConstant(0, getPointerTy()));
459        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
460                                   DAG.getConstant(1, getPointerTy()));
461        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
462        if (ObjGPRs == 2)
463          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
464        else {
465          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
466          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
467          MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
468        }
469        break;
470      }
471      case MVT::f64: {
472        SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
473                                    DAG.getVTList(MVT::i32, MVT::i32),
474                                    &Arg, 1);
475        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
476        if (ObjGPRs == 2)
477          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
478                                              Cvt.getValue(1)));
479        else {
480          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
481          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
482          MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
483                                             NULL, 0));
484        }
485        break;
486      }
487      }
488    } else {
489      assert(ObjSize != 0);
490      SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
491      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
492      MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
493    }
494
495    NumGPRs += ObjGPRs;
496    ArgOffset += ObjSize;
497  }
498
499  if (!MemOpChains.empty())
500    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
501                        &MemOpChains[0], MemOpChains.size());
502
503  // Build a sequence of copy-to-reg nodes chained together with token chain
504  // and flag operands which copy the outgoing args into the appropriate regs.
505  SDOperand InFlag;
506  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
507    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
508                             InFlag);
509    InFlag = Chain.getValue(1);
510  }
511
512  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
513  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
514  // node so that legalize doesn't hack it.
515  bool isDirect = false;
516  bool isARMFunc = false;
517  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
518    GlobalValue *GV = G->getGlobal();
519    isDirect = true;
520    bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
521                  GV->hasLinkOnceLinkage());
522    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
523                   getTargetMachine().getRelocationModel() != Reloc::Static;
524    isARMFunc = !Subtarget->isThumb() || isStub;
525    // tBX takes a register source operand.
526    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
527      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
528                                                           ARMCP::CPStub, 4);
529      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
530      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
531      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
532      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
533      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
534   } else
535      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
536  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
537    isDirect = true;
538    bool isStub = Subtarget->isTargetDarwin() &&
539                  getTargetMachine().getRelocationModel() != Reloc::Static;
540    isARMFunc = !Subtarget->isThumb() || isStub;
541    // tBX takes a register source operand.
542    const char *Sym = S->getSymbol();
543    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
544      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
545                                                           ARMCP::CPStub, 4);
546      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
547      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
548      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
549      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
550      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
551    } else
552      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
553  }
554
555  // FIXME: handle tail calls differently.
556  unsigned CallOpc;
557  if (Subtarget->isThumb()) {
558    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
559      CallOpc = ARMISD::CALL_NOLINK;
560    else
561      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
562  } else {
563    CallOpc = (isDirect || Subtarget->hasV5TOps())
564      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
565  }
566  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
567    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
568    Chain = DAG.getCopyToReg(Chain, ARM::LR,
569                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
570    InFlag = Chain.getValue(1);
571  }
572
573  std::vector<MVT::ValueType> NodeTys;
574  NodeTys.push_back(MVT::Other);   // Returns a chain
575  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
576
577  std::vector<SDOperand> Ops;
578  Ops.push_back(Chain);
579  Ops.push_back(Callee);
580
581  // Add argument registers to the end of the list so that they are known live
582  // into the call.
583  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
584    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
585                                  RegsToPass[i].second.getValueType()));
586
587  if (InFlag.Val)
588    Ops.push_back(InFlag);
589  Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
590  InFlag = Chain.getValue(1);
591
592  SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
593  Chain = DAG.getNode(ISD::CALLSEQ_END,
594                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
595                      ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
596  if (RetVT != MVT::Other)
597    InFlag = Chain.getValue(1);
598
599  std::vector<SDOperand> ResultVals;
600  NodeTys.clear();
601
602  // If the call has results, copy the values out of the ret val registers.
603  switch (RetVT) {
604  default: assert(0 && "Unexpected ret value!");
605  case MVT::Other:
606    break;
607  case MVT::i32:
608    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
609    ResultVals.push_back(Chain.getValue(0));
610    if (Op.Val->getValueType(1) == MVT::i32) {
611      // Returns a i64 value.
612      Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
613                                 Chain.getValue(2)).getValue(1);
614      ResultVals.push_back(Chain.getValue(0));
615      NodeTys.push_back(MVT::i32);
616    }
617    NodeTys.push_back(MVT::i32);
618    break;
619  case MVT::f32:
620    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
621    ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
622                                     Chain.getValue(0)));
623    NodeTys.push_back(MVT::f32);
624    break;
625  case MVT::f64: {
626    SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
627    SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
628    ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
629    NodeTys.push_back(MVT::f64);
630    break;
631  }
632  }
633
634  NodeTys.push_back(MVT::Other);
635
636  if (ResultVals.empty())
637    return Chain;
638
639  ResultVals.push_back(Chain);
640  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
641                              ResultVals.size());
642  return Res.getValue(Op.ResNo);
643}
644
645static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
646  SDOperand Copy;
647  SDOperand Chain = Op.getOperand(0);
648  switch(Op.getNumOperands()) {
649  default:
650    assert(0 && "Do not know how to return this many arguments!");
651    abort();
652  case 1: {
653    SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
654    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
655  }
656  case 3:
657    Op = Op.getOperand(1);
658    if (Op.getValueType() == MVT::f32) {
659      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
660    } else if (Op.getValueType() == MVT::f64) {
661      // Recursively legalize f64 -> i64.
662      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
663      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
664                         DAG.getConstant(0, MVT::i32));
665    }
666    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
667    if (DAG.getMachineFunction().liveout_empty())
668      DAG.getMachineFunction().addLiveOut(ARM::R0);
669    break;
670  case 5:
671    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
672    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
673    // If we haven't noted the R0+R1 are live out, do so now.
674    if (DAG.getMachineFunction().liveout_empty()) {
675      DAG.getMachineFunction().addLiveOut(ARM::R0);
676      DAG.getMachineFunction().addLiveOut(ARM::R1);
677    }
678    break;
679  }
680
681  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
682  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
683}
684
685// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
686// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
687// one of the above mentioned nodes. It has to be wrapped because otherwise
688// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
689// be used to form addressing mode. These wrapped nodes will be selected
690// into MOVi.
691static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
692  MVT::ValueType PtrVT = Op.getValueType();
693  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
694  SDOperand Res;
695  if (CP->isMachineConstantPoolEntry())
696    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
697                                    CP->getAlignment());
698  else
699    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
700                                    CP->getAlignment());
701  return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
702}
703
704SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
705                                                   SelectionDAG &DAG) {
706  MVT::ValueType PtrVT = getPointerTy();
707  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
708  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
709  if (RelocM == Reloc::PIC_) {
710    bool UseGOTOFF = GV->hasInternalLinkage();
711    ARMConstantPoolValue *CPV =
712      new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
713    SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
714    CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
715    SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
716    SDOperand Chain = Result.getValue(1);
717    SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
718    Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
719    if (!UseGOTOFF)
720      Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
721    return Result;
722  } else {
723    SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
724    CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
725    return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
726  }
727}
728
729/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
730/// even in dynamic-no-pic mode.
731static bool GVIsIndirectSymbol(GlobalValue *GV) {
732  return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
733          (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
734}
735
736SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
737                                                      SelectionDAG &DAG) {
738  MVT::ValueType PtrVT = getPointerTy();
739  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
740  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
741  bool IsIndirect = GVIsIndirectSymbol(GV);
742  SDOperand CPAddr;
743  if (RelocM == Reloc::Static)
744    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
745  else {
746    unsigned PCAdj = (RelocM != Reloc::PIC_)
747      ? 0 : (Subtarget->isThumb() ? 4 : 8);
748    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
749      : ARMCP::CPValue;
750    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
751                                                         Kind, PCAdj);
752    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
753  }
754  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
755
756  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
757  SDOperand Chain = Result.getValue(1);
758
759  if (RelocM == Reloc::PIC_) {
760    SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
761    Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
762  }
763  if (IsIndirect)
764    Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
765
766  return Result;
767}
768
769SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
770                                                      SelectionDAG &DAG){
771  assert(Subtarget->isTargetELF() &&
772         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
773  MVT::ValueType PtrVT = getPointerTy();
774  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
775  ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
776                                                       ARMPCLabelIndex,
777                                                       ARMCP::CPValue, PCAdj);
778  SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
779  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
780  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
781  SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
782  return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
783}
784
785static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
786                              unsigned VarArgsFrameIndex) {
787  // vastart just stores the address of the VarArgsFrameIndex slot into the
788  // memory location argument.
789  MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
790  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
791  SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
792  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
793                      SV->getOffset());
794}
795
796static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
797                                      unsigned *vRegs, unsigned ArgNo,
798                                      unsigned &NumGPRs, unsigned &ArgOffset) {
799  MachineFunction &MF = DAG.getMachineFunction();
800  MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
801  SDOperand Root = Op.getOperand(0);
802  std::vector<SDOperand> ArgValues;
803  SSARegMap *RegMap = MF.getSSARegMap();
804
805  static const unsigned GPRArgRegs[] = {
806    ARM::R0, ARM::R1, ARM::R2, ARM::R3
807  };
808
809  unsigned ObjSize;
810  unsigned ObjGPRs;
811  unsigned GPRPad;
812  unsigned StackPad;
813  unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
814  HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
815                    ObjSize, GPRPad, StackPad, Flags);
816  NumGPRs += GPRPad;
817  ArgOffset += StackPad;
818
819  SDOperand ArgValue;
820  if (ObjGPRs == 1) {
821    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
822    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
823    vRegs[NumGPRs] = VReg;
824    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
825    if (ObjectVT == MVT::f32)
826      ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
827  } else if (ObjGPRs == 2) {
828    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
829    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
830    vRegs[NumGPRs] = VReg;
831    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
832
833    VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
834    MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
835    vRegs[NumGPRs+1] = VReg;
836    SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
837
838    if (ObjectVT == MVT::i64)
839      ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
840    else
841      ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
842  }
843  NumGPRs += ObjGPRs;
844
845  if (ObjSize) {
846    // If the argument is actually used, emit a load from the right stack
847    // slot.
848    if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
849      MachineFrameInfo *MFI = MF.getFrameInfo();
850      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
851      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
852      if (ObjGPRs == 0)
853        ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
854      else {
855        SDOperand ArgValue2 =
856          DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
857        if (ObjectVT == MVT::i64)
858          ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
859        else
860          ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
861      }
862    } else {
863      // Don't emit a dead load.
864      ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
865    }
866
867    ArgOffset += ObjSize;   // Move on to the next argument.
868  }
869
870  return ArgValue;
871}
872
873SDOperand
874ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
875  std::vector<SDOperand> ArgValues;
876  SDOperand Root = Op.getOperand(0);
877  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
878  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
879  unsigned VRegs[4];
880
881  unsigned NumArgs = Op.Val->getNumValues()-1;
882  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
883    ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
884                                             NumGPRs, ArgOffset));
885
886  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
887  if (isVarArg) {
888    static const unsigned GPRArgRegs[] = {
889      ARM::R0, ARM::R1, ARM::R2, ARM::R3
890    };
891
892    MachineFunction &MF = DAG.getMachineFunction();
893    SSARegMap *RegMap = MF.getSSARegMap();
894    MachineFrameInfo *MFI = MF.getFrameInfo();
895    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
896    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
897    unsigned VARegSize = (4 - NumGPRs) * 4;
898    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
899    if (VARegSaveSize) {
900      // If this function is vararg, store any remaining integer argument regs
901      // to their spots on the stack so that they may be loaded by deferencing
902      // the result of va_next.
903      AFI->setVarArgsRegSaveSize(VARegSaveSize);
904      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
905                                                 VARegSaveSize - VARegSize);
906      SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
907
908      SmallVector<SDOperand, 4> MemOps;
909      for (; NumGPRs < 4; ++NumGPRs) {
910        unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
911        MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
912        SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
913        SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
914        MemOps.push_back(Store);
915        FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
916                          DAG.getConstant(4, getPointerTy()));
917      }
918      if (!MemOps.empty())
919        Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
920                           &MemOps[0], MemOps.size());
921    } else
922      // This will point to the next argument passed via stack.
923      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
924  }
925
926  ArgValues.push_back(Root);
927
928  // Return the new list of results.
929  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
930                                    Op.Val->value_end());
931  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
932}
933
934/// isFloatingPointZero - Return true if this is +0.0.
935static bool isFloatingPointZero(SDOperand Op) {
936  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
937    return CFP->isExactlyValue(0.0);
938  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
939    // Maybe this has already been legalized into the constant pool?
940    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
941      SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
942      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
943        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
944          return CFP->isExactlyValue(0.0);
945    }
946  }
947  return false;
948}
949
950static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
951  return ( isThumb && (C & ~255U) == 0) ||
952         (!isThumb && ARM_AM::getSOImmVal(C) != -1);
953}
954
955/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
956/// the given operands.
957static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
958                           SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
959  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
960    unsigned C = RHSC->getValue();
961    if (!isLegalCmpImmediate(C, isThumb)) {
962      // Constant does not fit, try adjusting it by one?
963      switch (CC) {
964      default: break;
965      case ISD::SETLT:
966      case ISD::SETGE:
967        if (isLegalCmpImmediate(C-1, isThumb)) {
968          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
969          RHS = DAG.getConstant(C-1, MVT::i32);
970        }
971        break;
972      case ISD::SETULT:
973      case ISD::SETUGE:
974        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
975          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
976          RHS = DAG.getConstant(C-1, MVT::i32);
977        }
978        break;
979      case ISD::SETLE:
980      case ISD::SETGT:
981        if (isLegalCmpImmediate(C+1, isThumb)) {
982          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
983          RHS = DAG.getConstant(C+1, MVT::i32);
984        }
985        break;
986      case ISD::SETULE:
987      case ISD::SETUGT:
988        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
989          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
990          RHS = DAG.getConstant(C+1, MVT::i32);
991        }
992        break;
993      }
994    }
995  }
996
997  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
998  ARMISD::NodeType CompareType;
999  switch (CondCode) {
1000  default:
1001    CompareType = ARMISD::CMP;
1002    break;
1003  case ARMCC::EQ:
1004  case ARMCC::NE:
1005  case ARMCC::MI:
1006  case ARMCC::PL:
1007    // Uses only N and Z Flags
1008    CompareType = ARMISD::CMPNZ;
1009    break;
1010  }
1011  ARMCC = DAG.getConstant(CondCode, MVT::i32);
1012  return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1013}
1014
1015/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1016static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1017  SDOperand Cmp;
1018  if (!isFloatingPointZero(RHS))
1019    Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1020  else
1021    Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1022  return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1023}
1024
1025static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1026                                const ARMSubtarget *ST) {
1027  MVT::ValueType VT = Op.getValueType();
1028  SDOperand LHS = Op.getOperand(0);
1029  SDOperand RHS = Op.getOperand(1);
1030  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1031  SDOperand TrueVal = Op.getOperand(2);
1032  SDOperand FalseVal = Op.getOperand(3);
1033
1034  if (LHS.getValueType() == MVT::i32) {
1035    SDOperand ARMCC;
1036    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1037    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
1038  }
1039
1040  ARMCC::CondCodes CondCode, CondCode2;
1041  if (FPCCToARMCC(CC, CondCode, CondCode2))
1042    std::swap(TrueVal, FalseVal);
1043
1044  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1045  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1046  SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1047                                 ARMCC, Cmp);
1048  if (CondCode2 != ARMCC::AL) {
1049    SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1050    // FIXME: Needs another CMP because flag can have but one use.
1051    SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1052    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
1053  }
1054  return Result;
1055}
1056
1057static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1058                            const ARMSubtarget *ST) {
1059  SDOperand  Chain = Op.getOperand(0);
1060  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1061  SDOperand    LHS = Op.getOperand(2);
1062  SDOperand    RHS = Op.getOperand(3);
1063  SDOperand   Dest = Op.getOperand(4);
1064
1065  if (LHS.getValueType() == MVT::i32) {
1066    SDOperand ARMCC;
1067    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1068    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
1069  }
1070
1071  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1072  ARMCC::CondCodes CondCode, CondCode2;
1073  if (FPCCToARMCC(CC, CondCode, CondCode2))
1074    // Swap the LHS/RHS of the comparison if needed.
1075    std::swap(LHS, RHS);
1076
1077  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1078  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1079  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1080  SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
1081  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1082  if (CondCode2 != ARMCC::AL) {
1083    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1084    SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
1085    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1086  }
1087  return Res;
1088}
1089
1090SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1091  SDOperand Chain = Op.getOperand(0);
1092  SDOperand Table = Op.getOperand(1);
1093  SDOperand Index = Op.getOperand(2);
1094
1095  MVT::ValueType PTy = getPointerTy();
1096  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1097  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1098  SDOperand UId =  DAG.getConstant(AFI->createJumpTableUId(), PTy);
1099  SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1100  Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1101  Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1102  SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1103  bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1104  Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1105  Chain = Addr.getValue(1);
1106  if (isPIC)
1107    Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1108  return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1109}
1110
1111static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1112  unsigned Opc =
1113    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1114  Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1115  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1116}
1117
1118static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1119  MVT::ValueType VT = Op.getValueType();
1120  unsigned Opc =
1121    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1122
1123  Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1124  return DAG.getNode(Opc, VT, Op);
1125}
1126
1127static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1128  // Implement fcopysign with a fabs and a conditional fneg.
1129  SDOperand Tmp0 = Op.getOperand(0);
1130  SDOperand Tmp1 = Op.getOperand(1);
1131  MVT::ValueType VT = Op.getValueType();
1132  MVT::ValueType SrcVT = Tmp1.getValueType();
1133  SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1134  SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1135  SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1136  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
1137}
1138
1139static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
1140  // Turn f64->i64 into FMRRD.
1141  assert(Op.getValueType() == MVT::i64 &&
1142         Op.getOperand(0).getValueType() == MVT::f64);
1143
1144  Op = Op.getOperand(0);
1145  SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1146                              &Op, 1);
1147
1148  // Merge the pieces into a single i64 value.
1149  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
1150}
1151
1152static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1153  // FIXME: All this code is target-independent.  Create a new target-indep
1154  // MULHILO node and move this code to the legalizer.
1155  //
1156  assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
1157
1158  SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1159                             DAG.getConstant(0, MVT::i32));
1160  SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1161                             DAG.getConstant(0, MVT::i32));
1162
1163  const TargetLowering &TL = DAG.getTargetLoweringInfo();
1164  unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
1165  unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
1166
1167  SDOperand Lo, Hi;
1168  // Figure out how to lower this multiply.
1169  if (LHSSB >= 33 && RHSSB >= 33) {
1170    // If the input values are both sign extended, we can emit a mulhs+mul.
1171    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1172    Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
1173  } else if (LHSSB == 32 && RHSSB == 32 &&
1174             TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
1175             TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
1176    // If the inputs are zero extended, use mulhu.
1177    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1178    Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
1179  } else {
1180    SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1181                               DAG.getConstant(1, MVT::i32));
1182    SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1183                               DAG.getConstant(1, MVT::i32));
1184
1185    // Lo,Hi = umul LHS, RHS.
1186    SDOperand Ops[] = { LL, RL };
1187    SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
1188                                   DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
1189    Lo = UMul64;
1190    Hi = UMul64.getValue(1);
1191    RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
1192    LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
1193    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
1194    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
1195  }
1196
1197  // Merge the pieces into a single i64 value.
1198  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1199}
1200
1201static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
1202  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1203  return DAG.getNode(ARMISD::MULHILOU,
1204                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1205}
1206
1207static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
1208  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1209  return DAG.getNode(ARMISD::MULHILOS,
1210                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1211}
1212
1213static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
1214                          const ARMSubtarget *ST) {
1215  assert(Op.getValueType() == MVT::i64 &&
1216         (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
1217         "Unknown shift to lower!");
1218
1219  // We only lower SRA, SRL of 1 here, all others use generic lowering.
1220  if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
1221      cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
1222    return SDOperand();
1223
1224  // If we are in thumb mode, we don't have RRX.
1225  if (ST->isThumb()) return SDOperand();
1226
1227  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
1228  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1229                             DAG.getConstant(0, MVT::i32));
1230  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1231                             DAG.getConstant(1, MVT::i32));
1232
1233  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1234  // captures the result into a carry flag.
1235  unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1236  Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1237
1238  // The low part is an ARMISD::RRX operand, which shifts the carry in.
1239  Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1240
1241  // Merge the pieces into a single i64 value.
1242  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1243}
1244
1245SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1246  switch (Op.getOpcode()) {
1247  default: assert(0 && "Don't know how to custom lower this!"); abort();
1248  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
1249  case ISD::GlobalAddress:
1250    return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1251      LowerGlobalAddressELF(Op, DAG);
1252  case ISD::CALL:          return LowerCALL(Op, DAG);
1253  case ISD::RET:           return LowerRET(Op, DAG);
1254  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
1255  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
1256  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
1257  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1258  case ISD::SINT_TO_FP:
1259  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
1260  case ISD::FP_TO_SINT:
1261  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
1262  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
1263  case ISD::BIT_CONVERT:   return LowerBIT_CONVERT(Op, DAG);
1264  case ISD::MUL:           return LowerMUL(Op, DAG);
1265  case ISD::MULHU:         return LowerMULHU(Op, DAG);
1266  case ISD::MULHS:         return LowerMULHS(Op, DAG);
1267  case ISD::SRL:
1268  case ISD::SRA:           return LowerSRx(Op, DAG, Subtarget);
1269  case ISD::FORMAL_ARGUMENTS:
1270    return LowerFORMAL_ARGUMENTS(Op, DAG);
1271  case ISD::RETURNADDR:    break;
1272  case ISD::FRAMEADDR:     break;
1273  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1274  }
1275  return SDOperand();
1276}
1277
1278//===----------------------------------------------------------------------===//
1279//                           ARM Scheduler Hooks
1280//===----------------------------------------------------------------------===//
1281
1282MachineBasicBlock *
1283ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1284                                           MachineBasicBlock *BB) {
1285  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1286  switch (MI->getOpcode()) {
1287  default: assert(false && "Unexpected instr type to insert");
1288  case ARM::tMOVCCr: {
1289    // To "insert" a SELECT_CC instruction, we actually have to insert the
1290    // diamond control-flow pattern.  The incoming instruction knows the
1291    // destination vreg to set, the condition code register to branch on, the
1292    // true/false values to select between, and a branch opcode to use.
1293    const BasicBlock *LLVM_BB = BB->getBasicBlock();
1294    ilist<MachineBasicBlock>::iterator It = BB;
1295    ++It;
1296
1297    //  thisMBB:
1298    //  ...
1299    //   TrueVal = ...
1300    //   cmpTY ccX, r1, r2
1301    //   bCC copy1MBB
1302    //   fallthrough --> copy0MBB
1303    MachineBasicBlock *thisMBB  = BB;
1304    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1305    MachineBasicBlock *sinkMBB  = new MachineBasicBlock(LLVM_BB);
1306    BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1307      .addImm(MI->getOperand(3).getImm());
1308    MachineFunction *F = BB->getParent();
1309    F->getBasicBlockList().insert(It, copy0MBB);
1310    F->getBasicBlockList().insert(It, sinkMBB);
1311    // Update machine-CFG edges by first adding all successors of the current
1312    // block to the new block which will contain the Phi node for the select.
1313    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1314        e = BB->succ_end(); i != e; ++i)
1315      sinkMBB->addSuccessor(*i);
1316    // Next, remove all successors of the current block, and add the true
1317    // and fallthrough blocks as its successors.
1318    while(!BB->succ_empty())
1319      BB->removeSuccessor(BB->succ_begin());
1320    BB->addSuccessor(copy0MBB);
1321    BB->addSuccessor(sinkMBB);
1322
1323    //  copy0MBB:
1324    //   %FalseValue = ...
1325    //   # fallthrough to sinkMBB
1326    BB = copy0MBB;
1327
1328    // Update machine-CFG edges
1329    BB->addSuccessor(sinkMBB);
1330
1331    //  sinkMBB:
1332    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1333    //  ...
1334    BB = sinkMBB;
1335    BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1336      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1337      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1338
1339    delete MI;   // The pseudo instruction is gone now.
1340    return BB;
1341  }
1342  }
1343}
1344
1345//===----------------------------------------------------------------------===//
1346//                           ARM Optimization Hooks
1347//===----------------------------------------------------------------------===//
1348
1349/// isLegalAddressImmediate - Return true if the integer value can be used
1350/// as the offset of the target addressing mode for load / store of the
1351/// given type.
1352static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1353                                    const ARMSubtarget *Subtarget) {
1354  if (V == 0)
1355    return true;
1356
1357  if (Subtarget->isThumb()) {
1358    if (V < 0)
1359      return false;
1360
1361    unsigned Scale = 1;
1362    switch (VT) {
1363    default: return false;
1364    case MVT::i1:
1365    case MVT::i8:
1366      // Scale == 1;
1367      break;
1368    case MVT::i16:
1369      // Scale == 2;
1370      Scale = 2;
1371      break;
1372    case MVT::i32:
1373      // Scale == 4;
1374      Scale = 4;
1375      break;
1376    }
1377
1378    if ((V & (Scale - 1)) != 0)
1379      return false;
1380    V /= Scale;
1381    return V == V & ((1LL << 5) - 1);
1382  }
1383
1384  if (V < 0)
1385    V = - V;
1386  switch (VT) {
1387  default: return false;
1388  case MVT::i1:
1389  case MVT::i8:
1390  case MVT::i32:
1391    // +- imm12
1392    return V == V & ((1LL << 12) - 1);
1393  case MVT::i16:
1394    // +- imm8
1395    return V == V & ((1LL << 8) - 1);
1396  case MVT::f32:
1397  case MVT::f64:
1398    if (!Subtarget->hasVFP2())
1399      return false;
1400    if ((V % 3) != 0)
1401      return false;
1402    V >>= 2;
1403    return V == V & ((1LL << 8) - 1);
1404  }
1405}
1406
1407/// isLegalAddressingMode - Return true if the addressing mode represented
1408/// by AM is legal for this target, for a load/store of the specified type.
1409bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1410                                              const Type *Ty) const {
1411  if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1412    return false;
1413
1414  // Can never fold addr of global into load/store.
1415  if (AM.BaseGV)
1416    return false;
1417
1418  switch (AM.Scale) {
1419  case 0:  // no scale reg, must be "r+i" or "r", or "i".
1420    break;
1421  case 1:
1422    if (Subtarget->isThumb())
1423      return false;
1424    // FALL THROUGH.
1425  default:
1426    // ARM doesn't support any R+R*scale+imm addr modes.
1427    if (AM.BaseOffs)
1428      return false;
1429
1430    int Scale = AM.Scale;
1431    switch (getValueType(Ty)) {
1432    default: return false;
1433    case MVT::i1:
1434    case MVT::i8:
1435    case MVT::i32:
1436    case MVT::i64:
1437      // This assumes i64 is legalized to a pair of i32. If not (i.e.
1438      // ldrd / strd are used, then its address mode is same as i16.
1439      // r + r
1440      if (Scale < 0) Scale = -Scale;
1441      if (Scale == 1)
1442        return true;
1443      // r + r << imm
1444      return isPowerOf2_32(Scale & ~1);
1445    case MVT::i16:
1446      // r + r
1447      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1448        return true;
1449      return false;
1450
1451    case MVT::isVoid:
1452      // Note, we allow "void" uses (basically, uses that aren't loads or
1453      // stores), because arm allows folding a scale into many arithmetic
1454      // operations.  This should be made more precise and revisited later.
1455
1456      // Allow r << imm, but the imm has to be a multiple of two.
1457      if (AM.Scale & 1) return false;
1458      return isPowerOf2_32(AM.Scale);
1459    }
1460    break;
1461  }
1462  return true;
1463}
1464
1465
1466static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1467                                   bool isSEXTLoad, SDOperand &Base,
1468                                   SDOperand &Offset, bool &isInc,
1469                                   SelectionDAG &DAG) {
1470  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1471    return false;
1472
1473  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1474    // AddressingMode 3
1475    Base = Ptr->getOperand(0);
1476    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1477      int RHSC = (int)RHS->getValue();
1478      if (RHSC < 0 && RHSC > -256) {
1479        isInc = false;
1480        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1481        return true;
1482      }
1483    }
1484    isInc = (Ptr->getOpcode() == ISD::ADD);
1485    Offset = Ptr->getOperand(1);
1486    return true;
1487  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1488    // AddressingMode 2
1489    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1490      int RHSC = (int)RHS->getValue();
1491      if (RHSC < 0 && RHSC > -0x1000) {
1492        isInc = false;
1493        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1494        Base = Ptr->getOperand(0);
1495        return true;
1496      }
1497    }
1498
1499    if (Ptr->getOpcode() == ISD::ADD) {
1500      isInc = true;
1501      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1502      if (ShOpcVal != ARM_AM::no_shift) {
1503        Base = Ptr->getOperand(1);
1504        Offset = Ptr->getOperand(0);
1505      } else {
1506        Base = Ptr->getOperand(0);
1507        Offset = Ptr->getOperand(1);
1508      }
1509      return true;
1510    }
1511
1512    isInc = (Ptr->getOpcode() == ISD::ADD);
1513    Base = Ptr->getOperand(0);
1514    Offset = Ptr->getOperand(1);
1515    return true;
1516  }
1517
1518  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1519  return false;
1520}
1521
1522/// getPreIndexedAddressParts - returns true by value, base pointer and
1523/// offset pointer and addressing mode by reference if the node's address
1524/// can be legally represented as pre-indexed load / store address.
1525bool
1526ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1527                                             SDOperand &Offset,
1528                                             ISD::MemIndexedMode &AM,
1529                                             SelectionDAG &DAG) {
1530  if (Subtarget->isThumb())
1531    return false;
1532
1533  MVT::ValueType VT;
1534  SDOperand Ptr;
1535  bool isSEXTLoad = false;
1536  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1537    Ptr = LD->getBasePtr();
1538    VT  = LD->getLoadedVT();
1539    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1540  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1541    Ptr = ST->getBasePtr();
1542    VT  = ST->getStoredVT();
1543  } else
1544    return false;
1545
1546  bool isInc;
1547  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1548                                        isInc, DAG);
1549  if (isLegal) {
1550    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1551    return true;
1552  }
1553  return false;
1554}
1555
1556/// getPostIndexedAddressParts - returns true by value, base pointer and
1557/// offset pointer and addressing mode by reference if this node can be
1558/// combined with a load / store to form a post-indexed load / store.
1559bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1560                                                   SDOperand &Base,
1561                                                   SDOperand &Offset,
1562                                                   ISD::MemIndexedMode &AM,
1563                                                   SelectionDAG &DAG) {
1564  if (Subtarget->isThumb())
1565    return false;
1566
1567  MVT::ValueType VT;
1568  SDOperand Ptr;
1569  bool isSEXTLoad = false;
1570  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1571    VT  = LD->getLoadedVT();
1572    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1573  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1574    VT  = ST->getStoredVT();
1575  } else
1576    return false;
1577
1578  bool isInc;
1579  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1580                                        isInc, DAG);
1581  if (isLegal) {
1582    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1583    return true;
1584  }
1585  return false;
1586}
1587
1588void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1589                                                       uint64_t Mask,
1590                                                       uint64_t &KnownZero,
1591                                                       uint64_t &KnownOne,
1592                                                       unsigned Depth) const {
1593  KnownZero = 0;
1594  KnownOne = 0;
1595  switch (Op.getOpcode()) {
1596  default: break;
1597  case ARMISD::CMOV: {
1598    // Bits are known zero/one if known on the LHS and RHS.
1599    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1600    if (KnownZero == 0 && KnownOne == 0) return;
1601
1602    uint64_t KnownZeroRHS, KnownOneRHS;
1603    ComputeMaskedBits(Op.getOperand(1), Mask,
1604                      KnownZeroRHS, KnownOneRHS, Depth+1);
1605    KnownZero &= KnownZeroRHS;
1606    KnownOne  &= KnownOneRHS;
1607    return;
1608  }
1609  }
1610}
1611
1612//===----------------------------------------------------------------------===//
1613//                           ARM Inline Assembly Support
1614//===----------------------------------------------------------------------===//
1615
1616/// getConstraintType - Given a constraint letter, return the type of
1617/// constraint it is for this target.
1618ARMTargetLowering::ConstraintType
1619ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1620  if (Constraint.size() == 1) {
1621    switch (Constraint[0]) {
1622    default:  break;
1623    case 'l': return C_RegisterClass;
1624    case 'w': return C_RegisterClass;
1625    }
1626  }
1627  return TargetLowering::getConstraintType(Constraint);
1628}
1629
1630std::pair<unsigned, const TargetRegisterClass*>
1631ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1632                                                MVT::ValueType VT) const {
1633  if (Constraint.size() == 1) {
1634    // GCC RS6000 Constraint Letters
1635    switch (Constraint[0]) {
1636    case 'l':
1637    // FIXME: in thumb mode, 'l' is only low-regs.
1638    // FALL THROUGH.
1639    case 'r':
1640      return std::make_pair(0U, ARM::GPRRegisterClass);
1641    case 'w':
1642      if (VT == MVT::f32)
1643        return std::make_pair(0U, ARM::SPRRegisterClass);
1644      if (VT == MVT::f64)
1645        return std::make_pair(0U, ARM::DPRRegisterClass);
1646      break;
1647    }
1648  }
1649  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1650}
1651
1652std::vector<unsigned> ARMTargetLowering::
1653getRegClassForInlineAsmConstraint(const std::string &Constraint,
1654                                  MVT::ValueType VT) const {
1655  if (Constraint.size() != 1)
1656    return std::vector<unsigned>();
1657
1658  switch (Constraint[0]) {      // GCC ARM Constraint Letters
1659  default: break;
1660  case 'l':
1661  case 'r':
1662    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1663                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1664                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1665                                 ARM::R12, ARM::LR, 0);
1666  case 'w':
1667    if (VT == MVT::f32)
1668      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1669                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1670                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1671                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1672                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1673                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1674                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1675                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1676    if (VT == MVT::f64)
1677      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1678                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1679                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1680                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1681      break;
1682  }
1683
1684  return std::vector<unsigned>();
1685}
1686