ARMISelLowering.cpp revision 15a1a226be46dfaaa15c537daa9722b6216a981d
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMCallingConv.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "MCTargetDesc/ARMAddressingModes.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/IntrinsicLowering.h" 37#include "llvm/CodeGen/MachineBasicBlock.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/MC/MCSectionMachO.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/ADT/StringExtras.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/Support/CommandLine.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include <sstream> 55using namespace llvm; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 59 60// This option should go away when tail calls fully work. 61static cl::opt<bool> 62EnableARMTailCalls("arm-tail-calls", cl::Hidden, 63 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 64 cl::init(false)); 65 66cl::opt<bool> 67EnableARMLongCalls("arm-long-calls", cl::Hidden, 68 cl::desc("Generate calls via indirect call instructions"), 69 cl::init(false)); 70 71static cl::opt<bool> 72ARMInterworking("arm-interworking", cl::Hidden, 73 cl::desc("Enable / disable ARM interworking (for debugging only)"), 74 cl::init(true)); 75 76namespace llvm { 77 class ARMCCState : public CCState { 78 public: 79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 81 LLVMContext &C, ParmContext PC) 82 : CCState(CC, isVarArg, MF, TM, locs, C) { 83 assert(((PC == Call) || (PC == Prologue)) && 84 "ARMCCState users must specify whether their context is call" 85 "or prologue generation."); 86 CallOrPrologue = PC; 87 } 88 }; 89} 90 91// The APCS parameter registers. 92static const unsigned GPRArgRegs[] = { 93 ARM::R0, ARM::R1, ARM::R2, ARM::R3 94}; 95 96void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 97 EVT PromotedBitwiseVT) { 98 if (VT != PromotedLdStVT) { 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 105 PromotedLdStVT.getSimpleVT()); 106 } 107 108 EVT ElemTy = VT.getVectorElementType(); 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 112 if (ElemTy != MVT::i32) { 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 117 } 118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 124 if (VT.isInteger()) { 125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 132 setTruncStoreAction(VT.getSimpleVT(), 133 (MVT::SimpleValueType)InnerVT, Expand); 134 } 135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 136 137 // Promote all bit-wise operations. 138 if (VT.isInteger() && VT != PromotedBitwiseVT) { 139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 140 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 141 PromotedBitwiseVT.getSimpleVT()); 142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 143 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 144 PromotedBitwiseVT.getSimpleVT()); 145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 147 PromotedBitwiseVT.getSimpleVT()); 148 } 149 150 // Neon does not support vector divide/remainder operations. 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 157} 158 159void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 160 addRegisterClass(VT, ARM::DPRRegisterClass); 161 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 162} 163 164void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 165 addRegisterClass(VT, ARM::QPRRegisterClass); 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 167} 168 169static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 171 return new TargetLoweringObjectFileMachO(); 172 173 return new ARMElfTargetObjectFile(); 174} 175 176ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 177 : TargetLowering(TM, createTLOF(TM)) { 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 179 RegInfo = TM.getRegisterInfo(); 180 Itins = TM.getInstrItineraryData(); 181 182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 183 184 if (Subtarget->isTargetDarwin()) { 185 // Uses VFP for Thumb libfuncs if available. 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 187 // Single-precision floating-point arithmetic. 188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 192 193 // Double-precision floating-point arithmetic. 194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 198 199 // Single-precision comparisons. 200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 208 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 217 218 // Double-precision comparisons. 219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 227 228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 236 237 // Floating-point to integer conversions. 238 // i64 conversions are done via library routines even when generating VFP 239 // instructions, so use the same ones. 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 244 245 // Conversions between floating types. 246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 248 249 // Integer to floating-point conversions. 250 // i64 conversions are done via library routines even when generating VFP 251 // instructions, so use the same ones. 252 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 253 // e.g., __floatunsidf vs. __floatunssidfvfp. 254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 258 } 259 } 260 261 // These libcalls are not available in 32-bit. 262 setLibcallName(RTLIB::SHL_I128, 0); 263 setLibcallName(RTLIB::SRL_I128, 0); 264 setLibcallName(RTLIB::SRA_I128, 0); 265 266 if (Subtarget->isAAPCS_ABI()) { 267 // Double-precision floating-point arithmetic helper functions 268 // RTABI chapter 4.1.2, Table 2 269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 277 278 // Double-precision floating-point comparison helper functions 279 // RTABI chapter 4.1.2, Table 3 280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 304 305 // Single-precision floating-point arithmetic helper functions 306 // RTABI chapter 4.1.2, Table 4 307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 315 316 // Single-precision floating-point comparison helper functions 317 // RTABI chapter 4.1.2, Table 5 318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 342 343 // Floating-point to integer conversions. 344 // RTABI chapter 4.1.2, Table 6 345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 361 362 // Conversions between floating types. 363 // RTABI chapter 4.1.2, Table 7 364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 368 369 // Integer to floating-point conversions. 370 // RTABI chapter 4.1.2, Table 8 371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 387 388 // Long long helper functions 389 // RTABI chapter 4.2, Table 9 390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 402 403 // Integer division functions 404 // RTABI chapter 4.3.1 405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 } 424 425 // Use divmod compiler-rt calls for iOS 5.0 and later. 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 430 } 431 432 if (Subtarget->isThumb1Only()) 433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 434 else 435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 438 if (!Subtarget->isFPOnlySP()) 439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 440 441 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 442 } 443 444 if (Subtarget->hasNEON()) { 445 addDRTypeForNEON(MVT::v2f32); 446 addDRTypeForNEON(MVT::v8i8); 447 addDRTypeForNEON(MVT::v4i16); 448 addDRTypeForNEON(MVT::v2i32); 449 addDRTypeForNEON(MVT::v1i64); 450 451 addQRTypeForNEON(MVT::v4f32); 452 addQRTypeForNEON(MVT::v2f64); 453 addQRTypeForNEON(MVT::v16i8); 454 addQRTypeForNEON(MVT::v8i16); 455 addQRTypeForNEON(MVT::v4i32); 456 addQRTypeForNEON(MVT::v2i64); 457 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 459 // neither Neon nor VFP support any arithmetic operations on it. 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 468 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 484 485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 486 487 // Neon does not support some operations on v1i64 and v2i64 types. 488 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 489 // Custom handling for some quad-vector types to detect VMULL. 490 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 491 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 492 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 493 // Custom handling for some vector types to avoid expensive expansions 494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 501 // a destination type that is wider than the source. 502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 504 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); 506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 508 setTargetDAGCombine(ISD::SHL); 509 setTargetDAGCombine(ISD::SRL); 510 setTargetDAGCombine(ISD::SRA); 511 setTargetDAGCombine(ISD::SIGN_EXTEND); 512 setTargetDAGCombine(ISD::ZERO_EXTEND); 513 setTargetDAGCombine(ISD::ANY_EXTEND); 514 setTargetDAGCombine(ISD::SELECT_CC); 515 setTargetDAGCombine(ISD::BUILD_VECTOR); 516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 518 setTargetDAGCombine(ISD::STORE); 519 setTargetDAGCombine(ISD::FP_TO_SINT); 520 setTargetDAGCombine(ISD::FP_TO_UINT); 521 setTargetDAGCombine(ISD::FDIV); 522 523 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand); 524 } 525 526 computeRegisterProperties(); 527 528 // ARM does not have f32 extending load. 529 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 530 531 // ARM does not have i1 sign extending load. 532 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 533 534 // ARM supports all 4 flavors of integer indexed load / store. 535 if (!Subtarget->isThumb1Only()) { 536 for (unsigned im = (unsigned)ISD::PRE_INC; 537 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 538 setIndexedLoadAction(im, MVT::i1, Legal); 539 setIndexedLoadAction(im, MVT::i8, Legal); 540 setIndexedLoadAction(im, MVT::i16, Legal); 541 setIndexedLoadAction(im, MVT::i32, Legal); 542 setIndexedStoreAction(im, MVT::i1, Legal); 543 setIndexedStoreAction(im, MVT::i8, Legal); 544 setIndexedStoreAction(im, MVT::i16, Legal); 545 setIndexedStoreAction(im, MVT::i32, Legal); 546 } 547 } 548 549 // i64 operation support. 550 setOperationAction(ISD::MUL, MVT::i64, Expand); 551 setOperationAction(ISD::MULHU, MVT::i32, Expand); 552 if (Subtarget->isThumb1Only()) { 553 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 554 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 555 } 556 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 557 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 558 setOperationAction(ISD::MULHS, MVT::i32, Expand); 559 560 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 561 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 562 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 563 setOperationAction(ISD::SRL, MVT::i64, Custom); 564 setOperationAction(ISD::SRA, MVT::i64, Custom); 565 566 if (!Subtarget->isThumb1Only()) { 567 // FIXME: We should do this for Thumb1 as well. 568 setOperationAction(ISD::ADDC, MVT::i32, Custom); 569 setOperationAction(ISD::ADDE, MVT::i32, Custom); 570 setOperationAction(ISD::SUBC, MVT::i32, Custom); 571 setOperationAction(ISD::SUBE, MVT::i32, Custom); 572 } 573 574 // ARM does not have ROTL. 575 setOperationAction(ISD::ROTL, MVT::i32, Expand); 576 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 577 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 578 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 579 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 580 581 // Only ARMv6 has BSWAP. 582 if (!Subtarget->hasV6Ops()) 583 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 584 585 // These are expanded into libcalls. 586 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 587 // v7M has a hardware divider 588 setOperationAction(ISD::SDIV, MVT::i32, Expand); 589 setOperationAction(ISD::UDIV, MVT::i32, Expand); 590 } 591 setOperationAction(ISD::SREM, MVT::i32, Expand); 592 setOperationAction(ISD::UREM, MVT::i32, Expand); 593 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 594 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 595 596 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 597 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 598 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 599 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 600 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 601 602 setOperationAction(ISD::TRAP, MVT::Other, Legal); 603 604 // Use the default implementation. 605 setOperationAction(ISD::VASTART, MVT::Other, Custom); 606 setOperationAction(ISD::VAARG, MVT::Other, Expand); 607 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 608 setOperationAction(ISD::VAEND, MVT::Other, Expand); 609 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 610 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 611 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 612 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 613 setExceptionPointerRegister(ARM::R0); 614 setExceptionSelectorRegister(ARM::R1); 615 616 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 617 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 618 // the default expansion. 619 // FIXME: This should be checking for v6k, not just v6. 620 if (Subtarget->hasDataBarrier() || 621 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 622 // membarrier needs custom lowering; the rest are legal and handled 623 // normally. 624 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 625 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 626 // Custom lowering for 64-bit ops 627 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 628 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 629 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 630 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 631 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 632 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 633 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 634 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 635 setInsertFencesForAtomic(true); 636 } else { 637 // Set them all for expansion, which will force libcalls. 638 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 639 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 640 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 644 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 645 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 646 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 647 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 648 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 649 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 650 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 651 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 652 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 653 // Unordered/Monotonic case. 654 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 655 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 656 // Since the libcalls include locking, fold in the fences 657 setShouldFoldAtomicFences(true); 658 } 659 660 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 661 662 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 663 if (!Subtarget->hasV6Ops()) { 664 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 666 } 667 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 668 669 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 670 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 671 // iff target supports vfp2. 672 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 673 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 674 } 675 676 // We want to custom lower some of our intrinsics. 677 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 678 if (Subtarget->isTargetDarwin()) { 679 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 680 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 681 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 682 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 683 } 684 685 setOperationAction(ISD::SETCC, MVT::i32, Expand); 686 setOperationAction(ISD::SETCC, MVT::f32, Expand); 687 setOperationAction(ISD::SETCC, MVT::f64, Expand); 688 setOperationAction(ISD::SELECT, MVT::i32, Custom); 689 setOperationAction(ISD::SELECT, MVT::f32, Custom); 690 setOperationAction(ISD::SELECT, MVT::f64, Custom); 691 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 692 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 693 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 694 695 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 696 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 697 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 698 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 699 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 700 701 // We don't support sin/cos/fmod/copysign/pow 702 setOperationAction(ISD::FSIN, MVT::f64, Expand); 703 setOperationAction(ISD::FSIN, MVT::f32, Expand); 704 setOperationAction(ISD::FCOS, MVT::f32, Expand); 705 setOperationAction(ISD::FCOS, MVT::f64, Expand); 706 setOperationAction(ISD::FREM, MVT::f64, Expand); 707 setOperationAction(ISD::FREM, MVT::f32, Expand); 708 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 709 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 710 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 711 } 712 setOperationAction(ISD::FPOW, MVT::f64, Expand); 713 setOperationAction(ISD::FPOW, MVT::f32, Expand); 714 715 setOperationAction(ISD::FMA, MVT::f64, Expand); 716 setOperationAction(ISD::FMA, MVT::f32, Expand); 717 718 // Various VFP goodness 719 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 720 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 721 if (Subtarget->hasVFP2()) { 722 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 723 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 724 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 725 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 726 } 727 // Special handling for half-precision FP. 728 if (!Subtarget->hasFP16()) { 729 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 730 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 731 } 732 } 733 734 // We have target-specific dag combine patterns for the following nodes: 735 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 736 setTargetDAGCombine(ISD::ADD); 737 setTargetDAGCombine(ISD::SUB); 738 setTargetDAGCombine(ISD::MUL); 739 740 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 741 setTargetDAGCombine(ISD::OR); 742 if (Subtarget->hasNEON()) 743 setTargetDAGCombine(ISD::AND); 744 745 setStackPointerRegisterToSaveRestore(ARM::SP); 746 747 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 748 setSchedulingPreference(Sched::RegPressure); 749 else 750 setSchedulingPreference(Sched::Hybrid); 751 752 //// temporary - rewrite interface to use type 753 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 754 755 // On ARM arguments smaller than 4 bytes are extended, so all arguments 756 // are at least 4 bytes aligned. 757 setMinStackArgumentAlignment(4); 758 759 benefitFromCodePlacementOpt = true; 760 761 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 762} 763 764// FIXME: It might make sense to define the representative register class as the 765// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 766// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 767// SPR's representative would be DPR_VFP2. This should work well if register 768// pressure tracking were modified such that a register use would increment the 769// pressure of the register class's representative and all of it's super 770// classes' representatives transitively. We have not implemented this because 771// of the difficulty prior to coalescing of modeling operand register classes 772// due to the common occurrence of cross class copies and subregister insertions 773// and extractions. 774std::pair<const TargetRegisterClass*, uint8_t> 775ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 776 const TargetRegisterClass *RRC = 0; 777 uint8_t Cost = 1; 778 switch (VT.getSimpleVT().SimpleTy) { 779 default: 780 return TargetLowering::findRepresentativeClass(VT); 781 // Use DPR as representative register class for all floating point 782 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 783 // the cost is 1 for both f32 and f64. 784 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 785 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 786 RRC = ARM::DPRRegisterClass; 787 // When NEON is used for SP, only half of the register file is available 788 // because operations that define both SP and DP results will be constrained 789 // to the VFP2 class (D0-D15). We currently model this constraint prior to 790 // coalescing by double-counting the SP regs. See the FIXME above. 791 if (Subtarget->useNEONForSinglePrecisionFP()) 792 Cost = 2; 793 break; 794 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 795 case MVT::v4f32: case MVT::v2f64: 796 RRC = ARM::DPRRegisterClass; 797 Cost = 2; 798 break; 799 case MVT::v4i64: 800 RRC = ARM::DPRRegisterClass; 801 Cost = 4; 802 break; 803 case MVT::v8i64: 804 RRC = ARM::DPRRegisterClass; 805 Cost = 8; 806 break; 807 } 808 return std::make_pair(RRC, Cost); 809} 810 811const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 812 switch (Opcode) { 813 default: return 0; 814 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 815 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 816 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 817 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 818 case ARMISD::CALL: return "ARMISD::CALL"; 819 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 820 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 821 case ARMISD::tCALL: return "ARMISD::tCALL"; 822 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 823 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 824 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 825 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 826 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 827 case ARMISD::CMP: return "ARMISD::CMP"; 828 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 829 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 830 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 831 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 832 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 833 case ARMISD::CMOV: return "ARMISD::CMOV"; 834 835 case ARMISD::RBIT: return "ARMISD::RBIT"; 836 837 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 838 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 839 case ARMISD::SITOF: return "ARMISD::SITOF"; 840 case ARMISD::UITOF: return "ARMISD::UITOF"; 841 842 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 843 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 844 case ARMISD::RRX: return "ARMISD::RRX"; 845 846 case ARMISD::ADDC: return "ARMISD::ADDC"; 847 case ARMISD::ADDE: return "ARMISD::ADDE"; 848 case ARMISD::SUBC: return "ARMISD::SUBC"; 849 case ARMISD::SUBE: return "ARMISD::SUBE"; 850 851 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 852 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 853 854 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 855 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 856 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 857 858 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 859 860 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 861 862 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 863 864 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 865 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 866 867 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 868 869 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 870 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 871 case ARMISD::VCGE: return "ARMISD::VCGE"; 872 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 873 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 874 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 875 case ARMISD::VCGT: return "ARMISD::VCGT"; 876 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 877 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 878 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 879 case ARMISD::VTST: return "ARMISD::VTST"; 880 881 case ARMISD::VSHL: return "ARMISD::VSHL"; 882 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 883 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 884 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 885 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 886 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 887 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 888 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 889 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 890 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 891 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 892 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 893 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 894 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 895 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 896 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 897 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 898 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 899 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 900 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 901 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 902 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 903 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 904 case ARMISD::VDUP: return "ARMISD::VDUP"; 905 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 906 case ARMISD::VEXT: return "ARMISD::VEXT"; 907 case ARMISD::VREV64: return "ARMISD::VREV64"; 908 case ARMISD::VREV32: return "ARMISD::VREV32"; 909 case ARMISD::VREV16: return "ARMISD::VREV16"; 910 case ARMISD::VZIP: return "ARMISD::VZIP"; 911 case ARMISD::VUZP: return "ARMISD::VUZP"; 912 case ARMISD::VTRN: return "ARMISD::VTRN"; 913 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 914 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 915 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 916 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 917 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 918 case ARMISD::FMAX: return "ARMISD::FMAX"; 919 case ARMISD::FMIN: return "ARMISD::FMIN"; 920 case ARMISD::BFI: return "ARMISD::BFI"; 921 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 922 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 923 case ARMISD::VBSL: return "ARMISD::VBSL"; 924 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 925 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 926 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 927 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 928 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 929 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 930 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 931 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 932 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 933 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 934 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 935 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 936 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 937 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 938 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 939 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 940 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 941 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 942 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 943 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 944 } 945} 946 947EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 948 if (!VT.isVector()) return getPointerTy(); 949 return VT.changeVectorElementTypeToInteger(); 950} 951 952/// getRegClassFor - Return the register class that should be used for the 953/// specified value type. 954TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 955 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 956 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 957 // load / store 4 to 8 consecutive D registers. 958 if (Subtarget->hasNEON()) { 959 if (VT == MVT::v4i64) 960 return ARM::QQPRRegisterClass; 961 else if (VT == MVT::v8i64) 962 return ARM::QQQQPRRegisterClass; 963 } 964 return TargetLowering::getRegClassFor(VT); 965} 966 967// Create a fast isel object. 968FastISel * 969ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 970 return ARM::createFastISel(funcInfo); 971} 972 973/// getMaximalGlobalOffset - Returns the maximal possible offset which can 974/// be used for loads / stores from the global. 975unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 976 return (Subtarget->isThumb1Only() ? 127 : 4095); 977} 978 979Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 980 unsigned NumVals = N->getNumValues(); 981 if (!NumVals) 982 return Sched::RegPressure; 983 984 for (unsigned i = 0; i != NumVals; ++i) { 985 EVT VT = N->getValueType(i); 986 if (VT == MVT::Glue || VT == MVT::Other) 987 continue; 988 if (VT.isFloatingPoint() || VT.isVector()) 989 return Sched::Latency; 990 } 991 992 if (!N->isMachineOpcode()) 993 return Sched::RegPressure; 994 995 // Load are scheduled for latency even if there instruction itinerary 996 // is not available. 997 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 998 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 999 1000 if (MCID.getNumDefs() == 0) 1001 return Sched::RegPressure; 1002 if (!Itins->isEmpty() && 1003 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1004 return Sched::Latency; 1005 1006 return Sched::RegPressure; 1007} 1008 1009//===----------------------------------------------------------------------===// 1010// Lowering Code 1011//===----------------------------------------------------------------------===// 1012 1013/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1014static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1015 switch (CC) { 1016 default: llvm_unreachable("Unknown condition code!"); 1017 case ISD::SETNE: return ARMCC::NE; 1018 case ISD::SETEQ: return ARMCC::EQ; 1019 case ISD::SETGT: return ARMCC::GT; 1020 case ISD::SETGE: return ARMCC::GE; 1021 case ISD::SETLT: return ARMCC::LT; 1022 case ISD::SETLE: return ARMCC::LE; 1023 case ISD::SETUGT: return ARMCC::HI; 1024 case ISD::SETUGE: return ARMCC::HS; 1025 case ISD::SETULT: return ARMCC::LO; 1026 case ISD::SETULE: return ARMCC::LS; 1027 } 1028} 1029 1030/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1031static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1032 ARMCC::CondCodes &CondCode2) { 1033 CondCode2 = ARMCC::AL; 1034 switch (CC) { 1035 default: llvm_unreachable("Unknown FP condition!"); 1036 case ISD::SETEQ: 1037 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1038 case ISD::SETGT: 1039 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1040 case ISD::SETGE: 1041 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1042 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1043 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1044 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1045 case ISD::SETO: CondCode = ARMCC::VC; break; 1046 case ISD::SETUO: CondCode = ARMCC::VS; break; 1047 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1048 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1049 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1050 case ISD::SETLT: 1051 case ISD::SETULT: CondCode = ARMCC::LT; break; 1052 case ISD::SETLE: 1053 case ISD::SETULE: CondCode = ARMCC::LE; break; 1054 case ISD::SETNE: 1055 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1056 } 1057} 1058 1059//===----------------------------------------------------------------------===// 1060// Calling Convention Implementation 1061//===----------------------------------------------------------------------===// 1062 1063#include "ARMGenCallingConv.inc" 1064 1065/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1066/// given CallingConvention value. 1067CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1068 bool Return, 1069 bool isVarArg) const { 1070 switch (CC) { 1071 default: 1072 llvm_unreachable("Unsupported calling convention"); 1073 case CallingConv::Fast: 1074 if (Subtarget->hasVFP2() && !isVarArg) { 1075 if (!Subtarget->isAAPCS_ABI()) 1076 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1077 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1078 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1079 } 1080 // Fallthrough 1081 case CallingConv::C: { 1082 // Use target triple & subtarget features to do actual dispatch. 1083 if (!Subtarget->isAAPCS_ABI()) 1084 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1085 else if (Subtarget->hasVFP2() && 1086 FloatABIType == FloatABI::Hard && !isVarArg) 1087 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1088 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1089 } 1090 case CallingConv::ARM_AAPCS_VFP: 1091 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1092 case CallingConv::ARM_AAPCS: 1093 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1094 case CallingConv::ARM_APCS: 1095 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1096 } 1097} 1098 1099/// LowerCallResult - Lower the result values of a call into the 1100/// appropriate copies out of appropriate physical registers. 1101SDValue 1102ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1103 CallingConv::ID CallConv, bool isVarArg, 1104 const SmallVectorImpl<ISD::InputArg> &Ins, 1105 DebugLoc dl, SelectionDAG &DAG, 1106 SmallVectorImpl<SDValue> &InVals) const { 1107 1108 // Assign locations to each value returned by this call. 1109 SmallVector<CCValAssign, 16> RVLocs; 1110 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1111 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1112 CCInfo.AnalyzeCallResult(Ins, 1113 CCAssignFnForNode(CallConv, /* Return*/ true, 1114 isVarArg)); 1115 1116 // Copy all of the result registers out of their specified physreg. 1117 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1118 CCValAssign VA = RVLocs[i]; 1119 1120 SDValue Val; 1121 if (VA.needsCustom()) { 1122 // Handle f64 or half of a v2f64. 1123 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1124 InFlag); 1125 Chain = Lo.getValue(1); 1126 InFlag = Lo.getValue(2); 1127 VA = RVLocs[++i]; // skip ahead to next loc 1128 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1129 InFlag); 1130 Chain = Hi.getValue(1); 1131 InFlag = Hi.getValue(2); 1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1133 1134 if (VA.getLocVT() == MVT::v2f64) { 1135 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1137 DAG.getConstant(0, MVT::i32)); 1138 1139 VA = RVLocs[++i]; // skip ahead to next loc 1140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1141 Chain = Lo.getValue(1); 1142 InFlag = Lo.getValue(2); 1143 VA = RVLocs[++i]; // skip ahead to next loc 1144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1145 Chain = Hi.getValue(1); 1146 InFlag = Hi.getValue(2); 1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1149 DAG.getConstant(1, MVT::i32)); 1150 } 1151 } else { 1152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1153 InFlag); 1154 Chain = Val.getValue(1); 1155 InFlag = Val.getValue(2); 1156 } 1157 1158 switch (VA.getLocInfo()) { 1159 default: llvm_unreachable("Unknown loc info!"); 1160 case CCValAssign::Full: break; 1161 case CCValAssign::BCvt: 1162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1163 break; 1164 } 1165 1166 InVals.push_back(Val); 1167 } 1168 1169 return Chain; 1170} 1171 1172/// LowerMemOpCallTo - Store the argument to the stack. 1173SDValue 1174ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1175 SDValue StackPtr, SDValue Arg, 1176 DebugLoc dl, SelectionDAG &DAG, 1177 const CCValAssign &VA, 1178 ISD::ArgFlagsTy Flags) const { 1179 unsigned LocMemOffset = VA.getLocMemOffset(); 1180 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1181 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1182 return DAG.getStore(Chain, dl, Arg, PtrOff, 1183 MachinePointerInfo::getStack(LocMemOffset), 1184 false, false, 0); 1185} 1186 1187void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1188 SDValue Chain, SDValue &Arg, 1189 RegsToPassVector &RegsToPass, 1190 CCValAssign &VA, CCValAssign &NextVA, 1191 SDValue &StackPtr, 1192 SmallVector<SDValue, 8> &MemOpChains, 1193 ISD::ArgFlagsTy Flags) const { 1194 1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1196 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1197 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1198 1199 if (NextVA.isRegLoc()) 1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1201 else { 1202 assert(NextVA.isMemLoc()); 1203 if (StackPtr.getNode() == 0) 1204 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1205 1206 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1207 dl, DAG, NextVA, 1208 Flags)); 1209 } 1210} 1211 1212/// LowerCall - Lowering a call into a callseq_start <- 1213/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1214/// nodes. 1215SDValue 1216ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1217 CallingConv::ID CallConv, bool isVarArg, 1218 bool &isTailCall, 1219 const SmallVectorImpl<ISD::OutputArg> &Outs, 1220 const SmallVectorImpl<SDValue> &OutVals, 1221 const SmallVectorImpl<ISD::InputArg> &Ins, 1222 DebugLoc dl, SelectionDAG &DAG, 1223 SmallVectorImpl<SDValue> &InVals) const { 1224 MachineFunction &MF = DAG.getMachineFunction(); 1225 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1226 bool IsSibCall = false; 1227 // Disable tail calls if they're not supported. 1228 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1229 isTailCall = false; 1230 if (isTailCall) { 1231 // Check if it's really possible to do a tail call. 1232 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1233 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1234 Outs, OutVals, Ins, DAG); 1235 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1236 // detected sibcalls. 1237 if (isTailCall) { 1238 ++NumTailCalls; 1239 IsSibCall = true; 1240 } 1241 } 1242 1243 // Analyze operands of the call, assigning locations to each operand. 1244 SmallVector<CCValAssign, 16> ArgLocs; 1245 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1246 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1247 CCInfo.AnalyzeCallOperands(Outs, 1248 CCAssignFnForNode(CallConv, /* Return*/ false, 1249 isVarArg)); 1250 1251 // Get a count of how many bytes are to be pushed on the stack. 1252 unsigned NumBytes = CCInfo.getNextStackOffset(); 1253 1254 // For tail calls, memory operands are available in our caller's stack. 1255 if (IsSibCall) 1256 NumBytes = 0; 1257 1258 // Adjust the stack pointer for the new arguments... 1259 // These operations are automatically eliminated by the prolog/epilog pass 1260 if (!IsSibCall) 1261 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1262 1263 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1264 1265 RegsToPassVector RegsToPass; 1266 SmallVector<SDValue, 8> MemOpChains; 1267 1268 // Walk the register/memloc assignments, inserting copies/loads. In the case 1269 // of tail call optimization, arguments are handled later. 1270 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1271 i != e; 1272 ++i, ++realArgIdx) { 1273 CCValAssign &VA = ArgLocs[i]; 1274 SDValue Arg = OutVals[realArgIdx]; 1275 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1276 bool isByVal = Flags.isByVal(); 1277 1278 // Promote the value if needed. 1279 switch (VA.getLocInfo()) { 1280 default: llvm_unreachable("Unknown loc info!"); 1281 case CCValAssign::Full: break; 1282 case CCValAssign::SExt: 1283 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1284 break; 1285 case CCValAssign::ZExt: 1286 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1287 break; 1288 case CCValAssign::AExt: 1289 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1290 break; 1291 case CCValAssign::BCvt: 1292 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1293 break; 1294 } 1295 1296 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1297 if (VA.needsCustom()) { 1298 if (VA.getLocVT() == MVT::v2f64) { 1299 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1300 DAG.getConstant(0, MVT::i32)); 1301 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1302 DAG.getConstant(1, MVT::i32)); 1303 1304 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1305 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1306 1307 VA = ArgLocs[++i]; // skip ahead to next loc 1308 if (VA.isRegLoc()) { 1309 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1310 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1311 } else { 1312 assert(VA.isMemLoc()); 1313 1314 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1315 dl, DAG, VA, Flags)); 1316 } 1317 } else { 1318 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1319 StackPtr, MemOpChains, Flags); 1320 } 1321 } else if (VA.isRegLoc()) { 1322 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1323 } else if (isByVal) { 1324 assert(VA.isMemLoc()); 1325 unsigned offset = 0; 1326 1327 // True if this byval aggregate will be split between registers 1328 // and memory. 1329 if (CCInfo.isFirstByValRegValid()) { 1330 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1331 unsigned int i, j; 1332 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1333 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1334 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1335 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1336 MachinePointerInfo(), 1337 false, false, 0); 1338 MemOpChains.push_back(Load.getValue(1)); 1339 RegsToPass.push_back(std::make_pair(j, Load)); 1340 } 1341 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1342 CCInfo.clearFirstByValReg(); 1343 } 1344 1345 unsigned LocMemOffset = VA.getLocMemOffset(); 1346 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1347 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1348 StkPtrOff); 1349 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1350 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1351 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1352 MVT::i32); 1353 // TODO: Disable AlwaysInline when it becomes possible 1354 // to emit a nested call sequence. 1355 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1356 Flags.getByValAlign(), 1357 /*isVolatile=*/false, 1358 /*AlwaysInline=*/true, 1359 MachinePointerInfo(0), 1360 MachinePointerInfo(0))); 1361 1362 } else if (!IsSibCall) { 1363 assert(VA.isMemLoc()); 1364 1365 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1366 dl, DAG, VA, Flags)); 1367 } 1368 } 1369 1370 if (!MemOpChains.empty()) 1371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1372 &MemOpChains[0], MemOpChains.size()); 1373 1374 // Build a sequence of copy-to-reg nodes chained together with token chain 1375 // and flag operands which copy the outgoing args into the appropriate regs. 1376 SDValue InFlag; 1377 // Tail call byval lowering might overwrite argument registers so in case of 1378 // tail call optimization the copies to registers are lowered later. 1379 if (!isTailCall) 1380 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1381 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1382 RegsToPass[i].second, InFlag); 1383 InFlag = Chain.getValue(1); 1384 } 1385 1386 // For tail calls lower the arguments to the 'real' stack slot. 1387 if (isTailCall) { 1388 // Force all the incoming stack arguments to be loaded from the stack 1389 // before any new outgoing arguments are stored to the stack, because the 1390 // outgoing stack slots may alias the incoming argument stack slots, and 1391 // the alias isn't otherwise explicit. This is slightly more conservative 1392 // than necessary, because it means that each store effectively depends 1393 // on every argument instead of just those arguments it would clobber. 1394 1395 // Do not flag preceding copytoreg stuff together with the following stuff. 1396 InFlag = SDValue(); 1397 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1398 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1399 RegsToPass[i].second, InFlag); 1400 InFlag = Chain.getValue(1); 1401 } 1402 InFlag =SDValue(); 1403 } 1404 1405 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1406 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1407 // node so that legalize doesn't hack it. 1408 bool isDirect = false; 1409 bool isARMFunc = false; 1410 bool isLocalARMFunc = false; 1411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1412 1413 if (EnableARMLongCalls) { 1414 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1415 && "long-calls with non-static relocation model!"); 1416 // Handle a global address or an external symbol. If it's not one of 1417 // those, the target's already in a register, so we don't need to do 1418 // anything extra. 1419 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1420 const GlobalValue *GV = G->getGlobal(); 1421 // Create a constant pool entry for the callee address 1422 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1423 ARMConstantPoolValue *CPV = 1424 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1425 1426 // Get the address of the callee into a register 1427 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1428 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1429 Callee = DAG.getLoad(getPointerTy(), dl, 1430 DAG.getEntryNode(), CPAddr, 1431 MachinePointerInfo::getConstantPool(), 1432 false, false, 0); 1433 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1434 const char *Sym = S->getSymbol(); 1435 1436 // Create a constant pool entry for the callee address 1437 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1438 ARMConstantPoolValue *CPV = 1439 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1440 ARMPCLabelIndex, 0); 1441 // Get the address of the callee into a register 1442 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1443 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1444 Callee = DAG.getLoad(getPointerTy(), dl, 1445 DAG.getEntryNode(), CPAddr, 1446 MachinePointerInfo::getConstantPool(), 1447 false, false, 0); 1448 } 1449 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1450 const GlobalValue *GV = G->getGlobal(); 1451 isDirect = true; 1452 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1453 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1454 getTargetMachine().getRelocationModel() != Reloc::Static; 1455 isARMFunc = !Subtarget->isThumb() || isStub; 1456 // ARM call to a local ARM function is predicable. 1457 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1458 // tBX takes a register source operand. 1459 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1460 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1461 ARMConstantPoolValue *CPV = 1462 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1463 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1464 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1465 Callee = DAG.getLoad(getPointerTy(), dl, 1466 DAG.getEntryNode(), CPAddr, 1467 MachinePointerInfo::getConstantPool(), 1468 false, false, 0); 1469 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1470 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1471 getPointerTy(), Callee, PICLabel); 1472 } else { 1473 // On ELF targets for PIC code, direct calls should go through the PLT 1474 unsigned OpFlags = 0; 1475 if (Subtarget->isTargetELF() && 1476 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1477 OpFlags = ARMII::MO_PLT; 1478 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1479 } 1480 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1481 isDirect = true; 1482 bool isStub = Subtarget->isTargetDarwin() && 1483 getTargetMachine().getRelocationModel() != Reloc::Static; 1484 isARMFunc = !Subtarget->isThumb() || isStub; 1485 // tBX takes a register source operand. 1486 const char *Sym = S->getSymbol(); 1487 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1488 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1489 ARMConstantPoolValue *CPV = 1490 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1491 ARMPCLabelIndex, 4); 1492 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1493 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1494 Callee = DAG.getLoad(getPointerTy(), dl, 1495 DAG.getEntryNode(), CPAddr, 1496 MachinePointerInfo::getConstantPool(), 1497 false, false, 0); 1498 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1499 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1500 getPointerTy(), Callee, PICLabel); 1501 } else { 1502 unsigned OpFlags = 0; 1503 // On ELF targets for PIC code, direct calls should go through the PLT 1504 if (Subtarget->isTargetELF() && 1505 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1506 OpFlags = ARMII::MO_PLT; 1507 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1508 } 1509 } 1510 1511 // FIXME: handle tail calls differently. 1512 unsigned CallOpc; 1513 if (Subtarget->isThumb()) { 1514 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1515 CallOpc = ARMISD::CALL_NOLINK; 1516 else 1517 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1518 } else { 1519 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1520 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1521 : ARMISD::CALL_NOLINK; 1522 } 1523 1524 std::vector<SDValue> Ops; 1525 Ops.push_back(Chain); 1526 Ops.push_back(Callee); 1527 1528 // Add argument registers to the end of the list so that they are known live 1529 // into the call. 1530 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1531 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1532 RegsToPass[i].second.getValueType())); 1533 1534 if (InFlag.getNode()) 1535 Ops.push_back(InFlag); 1536 1537 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1538 if (isTailCall) 1539 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1540 1541 // Returns a chain and a flag for retval copy to use. 1542 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1543 InFlag = Chain.getValue(1); 1544 1545 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1546 DAG.getIntPtrConstant(0, true), InFlag); 1547 if (!Ins.empty()) 1548 InFlag = Chain.getValue(1); 1549 1550 // Handle result values, copying them out of physregs into vregs that we 1551 // return. 1552 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1553 dl, DAG, InVals); 1554} 1555 1556/// HandleByVal - Every parameter *after* a byval parameter is passed 1557/// on the stack. Remember the next parameter register to allocate, 1558/// and then confiscate the rest of the parameter registers to insure 1559/// this. 1560void 1561llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1562 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1563 assert((State->getCallOrPrologue() == Prologue || 1564 State->getCallOrPrologue() == Call) && 1565 "unhandled ParmContext"); 1566 if ((!State->isFirstByValRegValid()) && 1567 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1568 State->setFirstByValReg(reg); 1569 // At a call site, a byval parameter that is split between 1570 // registers and memory needs its size truncated here. In a 1571 // function prologue, such byval parameters are reassembled in 1572 // memory, and are not truncated. 1573 if (State->getCallOrPrologue() == Call) { 1574 unsigned excess = 4 * (ARM::R4 - reg); 1575 assert(size >= excess && "expected larger existing stack allocation"); 1576 size -= excess; 1577 } 1578 } 1579 // Confiscate any remaining parameter registers to preclude their 1580 // assignment to subsequent parameters. 1581 while (State->AllocateReg(GPRArgRegs, 4)) 1582 ; 1583} 1584 1585/// MatchingStackOffset - Return true if the given stack call argument is 1586/// already available in the same position (relatively) of the caller's 1587/// incoming argument stack. 1588static 1589bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1590 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1591 const ARMInstrInfo *TII) { 1592 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1593 int FI = INT_MAX; 1594 if (Arg.getOpcode() == ISD::CopyFromReg) { 1595 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1596 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1597 return false; 1598 MachineInstr *Def = MRI->getVRegDef(VR); 1599 if (!Def) 1600 return false; 1601 if (!Flags.isByVal()) { 1602 if (!TII->isLoadFromStackSlot(Def, FI)) 1603 return false; 1604 } else { 1605 return false; 1606 } 1607 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1608 if (Flags.isByVal()) 1609 // ByVal argument is passed in as a pointer but it's now being 1610 // dereferenced. e.g. 1611 // define @foo(%struct.X* %A) { 1612 // tail call @bar(%struct.X* byval %A) 1613 // } 1614 return false; 1615 SDValue Ptr = Ld->getBasePtr(); 1616 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1617 if (!FINode) 1618 return false; 1619 FI = FINode->getIndex(); 1620 } else 1621 return false; 1622 1623 assert(FI != INT_MAX); 1624 if (!MFI->isFixedObjectIndex(FI)) 1625 return false; 1626 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1627} 1628 1629/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1630/// for tail call optimization. Targets which want to do tail call 1631/// optimization should implement this function. 1632bool 1633ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1634 CallingConv::ID CalleeCC, 1635 bool isVarArg, 1636 bool isCalleeStructRet, 1637 bool isCallerStructRet, 1638 const SmallVectorImpl<ISD::OutputArg> &Outs, 1639 const SmallVectorImpl<SDValue> &OutVals, 1640 const SmallVectorImpl<ISD::InputArg> &Ins, 1641 SelectionDAG& DAG) const { 1642 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1643 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1644 bool CCMatch = CallerCC == CalleeCC; 1645 1646 // Look for obvious safe cases to perform tail call optimization that do not 1647 // require ABI changes. This is what gcc calls sibcall. 1648 1649 // Do not sibcall optimize vararg calls unless the call site is not passing 1650 // any arguments. 1651 if (isVarArg && !Outs.empty()) 1652 return false; 1653 1654 // Also avoid sibcall optimization if either caller or callee uses struct 1655 // return semantics. 1656 if (isCalleeStructRet || isCallerStructRet) 1657 return false; 1658 1659 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1660 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1661 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1662 // support in the assembler and linker to be used. This would need to be 1663 // fixed to fully support tail calls in Thumb1. 1664 // 1665 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1666 // LR. This means if we need to reload LR, it takes an extra instructions, 1667 // which outweighs the value of the tail call; but here we don't know yet 1668 // whether LR is going to be used. Probably the right approach is to 1669 // generate the tail call here and turn it back into CALL/RET in 1670 // emitEpilogue if LR is used. 1671 1672 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1673 // but we need to make sure there are enough registers; the only valid 1674 // registers are the 4 used for parameters. We don't currently do this 1675 // case. 1676 if (Subtarget->isThumb1Only()) 1677 return false; 1678 1679 // If the calling conventions do not match, then we'd better make sure the 1680 // results are returned in the same way as what the caller expects. 1681 if (!CCMatch) { 1682 SmallVector<CCValAssign, 16> RVLocs1; 1683 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1684 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1685 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1686 1687 SmallVector<CCValAssign, 16> RVLocs2; 1688 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1689 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1690 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1691 1692 if (RVLocs1.size() != RVLocs2.size()) 1693 return false; 1694 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1695 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1696 return false; 1697 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1698 return false; 1699 if (RVLocs1[i].isRegLoc()) { 1700 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1701 return false; 1702 } else { 1703 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1704 return false; 1705 } 1706 } 1707 } 1708 1709 // If the callee takes no arguments then go on to check the results of the 1710 // call. 1711 if (!Outs.empty()) { 1712 // Check if stack adjustment is needed. For now, do not do this if any 1713 // argument is passed on the stack. 1714 SmallVector<CCValAssign, 16> ArgLocs; 1715 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1716 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1717 CCInfo.AnalyzeCallOperands(Outs, 1718 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1719 if (CCInfo.getNextStackOffset()) { 1720 MachineFunction &MF = DAG.getMachineFunction(); 1721 1722 // Check if the arguments are already laid out in the right way as 1723 // the caller's fixed stack objects. 1724 MachineFrameInfo *MFI = MF.getFrameInfo(); 1725 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1726 const ARMInstrInfo *TII = 1727 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1728 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1729 i != e; 1730 ++i, ++realArgIdx) { 1731 CCValAssign &VA = ArgLocs[i]; 1732 EVT RegVT = VA.getLocVT(); 1733 SDValue Arg = OutVals[realArgIdx]; 1734 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1735 if (VA.getLocInfo() == CCValAssign::Indirect) 1736 return false; 1737 if (VA.needsCustom()) { 1738 // f64 and vector types are split into multiple registers or 1739 // register/stack-slot combinations. The types will not match 1740 // the registers; give up on memory f64 refs until we figure 1741 // out what to do about this. 1742 if (!VA.isRegLoc()) 1743 return false; 1744 if (!ArgLocs[++i].isRegLoc()) 1745 return false; 1746 if (RegVT == MVT::v2f64) { 1747 if (!ArgLocs[++i].isRegLoc()) 1748 return false; 1749 if (!ArgLocs[++i].isRegLoc()) 1750 return false; 1751 } 1752 } else if (!VA.isRegLoc()) { 1753 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1754 MFI, MRI, TII)) 1755 return false; 1756 } 1757 } 1758 } 1759 } 1760 1761 return true; 1762} 1763 1764SDValue 1765ARMTargetLowering::LowerReturn(SDValue Chain, 1766 CallingConv::ID CallConv, bool isVarArg, 1767 const SmallVectorImpl<ISD::OutputArg> &Outs, 1768 const SmallVectorImpl<SDValue> &OutVals, 1769 DebugLoc dl, SelectionDAG &DAG) const { 1770 1771 // CCValAssign - represent the assignment of the return value to a location. 1772 SmallVector<CCValAssign, 16> RVLocs; 1773 1774 // CCState - Info about the registers and stack slots. 1775 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1776 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1777 1778 // Analyze outgoing return values. 1779 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1780 isVarArg)); 1781 1782 // If this is the first return lowered for this function, add 1783 // the regs to the liveout set for the function. 1784 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1785 for (unsigned i = 0; i != RVLocs.size(); ++i) 1786 if (RVLocs[i].isRegLoc()) 1787 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1788 } 1789 1790 SDValue Flag; 1791 1792 // Copy the result values into the output registers. 1793 for (unsigned i = 0, realRVLocIdx = 0; 1794 i != RVLocs.size(); 1795 ++i, ++realRVLocIdx) { 1796 CCValAssign &VA = RVLocs[i]; 1797 assert(VA.isRegLoc() && "Can only return in registers!"); 1798 1799 SDValue Arg = OutVals[realRVLocIdx]; 1800 1801 switch (VA.getLocInfo()) { 1802 default: llvm_unreachable("Unknown loc info!"); 1803 case CCValAssign::Full: break; 1804 case CCValAssign::BCvt: 1805 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1806 break; 1807 } 1808 1809 if (VA.needsCustom()) { 1810 if (VA.getLocVT() == MVT::v2f64) { 1811 // Extract the first half and return it in two registers. 1812 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1813 DAG.getConstant(0, MVT::i32)); 1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1815 DAG.getVTList(MVT::i32, MVT::i32), Half); 1816 1817 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1818 Flag = Chain.getValue(1); 1819 VA = RVLocs[++i]; // skip ahead to next loc 1820 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1821 HalfGPRs.getValue(1), Flag); 1822 Flag = Chain.getValue(1); 1823 VA = RVLocs[++i]; // skip ahead to next loc 1824 1825 // Extract the 2nd half and fall through to handle it as an f64 value. 1826 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1827 DAG.getConstant(1, MVT::i32)); 1828 } 1829 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1830 // available. 1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1832 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1833 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1834 Flag = Chain.getValue(1); 1835 VA = RVLocs[++i]; // skip ahead to next loc 1836 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1837 Flag); 1838 } else 1839 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1840 1841 // Guarantee that all emitted copies are 1842 // stuck together, avoiding something bad. 1843 Flag = Chain.getValue(1); 1844 } 1845 1846 SDValue result; 1847 if (Flag.getNode()) 1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1849 else // Return Void 1850 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1851 1852 return result; 1853} 1854 1855bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1856 if (N->getNumValues() != 1) 1857 return false; 1858 if (!N->hasNUsesOfValue(1, 0)) 1859 return false; 1860 1861 unsigned NumCopies = 0; 1862 SDNode* Copies[2]; 1863 SDNode *Use = *N->use_begin(); 1864 if (Use->getOpcode() == ISD::CopyToReg) { 1865 Copies[NumCopies++] = Use; 1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1867 // f64 returned in a pair of GPRs. 1868 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1869 UI != UE; ++UI) { 1870 if (UI->getOpcode() != ISD::CopyToReg) 1871 return false; 1872 Copies[UI.getUse().getResNo()] = *UI; 1873 ++NumCopies; 1874 } 1875 } else if (Use->getOpcode() == ISD::BITCAST) { 1876 // f32 returned in a single GPR. 1877 if (!Use->hasNUsesOfValue(1, 0)) 1878 return false; 1879 Use = *Use->use_begin(); 1880 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1881 return false; 1882 Copies[NumCopies++] = Use; 1883 } else { 1884 return false; 1885 } 1886 1887 if (NumCopies != 1 && NumCopies != 2) 1888 return false; 1889 1890 bool HasRet = false; 1891 for (unsigned i = 0; i < NumCopies; ++i) { 1892 SDNode *Copy = Copies[i]; 1893 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1894 UI != UE; ++UI) { 1895 if (UI->getOpcode() == ISD::CopyToReg) { 1896 SDNode *Use = *UI; 1897 if (Use == Copies[0] || Use == Copies[1]) 1898 continue; 1899 return false; 1900 } 1901 if (UI->getOpcode() != ARMISD::RET_FLAG) 1902 return false; 1903 HasRet = true; 1904 } 1905 } 1906 1907 return HasRet; 1908} 1909 1910bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1911 if (!EnableARMTailCalls) 1912 return false; 1913 1914 if (!CI->isTailCall()) 1915 return false; 1916 1917 return !Subtarget->isThumb1Only(); 1918} 1919 1920// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1921// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1922// one of the above mentioned nodes. It has to be wrapped because otherwise 1923// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1924// be used to form addressing mode. These wrapped nodes will be selected 1925// into MOVi. 1926static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1927 EVT PtrVT = Op.getValueType(); 1928 // FIXME there is no actual debug info here 1929 DebugLoc dl = Op.getDebugLoc(); 1930 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1931 SDValue Res; 1932 if (CP->isMachineConstantPoolEntry()) 1933 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1934 CP->getAlignment()); 1935 else 1936 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1937 CP->getAlignment()); 1938 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1939} 1940 1941unsigned ARMTargetLowering::getJumpTableEncoding() const { 1942 return MachineJumpTableInfo::EK_Inline; 1943} 1944 1945SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1946 SelectionDAG &DAG) const { 1947 MachineFunction &MF = DAG.getMachineFunction(); 1948 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1949 unsigned ARMPCLabelIndex = 0; 1950 DebugLoc DL = Op.getDebugLoc(); 1951 EVT PtrVT = getPointerTy(); 1952 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1953 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1954 SDValue CPAddr; 1955 if (RelocM == Reloc::Static) { 1956 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1957 } else { 1958 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1959 ARMPCLabelIndex = AFI->createPICLabelUId(); 1960 ARMConstantPoolValue *CPV = 1961 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 1962 ARMCP::CPBlockAddress, PCAdj); 1963 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1964 } 1965 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1966 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1967 MachinePointerInfo::getConstantPool(), 1968 false, false, 0); 1969 if (RelocM == Reloc::Static) 1970 return Result; 1971 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1972 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1973} 1974 1975// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1976SDValue 1977ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1978 SelectionDAG &DAG) const { 1979 DebugLoc dl = GA->getDebugLoc(); 1980 EVT PtrVT = getPointerTy(); 1981 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1982 MachineFunction &MF = DAG.getMachineFunction(); 1983 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1984 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1985 ARMConstantPoolValue *CPV = 1986 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 1987 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1988 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1989 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1990 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1991 MachinePointerInfo::getConstantPool(), 1992 false, false, 0); 1993 SDValue Chain = Argument.getValue(1); 1994 1995 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1996 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1997 1998 // call __tls_get_addr. 1999 ArgListTy Args; 2000 ArgListEntry Entry; 2001 Entry.Node = Argument; 2002 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2003 Args.push_back(Entry); 2004 // FIXME: is there useful debug info available here? 2005 std::pair<SDValue, SDValue> CallResult = 2006 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2007 false, false, false, false, 2008 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2009 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2010 return CallResult.first; 2011} 2012 2013// Lower ISD::GlobalTLSAddress using the "initial exec" or 2014// "local exec" model. 2015SDValue 2016ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2017 SelectionDAG &DAG) const { 2018 const GlobalValue *GV = GA->getGlobal(); 2019 DebugLoc dl = GA->getDebugLoc(); 2020 SDValue Offset; 2021 SDValue Chain = DAG.getEntryNode(); 2022 EVT PtrVT = getPointerTy(); 2023 // Get the Thread Pointer 2024 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2025 2026 if (GV->isDeclaration()) { 2027 MachineFunction &MF = DAG.getMachineFunction(); 2028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2029 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2030 // Initial exec model. 2031 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2032 ARMConstantPoolValue *CPV = 2033 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2034 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2035 true); 2036 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2037 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2038 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2039 MachinePointerInfo::getConstantPool(), 2040 false, false, 0); 2041 Chain = Offset.getValue(1); 2042 2043 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2044 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2045 2046 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2047 MachinePointerInfo::getConstantPool(), 2048 false, false, 0); 2049 } else { 2050 // local exec model 2051 ARMConstantPoolValue *CPV = 2052 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2053 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2054 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2055 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2056 MachinePointerInfo::getConstantPool(), 2057 false, false, 0); 2058 } 2059 2060 // The address of the thread local variable is the add of the thread 2061 // pointer with the offset of the variable. 2062 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2063} 2064 2065SDValue 2066ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2067 // TODO: implement the "local dynamic" model 2068 assert(Subtarget->isTargetELF() && 2069 "TLS not implemented for non-ELF targets"); 2070 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2071 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2072 // otherwise use the "Local Exec" TLS Model 2073 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2074 return LowerToTLSGeneralDynamicModel(GA, DAG); 2075 else 2076 return LowerToTLSExecModels(GA, DAG); 2077} 2078 2079SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2080 SelectionDAG &DAG) const { 2081 EVT PtrVT = getPointerTy(); 2082 DebugLoc dl = Op.getDebugLoc(); 2083 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2084 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2085 if (RelocM == Reloc::PIC_) { 2086 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2087 ARMConstantPoolValue *CPV = 2088 ARMConstantPoolConstant::Create(GV, 2089 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2090 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2091 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2092 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2093 CPAddr, 2094 MachinePointerInfo::getConstantPool(), 2095 false, false, 0); 2096 SDValue Chain = Result.getValue(1); 2097 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2098 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2099 if (!UseGOTOFF) 2100 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2101 MachinePointerInfo::getGOT(), false, false, 0); 2102 return Result; 2103 } 2104 2105 // If we have T2 ops, we can materialize the address directly via movt/movw 2106 // pair. This is always cheaper. 2107 if (Subtarget->useMovt()) { 2108 ++NumMovwMovt; 2109 // FIXME: Once remat is capable of dealing with instructions with register 2110 // operands, expand this into two nodes. 2111 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2112 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2113 } else { 2114 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2115 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2116 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2117 MachinePointerInfo::getConstantPool(), 2118 false, false, 0); 2119 } 2120} 2121 2122SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2123 SelectionDAG &DAG) const { 2124 EVT PtrVT = getPointerTy(); 2125 DebugLoc dl = Op.getDebugLoc(); 2126 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2127 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2128 MachineFunction &MF = DAG.getMachineFunction(); 2129 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2130 2131 // FIXME: Enable this for static codegen when tool issues are fixed. 2132 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2133 ++NumMovwMovt; 2134 // FIXME: Once remat is capable of dealing with instructions with register 2135 // operands, expand this into two nodes. 2136 if (RelocM == Reloc::Static) 2137 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2138 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2139 2140 unsigned Wrapper = (RelocM == Reloc::PIC_) 2141 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2142 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2143 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2144 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2145 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2146 MachinePointerInfo::getGOT(), false, false, 0); 2147 return Result; 2148 } 2149 2150 unsigned ARMPCLabelIndex = 0; 2151 SDValue CPAddr; 2152 if (RelocM == Reloc::Static) { 2153 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2154 } else { 2155 ARMPCLabelIndex = AFI->createPICLabelUId(); 2156 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2157 ARMConstantPoolValue *CPV = 2158 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2159 PCAdj); 2160 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2161 } 2162 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2163 2164 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2165 MachinePointerInfo::getConstantPool(), 2166 false, false, 0); 2167 SDValue Chain = Result.getValue(1); 2168 2169 if (RelocM == Reloc::PIC_) { 2170 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2171 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2172 } 2173 2174 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2175 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2176 false, false, 0); 2177 2178 return Result; 2179} 2180 2181SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2182 SelectionDAG &DAG) const { 2183 assert(Subtarget->isTargetELF() && 2184 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2185 MachineFunction &MF = DAG.getMachineFunction(); 2186 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2187 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2188 EVT PtrVT = getPointerTy(); 2189 DebugLoc dl = Op.getDebugLoc(); 2190 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2191 ARMConstantPoolValue *CPV = 2192 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2193 ARMPCLabelIndex, PCAdj); 2194 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2195 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2196 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2197 MachinePointerInfo::getConstantPool(), 2198 false, false, 0); 2199 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2200 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2201} 2202 2203SDValue 2204ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2205 const { 2206 DebugLoc dl = Op.getDebugLoc(); 2207 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2208 Op.getOperand(0), Op.getOperand(1)); 2209} 2210 2211SDValue 2212ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2213 DebugLoc dl = Op.getDebugLoc(); 2214 SDValue Val = DAG.getConstant(0, MVT::i32); 2215 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2216 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2217 Op.getOperand(1), Val); 2218} 2219 2220SDValue 2221ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2222 DebugLoc dl = Op.getDebugLoc(); 2223 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2224 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2225} 2226 2227SDValue 2228ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2229 const ARMSubtarget *Subtarget) const { 2230 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2231 DebugLoc dl = Op.getDebugLoc(); 2232 switch (IntNo) { 2233 default: return SDValue(); // Don't custom lower most intrinsics. 2234 case Intrinsic::arm_thread_pointer: { 2235 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2236 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2237 } 2238 case Intrinsic::eh_sjlj_lsda: { 2239 MachineFunction &MF = DAG.getMachineFunction(); 2240 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2241 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2242 EVT PtrVT = getPointerTy(); 2243 DebugLoc dl = Op.getDebugLoc(); 2244 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2245 SDValue CPAddr; 2246 unsigned PCAdj = (RelocM != Reloc::PIC_) 2247 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2248 ARMConstantPoolValue *CPV = 2249 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2250 ARMCP::CPLSDA, PCAdj); 2251 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2252 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2253 SDValue Result = 2254 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2255 MachinePointerInfo::getConstantPool(), 2256 false, false, 0); 2257 2258 if (RelocM == Reloc::PIC_) { 2259 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2260 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2261 } 2262 return Result; 2263 } 2264 case Intrinsic::arm_neon_vmulls: 2265 case Intrinsic::arm_neon_vmullu: { 2266 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2267 ? ARMISD::VMULLs : ARMISD::VMULLu; 2268 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2269 Op.getOperand(1), Op.getOperand(2)); 2270 } 2271 } 2272} 2273 2274static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2275 const ARMSubtarget *Subtarget) { 2276 DebugLoc dl = Op.getDebugLoc(); 2277 if (!Subtarget->hasDataBarrier()) { 2278 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2279 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2280 // here. 2281 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2282 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2283 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2284 DAG.getConstant(0, MVT::i32)); 2285 } 2286 2287 SDValue Op5 = Op.getOperand(5); 2288 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2289 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2290 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2291 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2292 2293 ARM_MB::MemBOpt DMBOpt; 2294 if (isDeviceBarrier) 2295 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2296 else 2297 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2298 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2299 DAG.getConstant(DMBOpt, MVT::i32)); 2300} 2301 2302 2303static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2304 const ARMSubtarget *Subtarget) { 2305 // FIXME: handle "fence singlethread" more efficiently. 2306 DebugLoc dl = Op.getDebugLoc(); 2307 if (!Subtarget->hasDataBarrier()) { 2308 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2309 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2310 // here. 2311 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2312 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2313 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2314 DAG.getConstant(0, MVT::i32)); 2315 } 2316 2317 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2318 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2319} 2320 2321static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2322 const ARMSubtarget *Subtarget) { 2323 // ARM pre v5TE and Thumb1 does not have preload instructions. 2324 if (!(Subtarget->isThumb2() || 2325 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2326 // Just preserve the chain. 2327 return Op.getOperand(0); 2328 2329 DebugLoc dl = Op.getDebugLoc(); 2330 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2331 if (!isRead && 2332 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2333 // ARMv7 with MP extension has PLDW. 2334 return Op.getOperand(0); 2335 2336 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2337 if (Subtarget->isThumb()) { 2338 // Invert the bits. 2339 isRead = ~isRead & 1; 2340 isData = ~isData & 1; 2341 } 2342 2343 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2344 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2345 DAG.getConstant(isData, MVT::i32)); 2346} 2347 2348static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2349 MachineFunction &MF = DAG.getMachineFunction(); 2350 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2351 2352 // vastart just stores the address of the VarArgsFrameIndex slot into the 2353 // memory location argument. 2354 DebugLoc dl = Op.getDebugLoc(); 2355 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2356 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2358 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2359 MachinePointerInfo(SV), false, false, 0); 2360} 2361 2362SDValue 2363ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2364 SDValue &Root, SelectionDAG &DAG, 2365 DebugLoc dl) const { 2366 MachineFunction &MF = DAG.getMachineFunction(); 2367 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2368 2369 TargetRegisterClass *RC; 2370 if (AFI->isThumb1OnlyFunction()) 2371 RC = ARM::tGPRRegisterClass; 2372 else 2373 RC = ARM::GPRRegisterClass; 2374 2375 // Transform the arguments stored in physical registers into virtual ones. 2376 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2377 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2378 2379 SDValue ArgValue2; 2380 if (NextVA.isMemLoc()) { 2381 MachineFrameInfo *MFI = MF.getFrameInfo(); 2382 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2383 2384 // Create load node to retrieve arguments from the stack. 2385 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2386 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2387 MachinePointerInfo::getFixedStack(FI), 2388 false, false, 0); 2389 } else { 2390 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2391 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2392 } 2393 2394 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2395} 2396 2397void 2398ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2399 unsigned &VARegSize, unsigned &VARegSaveSize) 2400 const { 2401 unsigned NumGPRs; 2402 if (CCInfo.isFirstByValRegValid()) 2403 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2404 else { 2405 unsigned int firstUnalloced; 2406 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2407 sizeof(GPRArgRegs) / 2408 sizeof(GPRArgRegs[0])); 2409 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2410 } 2411 2412 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2413 VARegSize = NumGPRs * 4; 2414 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2415} 2416 2417// The remaining GPRs hold either the beginning of variable-argument 2418// data, or the beginning of an aggregate passed by value (usuall 2419// byval). Either way, we allocate stack slots adjacent to the data 2420// provided by our caller, and store the unallocated registers there. 2421// If this is a variadic function, the va_list pointer will begin with 2422// these values; otherwise, this reassembles a (byval) structure that 2423// was split between registers and memory. 2424void 2425ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2426 DebugLoc dl, SDValue &Chain, 2427 unsigned ArgOffset) const { 2428 MachineFunction &MF = DAG.getMachineFunction(); 2429 MachineFrameInfo *MFI = MF.getFrameInfo(); 2430 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2431 unsigned firstRegToSaveIndex; 2432 if (CCInfo.isFirstByValRegValid()) 2433 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2434 else { 2435 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2436 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2437 } 2438 2439 unsigned VARegSize, VARegSaveSize; 2440 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2441 if (VARegSaveSize) { 2442 // If this function is vararg, store any remaining integer argument regs 2443 // to their spots on the stack so that they may be loaded by deferencing 2444 // the result of va_next. 2445 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2446 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2447 ArgOffset + VARegSaveSize 2448 - VARegSize, 2449 false)); 2450 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2451 getPointerTy()); 2452 2453 SmallVector<SDValue, 4> MemOps; 2454 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2455 TargetRegisterClass *RC; 2456 if (AFI->isThumb1OnlyFunction()) 2457 RC = ARM::tGPRRegisterClass; 2458 else 2459 RC = ARM::GPRRegisterClass; 2460 2461 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2462 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2463 SDValue Store = 2464 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2465 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2466 false, false, 0); 2467 MemOps.push_back(Store); 2468 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2469 DAG.getConstant(4, getPointerTy())); 2470 } 2471 if (!MemOps.empty()) 2472 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2473 &MemOps[0], MemOps.size()); 2474 } else 2475 // This will point to the next argument passed via stack. 2476 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2477} 2478 2479SDValue 2480ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2481 CallingConv::ID CallConv, bool isVarArg, 2482 const SmallVectorImpl<ISD::InputArg> 2483 &Ins, 2484 DebugLoc dl, SelectionDAG &DAG, 2485 SmallVectorImpl<SDValue> &InVals) 2486 const { 2487 MachineFunction &MF = DAG.getMachineFunction(); 2488 MachineFrameInfo *MFI = MF.getFrameInfo(); 2489 2490 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2491 2492 // Assign locations to all of the incoming arguments. 2493 SmallVector<CCValAssign, 16> ArgLocs; 2494 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2495 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2496 CCInfo.AnalyzeFormalArguments(Ins, 2497 CCAssignFnForNode(CallConv, /* Return*/ false, 2498 isVarArg)); 2499 2500 SmallVector<SDValue, 16> ArgValues; 2501 int lastInsIndex = -1; 2502 2503 SDValue ArgValue; 2504 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2505 CCValAssign &VA = ArgLocs[i]; 2506 2507 // Arguments stored in registers. 2508 if (VA.isRegLoc()) { 2509 EVT RegVT = VA.getLocVT(); 2510 2511 if (VA.needsCustom()) { 2512 // f64 and vector types are split up into multiple registers or 2513 // combinations of registers and stack slots. 2514 if (VA.getLocVT() == MVT::v2f64) { 2515 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2516 Chain, DAG, dl); 2517 VA = ArgLocs[++i]; // skip ahead to next loc 2518 SDValue ArgValue2; 2519 if (VA.isMemLoc()) { 2520 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2521 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2522 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2523 MachinePointerInfo::getFixedStack(FI), 2524 false, false, 0); 2525 } else { 2526 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2527 Chain, DAG, dl); 2528 } 2529 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2531 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2532 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2533 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2534 } else 2535 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2536 2537 } else { 2538 TargetRegisterClass *RC; 2539 2540 if (RegVT == MVT::f32) 2541 RC = ARM::SPRRegisterClass; 2542 else if (RegVT == MVT::f64) 2543 RC = ARM::DPRRegisterClass; 2544 else if (RegVT == MVT::v2f64) 2545 RC = ARM::QPRRegisterClass; 2546 else if (RegVT == MVT::i32) 2547 RC = (AFI->isThumb1OnlyFunction() ? 2548 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2549 else 2550 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2551 2552 // Transform the arguments in physical registers into virtual ones. 2553 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2554 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2555 } 2556 2557 // If this is an 8 or 16-bit value, it is really passed promoted 2558 // to 32 bits. Insert an assert[sz]ext to capture this, then 2559 // truncate to the right size. 2560 switch (VA.getLocInfo()) { 2561 default: llvm_unreachable("Unknown loc info!"); 2562 case CCValAssign::Full: break; 2563 case CCValAssign::BCvt: 2564 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2565 break; 2566 case CCValAssign::SExt: 2567 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2568 DAG.getValueType(VA.getValVT())); 2569 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2570 break; 2571 case CCValAssign::ZExt: 2572 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2573 DAG.getValueType(VA.getValVT())); 2574 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2575 break; 2576 } 2577 2578 InVals.push_back(ArgValue); 2579 2580 } else { // VA.isRegLoc() 2581 2582 // sanity check 2583 assert(VA.isMemLoc()); 2584 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2585 2586 int index = ArgLocs[i].getValNo(); 2587 2588 // Some Ins[] entries become multiple ArgLoc[] entries. 2589 // Process them only once. 2590 if (index != lastInsIndex) 2591 { 2592 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2593 // FIXME: For now, all byval parameter objects are marked mutable. 2594 // This can be changed with more analysis. 2595 // In case of tail call optimization mark all arguments mutable. 2596 // Since they could be overwritten by lowering of arguments in case of 2597 // a tail call. 2598 if (Flags.isByVal()) { 2599 unsigned VARegSize, VARegSaveSize; 2600 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2601 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2602 unsigned Bytes = Flags.getByValSize() - VARegSize; 2603 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2604 int FI = MFI->CreateFixedObject(Bytes, 2605 VA.getLocMemOffset(), false); 2606 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2607 } else { 2608 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2609 VA.getLocMemOffset(), true); 2610 2611 // Create load nodes to retrieve arguments from the stack. 2612 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2613 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2614 MachinePointerInfo::getFixedStack(FI), 2615 false, false, 0)); 2616 } 2617 lastInsIndex = index; 2618 } 2619 } 2620 } 2621 2622 // varargs 2623 if (isVarArg) 2624 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2625 2626 return Chain; 2627} 2628 2629/// isFloatingPointZero - Return true if this is +0.0. 2630static bool isFloatingPointZero(SDValue Op) { 2631 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2632 return CFP->getValueAPF().isPosZero(); 2633 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2634 // Maybe this has already been legalized into the constant pool? 2635 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2636 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2637 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2638 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2639 return CFP->getValueAPF().isPosZero(); 2640 } 2641 } 2642 return false; 2643} 2644 2645/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2646/// the given operands. 2647SDValue 2648ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2649 SDValue &ARMcc, SelectionDAG &DAG, 2650 DebugLoc dl) const { 2651 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2652 unsigned C = RHSC->getZExtValue(); 2653 if (!isLegalICmpImmediate(C)) { 2654 // Constant does not fit, try adjusting it by one? 2655 switch (CC) { 2656 default: break; 2657 case ISD::SETLT: 2658 case ISD::SETGE: 2659 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2660 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2661 RHS = DAG.getConstant(C-1, MVT::i32); 2662 } 2663 break; 2664 case ISD::SETULT: 2665 case ISD::SETUGE: 2666 if (C != 0 && isLegalICmpImmediate(C-1)) { 2667 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2668 RHS = DAG.getConstant(C-1, MVT::i32); 2669 } 2670 break; 2671 case ISD::SETLE: 2672 case ISD::SETGT: 2673 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2674 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2675 RHS = DAG.getConstant(C+1, MVT::i32); 2676 } 2677 break; 2678 case ISD::SETULE: 2679 case ISD::SETUGT: 2680 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2681 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2682 RHS = DAG.getConstant(C+1, MVT::i32); 2683 } 2684 break; 2685 } 2686 } 2687 } 2688 2689 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2690 ARMISD::NodeType CompareType; 2691 switch (CondCode) { 2692 default: 2693 CompareType = ARMISD::CMP; 2694 break; 2695 case ARMCC::EQ: 2696 case ARMCC::NE: 2697 // Uses only Z Flag 2698 CompareType = ARMISD::CMPZ; 2699 break; 2700 } 2701 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2702 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2703} 2704 2705/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2706SDValue 2707ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2708 DebugLoc dl) const { 2709 SDValue Cmp; 2710 if (!isFloatingPointZero(RHS)) 2711 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2712 else 2713 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2714 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2715} 2716 2717/// duplicateCmp - Glue values can have only one use, so this function 2718/// duplicates a comparison node. 2719SDValue 2720ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2721 unsigned Opc = Cmp.getOpcode(); 2722 DebugLoc DL = Cmp.getDebugLoc(); 2723 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2724 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2725 2726 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2727 Cmp = Cmp.getOperand(0); 2728 Opc = Cmp.getOpcode(); 2729 if (Opc == ARMISD::CMPFP) 2730 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2731 else { 2732 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2733 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2734 } 2735 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2736} 2737 2738SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2739 SDValue Cond = Op.getOperand(0); 2740 SDValue SelectTrue = Op.getOperand(1); 2741 SDValue SelectFalse = Op.getOperand(2); 2742 DebugLoc dl = Op.getDebugLoc(); 2743 2744 // Convert: 2745 // 2746 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2747 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2748 // 2749 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2750 const ConstantSDNode *CMOVTrue = 2751 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2752 const ConstantSDNode *CMOVFalse = 2753 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2754 2755 if (CMOVTrue && CMOVFalse) { 2756 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2757 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2758 2759 SDValue True; 2760 SDValue False; 2761 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2762 True = SelectTrue; 2763 False = SelectFalse; 2764 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2765 True = SelectFalse; 2766 False = SelectTrue; 2767 } 2768 2769 if (True.getNode() && False.getNode()) { 2770 EVT VT = Op.getValueType(); 2771 SDValue ARMcc = Cond.getOperand(2); 2772 SDValue CCR = Cond.getOperand(3); 2773 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2774 assert(True.getValueType() == VT); 2775 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2776 } 2777 } 2778 } 2779 2780 return DAG.getSelectCC(dl, Cond, 2781 DAG.getConstant(0, Cond.getValueType()), 2782 SelectTrue, SelectFalse, ISD::SETNE); 2783} 2784 2785SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2786 EVT VT = Op.getValueType(); 2787 SDValue LHS = Op.getOperand(0); 2788 SDValue RHS = Op.getOperand(1); 2789 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2790 SDValue TrueVal = Op.getOperand(2); 2791 SDValue FalseVal = Op.getOperand(3); 2792 DebugLoc dl = Op.getDebugLoc(); 2793 2794 if (LHS.getValueType() == MVT::i32) { 2795 SDValue ARMcc; 2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2797 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2798 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2799 } 2800 2801 ARMCC::CondCodes CondCode, CondCode2; 2802 FPCCToARMCC(CC, CondCode, CondCode2); 2803 2804 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2805 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2807 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2808 ARMcc, CCR, Cmp); 2809 if (CondCode2 != ARMCC::AL) { 2810 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2811 // FIXME: Needs another CMP because flag can have but one use. 2812 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2813 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2814 Result, TrueVal, ARMcc2, CCR, Cmp2); 2815 } 2816 return Result; 2817} 2818 2819/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2820/// to morph to an integer compare sequence. 2821static bool canChangeToInt(SDValue Op, bool &SeenZero, 2822 const ARMSubtarget *Subtarget) { 2823 SDNode *N = Op.getNode(); 2824 if (!N->hasOneUse()) 2825 // Otherwise it requires moving the value from fp to integer registers. 2826 return false; 2827 if (!N->getNumValues()) 2828 return false; 2829 EVT VT = Op.getValueType(); 2830 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2831 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2832 // vmrs are very slow, e.g. cortex-a8. 2833 return false; 2834 2835 if (isFloatingPointZero(Op)) { 2836 SeenZero = true; 2837 return true; 2838 } 2839 return ISD::isNormalLoad(N); 2840} 2841 2842static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2843 if (isFloatingPointZero(Op)) 2844 return DAG.getConstant(0, MVT::i32); 2845 2846 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2847 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2848 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2849 Ld->isVolatile(), Ld->isNonTemporal(), 2850 Ld->getAlignment()); 2851 2852 llvm_unreachable("Unknown VFP cmp argument!"); 2853} 2854 2855static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2856 SDValue &RetVal1, SDValue &RetVal2) { 2857 if (isFloatingPointZero(Op)) { 2858 RetVal1 = DAG.getConstant(0, MVT::i32); 2859 RetVal2 = DAG.getConstant(0, MVT::i32); 2860 return; 2861 } 2862 2863 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2864 SDValue Ptr = Ld->getBasePtr(); 2865 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2866 Ld->getChain(), Ptr, 2867 Ld->getPointerInfo(), 2868 Ld->isVolatile(), Ld->isNonTemporal(), 2869 Ld->getAlignment()); 2870 2871 EVT PtrType = Ptr.getValueType(); 2872 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2873 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2874 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2875 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2876 Ld->getChain(), NewPtr, 2877 Ld->getPointerInfo().getWithOffset(4), 2878 Ld->isVolatile(), Ld->isNonTemporal(), 2879 NewAlign); 2880 return; 2881 } 2882 2883 llvm_unreachable("Unknown VFP cmp argument!"); 2884} 2885 2886/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2887/// f32 and even f64 comparisons to integer ones. 2888SDValue 2889ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2890 SDValue Chain = Op.getOperand(0); 2891 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2892 SDValue LHS = Op.getOperand(2); 2893 SDValue RHS = Op.getOperand(3); 2894 SDValue Dest = Op.getOperand(4); 2895 DebugLoc dl = Op.getDebugLoc(); 2896 2897 bool SeenZero = false; 2898 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2899 canChangeToInt(RHS, SeenZero, Subtarget) && 2900 // If one of the operand is zero, it's safe to ignore the NaN case since 2901 // we only care about equality comparisons. 2902 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2903 // If unsafe fp math optimization is enabled and there are no other uses of 2904 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2905 // to an integer comparison. 2906 if (CC == ISD::SETOEQ) 2907 CC = ISD::SETEQ; 2908 else if (CC == ISD::SETUNE) 2909 CC = ISD::SETNE; 2910 2911 SDValue ARMcc; 2912 if (LHS.getValueType() == MVT::f32) { 2913 LHS = bitcastf32Toi32(LHS, DAG); 2914 RHS = bitcastf32Toi32(RHS, DAG); 2915 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2916 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2917 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2918 Chain, Dest, ARMcc, CCR, Cmp); 2919 } 2920 2921 SDValue LHS1, LHS2; 2922 SDValue RHS1, RHS2; 2923 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2924 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2925 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2926 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2927 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2928 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2929 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2930 } 2931 2932 return SDValue(); 2933} 2934 2935SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2936 SDValue Chain = Op.getOperand(0); 2937 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2938 SDValue LHS = Op.getOperand(2); 2939 SDValue RHS = Op.getOperand(3); 2940 SDValue Dest = Op.getOperand(4); 2941 DebugLoc dl = Op.getDebugLoc(); 2942 2943 if (LHS.getValueType() == MVT::i32) { 2944 SDValue ARMcc; 2945 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2946 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2947 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2948 Chain, Dest, ARMcc, CCR, Cmp); 2949 } 2950 2951 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2952 2953 if (UnsafeFPMath && 2954 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2955 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2956 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2957 if (Result.getNode()) 2958 return Result; 2959 } 2960 2961 ARMCC::CondCodes CondCode, CondCode2; 2962 FPCCToARMCC(CC, CondCode, CondCode2); 2963 2964 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2965 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2966 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2967 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2968 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2969 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2970 if (CondCode2 != ARMCC::AL) { 2971 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2972 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2973 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2974 } 2975 return Res; 2976} 2977 2978SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2979 SDValue Chain = Op.getOperand(0); 2980 SDValue Table = Op.getOperand(1); 2981 SDValue Index = Op.getOperand(2); 2982 DebugLoc dl = Op.getDebugLoc(); 2983 2984 EVT PTy = getPointerTy(); 2985 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2986 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2987 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2988 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2989 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2990 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2991 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2992 if (Subtarget->isThumb2()) { 2993 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2994 // which does another jump to the destination. This also makes it easier 2995 // to translate it to TBB / TBH later. 2996 // FIXME: This might not work if the function is extremely large. 2997 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2998 Addr, Op.getOperand(2), JTI, UId); 2999 } 3000 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 3001 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 3002 MachinePointerInfo::getJumpTable(), 3003 false, false, 0); 3004 Chain = Addr.getValue(1); 3005 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3006 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3007 } else { 3008 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3009 MachinePointerInfo::getJumpTable(), false, false, 0); 3010 Chain = Addr.getValue(1); 3011 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3012 } 3013} 3014 3015static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3016 DebugLoc dl = Op.getDebugLoc(); 3017 unsigned Opc; 3018 3019 switch (Op.getOpcode()) { 3020 default: 3021 assert(0 && "Invalid opcode!"); 3022 case ISD::FP_TO_SINT: 3023 Opc = ARMISD::FTOSI; 3024 break; 3025 case ISD::FP_TO_UINT: 3026 Opc = ARMISD::FTOUI; 3027 break; 3028 } 3029 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3030 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3031} 3032 3033static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3034 EVT VT = Op.getValueType(); 3035 DebugLoc dl = Op.getDebugLoc(); 3036 3037 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3038 "Invalid type for custom lowering!"); 3039 if (VT != MVT::v4f32) 3040 return DAG.UnrollVectorOp(Op.getNode()); 3041 3042 unsigned CastOpc; 3043 unsigned Opc; 3044 switch (Op.getOpcode()) { 3045 default: 3046 assert(0 && "Invalid opcode!"); 3047 case ISD::SINT_TO_FP: 3048 CastOpc = ISD::SIGN_EXTEND; 3049 Opc = ISD::SINT_TO_FP; 3050 break; 3051 case ISD::UINT_TO_FP: 3052 CastOpc = ISD::ZERO_EXTEND; 3053 Opc = ISD::UINT_TO_FP; 3054 break; 3055 } 3056 3057 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3058 return DAG.getNode(Opc, dl, VT, Op); 3059} 3060 3061static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3062 EVT VT = Op.getValueType(); 3063 if (VT.isVector()) 3064 return LowerVectorINT_TO_FP(Op, DAG); 3065 3066 DebugLoc dl = Op.getDebugLoc(); 3067 unsigned Opc; 3068 3069 switch (Op.getOpcode()) { 3070 default: 3071 assert(0 && "Invalid opcode!"); 3072 case ISD::SINT_TO_FP: 3073 Opc = ARMISD::SITOF; 3074 break; 3075 case ISD::UINT_TO_FP: 3076 Opc = ARMISD::UITOF; 3077 break; 3078 } 3079 3080 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3081 return DAG.getNode(Opc, dl, VT, Op); 3082} 3083 3084SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3085 // Implement fcopysign with a fabs and a conditional fneg. 3086 SDValue Tmp0 = Op.getOperand(0); 3087 SDValue Tmp1 = Op.getOperand(1); 3088 DebugLoc dl = Op.getDebugLoc(); 3089 EVT VT = Op.getValueType(); 3090 EVT SrcVT = Tmp1.getValueType(); 3091 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3092 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3093 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3094 3095 if (UseNEON) { 3096 // Use VBSL to copy the sign bit. 3097 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3098 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3099 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3100 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3101 if (VT == MVT::f64) 3102 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3103 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3104 DAG.getConstant(32, MVT::i32)); 3105 else /*if (VT == MVT::f32)*/ 3106 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3107 if (SrcVT == MVT::f32) { 3108 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3109 if (VT == MVT::f64) 3110 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3111 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3112 DAG.getConstant(32, MVT::i32)); 3113 } else if (VT == MVT::f32) 3114 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3115 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3116 DAG.getConstant(32, MVT::i32)); 3117 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3118 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3119 3120 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3121 MVT::i32); 3122 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3123 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3124 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3125 3126 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3127 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3128 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3129 if (VT == MVT::f32) { 3130 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3131 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3132 DAG.getConstant(0, MVT::i32)); 3133 } else { 3134 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3135 } 3136 3137 return Res; 3138 } 3139 3140 // Bitcast operand 1 to i32. 3141 if (SrcVT == MVT::f64) 3142 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3143 &Tmp1, 1).getValue(1); 3144 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3145 3146 // Or in the signbit with integer operations. 3147 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3148 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3149 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3150 if (VT == MVT::f32) { 3151 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3152 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3153 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3154 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3155 } 3156 3157 // f64: Or the high part with signbit and then combine two parts. 3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3159 &Tmp0, 1); 3160 SDValue Lo = Tmp0.getValue(0); 3161 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3162 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3163 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3164} 3165 3166SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3167 MachineFunction &MF = DAG.getMachineFunction(); 3168 MachineFrameInfo *MFI = MF.getFrameInfo(); 3169 MFI->setReturnAddressIsTaken(true); 3170 3171 EVT VT = Op.getValueType(); 3172 DebugLoc dl = Op.getDebugLoc(); 3173 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3174 if (Depth) { 3175 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3176 SDValue Offset = DAG.getConstant(4, MVT::i32); 3177 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3178 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3179 MachinePointerInfo(), false, false, 0); 3180 } 3181 3182 // Return LR, which contains the return address. Mark it an implicit live-in. 3183 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3184 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3185} 3186 3187SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3188 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3189 MFI->setFrameAddressIsTaken(true); 3190 3191 EVT VT = Op.getValueType(); 3192 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3193 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3194 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3195 ? ARM::R7 : ARM::R11; 3196 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3197 while (Depth--) 3198 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3199 MachinePointerInfo(), 3200 false, false, 0); 3201 return FrameAddr; 3202} 3203 3204/// ExpandBITCAST - If the target supports VFP, this function is called to 3205/// expand a bit convert where either the source or destination type is i64 to 3206/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3207/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3208/// vectors), since the legalizer won't know what to do with that. 3209static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3210 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3211 DebugLoc dl = N->getDebugLoc(); 3212 SDValue Op = N->getOperand(0); 3213 3214 // This function is only supposed to be called for i64 types, either as the 3215 // source or destination of the bit convert. 3216 EVT SrcVT = Op.getValueType(); 3217 EVT DstVT = N->getValueType(0); 3218 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3219 "ExpandBITCAST called for non-i64 type"); 3220 3221 // Turn i64->f64 into VMOVDRR. 3222 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3223 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3224 DAG.getConstant(0, MVT::i32)); 3225 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3226 DAG.getConstant(1, MVT::i32)); 3227 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3228 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3229 } 3230 3231 // Turn f64->i64 into VMOVRRD. 3232 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3233 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3234 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3235 // Merge the pieces into a single i64 value. 3236 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3237 } 3238 3239 return SDValue(); 3240} 3241 3242/// getZeroVector - Returns a vector of specified type with all zero elements. 3243/// Zero vectors are used to represent vector negation and in those cases 3244/// will be implemented with the NEON VNEG instruction. However, VNEG does 3245/// not support i64 elements, so sometimes the zero vectors will need to be 3246/// explicitly constructed. Regardless, use a canonical VMOV to create the 3247/// zero vector. 3248static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3249 assert(VT.isVector() && "Expected a vector type"); 3250 // The canonical modified immediate encoding of a zero vector is....0! 3251 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3252 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3253 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3254 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3255} 3256 3257/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3258/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3259SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3260 SelectionDAG &DAG) const { 3261 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3262 EVT VT = Op.getValueType(); 3263 unsigned VTBits = VT.getSizeInBits(); 3264 DebugLoc dl = Op.getDebugLoc(); 3265 SDValue ShOpLo = Op.getOperand(0); 3266 SDValue ShOpHi = Op.getOperand(1); 3267 SDValue ShAmt = Op.getOperand(2); 3268 SDValue ARMcc; 3269 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3270 3271 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3272 3273 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3274 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3275 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3276 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3277 DAG.getConstant(VTBits, MVT::i32)); 3278 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3279 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3280 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3281 3282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3283 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3284 ARMcc, DAG, dl); 3285 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3286 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3287 CCR, Cmp); 3288 3289 SDValue Ops[2] = { Lo, Hi }; 3290 return DAG.getMergeValues(Ops, 2, dl); 3291} 3292 3293/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3294/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3295SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3296 SelectionDAG &DAG) const { 3297 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3298 EVT VT = Op.getValueType(); 3299 unsigned VTBits = VT.getSizeInBits(); 3300 DebugLoc dl = Op.getDebugLoc(); 3301 SDValue ShOpLo = Op.getOperand(0); 3302 SDValue ShOpHi = Op.getOperand(1); 3303 SDValue ShAmt = Op.getOperand(2); 3304 SDValue ARMcc; 3305 3306 assert(Op.getOpcode() == ISD::SHL_PARTS); 3307 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3308 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3309 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3310 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3311 DAG.getConstant(VTBits, MVT::i32)); 3312 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3313 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3314 3315 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3316 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3317 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3318 ARMcc, DAG, dl); 3319 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3320 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3321 CCR, Cmp); 3322 3323 SDValue Ops[2] = { Lo, Hi }; 3324 return DAG.getMergeValues(Ops, 2, dl); 3325} 3326 3327SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3328 SelectionDAG &DAG) const { 3329 // The rounding mode is in bits 23:22 of the FPSCR. 3330 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3331 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3332 // so that the shift + and get folded into a bitfield extract. 3333 DebugLoc dl = Op.getDebugLoc(); 3334 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3335 DAG.getConstant(Intrinsic::arm_get_fpscr, 3336 MVT::i32)); 3337 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3338 DAG.getConstant(1U << 22, MVT::i32)); 3339 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3340 DAG.getConstant(22, MVT::i32)); 3341 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3342 DAG.getConstant(3, MVT::i32)); 3343} 3344 3345static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3346 const ARMSubtarget *ST) { 3347 EVT VT = N->getValueType(0); 3348 DebugLoc dl = N->getDebugLoc(); 3349 3350 if (!ST->hasV6T2Ops()) 3351 return SDValue(); 3352 3353 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3354 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3355} 3356 3357static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3358 const ARMSubtarget *ST) { 3359 EVT VT = N->getValueType(0); 3360 DebugLoc dl = N->getDebugLoc(); 3361 3362 if (!VT.isVector()) 3363 return SDValue(); 3364 3365 // Lower vector shifts on NEON to use VSHL. 3366 assert(ST->hasNEON() && "unexpected vector shift"); 3367 3368 // Left shifts translate directly to the vshiftu intrinsic. 3369 if (N->getOpcode() == ISD::SHL) 3370 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3371 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3372 N->getOperand(0), N->getOperand(1)); 3373 3374 assert((N->getOpcode() == ISD::SRA || 3375 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3376 3377 // NEON uses the same intrinsics for both left and right shifts. For 3378 // right shifts, the shift amounts are negative, so negate the vector of 3379 // shift amounts. 3380 EVT ShiftVT = N->getOperand(1).getValueType(); 3381 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3382 getZeroVector(ShiftVT, DAG, dl), 3383 N->getOperand(1)); 3384 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3385 Intrinsic::arm_neon_vshifts : 3386 Intrinsic::arm_neon_vshiftu); 3387 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3388 DAG.getConstant(vshiftInt, MVT::i32), 3389 N->getOperand(0), NegatedCount); 3390} 3391 3392static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3393 const ARMSubtarget *ST) { 3394 EVT VT = N->getValueType(0); 3395 DebugLoc dl = N->getDebugLoc(); 3396 3397 // We can get here for a node like i32 = ISD::SHL i32, i64 3398 if (VT != MVT::i64) 3399 return SDValue(); 3400 3401 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3402 "Unknown shift to lower!"); 3403 3404 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3405 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3406 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3407 return SDValue(); 3408 3409 // If we are in thumb mode, we don't have RRX. 3410 if (ST->isThumb1Only()) return SDValue(); 3411 3412 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3413 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3414 DAG.getConstant(0, MVT::i32)); 3415 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3416 DAG.getConstant(1, MVT::i32)); 3417 3418 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3419 // captures the result into a carry flag. 3420 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3421 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3422 3423 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3424 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3425 3426 // Merge the pieces into a single i64 value. 3427 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3428} 3429 3430static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3431 SDValue TmpOp0, TmpOp1; 3432 bool Invert = false; 3433 bool Swap = false; 3434 unsigned Opc = 0; 3435 3436 SDValue Op0 = Op.getOperand(0); 3437 SDValue Op1 = Op.getOperand(1); 3438 SDValue CC = Op.getOperand(2); 3439 EVT VT = Op.getValueType(); 3440 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3441 DebugLoc dl = Op.getDebugLoc(); 3442 3443 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3444 switch (SetCCOpcode) { 3445 default: llvm_unreachable("Illegal FP comparison"); break; 3446 case ISD::SETUNE: 3447 case ISD::SETNE: Invert = true; // Fallthrough 3448 case ISD::SETOEQ: 3449 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3450 case ISD::SETOLT: 3451 case ISD::SETLT: Swap = true; // Fallthrough 3452 case ISD::SETOGT: 3453 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3454 case ISD::SETOLE: 3455 case ISD::SETLE: Swap = true; // Fallthrough 3456 case ISD::SETOGE: 3457 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3458 case ISD::SETUGE: Swap = true; // Fallthrough 3459 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3460 case ISD::SETUGT: Swap = true; // Fallthrough 3461 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3462 case ISD::SETUEQ: Invert = true; // Fallthrough 3463 case ISD::SETONE: 3464 // Expand this to (OLT | OGT). 3465 TmpOp0 = Op0; 3466 TmpOp1 = Op1; 3467 Opc = ISD::OR; 3468 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3469 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3470 break; 3471 case ISD::SETUO: Invert = true; // Fallthrough 3472 case ISD::SETO: 3473 // Expand this to (OLT | OGE). 3474 TmpOp0 = Op0; 3475 TmpOp1 = Op1; 3476 Opc = ISD::OR; 3477 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3478 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3479 break; 3480 } 3481 } else { 3482 // Integer comparisons. 3483 switch (SetCCOpcode) { 3484 default: llvm_unreachable("Illegal integer comparison"); break; 3485 case ISD::SETNE: Invert = true; 3486 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3487 case ISD::SETLT: Swap = true; 3488 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3489 case ISD::SETLE: Swap = true; 3490 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3491 case ISD::SETULT: Swap = true; 3492 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3493 case ISD::SETULE: Swap = true; 3494 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3495 } 3496 3497 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3498 if (Opc == ARMISD::VCEQ) { 3499 3500 SDValue AndOp; 3501 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3502 AndOp = Op0; 3503 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3504 AndOp = Op1; 3505 3506 // Ignore bitconvert. 3507 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3508 AndOp = AndOp.getOperand(0); 3509 3510 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3511 Opc = ARMISD::VTST; 3512 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3513 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3514 Invert = !Invert; 3515 } 3516 } 3517 } 3518 3519 if (Swap) 3520 std::swap(Op0, Op1); 3521 3522 // If one of the operands is a constant vector zero, attempt to fold the 3523 // comparison to a specialized compare-against-zero form. 3524 SDValue SingleOp; 3525 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3526 SingleOp = Op0; 3527 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3528 if (Opc == ARMISD::VCGE) 3529 Opc = ARMISD::VCLEZ; 3530 else if (Opc == ARMISD::VCGT) 3531 Opc = ARMISD::VCLTZ; 3532 SingleOp = Op1; 3533 } 3534 3535 SDValue Result; 3536 if (SingleOp.getNode()) { 3537 switch (Opc) { 3538 case ARMISD::VCEQ: 3539 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3540 case ARMISD::VCGE: 3541 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3542 case ARMISD::VCLEZ: 3543 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3544 case ARMISD::VCGT: 3545 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3546 case ARMISD::VCLTZ: 3547 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3548 default: 3549 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3550 } 3551 } else { 3552 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3553 } 3554 3555 if (Invert) 3556 Result = DAG.getNOT(dl, Result, VT); 3557 3558 return Result; 3559} 3560 3561/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3562/// valid vector constant for a NEON instruction with a "modified immediate" 3563/// operand (e.g., VMOV). If so, return the encoded value. 3564static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3565 unsigned SplatBitSize, SelectionDAG &DAG, 3566 EVT &VT, bool is128Bits, NEONModImmType type) { 3567 unsigned OpCmode, Imm; 3568 3569 // SplatBitSize is set to the smallest size that splats the vector, so a 3570 // zero vector will always have SplatBitSize == 8. However, NEON modified 3571 // immediate instructions others than VMOV do not support the 8-bit encoding 3572 // of a zero vector, and the default encoding of zero is supposed to be the 3573 // 32-bit version. 3574 if (SplatBits == 0) 3575 SplatBitSize = 32; 3576 3577 switch (SplatBitSize) { 3578 case 8: 3579 if (type != VMOVModImm) 3580 return SDValue(); 3581 // Any 1-byte value is OK. Op=0, Cmode=1110. 3582 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3583 OpCmode = 0xe; 3584 Imm = SplatBits; 3585 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3586 break; 3587 3588 case 16: 3589 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3590 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3591 if ((SplatBits & ~0xff) == 0) { 3592 // Value = 0x00nn: Op=x, Cmode=100x. 3593 OpCmode = 0x8; 3594 Imm = SplatBits; 3595 break; 3596 } 3597 if ((SplatBits & ~0xff00) == 0) { 3598 // Value = 0xnn00: Op=x, Cmode=101x. 3599 OpCmode = 0xa; 3600 Imm = SplatBits >> 8; 3601 break; 3602 } 3603 return SDValue(); 3604 3605 case 32: 3606 // NEON's 32-bit VMOV supports splat values where: 3607 // * only one byte is nonzero, or 3608 // * the least significant byte is 0xff and the second byte is nonzero, or 3609 // * the least significant 2 bytes are 0xff and the third is nonzero. 3610 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3611 if ((SplatBits & ~0xff) == 0) { 3612 // Value = 0x000000nn: Op=x, Cmode=000x. 3613 OpCmode = 0; 3614 Imm = SplatBits; 3615 break; 3616 } 3617 if ((SplatBits & ~0xff00) == 0) { 3618 // Value = 0x0000nn00: Op=x, Cmode=001x. 3619 OpCmode = 0x2; 3620 Imm = SplatBits >> 8; 3621 break; 3622 } 3623 if ((SplatBits & ~0xff0000) == 0) { 3624 // Value = 0x00nn0000: Op=x, Cmode=010x. 3625 OpCmode = 0x4; 3626 Imm = SplatBits >> 16; 3627 break; 3628 } 3629 if ((SplatBits & ~0xff000000) == 0) { 3630 // Value = 0xnn000000: Op=x, Cmode=011x. 3631 OpCmode = 0x6; 3632 Imm = SplatBits >> 24; 3633 break; 3634 } 3635 3636 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3637 if (type == OtherModImm) return SDValue(); 3638 3639 if ((SplatBits & ~0xffff) == 0 && 3640 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3641 // Value = 0x0000nnff: Op=x, Cmode=1100. 3642 OpCmode = 0xc; 3643 Imm = SplatBits >> 8; 3644 SplatBits |= 0xff; 3645 break; 3646 } 3647 3648 if ((SplatBits & ~0xffffff) == 0 && 3649 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3650 // Value = 0x00nnffff: Op=x, Cmode=1101. 3651 OpCmode = 0xd; 3652 Imm = SplatBits >> 16; 3653 SplatBits |= 0xffff; 3654 break; 3655 } 3656 3657 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3658 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3659 // VMOV.I32. A (very) minor optimization would be to replicate the value 3660 // and fall through here to test for a valid 64-bit splat. But, then the 3661 // caller would also need to check and handle the change in size. 3662 return SDValue(); 3663 3664 case 64: { 3665 if (type != VMOVModImm) 3666 return SDValue(); 3667 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3668 uint64_t BitMask = 0xff; 3669 uint64_t Val = 0; 3670 unsigned ImmMask = 1; 3671 Imm = 0; 3672 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3673 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3674 Val |= BitMask; 3675 Imm |= ImmMask; 3676 } else if ((SplatBits & BitMask) != 0) { 3677 return SDValue(); 3678 } 3679 BitMask <<= 8; 3680 ImmMask <<= 1; 3681 } 3682 // Op=1, Cmode=1110. 3683 OpCmode = 0x1e; 3684 SplatBits = Val; 3685 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3686 break; 3687 } 3688 3689 default: 3690 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3691 return SDValue(); 3692 } 3693 3694 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3695 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3696} 3697 3698static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3699 bool &ReverseVEXT, unsigned &Imm) { 3700 unsigned NumElts = VT.getVectorNumElements(); 3701 ReverseVEXT = false; 3702 3703 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3704 if (M[0] < 0) 3705 return false; 3706 3707 Imm = M[0]; 3708 3709 // If this is a VEXT shuffle, the immediate value is the index of the first 3710 // element. The other shuffle indices must be the successive elements after 3711 // the first one. 3712 unsigned ExpectedElt = Imm; 3713 for (unsigned i = 1; i < NumElts; ++i) { 3714 // Increment the expected index. If it wraps around, it may still be 3715 // a VEXT but the source vectors must be swapped. 3716 ExpectedElt += 1; 3717 if (ExpectedElt == NumElts * 2) { 3718 ExpectedElt = 0; 3719 ReverseVEXT = true; 3720 } 3721 3722 if (M[i] < 0) continue; // ignore UNDEF indices 3723 if (ExpectedElt != static_cast<unsigned>(M[i])) 3724 return false; 3725 } 3726 3727 // Adjust the index value if the source operands will be swapped. 3728 if (ReverseVEXT) 3729 Imm -= NumElts; 3730 3731 return true; 3732} 3733 3734/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3735/// instruction with the specified blocksize. (The order of the elements 3736/// within each block of the vector is reversed.) 3737static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3738 unsigned BlockSize) { 3739 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3740 "Only possible block sizes for VREV are: 16, 32, 64"); 3741 3742 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3743 if (EltSz == 64) 3744 return false; 3745 3746 unsigned NumElts = VT.getVectorNumElements(); 3747 unsigned BlockElts = M[0] + 1; 3748 // If the first shuffle index is UNDEF, be optimistic. 3749 if (M[0] < 0) 3750 BlockElts = BlockSize / EltSz; 3751 3752 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3753 return false; 3754 3755 for (unsigned i = 0; i < NumElts; ++i) { 3756 if (M[i] < 0) continue; // ignore UNDEF indices 3757 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3758 return false; 3759 } 3760 3761 return true; 3762} 3763 3764static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) { 3765 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3766 // range, then 0 is placed into the resulting vector. So pretty much any mask 3767 // of 8 elements can work here. 3768 return VT == MVT::v8i8 && M.size() == 8; 3769} 3770 3771static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3772 unsigned &WhichResult) { 3773 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3774 if (EltSz == 64) 3775 return false; 3776 3777 unsigned NumElts = VT.getVectorNumElements(); 3778 WhichResult = (M[0] == 0 ? 0 : 1); 3779 for (unsigned i = 0; i < NumElts; i += 2) { 3780 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3781 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3782 return false; 3783 } 3784 return true; 3785} 3786 3787/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3788/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3789/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3790static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3791 unsigned &WhichResult) { 3792 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3793 if (EltSz == 64) 3794 return false; 3795 3796 unsigned NumElts = VT.getVectorNumElements(); 3797 WhichResult = (M[0] == 0 ? 0 : 1); 3798 for (unsigned i = 0; i < NumElts; i += 2) { 3799 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3800 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3801 return false; 3802 } 3803 return true; 3804} 3805 3806static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3807 unsigned &WhichResult) { 3808 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3809 if (EltSz == 64) 3810 return false; 3811 3812 unsigned NumElts = VT.getVectorNumElements(); 3813 WhichResult = (M[0] == 0 ? 0 : 1); 3814 for (unsigned i = 0; i != NumElts; ++i) { 3815 if (M[i] < 0) continue; // ignore UNDEF indices 3816 if ((unsigned) M[i] != 2 * i + WhichResult) 3817 return false; 3818 } 3819 3820 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3821 if (VT.is64BitVector() && EltSz == 32) 3822 return false; 3823 3824 return true; 3825} 3826 3827/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3828/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3829/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3830static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3831 unsigned &WhichResult) { 3832 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3833 if (EltSz == 64) 3834 return false; 3835 3836 unsigned Half = VT.getVectorNumElements() / 2; 3837 WhichResult = (M[0] == 0 ? 0 : 1); 3838 for (unsigned j = 0; j != 2; ++j) { 3839 unsigned Idx = WhichResult; 3840 for (unsigned i = 0; i != Half; ++i) { 3841 int MIdx = M[i + j * Half]; 3842 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3843 return false; 3844 Idx += 2; 3845 } 3846 } 3847 3848 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3849 if (VT.is64BitVector() && EltSz == 32) 3850 return false; 3851 3852 return true; 3853} 3854 3855static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3856 unsigned &WhichResult) { 3857 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3858 if (EltSz == 64) 3859 return false; 3860 3861 unsigned NumElts = VT.getVectorNumElements(); 3862 WhichResult = (M[0] == 0 ? 0 : 1); 3863 unsigned Idx = WhichResult * NumElts / 2; 3864 for (unsigned i = 0; i != NumElts; i += 2) { 3865 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3866 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3867 return false; 3868 Idx += 1; 3869 } 3870 3871 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3872 if (VT.is64BitVector() && EltSz == 32) 3873 return false; 3874 3875 return true; 3876} 3877 3878/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3879/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3880/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3881static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3882 unsigned &WhichResult) { 3883 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3884 if (EltSz == 64) 3885 return false; 3886 3887 unsigned NumElts = VT.getVectorNumElements(); 3888 WhichResult = (M[0] == 0 ? 0 : 1); 3889 unsigned Idx = WhichResult * NumElts / 2; 3890 for (unsigned i = 0; i != NumElts; i += 2) { 3891 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3892 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3893 return false; 3894 Idx += 1; 3895 } 3896 3897 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3898 if (VT.is64BitVector() && EltSz == 32) 3899 return false; 3900 3901 return true; 3902} 3903 3904// If N is an integer constant that can be moved into a register in one 3905// instruction, return an SDValue of such a constant (will become a MOV 3906// instruction). Otherwise return null. 3907static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3908 const ARMSubtarget *ST, DebugLoc dl) { 3909 uint64_t Val; 3910 if (!isa<ConstantSDNode>(N)) 3911 return SDValue(); 3912 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3913 3914 if (ST->isThumb1Only()) { 3915 if (Val <= 255 || ~Val <= 255) 3916 return DAG.getConstant(Val, MVT::i32); 3917 } else { 3918 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3919 return DAG.getConstant(Val, MVT::i32); 3920 } 3921 return SDValue(); 3922} 3923 3924// If this is a case we can't handle, return null and let the default 3925// expansion code take care of it. 3926SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3927 const ARMSubtarget *ST) const { 3928 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3929 DebugLoc dl = Op.getDebugLoc(); 3930 EVT VT = Op.getValueType(); 3931 3932 APInt SplatBits, SplatUndef; 3933 unsigned SplatBitSize; 3934 bool HasAnyUndefs; 3935 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3936 if (SplatBitSize <= 64) { 3937 // Check if an immediate VMOV works. 3938 EVT VmovVT; 3939 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3940 SplatUndef.getZExtValue(), SplatBitSize, 3941 DAG, VmovVT, VT.is128BitVector(), 3942 VMOVModImm); 3943 if (Val.getNode()) { 3944 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3945 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3946 } 3947 3948 // Try an immediate VMVN. 3949 uint64_t NegatedImm = (~SplatBits).getZExtValue(); 3950 Val = isNEONModifiedImm(NegatedImm, 3951 SplatUndef.getZExtValue(), SplatBitSize, 3952 DAG, VmovVT, VT.is128BitVector(), 3953 VMVNModImm); 3954 if (Val.getNode()) { 3955 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3956 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3957 } 3958 } 3959 } 3960 3961 // Scan through the operands to see if only one value is used. 3962 unsigned NumElts = VT.getVectorNumElements(); 3963 bool isOnlyLowElement = true; 3964 bool usesOnlyOneValue = true; 3965 bool isConstant = true; 3966 SDValue Value; 3967 for (unsigned i = 0; i < NumElts; ++i) { 3968 SDValue V = Op.getOperand(i); 3969 if (V.getOpcode() == ISD::UNDEF) 3970 continue; 3971 if (i > 0) 3972 isOnlyLowElement = false; 3973 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3974 isConstant = false; 3975 3976 if (!Value.getNode()) 3977 Value = V; 3978 else if (V != Value) 3979 usesOnlyOneValue = false; 3980 } 3981 3982 if (!Value.getNode()) 3983 return DAG.getUNDEF(VT); 3984 3985 if (isOnlyLowElement) 3986 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3987 3988 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3989 3990 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3991 // i32 and try again. 3992 if (usesOnlyOneValue && EltSize <= 32) { 3993 if (!isConstant) 3994 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3995 if (VT.getVectorElementType().isFloatingPoint()) { 3996 SmallVector<SDValue, 8> Ops; 3997 for (unsigned i = 0; i < NumElts; ++i) 3998 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 3999 Op.getOperand(i))); 4000 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 4001 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4002 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4003 if (Val.getNode()) 4004 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4005 } 4006 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4007 if (Val.getNode()) 4008 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4009 } 4010 4011 // If all elements are constants and the case above didn't get hit, fall back 4012 // to the default expansion, which will generate a load from the constant 4013 // pool. 4014 if (isConstant) 4015 return SDValue(); 4016 4017 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4018 if (NumElts >= 4) { 4019 SDValue shuffle = ReconstructShuffle(Op, DAG); 4020 if (shuffle != SDValue()) 4021 return shuffle; 4022 } 4023 4024 // Vectors with 32- or 64-bit elements can be built by directly assigning 4025 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4026 // will be legalized. 4027 if (EltSize >= 32) { 4028 // Do the expansion with floating-point types, since that is what the VFP 4029 // registers are defined to use, and since i64 is not legal. 4030 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4031 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4032 SmallVector<SDValue, 8> Ops; 4033 for (unsigned i = 0; i < NumElts; ++i) 4034 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4035 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4036 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4037 } 4038 4039 return SDValue(); 4040} 4041 4042// Gather data to see if the operation can be modelled as a 4043// shuffle in combination with VEXTs. 4044SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4045 SelectionDAG &DAG) const { 4046 DebugLoc dl = Op.getDebugLoc(); 4047 EVT VT = Op.getValueType(); 4048 unsigned NumElts = VT.getVectorNumElements(); 4049 4050 SmallVector<SDValue, 2> SourceVecs; 4051 SmallVector<unsigned, 2> MinElts; 4052 SmallVector<unsigned, 2> MaxElts; 4053 4054 for (unsigned i = 0; i < NumElts; ++i) { 4055 SDValue V = Op.getOperand(i); 4056 if (V.getOpcode() == ISD::UNDEF) 4057 continue; 4058 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4059 // A shuffle can only come from building a vector from various 4060 // elements of other vectors. 4061 return SDValue(); 4062 } else if (V.getOperand(0).getValueType().getVectorElementType() != 4063 VT.getVectorElementType()) { 4064 // This code doesn't know how to handle shuffles where the vector 4065 // element types do not match (this happens because type legalization 4066 // promotes the return type of EXTRACT_VECTOR_ELT). 4067 // FIXME: It might be appropriate to extend this code to handle 4068 // mismatched types. 4069 return SDValue(); 4070 } 4071 4072 // Record this extraction against the appropriate vector if possible... 4073 SDValue SourceVec = V.getOperand(0); 4074 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4075 bool FoundSource = false; 4076 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4077 if (SourceVecs[j] == SourceVec) { 4078 if (MinElts[j] > EltNo) 4079 MinElts[j] = EltNo; 4080 if (MaxElts[j] < EltNo) 4081 MaxElts[j] = EltNo; 4082 FoundSource = true; 4083 break; 4084 } 4085 } 4086 4087 // Or record a new source if not... 4088 if (!FoundSource) { 4089 SourceVecs.push_back(SourceVec); 4090 MinElts.push_back(EltNo); 4091 MaxElts.push_back(EltNo); 4092 } 4093 } 4094 4095 // Currently only do something sane when at most two source vectors 4096 // involved. 4097 if (SourceVecs.size() > 2) 4098 return SDValue(); 4099 4100 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4101 int VEXTOffsets[2] = {0, 0}; 4102 4103 // This loop extracts the usage patterns of the source vectors 4104 // and prepares appropriate SDValues for a shuffle if possible. 4105 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4106 if (SourceVecs[i].getValueType() == VT) { 4107 // No VEXT necessary 4108 ShuffleSrcs[i] = SourceVecs[i]; 4109 VEXTOffsets[i] = 0; 4110 continue; 4111 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4112 // It probably isn't worth padding out a smaller vector just to 4113 // break it down again in a shuffle. 4114 return SDValue(); 4115 } 4116 4117 // Since only 64-bit and 128-bit vectors are legal on ARM and 4118 // we've eliminated the other cases... 4119 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4120 "unexpected vector sizes in ReconstructShuffle"); 4121 4122 if (MaxElts[i] - MinElts[i] >= NumElts) { 4123 // Span too large for a VEXT to cope 4124 return SDValue(); 4125 } 4126 4127 if (MinElts[i] >= NumElts) { 4128 // The extraction can just take the second half 4129 VEXTOffsets[i] = NumElts; 4130 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4131 SourceVecs[i], 4132 DAG.getIntPtrConstant(NumElts)); 4133 } else if (MaxElts[i] < NumElts) { 4134 // The extraction can just take the first half 4135 VEXTOffsets[i] = 0; 4136 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4137 SourceVecs[i], 4138 DAG.getIntPtrConstant(0)); 4139 } else { 4140 // An actual VEXT is needed 4141 VEXTOffsets[i] = MinElts[i]; 4142 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4143 SourceVecs[i], 4144 DAG.getIntPtrConstant(0)); 4145 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4146 SourceVecs[i], 4147 DAG.getIntPtrConstant(NumElts)); 4148 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4149 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4150 } 4151 } 4152 4153 SmallVector<int, 8> Mask; 4154 4155 for (unsigned i = 0; i < NumElts; ++i) { 4156 SDValue Entry = Op.getOperand(i); 4157 if (Entry.getOpcode() == ISD::UNDEF) { 4158 Mask.push_back(-1); 4159 continue; 4160 } 4161 4162 SDValue ExtractVec = Entry.getOperand(0); 4163 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4164 .getOperand(1))->getSExtValue(); 4165 if (ExtractVec == SourceVecs[0]) { 4166 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4167 } else { 4168 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4169 } 4170 } 4171 4172 // Final check before we try to produce nonsense... 4173 if (isShuffleMaskLegal(Mask, VT)) 4174 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4175 &Mask[0]); 4176 4177 return SDValue(); 4178} 4179 4180/// isShuffleMaskLegal - Targets can use this to indicate that they only 4181/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4182/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4183/// are assumed to be legal. 4184bool 4185ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4186 EVT VT) const { 4187 if (VT.getVectorNumElements() == 4 && 4188 (VT.is128BitVector() || VT.is64BitVector())) { 4189 unsigned PFIndexes[4]; 4190 for (unsigned i = 0; i != 4; ++i) { 4191 if (M[i] < 0) 4192 PFIndexes[i] = 8; 4193 else 4194 PFIndexes[i] = M[i]; 4195 } 4196 4197 // Compute the index in the perfect shuffle table. 4198 unsigned PFTableIndex = 4199 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4200 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4201 unsigned Cost = (PFEntry >> 30); 4202 4203 if (Cost <= 4) 4204 return true; 4205 } 4206 4207 bool ReverseVEXT; 4208 unsigned Imm, WhichResult; 4209 4210 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4211 return (EltSize >= 32 || 4212 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4213 isVREVMask(M, VT, 64) || 4214 isVREVMask(M, VT, 32) || 4215 isVREVMask(M, VT, 16) || 4216 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4217 isVTBLMask(M, VT) || 4218 isVTRNMask(M, VT, WhichResult) || 4219 isVUZPMask(M, VT, WhichResult) || 4220 isVZIPMask(M, VT, WhichResult) || 4221 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4222 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4223 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4224} 4225 4226/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4227/// the specified operations to build the shuffle. 4228static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4229 SDValue RHS, SelectionDAG &DAG, 4230 DebugLoc dl) { 4231 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4232 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4233 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4234 4235 enum { 4236 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4237 OP_VREV, 4238 OP_VDUP0, 4239 OP_VDUP1, 4240 OP_VDUP2, 4241 OP_VDUP3, 4242 OP_VEXT1, 4243 OP_VEXT2, 4244 OP_VEXT3, 4245 OP_VUZPL, // VUZP, left result 4246 OP_VUZPR, // VUZP, right result 4247 OP_VZIPL, // VZIP, left result 4248 OP_VZIPR, // VZIP, right result 4249 OP_VTRNL, // VTRN, left result 4250 OP_VTRNR // VTRN, right result 4251 }; 4252 4253 if (OpNum == OP_COPY) { 4254 if (LHSID == (1*9+2)*9+3) return LHS; 4255 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4256 return RHS; 4257 } 4258 4259 SDValue OpLHS, OpRHS; 4260 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4261 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4262 EVT VT = OpLHS.getValueType(); 4263 4264 switch (OpNum) { 4265 default: llvm_unreachable("Unknown shuffle opcode!"); 4266 case OP_VREV: 4267 // VREV divides the vector in half and swaps within the half. 4268 if (VT.getVectorElementType() == MVT::i32 || 4269 VT.getVectorElementType() == MVT::f32) 4270 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4271 // vrev <4 x i16> -> VREV32 4272 if (VT.getVectorElementType() == MVT::i16) 4273 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4274 // vrev <4 x i8> -> VREV16 4275 assert(VT.getVectorElementType() == MVT::i8); 4276 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4277 case OP_VDUP0: 4278 case OP_VDUP1: 4279 case OP_VDUP2: 4280 case OP_VDUP3: 4281 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4282 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4283 case OP_VEXT1: 4284 case OP_VEXT2: 4285 case OP_VEXT3: 4286 return DAG.getNode(ARMISD::VEXT, dl, VT, 4287 OpLHS, OpRHS, 4288 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4289 case OP_VUZPL: 4290 case OP_VUZPR: 4291 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4292 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4293 case OP_VZIPL: 4294 case OP_VZIPR: 4295 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4296 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4297 case OP_VTRNL: 4298 case OP_VTRNR: 4299 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4300 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4301 } 4302} 4303 4304static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4305 SmallVectorImpl<int> &ShuffleMask, 4306 SelectionDAG &DAG) { 4307 // Check to see if we can use the VTBL instruction. 4308 SDValue V1 = Op.getOperand(0); 4309 SDValue V2 = Op.getOperand(1); 4310 DebugLoc DL = Op.getDebugLoc(); 4311 4312 SmallVector<SDValue, 8> VTBLMask; 4313 for (SmallVectorImpl<int>::iterator 4314 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4315 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4316 4317 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4318 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4319 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4320 &VTBLMask[0], 8)); 4321 4322 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4323 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4324 &VTBLMask[0], 8)); 4325} 4326 4327static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4328 SDValue V1 = Op.getOperand(0); 4329 SDValue V2 = Op.getOperand(1); 4330 DebugLoc dl = Op.getDebugLoc(); 4331 EVT VT = Op.getValueType(); 4332 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4333 SmallVector<int, 8> ShuffleMask; 4334 4335 // Convert shuffles that are directly supported on NEON to target-specific 4336 // DAG nodes, instead of keeping them as shuffles and matching them again 4337 // during code selection. This is more efficient and avoids the possibility 4338 // of inconsistencies between legalization and selection. 4339 // FIXME: floating-point vectors should be canonicalized to integer vectors 4340 // of the same time so that they get CSEd properly. 4341 SVN->getMask(ShuffleMask); 4342 4343 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4344 if (EltSize <= 32) { 4345 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4346 int Lane = SVN->getSplatIndex(); 4347 // If this is undef splat, generate it via "just" vdup, if possible. 4348 if (Lane == -1) Lane = 0; 4349 4350 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4351 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4352 } 4353 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4354 DAG.getConstant(Lane, MVT::i32)); 4355 } 4356 4357 bool ReverseVEXT; 4358 unsigned Imm; 4359 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4360 if (ReverseVEXT) 4361 std::swap(V1, V2); 4362 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4363 DAG.getConstant(Imm, MVT::i32)); 4364 } 4365 4366 if (isVREVMask(ShuffleMask, VT, 64)) 4367 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4368 if (isVREVMask(ShuffleMask, VT, 32)) 4369 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4370 if (isVREVMask(ShuffleMask, VT, 16)) 4371 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4372 4373 // Check for Neon shuffles that modify both input vectors in place. 4374 // If both results are used, i.e., if there are two shuffles with the same 4375 // source operands and with masks corresponding to both results of one of 4376 // these operations, DAG memoization will ensure that a single node is 4377 // used for both shuffles. 4378 unsigned WhichResult; 4379 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4381 V1, V2).getValue(WhichResult); 4382 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4383 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4384 V1, V2).getValue(WhichResult); 4385 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4386 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4387 V1, V2).getValue(WhichResult); 4388 4389 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4390 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4391 V1, V1).getValue(WhichResult); 4392 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4393 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4394 V1, V1).getValue(WhichResult); 4395 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4396 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4397 V1, V1).getValue(WhichResult); 4398 } 4399 4400 // If the shuffle is not directly supported and it has 4 elements, use 4401 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4402 unsigned NumElts = VT.getVectorNumElements(); 4403 if (NumElts == 4) { 4404 unsigned PFIndexes[4]; 4405 for (unsigned i = 0; i != 4; ++i) { 4406 if (ShuffleMask[i] < 0) 4407 PFIndexes[i] = 8; 4408 else 4409 PFIndexes[i] = ShuffleMask[i]; 4410 } 4411 4412 // Compute the index in the perfect shuffle table. 4413 unsigned PFTableIndex = 4414 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4415 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4416 unsigned Cost = (PFEntry >> 30); 4417 4418 if (Cost <= 4) 4419 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4420 } 4421 4422 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4423 if (EltSize >= 32) { 4424 // Do the expansion with floating-point types, since that is what the VFP 4425 // registers are defined to use, and since i64 is not legal. 4426 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4427 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4428 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4429 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4430 SmallVector<SDValue, 8> Ops; 4431 for (unsigned i = 0; i < NumElts; ++i) { 4432 if (ShuffleMask[i] < 0) 4433 Ops.push_back(DAG.getUNDEF(EltVT)); 4434 else 4435 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4436 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4437 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4438 MVT::i32))); 4439 } 4440 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4441 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4442 } 4443 4444 if (VT == MVT::v8i8) { 4445 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4446 if (NewOp.getNode()) 4447 return NewOp; 4448 } 4449 4450 return SDValue(); 4451} 4452 4453static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4454 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4455 SDValue Lane = Op.getOperand(1); 4456 if (!isa<ConstantSDNode>(Lane)) 4457 return SDValue(); 4458 4459 SDValue Vec = Op.getOperand(0); 4460 if (Op.getValueType() == MVT::i32 && 4461 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4462 DebugLoc dl = Op.getDebugLoc(); 4463 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4464 } 4465 4466 return Op; 4467} 4468 4469static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4470 // The only time a CONCAT_VECTORS operation can have legal types is when 4471 // two 64-bit vectors are concatenated to a 128-bit vector. 4472 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4473 "unexpected CONCAT_VECTORS"); 4474 DebugLoc dl = Op.getDebugLoc(); 4475 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4476 SDValue Op0 = Op.getOperand(0); 4477 SDValue Op1 = Op.getOperand(1); 4478 if (Op0.getOpcode() != ISD::UNDEF) 4479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4480 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4481 DAG.getIntPtrConstant(0)); 4482 if (Op1.getOpcode() != ISD::UNDEF) 4483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4484 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4485 DAG.getIntPtrConstant(1)); 4486 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4487} 4488 4489/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4490/// element has been zero/sign-extended, depending on the isSigned parameter, 4491/// from an integer type half its size. 4492static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4493 bool isSigned) { 4494 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4495 EVT VT = N->getValueType(0); 4496 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4497 SDNode *BVN = N->getOperand(0).getNode(); 4498 if (BVN->getValueType(0) != MVT::v4i32 || 4499 BVN->getOpcode() != ISD::BUILD_VECTOR) 4500 return false; 4501 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4502 unsigned HiElt = 1 - LoElt; 4503 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4504 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4505 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4506 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4507 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4508 return false; 4509 if (isSigned) { 4510 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4511 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4512 return true; 4513 } else { 4514 if (Hi0->isNullValue() && Hi1->isNullValue()) 4515 return true; 4516 } 4517 return false; 4518 } 4519 4520 if (N->getOpcode() != ISD::BUILD_VECTOR) 4521 return false; 4522 4523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4524 SDNode *Elt = N->getOperand(i).getNode(); 4525 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4526 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4527 unsigned HalfSize = EltSize / 2; 4528 if (isSigned) { 4529 if (!isIntN(HalfSize, C->getSExtValue())) 4530 return false; 4531 } else { 4532 if (!isUIntN(HalfSize, C->getZExtValue())) 4533 return false; 4534 } 4535 continue; 4536 } 4537 return false; 4538 } 4539 4540 return true; 4541} 4542 4543/// isSignExtended - Check if a node is a vector value that is sign-extended 4544/// or a constant BUILD_VECTOR with sign-extended elements. 4545static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4546 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4547 return true; 4548 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4549 return true; 4550 return false; 4551} 4552 4553/// isZeroExtended - Check if a node is a vector value that is zero-extended 4554/// or a constant BUILD_VECTOR with zero-extended elements. 4555static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4556 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4557 return true; 4558 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4559 return true; 4560 return false; 4561} 4562 4563/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4564/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4565static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4566 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4567 return N->getOperand(0); 4568 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4569 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4570 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4571 LD->isNonTemporal(), LD->getAlignment()); 4572 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4573 // have been legalized as a BITCAST from v4i32. 4574 if (N->getOpcode() == ISD::BITCAST) { 4575 SDNode *BVN = N->getOperand(0).getNode(); 4576 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4577 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4578 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4579 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4580 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4581 } 4582 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4583 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4584 EVT VT = N->getValueType(0); 4585 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4586 unsigned NumElts = VT.getVectorNumElements(); 4587 MVT TruncVT = MVT::getIntegerVT(EltSize); 4588 SmallVector<SDValue, 8> Ops; 4589 for (unsigned i = 0; i != NumElts; ++i) { 4590 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4591 const APInt &CInt = C->getAPIntValue(); 4592 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4593 } 4594 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4595 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4596} 4597 4598static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4599 unsigned Opcode = N->getOpcode(); 4600 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4601 SDNode *N0 = N->getOperand(0).getNode(); 4602 SDNode *N1 = N->getOperand(1).getNode(); 4603 return N0->hasOneUse() && N1->hasOneUse() && 4604 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4605 } 4606 return false; 4607} 4608 4609static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4610 unsigned Opcode = N->getOpcode(); 4611 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4612 SDNode *N0 = N->getOperand(0).getNode(); 4613 SDNode *N1 = N->getOperand(1).getNode(); 4614 return N0->hasOneUse() && N1->hasOneUse() && 4615 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4616 } 4617 return false; 4618} 4619 4620static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4621 // Multiplications are only custom-lowered for 128-bit vectors so that 4622 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4623 EVT VT = Op.getValueType(); 4624 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4625 SDNode *N0 = Op.getOperand(0).getNode(); 4626 SDNode *N1 = Op.getOperand(1).getNode(); 4627 unsigned NewOpc = 0; 4628 bool isMLA = false; 4629 bool isN0SExt = isSignExtended(N0, DAG); 4630 bool isN1SExt = isSignExtended(N1, DAG); 4631 if (isN0SExt && isN1SExt) 4632 NewOpc = ARMISD::VMULLs; 4633 else { 4634 bool isN0ZExt = isZeroExtended(N0, DAG); 4635 bool isN1ZExt = isZeroExtended(N1, DAG); 4636 if (isN0ZExt && isN1ZExt) 4637 NewOpc = ARMISD::VMULLu; 4638 else if (isN1SExt || isN1ZExt) { 4639 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4640 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4641 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4642 NewOpc = ARMISD::VMULLs; 4643 isMLA = true; 4644 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4645 NewOpc = ARMISD::VMULLu; 4646 isMLA = true; 4647 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4648 std::swap(N0, N1); 4649 NewOpc = ARMISD::VMULLu; 4650 isMLA = true; 4651 } 4652 } 4653 4654 if (!NewOpc) { 4655 if (VT == MVT::v2i64) 4656 // Fall through to expand this. It is not legal. 4657 return SDValue(); 4658 else 4659 // Other vector multiplications are legal. 4660 return Op; 4661 } 4662 } 4663 4664 // Legalize to a VMULL instruction. 4665 DebugLoc DL = Op.getDebugLoc(); 4666 SDValue Op0; 4667 SDValue Op1 = SkipExtension(N1, DAG); 4668 if (!isMLA) { 4669 Op0 = SkipExtension(N0, DAG); 4670 assert(Op0.getValueType().is64BitVector() && 4671 Op1.getValueType().is64BitVector() && 4672 "unexpected types for extended operands to VMULL"); 4673 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4674 } 4675 4676 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4677 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4678 // vmull q0, d4, d6 4679 // vmlal q0, d5, d6 4680 // is faster than 4681 // vaddl q0, d4, d5 4682 // vmovl q1, d6 4683 // vmul q0, q0, q1 4684 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4685 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4686 EVT Op1VT = Op1.getValueType(); 4687 return DAG.getNode(N0->getOpcode(), DL, VT, 4688 DAG.getNode(NewOpc, DL, VT, 4689 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4690 DAG.getNode(NewOpc, DL, VT, 4691 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4692} 4693 4694static SDValue 4695LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4696 // Convert to float 4697 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4698 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4699 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4700 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4701 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4702 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4703 // Get reciprocal estimate. 4704 // float4 recip = vrecpeq_f32(yf); 4705 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4706 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4707 // Because char has a smaller range than uchar, we can actually get away 4708 // without any newton steps. This requires that we use a weird bias 4709 // of 0xb000, however (again, this has been exhaustively tested). 4710 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4711 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4712 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4713 Y = DAG.getConstant(0xb000, MVT::i32); 4714 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4715 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4716 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4717 // Convert back to short. 4718 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4719 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4720 return X; 4721} 4722 4723static SDValue 4724LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4725 SDValue N2; 4726 // Convert to float. 4727 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4728 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4729 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4730 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4731 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4732 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4733 4734 // Use reciprocal estimate and one refinement step. 4735 // float4 recip = vrecpeq_f32(yf); 4736 // recip *= vrecpsq_f32(yf, recip); 4737 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4738 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4739 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4740 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4741 N1, N2); 4742 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4743 // Because short has a smaller range than ushort, we can actually get away 4744 // with only a single newton step. This requires that we use a weird bias 4745 // of 89, however (again, this has been exhaustively tested). 4746 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4747 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4748 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4749 N1 = DAG.getConstant(0x89, MVT::i32); 4750 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4751 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4752 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4753 // Convert back to integer and return. 4754 // return vmovn_s32(vcvt_s32_f32(result)); 4755 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4756 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4757 return N0; 4758} 4759 4760static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4761 EVT VT = Op.getValueType(); 4762 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4763 "unexpected type for custom-lowering ISD::SDIV"); 4764 4765 DebugLoc dl = Op.getDebugLoc(); 4766 SDValue N0 = Op.getOperand(0); 4767 SDValue N1 = Op.getOperand(1); 4768 SDValue N2, N3; 4769 4770 if (VT == MVT::v8i8) { 4771 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4772 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4773 4774 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4775 DAG.getIntPtrConstant(4)); 4776 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4777 DAG.getIntPtrConstant(4)); 4778 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4779 DAG.getIntPtrConstant(0)); 4780 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4781 DAG.getIntPtrConstant(0)); 4782 4783 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4784 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4785 4786 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4787 N0 = LowerCONCAT_VECTORS(N0, DAG); 4788 4789 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4790 return N0; 4791 } 4792 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4793} 4794 4795static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4796 EVT VT = Op.getValueType(); 4797 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4798 "unexpected type for custom-lowering ISD::UDIV"); 4799 4800 DebugLoc dl = Op.getDebugLoc(); 4801 SDValue N0 = Op.getOperand(0); 4802 SDValue N1 = Op.getOperand(1); 4803 SDValue N2, N3; 4804 4805 if (VT == MVT::v8i8) { 4806 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4807 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4808 4809 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4810 DAG.getIntPtrConstant(4)); 4811 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4812 DAG.getIntPtrConstant(4)); 4813 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4814 DAG.getIntPtrConstant(0)); 4815 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4816 DAG.getIntPtrConstant(0)); 4817 4818 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4819 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4820 4821 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4822 N0 = LowerCONCAT_VECTORS(N0, DAG); 4823 4824 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4825 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4826 N0); 4827 return N0; 4828 } 4829 4830 // v4i16 sdiv ... Convert to float. 4831 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4832 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4833 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4834 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4835 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4836 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4837 4838 // Use reciprocal estimate and two refinement steps. 4839 // float4 recip = vrecpeq_f32(yf); 4840 // recip *= vrecpsq_f32(yf, recip); 4841 // recip *= vrecpsq_f32(yf, recip); 4842 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4843 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4844 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4845 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4846 BN1, N2); 4847 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4848 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4849 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4850 BN1, N2); 4851 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4852 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4853 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4854 // and that it will never cause us to return an answer too large). 4855 // float4 result = as_float4(as_int4(xf*recip) + 2); 4856 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4857 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4858 N1 = DAG.getConstant(2, MVT::i32); 4859 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4860 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4861 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4862 // Convert back to integer and return. 4863 // return vmovn_u32(vcvt_s32_f32(result)); 4864 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4865 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4866 return N0; 4867} 4868 4869static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4870 EVT VT = Op.getNode()->getValueType(0); 4871 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4872 4873 unsigned Opc; 4874 bool ExtraOp = false; 4875 switch (Op.getOpcode()) { 4876 default: assert(0 && "Invalid code"); 4877 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4878 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4879 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4880 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4881 } 4882 4883 if (!ExtraOp) 4884 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4885 Op.getOperand(1)); 4886 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4887 Op.getOperand(1), Op.getOperand(2)); 4888} 4889 4890static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 4891 // Monotonic load/store is legal for all targets 4892 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 4893 return Op; 4894 4895 // Aquire/Release load/store is not legal for targets without a 4896 // dmb or equivalent available. 4897 return SDValue(); 4898} 4899 4900 4901static void 4902ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 4903 SelectionDAG &DAG, unsigned NewOp) { 4904 DebugLoc dl = Node->getDebugLoc(); 4905 assert (Node->getValueType(0) == MVT::i64 && 4906 "Only know how to expand i64 atomics"); 4907 4908 SmallVector<SDValue, 6> Ops; 4909 Ops.push_back(Node->getOperand(0)); // Chain 4910 Ops.push_back(Node->getOperand(1)); // Ptr 4911 // Low part of Val1 4912 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4913 Node->getOperand(2), DAG.getIntPtrConstant(0))); 4914 // High part of Val1 4915 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4916 Node->getOperand(2), DAG.getIntPtrConstant(1))); 4917 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 4918 // High part of Val1 4919 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4920 Node->getOperand(3), DAG.getIntPtrConstant(0))); 4921 // High part of Val2 4922 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4923 Node->getOperand(3), DAG.getIntPtrConstant(1))); 4924 } 4925 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4926 SDValue Result = 4927 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 4928 cast<MemSDNode>(Node)->getMemOperand()); 4929 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 4930 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 4931 Results.push_back(Result.getValue(2)); 4932} 4933 4934SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4935 switch (Op.getOpcode()) { 4936 default: llvm_unreachable("Don't know how to custom lower this!"); 4937 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4938 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4939 case ISD::GlobalAddress: 4940 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 4941 LowerGlobalAddressELF(Op, DAG); 4942 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4943 case ISD::SELECT: return LowerSELECT(Op, DAG); 4944 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4945 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 4946 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 4947 case ISD::VASTART: return LowerVASTART(Op, DAG); 4948 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 4949 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 4950 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 4951 case ISD::SINT_TO_FP: 4952 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 4953 case ISD::FP_TO_SINT: 4954 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 4955 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4956 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4957 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4958 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 4959 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 4960 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 4961 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); 4962 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 4963 Subtarget); 4964 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 4965 case ISD::SHL: 4966 case ISD::SRL: 4967 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 4968 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 4969 case ISD::SRL_PARTS: 4970 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 4971 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 4972 case ISD::SETCC: return LowerVSETCC(Op, DAG); 4973 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 4974 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4975 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4976 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 4977 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4978 case ISD::MUL: return LowerMUL(Op, DAG); 4979 case ISD::SDIV: return LowerSDIV(Op, DAG); 4980 case ISD::UDIV: return LowerUDIV(Op, DAG); 4981 case ISD::ADDC: 4982 case ISD::ADDE: 4983 case ISD::SUBC: 4984 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 4985 case ISD::ATOMIC_LOAD: 4986 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 4987 } 4988 return SDValue(); 4989} 4990 4991/// ReplaceNodeResults - Replace the results of node with an illegal result 4992/// type with new values built out of custom code. 4993void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 4994 SmallVectorImpl<SDValue>&Results, 4995 SelectionDAG &DAG) const { 4996 SDValue Res; 4997 switch (N->getOpcode()) { 4998 default: 4999 llvm_unreachable("Don't know how to custom expand this!"); 5000 break; 5001 case ISD::BITCAST: 5002 Res = ExpandBITCAST(N, DAG); 5003 break; 5004 case ISD::SRL: 5005 case ISD::SRA: 5006 Res = Expand64BitShift(N, DAG, Subtarget); 5007 break; 5008 case ISD::ATOMIC_LOAD_ADD: 5009 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5010 return; 5011 case ISD::ATOMIC_LOAD_AND: 5012 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5013 return; 5014 case ISD::ATOMIC_LOAD_NAND: 5015 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5016 return; 5017 case ISD::ATOMIC_LOAD_OR: 5018 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5019 return; 5020 case ISD::ATOMIC_LOAD_SUB: 5021 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5022 return; 5023 case ISD::ATOMIC_LOAD_XOR: 5024 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5025 return; 5026 case ISD::ATOMIC_SWAP: 5027 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5028 return; 5029 case ISD::ATOMIC_CMP_SWAP: 5030 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5031 return; 5032 } 5033 if (Res.getNode()) 5034 Results.push_back(Res); 5035} 5036 5037//===----------------------------------------------------------------------===// 5038// ARM Scheduler Hooks 5039//===----------------------------------------------------------------------===// 5040 5041MachineBasicBlock * 5042ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5043 MachineBasicBlock *BB, 5044 unsigned Size) const { 5045 unsigned dest = MI->getOperand(0).getReg(); 5046 unsigned ptr = MI->getOperand(1).getReg(); 5047 unsigned oldval = MI->getOperand(2).getReg(); 5048 unsigned newval = MI->getOperand(3).getReg(); 5049 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5050 DebugLoc dl = MI->getDebugLoc(); 5051 bool isThumb2 = Subtarget->isThumb2(); 5052 5053 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5054 unsigned scratch = 5055 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5056 : ARM::GPRRegisterClass); 5057 5058 if (isThumb2) { 5059 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5060 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5061 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5062 } 5063 5064 unsigned ldrOpc, strOpc; 5065 switch (Size) { 5066 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5067 case 1: 5068 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5069 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5070 break; 5071 case 2: 5072 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5073 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5074 break; 5075 case 4: 5076 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5077 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5078 break; 5079 } 5080 5081 MachineFunction *MF = BB->getParent(); 5082 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5083 MachineFunction::iterator It = BB; 5084 ++It; // insert the new blocks after the current block 5085 5086 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5087 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5088 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5089 MF->insert(It, loop1MBB); 5090 MF->insert(It, loop2MBB); 5091 MF->insert(It, exitMBB); 5092 5093 // Transfer the remainder of BB and its successor edges to exitMBB. 5094 exitMBB->splice(exitMBB->begin(), BB, 5095 llvm::next(MachineBasicBlock::iterator(MI)), 5096 BB->end()); 5097 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5098 5099 // thisMBB: 5100 // ... 5101 // fallthrough --> loop1MBB 5102 BB->addSuccessor(loop1MBB); 5103 5104 // loop1MBB: 5105 // ldrex dest, [ptr] 5106 // cmp dest, oldval 5107 // bne exitMBB 5108 BB = loop1MBB; 5109 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5110 if (ldrOpc == ARM::t2LDREX) 5111 MIB.addImm(0); 5112 AddDefaultPred(MIB); 5113 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5114 .addReg(dest).addReg(oldval)); 5115 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5116 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5117 BB->addSuccessor(loop2MBB); 5118 BB->addSuccessor(exitMBB); 5119 5120 // loop2MBB: 5121 // strex scratch, newval, [ptr] 5122 // cmp scratch, #0 5123 // bne loop1MBB 5124 BB = loop2MBB; 5125 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5126 if (strOpc == ARM::t2STREX) 5127 MIB.addImm(0); 5128 AddDefaultPred(MIB); 5129 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5130 .addReg(scratch).addImm(0)); 5131 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5132 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5133 BB->addSuccessor(loop1MBB); 5134 BB->addSuccessor(exitMBB); 5135 5136 // exitMBB: 5137 // ... 5138 BB = exitMBB; 5139 5140 MI->eraseFromParent(); // The instruction is gone now. 5141 5142 return BB; 5143} 5144 5145MachineBasicBlock * 5146ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5147 unsigned Size, unsigned BinOpcode) const { 5148 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5149 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5150 5151 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5152 MachineFunction *MF = BB->getParent(); 5153 MachineFunction::iterator It = BB; 5154 ++It; 5155 5156 unsigned dest = MI->getOperand(0).getReg(); 5157 unsigned ptr = MI->getOperand(1).getReg(); 5158 unsigned incr = MI->getOperand(2).getReg(); 5159 DebugLoc dl = MI->getDebugLoc(); 5160 bool isThumb2 = Subtarget->isThumb2(); 5161 5162 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5163 if (isThumb2) { 5164 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5165 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5166 } 5167 5168 unsigned ldrOpc, strOpc; 5169 switch (Size) { 5170 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5171 case 1: 5172 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5173 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5174 break; 5175 case 2: 5176 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5177 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5178 break; 5179 case 4: 5180 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5181 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5182 break; 5183 } 5184 5185 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5186 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5187 MF->insert(It, loopMBB); 5188 MF->insert(It, exitMBB); 5189 5190 // Transfer the remainder of BB and its successor edges to exitMBB. 5191 exitMBB->splice(exitMBB->begin(), BB, 5192 llvm::next(MachineBasicBlock::iterator(MI)), 5193 BB->end()); 5194 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5195 5196 TargetRegisterClass *TRC = 5197 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5198 unsigned scratch = MRI.createVirtualRegister(TRC); 5199 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5200 5201 // thisMBB: 5202 // ... 5203 // fallthrough --> loopMBB 5204 BB->addSuccessor(loopMBB); 5205 5206 // loopMBB: 5207 // ldrex dest, ptr 5208 // <binop> scratch2, dest, incr 5209 // strex scratch, scratch2, ptr 5210 // cmp scratch, #0 5211 // bne- loopMBB 5212 // fallthrough --> exitMBB 5213 BB = loopMBB; 5214 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5215 if (ldrOpc == ARM::t2LDREX) 5216 MIB.addImm(0); 5217 AddDefaultPred(MIB); 5218 if (BinOpcode) { 5219 // operand order needs to go the other way for NAND 5220 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5221 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5222 addReg(incr).addReg(dest)).addReg(0); 5223 else 5224 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5225 addReg(dest).addReg(incr)).addReg(0); 5226 } 5227 5228 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5229 if (strOpc == ARM::t2STREX) 5230 MIB.addImm(0); 5231 AddDefaultPred(MIB); 5232 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5233 .addReg(scratch).addImm(0)); 5234 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5235 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5236 5237 BB->addSuccessor(loopMBB); 5238 BB->addSuccessor(exitMBB); 5239 5240 // exitMBB: 5241 // ... 5242 BB = exitMBB; 5243 5244 MI->eraseFromParent(); // The instruction is gone now. 5245 5246 return BB; 5247} 5248 5249MachineBasicBlock * 5250ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5251 MachineBasicBlock *BB, 5252 unsigned Size, 5253 bool signExtend, 5254 ARMCC::CondCodes Cond) const { 5255 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5256 5257 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5258 MachineFunction *MF = BB->getParent(); 5259 MachineFunction::iterator It = BB; 5260 ++It; 5261 5262 unsigned dest = MI->getOperand(0).getReg(); 5263 unsigned ptr = MI->getOperand(1).getReg(); 5264 unsigned incr = MI->getOperand(2).getReg(); 5265 unsigned oldval = dest; 5266 DebugLoc dl = MI->getDebugLoc(); 5267 bool isThumb2 = Subtarget->isThumb2(); 5268 5269 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5270 if (isThumb2) { 5271 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5272 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5273 } 5274 5275 unsigned ldrOpc, strOpc, extendOpc; 5276 switch (Size) { 5277 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5278 case 1: 5279 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5280 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5281 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5282 break; 5283 case 2: 5284 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5285 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5286 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5287 break; 5288 case 4: 5289 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5290 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5291 extendOpc = 0; 5292 break; 5293 } 5294 5295 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5296 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5297 MF->insert(It, loopMBB); 5298 MF->insert(It, exitMBB); 5299 5300 // Transfer the remainder of BB and its successor edges to exitMBB. 5301 exitMBB->splice(exitMBB->begin(), BB, 5302 llvm::next(MachineBasicBlock::iterator(MI)), 5303 BB->end()); 5304 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5305 5306 TargetRegisterClass *TRC = 5307 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5308 unsigned scratch = MRI.createVirtualRegister(TRC); 5309 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5310 5311 // thisMBB: 5312 // ... 5313 // fallthrough --> loopMBB 5314 BB->addSuccessor(loopMBB); 5315 5316 // loopMBB: 5317 // ldrex dest, ptr 5318 // (sign extend dest, if required) 5319 // cmp dest, incr 5320 // cmov.cond scratch2, dest, incr 5321 // strex scratch, scratch2, ptr 5322 // cmp scratch, #0 5323 // bne- loopMBB 5324 // fallthrough --> exitMBB 5325 BB = loopMBB; 5326 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5327 if (ldrOpc == ARM::t2LDREX) 5328 MIB.addImm(0); 5329 AddDefaultPred(MIB); 5330 5331 // Sign extend the value, if necessary. 5332 if (signExtend && extendOpc) { 5333 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5334 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5335 .addReg(dest) 5336 .addImm(0)); 5337 } 5338 5339 // Build compare and cmov instructions. 5340 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5341 .addReg(oldval).addReg(incr)); 5342 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5343 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5344 5345 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5346 if (strOpc == ARM::t2STREX) 5347 MIB.addImm(0); 5348 AddDefaultPred(MIB); 5349 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5350 .addReg(scratch).addImm(0)); 5351 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5352 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5353 5354 BB->addSuccessor(loopMBB); 5355 BB->addSuccessor(exitMBB); 5356 5357 // exitMBB: 5358 // ... 5359 BB = exitMBB; 5360 5361 MI->eraseFromParent(); // The instruction is gone now. 5362 5363 return BB; 5364} 5365 5366MachineBasicBlock * 5367ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5368 unsigned Op1, unsigned Op2, 5369 bool NeedsCarry, bool IsCmpxchg) const { 5370 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5371 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5372 5373 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5374 MachineFunction *MF = BB->getParent(); 5375 MachineFunction::iterator It = BB; 5376 ++It; 5377 5378 unsigned destlo = MI->getOperand(0).getReg(); 5379 unsigned desthi = MI->getOperand(1).getReg(); 5380 unsigned ptr = MI->getOperand(2).getReg(); 5381 unsigned vallo = MI->getOperand(3).getReg(); 5382 unsigned valhi = MI->getOperand(4).getReg(); 5383 DebugLoc dl = MI->getDebugLoc(); 5384 bool isThumb2 = Subtarget->isThumb2(); 5385 5386 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5387 if (isThumb2) { 5388 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5389 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5390 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5391 } 5392 5393 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5394 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5395 5396 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5397 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5398 if (IsCmpxchg) { 5399 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5400 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5401 } 5402 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5403 MF->insert(It, loopMBB); 5404 if (IsCmpxchg) { 5405 MF->insert(It, contBB); 5406 MF->insert(It, cont2BB); 5407 } 5408 MF->insert(It, exitMBB); 5409 5410 // Transfer the remainder of BB and its successor edges to exitMBB. 5411 exitMBB->splice(exitMBB->begin(), BB, 5412 llvm::next(MachineBasicBlock::iterator(MI)), 5413 BB->end()); 5414 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5415 5416 TargetRegisterClass *TRC = 5417 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5418 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5419 5420 // thisMBB: 5421 // ... 5422 // fallthrough --> loopMBB 5423 BB->addSuccessor(loopMBB); 5424 5425 // loopMBB: 5426 // ldrexd r2, r3, ptr 5427 // <binopa> r0, r2, incr 5428 // <binopb> r1, r3, incr 5429 // strexd storesuccess, r0, r1, ptr 5430 // cmp storesuccess, #0 5431 // bne- loopMBB 5432 // fallthrough --> exitMBB 5433 // 5434 // Note that the registers are explicitly specified because there is not any 5435 // way to force the register allocator to allocate a register pair. 5436 // 5437 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5438 // need to properly enforce the restriction that the two output registers 5439 // for ldrexd must be different. 5440 BB = loopMBB; 5441 // Load 5442 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5443 .addReg(ARM::R2, RegState::Define) 5444 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5445 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5446 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5447 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5448 5449 if (IsCmpxchg) { 5450 // Add early exit 5451 for (unsigned i = 0; i < 2; i++) { 5452 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5453 ARM::CMPrr)) 5454 .addReg(i == 0 ? destlo : desthi) 5455 .addReg(i == 0 ? vallo : valhi)); 5456 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5457 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5458 BB->addSuccessor(exitMBB); 5459 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5460 BB = (i == 0 ? contBB : cont2BB); 5461 } 5462 5463 // Copy to physregs for strexd 5464 unsigned setlo = MI->getOperand(5).getReg(); 5465 unsigned sethi = MI->getOperand(6).getReg(); 5466 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5467 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5468 } else if (Op1) { 5469 // Perform binary operation 5470 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5471 .addReg(destlo).addReg(vallo)) 5472 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5473 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5474 .addReg(desthi).addReg(valhi)).addReg(0); 5475 } else { 5476 // Copy to physregs for strexd 5477 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5478 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5479 } 5480 5481 // Store 5482 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5483 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5484 // Cmp+jump 5485 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5486 .addReg(storesuccess).addImm(0)); 5487 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5488 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5489 5490 BB->addSuccessor(loopMBB); 5491 BB->addSuccessor(exitMBB); 5492 5493 // exitMBB: 5494 // ... 5495 BB = exitMBB; 5496 5497 MI->eraseFromParent(); // The instruction is gone now. 5498 5499 return BB; 5500} 5501 5502/// EmitBasePointerRecalculation - For functions using a base pointer, we 5503/// rematerialize it (via the frame pointer). 5504void ARMTargetLowering:: 5505EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB, 5506 MachineBasicBlock *DispatchBB) const { 5507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5508 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 5509 MachineFunction &MF = *MI->getParent()->getParent(); 5510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5511 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 5512 5513 if (!RI.hasBasePointer(MF)) return; 5514 5515 MachineBasicBlock::iterator MBBI = MI; 5516 5517 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 5518 unsigned FramePtr = RI.getFrameRegister(MF); 5519 assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 5520 "Base pointer without frame pointer?"); 5521 5522 if (AFI->isThumb2Function()) 5523 llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5524 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5525 else if (AFI->isThumbFunction()) 5526 llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5527 FramePtr, -NumBytes, *AII, RI); 5528 else 5529 llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5530 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5531 5532 if (!RI.needsStackRealignment(MF)) return; 5533 5534 // If there's dynamic realignment, adjust for it. 5535 MachineFrameInfo *MFI = MF.getFrameInfo(); 5536 unsigned MaxAlign = MFI->getMaxAlignment(); 5537 assert(!AFI->isThumb1OnlyFunction()); 5538 5539 // Emit bic r6, r6, MaxAlign 5540 unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 5541 AddDefaultCC( 5542 AddDefaultPred( 5543 BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6) 5544 .addReg(ARM::R6, RegState::Kill) 5545 .addImm(MaxAlign - 1))); 5546} 5547 5548/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5549/// registers the function context. 5550void ARMTargetLowering:: 5551SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5552 MachineBasicBlock *DispatchBB, int FI) const { 5553 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5554 DebugLoc dl = MI->getDebugLoc(); 5555 MachineFunction *MF = MBB->getParent(); 5556 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5557 MachineConstantPool *MCP = MF->getConstantPool(); 5558 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5559 const Function *F = MF->getFunction(); 5560 5561 bool isThumb = Subtarget->isThumb(); 5562 bool isThumb2 = Subtarget->isThumb2(); 5563 5564 unsigned PCLabelId = AFI->createPICLabelUId(); 5565 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5566 ARMConstantPoolValue *CPV = 5567 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5568 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5569 5570 const TargetRegisterClass *TRC = 5571 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5572 5573 // Grab constant pool and fixed stack memory operands. 5574 MachineMemOperand *CPMMO = 5575 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5576 MachineMemOperand::MOLoad, 4, 4); 5577 5578 MachineMemOperand *FIMMOSt = 5579 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5580 MachineMemOperand::MOStore, 4, 4); 5581 5582 EmitBasePointerRecalculation(MI, MBB, DispatchBB); 5583 5584 // Load the address of the dispatch MBB into the jump buffer. 5585 if (isThumb2) { 5586 // Incoming value: jbuf 5587 // ldr.n r5, LCPI1_1 5588 // orr r5, r5, #1 5589 // add r5, pc 5590 // str r5, [$jbuf, #+4] ; &jbuf[1] 5591 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5592 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5593 .addConstantPoolIndex(CPI) 5594 .addMemOperand(CPMMO)); 5595 // Set the low bit because of thumb mode. 5596 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5597 AddDefaultCC( 5598 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5599 .addReg(NewVReg1, RegState::Kill) 5600 .addImm(0x01))); 5601 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5602 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5603 .addReg(NewVReg2, RegState::Kill) 5604 .addImm(PCLabelId); 5605 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5606 .addReg(NewVReg3, RegState::Kill) 5607 .addFrameIndex(FI) 5608 .addImm(36) // &jbuf[1] :: pc 5609 .addMemOperand(FIMMOSt)); 5610 } else if (isThumb) { 5611 // Incoming value: jbuf 5612 // ldr.n r1, LCPI1_4 5613 // add r1, pc 5614 // mov r2, #1 5615 // orrs r1, r2 5616 // add r2, $jbuf, #+4 ; &jbuf[1] 5617 // str r1, [r2] 5618 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5619 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5620 .addConstantPoolIndex(CPI) 5621 .addMemOperand(CPMMO)); 5622 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5623 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5624 .addReg(NewVReg1, RegState::Kill) 5625 .addImm(PCLabelId); 5626 // Set the low bit because of thumb mode. 5627 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5628 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5629 .addReg(ARM::CPSR, RegState::Define) 5630 .addImm(1)); 5631 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5632 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5633 .addReg(ARM::CPSR, RegState::Define) 5634 .addReg(NewVReg2, RegState::Kill) 5635 .addReg(NewVReg3, RegState::Kill)); 5636 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5637 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5638 .addFrameIndex(FI) 5639 .addImm(36)); // &jbuf[1] :: pc 5640 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5641 .addReg(NewVReg4, RegState::Kill) 5642 .addReg(NewVReg5, RegState::Kill) 5643 .addImm(0) 5644 .addMemOperand(FIMMOSt)); 5645 } else { 5646 // Incoming value: jbuf 5647 // ldr r1, LCPI1_1 5648 // add r1, pc, r1 5649 // str r1, [$jbuf, #+4] ; &jbuf[1] 5650 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5651 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5652 .addConstantPoolIndex(CPI) 5653 .addImm(0) 5654 .addMemOperand(CPMMO)); 5655 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5656 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5657 .addReg(NewVReg1, RegState::Kill) 5658 .addImm(PCLabelId)); 5659 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5660 .addReg(NewVReg2, RegState::Kill) 5661 .addFrameIndex(FI) 5662 .addImm(36) // &jbuf[1] :: pc 5663 .addMemOperand(FIMMOSt)); 5664 } 5665} 5666 5667MachineBasicBlock *ARMTargetLowering:: 5668EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5669 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5670 DebugLoc dl = MI->getDebugLoc(); 5671 MachineFunction *MF = MBB->getParent(); 5672 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5673 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5674 MachineFrameInfo *MFI = MF->getFrameInfo(); 5675 int FI = MFI->getFunctionContextIndex(); 5676 5677 const TargetRegisterClass *TRC = 5678 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5679 5680 // Get a mapping of the call site numbers to all of the landing pads they're 5681 // associated with. 5682 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5683 unsigned MaxCSNum = 0; 5684 MachineModuleInfo &MMI = MF->getMMI(); 5685 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) { 5686 if (!BB->isLandingPad()) continue; 5687 5688 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5689 // pad. 5690 for (MachineBasicBlock::iterator 5691 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5692 if (!II->isEHLabel()) continue; 5693 5694 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5695 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5696 5697 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5698 for (SmallVectorImpl<unsigned>::iterator 5699 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5700 CSI != CSE; ++CSI) { 5701 CallSiteNumToLPad[*CSI].push_back(BB); 5702 MaxCSNum = std::max(MaxCSNum, *CSI); 5703 } 5704 break; 5705 } 5706 } 5707 5708 // Get an ordered list of the machine basic blocks for the jump table. 5709 std::vector<MachineBasicBlock*> LPadList; 5710 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs; 5711 LPadList.reserve(CallSiteNumToLPad.size()); 5712 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5713 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5714 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5715 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) { 5716 LPadList.push_back(*II); 5717 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end()); 5718 } 5719 } 5720 5721 assert(!LPadList.empty() && 5722 "No landing pad destinations for the dispatch jump table!"); 5723 5724 // Create the jump table and associated information. 5725 MachineJumpTableInfo *JTI = 5726 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5727 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5728 unsigned UId = AFI->createJumpTableUId(); 5729 5730 // Create the MBBs for the dispatch code. 5731 5732 // Shove the dispatch's address into the return slot in the function context. 5733 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 5734 DispatchBB->setIsLandingPad(); 5735 5736 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 5737 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 5738 DispatchBB->addSuccessor(TrapBB); 5739 5740 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 5741 DispatchBB->addSuccessor(DispContBB); 5742 5743 // Insert and MBBs. 5744 MF->insert(MF->end(), DispatchBB); 5745 MF->insert(MF->end(), DispContBB); 5746 MF->insert(MF->end(), TrapBB); 5747 5748 // Insert code into the entry block that creates and registers the function 5749 // context. 5750 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 5751 5752 MachineMemOperand *FIMMOLd = 5753 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5754 MachineMemOperand::MOLoad | 5755 MachineMemOperand::MOVolatile, 4, 4); 5756 5757 unsigned NumLPads = LPadList.size(); 5758 if (Subtarget->isThumb2()) { 5759 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5760 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 5761 .addFrameIndex(FI) 5762 .addImm(4) 5763 .addMemOperand(FIMMOLd)); 5764 5765 if (NumLPads < 256) { 5766 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 5767 .addReg(NewVReg1) 5768 .addImm(LPadList.size())); 5769 } else { 5770 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5771 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) 5772 .addImm(NumLPads & 0xFFFF)); 5773 5774 unsigned VReg2 = VReg1; 5775 if ((NumLPads & 0xFFFF0000) != 0) { 5776 VReg2 = MRI->createVirtualRegister(TRC); 5777 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2) 5778 .addReg(VReg1) 5779 .addImm(NumLPads >> 16)); 5780 } 5781 5782 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr)) 5783 .addReg(NewVReg1) 5784 .addReg(VReg2)); 5785 } 5786 5787 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 5788 .addMBB(TrapBB) 5789 .addImm(ARMCC::HI) 5790 .addReg(ARM::CPSR); 5791 5792 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5793 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3) 5794 .addJumpTableIndex(MJTI) 5795 .addImm(UId)); 5796 5797 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5798 AddDefaultCC( 5799 AddDefaultPred( 5800 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4) 5801 .addReg(NewVReg3, RegState::Kill) 5802 .addReg(NewVReg1) 5803 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5804 5805 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 5806 .addReg(NewVReg4, RegState::Kill) 5807 .addReg(NewVReg1) 5808 .addJumpTableIndex(MJTI) 5809 .addImm(UId); 5810 } else if (Subtarget->isThumb()) { 5811 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5812 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 5813 .addFrameIndex(FI) 5814 .addImm(1) 5815 .addMemOperand(FIMMOLd)); 5816 5817 if (NumLPads < 256) { 5818 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 5819 .addReg(NewVReg1) 5820 .addImm(NumLPads)); 5821 } else { 5822 MachineConstantPool *ConstantPool = MF->getConstantPool(); 5823 const Constant *C = 5824 ConstantInt::get(Type::getInt32Ty(MF->getFunction()->getContext()), 5825 NumLPads); 5826 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 5827 5828 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5829 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci)) 5830 .addReg(VReg1, RegState::Define) 5831 .addConstantPoolIndex(Idx)); 5832 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr)) 5833 .addReg(NewVReg1) 5834 .addReg(VReg1)); 5835 } 5836 5837 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 5838 .addMBB(TrapBB) 5839 .addImm(ARMCC::HI) 5840 .addReg(ARM::CPSR); 5841 5842 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5843 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 5844 .addReg(ARM::CPSR, RegState::Define) 5845 .addReg(NewVReg1) 5846 .addImm(2)); 5847 5848 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5849 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 5850 .addJumpTableIndex(MJTI) 5851 .addImm(UId)); 5852 5853 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5854 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 5855 .addReg(ARM::CPSR, RegState::Define) 5856 .addReg(NewVReg2, RegState::Kill) 5857 .addReg(NewVReg3)); 5858 5859 MachineMemOperand *JTMMOLd = 5860 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5861 MachineMemOperand::MOLoad, 4, 4); 5862 5863 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5864 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 5865 .addReg(NewVReg4, RegState::Kill) 5866 .addImm(0) 5867 .addMemOperand(JTMMOLd)); 5868 5869 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 5870 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 5871 .addReg(ARM::CPSR, RegState::Define) 5872 .addReg(NewVReg5, RegState::Kill) 5873 .addReg(NewVReg3)); 5874 5875 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 5876 .addReg(NewVReg6, RegState::Kill) 5877 .addJumpTableIndex(MJTI) 5878 .addImm(UId); 5879 } else { 5880 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5881 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 5882 .addFrameIndex(FI) 5883 .addImm(4) 5884 .addMemOperand(FIMMOLd)); 5885 5886 if (NumLPads < 256) { 5887 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 5888 .addReg(NewVReg1) 5889 .addImm(NumLPads)); 5890 } else { 5891 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5892 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) 5893 .addImm(NumLPads & 0xFFFF)); 5894 5895 unsigned VReg2 = VReg1; 5896 if ((NumLPads & 0xFFFF0000) != 0) { 5897 VReg2 = MRI->createVirtualRegister(TRC); 5898 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2) 5899 .addReg(VReg1) 5900 .addImm(NumLPads >> 16)); 5901 } 5902 5903 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 5904 .addReg(NewVReg1) 5905 .addReg(VReg2)); 5906 } 5907 5908 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5909 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), NewVReg2) 5910 .addImm(LPadList.size())); 5911 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 5912 .addReg(NewVReg1) 5913 .addReg(NewVReg2)); 5914 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 5915 .addMBB(TrapBB) 5916 .addImm(ARMCC::HI) 5917 .addReg(ARM::CPSR); 5918 5919 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5920 AddDefaultCC( 5921 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3) 5922 .addReg(NewVReg1) 5923 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5924 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5925 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4) 5926 .addJumpTableIndex(MJTI) 5927 .addImm(UId)); 5928 5929 MachineMemOperand *JTMMOLd = 5930 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5931 MachineMemOperand::MOLoad, 4, 4); 5932 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5933 AddDefaultPred( 5934 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5) 5935 .addReg(NewVReg3, RegState::Kill) 5936 .addReg(NewVReg4) 5937 .addImm(0) 5938 .addMemOperand(JTMMOLd)); 5939 5940 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 5941 .addReg(NewVReg5, RegState::Kill) 5942 .addReg(NewVReg4) 5943 .addJumpTableIndex(MJTI) 5944 .addImm(UId); 5945 } 5946 5947 // Add the jump table entries as successors to the MBB. 5948 MachineBasicBlock *PrevMBB = 0; 5949 for (std::vector<MachineBasicBlock*>::iterator 5950 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) { 5951 MachineBasicBlock *CurMBB = *I; 5952 if (PrevMBB != CurMBB) 5953 DispContBB->addSuccessor(CurMBB); 5954 PrevMBB = CurMBB; 5955 } 5956 5957 // N.B. the order the invoke BBs are processed in doesn't matter here. 5958 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 5959 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 5960 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF); 5961 SmallVector<MachineBasicBlock*, 64> MBBLPads; 5962 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator 5963 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) { 5964 MachineBasicBlock *BB = *I; 5965 5966 // Remove the landing pad successor from the invoke block and replace it 5967 // with the new dispatch block. 5968 for (MachineBasicBlock::succ_iterator 5969 SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) { 5970 MachineBasicBlock *SMBB = *SI; 5971 if (SMBB->isLandingPad()) { 5972 BB->removeSuccessor(SMBB); 5973 MBBLPads.push_back(SMBB); 5974 } 5975 } 5976 5977 BB->addSuccessor(DispatchBB); 5978 5979 // Find the invoke call and mark all of the callee-saved registers as 5980 // 'implicit defined' so that they're spilled. This prevents code from 5981 // moving instructions to before the EH block, where they will never be 5982 // executed. 5983 for (MachineBasicBlock::reverse_iterator 5984 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) { 5985 if (!II->getDesc().isCall()) continue; 5986 5987 DenseMap<unsigned, bool> DefRegs; 5988 for (MachineInstr::mop_iterator 5989 OI = II->operands_begin(), OE = II->operands_end(); 5990 OI != OE; ++OI) { 5991 if (!OI->isReg()) continue; 5992 DefRegs[OI->getReg()] = true; 5993 } 5994 5995 MachineInstrBuilder MIB(&*II); 5996 5997 for (unsigned i = 0; SavedRegs[i] != 0; ++i) { 5998 if (!TRC->contains(SavedRegs[i])) continue; 5999 if (!DefRegs[SavedRegs[i]]) 6000 MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead); 6001 } 6002 6003 break; 6004 } 6005 } 6006 6007 // Mark all former landing pads as non-landing pads. The dispatch is the only 6008 // landing pad now. 6009 for (SmallVectorImpl<MachineBasicBlock*>::iterator 6010 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I) 6011 (*I)->setIsLandingPad(false); 6012 6013 // The instruction is gone now. 6014 MI->eraseFromParent(); 6015 6016 return MBB; 6017} 6018 6019static 6020MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 6021 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 6022 E = MBB->succ_end(); I != E; ++I) 6023 if (*I != Succ) 6024 return *I; 6025 llvm_unreachable("Expecting a BB with two successors!"); 6026} 6027 6028MachineBasicBlock * 6029ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6030 MachineBasicBlock *BB) const { 6031 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6032 DebugLoc dl = MI->getDebugLoc(); 6033 bool isThumb2 = Subtarget->isThumb2(); 6034 switch (MI->getOpcode()) { 6035 default: { 6036 MI->dump(); 6037 llvm_unreachable("Unexpected instr type to insert"); 6038 } 6039 // The Thumb2 pre-indexed stores have the same MI operands, they just 6040 // define them differently in the .td files from the isel patterns, so 6041 // they need pseudos. 6042 case ARM::t2STR_preidx: 6043 MI->setDesc(TII->get(ARM::t2STR_PRE)); 6044 return BB; 6045 case ARM::t2STRB_preidx: 6046 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 6047 return BB; 6048 case ARM::t2STRH_preidx: 6049 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 6050 return BB; 6051 6052 case ARM::STRi_preidx: 6053 case ARM::STRBi_preidx: { 6054 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 6055 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 6056 // Decode the offset. 6057 unsigned Offset = MI->getOperand(4).getImm(); 6058 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 6059 Offset = ARM_AM::getAM2Offset(Offset); 6060 if (isSub) 6061 Offset = -Offset; 6062 6063 MachineMemOperand *MMO = *MI->memoperands_begin(); 6064 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 6065 .addOperand(MI->getOperand(0)) // Rn_wb 6066 .addOperand(MI->getOperand(1)) // Rt 6067 .addOperand(MI->getOperand(2)) // Rn 6068 .addImm(Offset) // offset (skip GPR==zero_reg) 6069 .addOperand(MI->getOperand(5)) // pred 6070 .addOperand(MI->getOperand(6)) 6071 .addMemOperand(MMO); 6072 MI->eraseFromParent(); 6073 return BB; 6074 } 6075 case ARM::STRr_preidx: 6076 case ARM::STRBr_preidx: 6077 case ARM::STRH_preidx: { 6078 unsigned NewOpc; 6079 switch (MI->getOpcode()) { 6080 default: llvm_unreachable("unexpected opcode!"); 6081 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 6082 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 6083 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 6084 } 6085 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 6086 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 6087 MIB.addOperand(MI->getOperand(i)); 6088 MI->eraseFromParent(); 6089 return BB; 6090 } 6091 case ARM::ATOMIC_LOAD_ADD_I8: 6092 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6093 case ARM::ATOMIC_LOAD_ADD_I16: 6094 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6095 case ARM::ATOMIC_LOAD_ADD_I32: 6096 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6097 6098 case ARM::ATOMIC_LOAD_AND_I8: 6099 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6100 case ARM::ATOMIC_LOAD_AND_I16: 6101 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6102 case ARM::ATOMIC_LOAD_AND_I32: 6103 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6104 6105 case ARM::ATOMIC_LOAD_OR_I8: 6106 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6107 case ARM::ATOMIC_LOAD_OR_I16: 6108 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6109 case ARM::ATOMIC_LOAD_OR_I32: 6110 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6111 6112 case ARM::ATOMIC_LOAD_XOR_I8: 6113 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6114 case ARM::ATOMIC_LOAD_XOR_I16: 6115 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6116 case ARM::ATOMIC_LOAD_XOR_I32: 6117 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6118 6119 case ARM::ATOMIC_LOAD_NAND_I8: 6120 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6121 case ARM::ATOMIC_LOAD_NAND_I16: 6122 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6123 case ARM::ATOMIC_LOAD_NAND_I32: 6124 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6125 6126 case ARM::ATOMIC_LOAD_SUB_I8: 6127 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6128 case ARM::ATOMIC_LOAD_SUB_I16: 6129 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6130 case ARM::ATOMIC_LOAD_SUB_I32: 6131 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6132 6133 case ARM::ATOMIC_LOAD_MIN_I8: 6134 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 6135 case ARM::ATOMIC_LOAD_MIN_I16: 6136 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 6137 case ARM::ATOMIC_LOAD_MIN_I32: 6138 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 6139 6140 case ARM::ATOMIC_LOAD_MAX_I8: 6141 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 6142 case ARM::ATOMIC_LOAD_MAX_I16: 6143 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 6144 case ARM::ATOMIC_LOAD_MAX_I32: 6145 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 6146 6147 case ARM::ATOMIC_LOAD_UMIN_I8: 6148 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 6149 case ARM::ATOMIC_LOAD_UMIN_I16: 6150 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 6151 case ARM::ATOMIC_LOAD_UMIN_I32: 6152 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 6153 6154 case ARM::ATOMIC_LOAD_UMAX_I8: 6155 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 6156 case ARM::ATOMIC_LOAD_UMAX_I16: 6157 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 6158 case ARM::ATOMIC_LOAD_UMAX_I32: 6159 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 6160 6161 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 6162 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 6163 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 6164 6165 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 6166 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 6167 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 6168 6169 6170 case ARM::ATOMADD6432: 6171 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 6172 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 6173 /*NeedsCarry*/ true); 6174 case ARM::ATOMSUB6432: 6175 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6176 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6177 /*NeedsCarry*/ true); 6178 case ARM::ATOMOR6432: 6179 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 6180 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6181 case ARM::ATOMXOR6432: 6182 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6183 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6184 case ARM::ATOMAND6432: 6185 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6186 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6187 case ARM::ATOMSWAP6432: 6188 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6189 case ARM::ATOMCMPXCHG6432: 6190 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6191 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6192 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6193 6194 case ARM::tMOVCCr_pseudo: { 6195 // To "insert" a SELECT_CC instruction, we actually have to insert the 6196 // diamond control-flow pattern. The incoming instruction knows the 6197 // destination vreg to set, the condition code register to branch on, the 6198 // true/false values to select between, and a branch opcode to use. 6199 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6200 MachineFunction::iterator It = BB; 6201 ++It; 6202 6203 // thisMBB: 6204 // ... 6205 // TrueVal = ... 6206 // cmpTY ccX, r1, r2 6207 // bCC copy1MBB 6208 // fallthrough --> copy0MBB 6209 MachineBasicBlock *thisMBB = BB; 6210 MachineFunction *F = BB->getParent(); 6211 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6212 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6213 F->insert(It, copy0MBB); 6214 F->insert(It, sinkMBB); 6215 6216 // Transfer the remainder of BB and its successor edges to sinkMBB. 6217 sinkMBB->splice(sinkMBB->begin(), BB, 6218 llvm::next(MachineBasicBlock::iterator(MI)), 6219 BB->end()); 6220 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6221 6222 BB->addSuccessor(copy0MBB); 6223 BB->addSuccessor(sinkMBB); 6224 6225 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6226 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6227 6228 // copy0MBB: 6229 // %FalseValue = ... 6230 // # fallthrough to sinkMBB 6231 BB = copy0MBB; 6232 6233 // Update machine-CFG edges 6234 BB->addSuccessor(sinkMBB); 6235 6236 // sinkMBB: 6237 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6238 // ... 6239 BB = sinkMBB; 6240 BuildMI(*BB, BB->begin(), dl, 6241 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6242 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6243 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6244 6245 MI->eraseFromParent(); // The pseudo instruction is gone now. 6246 return BB; 6247 } 6248 6249 case ARM::BCCi64: 6250 case ARM::BCCZi64: { 6251 // If there is an unconditional branch to the other successor, remove it. 6252 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6253 6254 // Compare both parts that make up the double comparison separately for 6255 // equality. 6256 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6257 6258 unsigned LHS1 = MI->getOperand(1).getReg(); 6259 unsigned LHS2 = MI->getOperand(2).getReg(); 6260 if (RHSisZero) { 6261 AddDefaultPred(BuildMI(BB, dl, 6262 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6263 .addReg(LHS1).addImm(0)); 6264 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6265 .addReg(LHS2).addImm(0) 6266 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6267 } else { 6268 unsigned RHS1 = MI->getOperand(3).getReg(); 6269 unsigned RHS2 = MI->getOperand(4).getReg(); 6270 AddDefaultPred(BuildMI(BB, dl, 6271 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6272 .addReg(LHS1).addReg(RHS1)); 6273 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6274 .addReg(LHS2).addReg(RHS2) 6275 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6276 } 6277 6278 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6279 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6280 if (MI->getOperand(0).getImm() == ARMCC::NE) 6281 std::swap(destMBB, exitMBB); 6282 6283 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6284 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6285 if (isThumb2) 6286 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6287 else 6288 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6289 6290 MI->eraseFromParent(); // The pseudo instruction is gone now. 6291 return BB; 6292 } 6293 6294 case ARM::Int_eh_sjlj_setjmp: 6295 case ARM::Int_eh_sjlj_setjmp_nofp: 6296 case ARM::tInt_eh_sjlj_setjmp: 6297 case ARM::t2Int_eh_sjlj_setjmp: 6298 case ARM::t2Int_eh_sjlj_setjmp_nofp: 6299 EmitSjLjDispatchBlock(MI, BB); 6300 return BB; 6301 6302 case ARM::ABS: 6303 case ARM::t2ABS: { 6304 // To insert an ABS instruction, we have to insert the 6305 // diamond control-flow pattern. The incoming instruction knows the 6306 // source vreg to test against 0, the destination vreg to set, 6307 // the condition code register to branch on, the 6308 // true/false values to select between, and a branch opcode to use. 6309 // It transforms 6310 // V1 = ABS V0 6311 // into 6312 // V2 = MOVS V0 6313 // BCC (branch to SinkBB if V0 >= 0) 6314 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6315 // SinkBB: V1 = PHI(V2, V3) 6316 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6317 MachineFunction::iterator BBI = BB; 6318 ++BBI; 6319 MachineFunction *Fn = BB->getParent(); 6320 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6321 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6322 Fn->insert(BBI, RSBBB); 6323 Fn->insert(BBI, SinkBB); 6324 6325 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6326 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6327 bool isThumb2 = Subtarget->isThumb2(); 6328 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6329 // In Thumb mode S must not be specified if source register is the SP or 6330 // PC and if destination register is the SP, so restrict register class 6331 unsigned NewMovDstReg = MRI.createVirtualRegister( 6332 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6333 unsigned NewRsbDstReg = MRI.createVirtualRegister( 6334 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6335 6336 // Transfer the remainder of BB and its successor edges to sinkMBB. 6337 SinkBB->splice(SinkBB->begin(), BB, 6338 llvm::next(MachineBasicBlock::iterator(MI)), 6339 BB->end()); 6340 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6341 6342 BB->addSuccessor(RSBBB); 6343 BB->addSuccessor(SinkBB); 6344 6345 // fall through to SinkMBB 6346 RSBBB->addSuccessor(SinkBB); 6347 6348 // insert a movs at the end of BB 6349 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr), 6350 NewMovDstReg) 6351 .addReg(ABSSrcReg, RegState::Kill) 6352 .addImm((unsigned)ARMCC::AL).addReg(0) 6353 .addReg(ARM::CPSR, RegState::Define); 6354 6355 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6356 BuildMI(BB, dl, 6357 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6358 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6359 6360 // insert rsbri in RSBBB 6361 // Note: BCC and rsbri will be converted into predicated rsbmi 6362 // by if-conversion pass 6363 BuildMI(*RSBBB, RSBBB->begin(), dl, 6364 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6365 .addReg(NewMovDstReg, RegState::Kill) 6366 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6367 6368 // insert PHI in SinkBB, 6369 // reuse ABSDstReg to not change uses of ABS instruction 6370 BuildMI(*SinkBB, SinkBB->begin(), dl, 6371 TII->get(ARM::PHI), ABSDstReg) 6372 .addReg(NewRsbDstReg).addMBB(RSBBB) 6373 .addReg(NewMovDstReg).addMBB(BB); 6374 6375 // remove ABS instruction 6376 MI->eraseFromParent(); 6377 6378 // return last added BB 6379 return SinkBB; 6380 } 6381 } 6382} 6383 6384void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6385 SDNode *Node) const { 6386 const MCInstrDesc *MCID = &MI->getDesc(); 6387 if (!MCID->hasPostISelHook()) { 6388 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6389 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6390 return; 6391 } 6392 6393 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6394 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6395 // operand is still set to noreg. If needed, set the optional operand's 6396 // register to CPSR, and remove the redundant implicit def. 6397 // 6398 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6399 6400 // Rename pseudo opcodes. 6401 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 6402 if (NewOpc) { 6403 const ARMBaseInstrInfo *TII = 6404 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 6405 MCID = &TII->get(NewOpc); 6406 6407 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 && 6408 "converted opcode should be the same except for cc_out"); 6409 6410 MI->setDesc(*MCID); 6411 6412 // Add the optional cc_out operand 6413 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); 6414 } 6415 unsigned ccOutIdx = MCID->getNumOperands() - 1; 6416 6417 // Any ARM instruction that sets the 's' bit should specify an optional 6418 // "cc_out" operand in the last operand position. 6419 if (!MCID->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { 6420 assert(!NewOpc && "Optional cc_out operand required"); 6421 return; 6422 } 6423 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 6424 // since we already have an optional CPSR def. 6425 bool definesCPSR = false; 6426 bool deadCPSR = false; 6427 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands(); 6428 i != e; ++i) { 6429 const MachineOperand &MO = MI->getOperand(i); 6430 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 6431 definesCPSR = true; 6432 if (MO.isDead()) 6433 deadCPSR = true; 6434 MI->RemoveOperand(i); 6435 break; 6436 } 6437 } 6438 if (!definesCPSR) { 6439 assert(!NewOpc && "Optional cc_out operand required"); 6440 return; 6441 } 6442 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 6443 if (deadCPSR) { 6444 assert(!MI->getOperand(ccOutIdx).getReg() && 6445 "expect uninitialized optional cc_out operand"); 6446 return; 6447 } 6448 6449 // If this instruction was defined with an optional CPSR def and its dag node 6450 // had a live implicit CPSR def, then activate the optional CPSR def. 6451 MachineOperand &MO = MI->getOperand(ccOutIdx); 6452 MO.setReg(ARM::CPSR); 6453 MO.setIsDef(true); 6454} 6455 6456//===----------------------------------------------------------------------===// 6457// ARM Optimization Hooks 6458//===----------------------------------------------------------------------===// 6459 6460static 6461SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 6462 TargetLowering::DAGCombinerInfo &DCI) { 6463 SelectionDAG &DAG = DCI.DAG; 6464 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6465 EVT VT = N->getValueType(0); 6466 unsigned Opc = N->getOpcode(); 6467 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 6468 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 6469 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 6470 ISD::CondCode CC = ISD::SETCC_INVALID; 6471 6472 if (isSlctCC) { 6473 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 6474 } else { 6475 SDValue CCOp = Slct.getOperand(0); 6476 if (CCOp.getOpcode() == ISD::SETCC) 6477 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 6478 } 6479 6480 bool DoXform = false; 6481 bool InvCC = false; 6482 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 6483 "Bad input!"); 6484 6485 if (LHS.getOpcode() == ISD::Constant && 6486 cast<ConstantSDNode>(LHS)->isNullValue()) { 6487 DoXform = true; 6488 } else if (CC != ISD::SETCC_INVALID && 6489 RHS.getOpcode() == ISD::Constant && 6490 cast<ConstantSDNode>(RHS)->isNullValue()) { 6491 std::swap(LHS, RHS); 6492 SDValue Op0 = Slct.getOperand(0); 6493 EVT OpVT = isSlctCC ? Op0.getValueType() : 6494 Op0.getOperand(0).getValueType(); 6495 bool isInt = OpVT.isInteger(); 6496 CC = ISD::getSetCCInverse(CC, isInt); 6497 6498 if (!TLI.isCondCodeLegal(CC, OpVT)) 6499 return SDValue(); // Inverse operator isn't legal. 6500 6501 DoXform = true; 6502 InvCC = true; 6503 } 6504 6505 if (DoXform) { 6506 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 6507 if (isSlctCC) 6508 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 6509 Slct.getOperand(0), Slct.getOperand(1), CC); 6510 SDValue CCOp = Slct.getOperand(0); 6511 if (InvCC) 6512 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 6513 CCOp.getOperand(0), CCOp.getOperand(1), CC); 6514 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 6515 CCOp, OtherOp, Result); 6516 } 6517 return SDValue(); 6518} 6519 6520// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 6521// (only after legalization). 6522static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 6523 TargetLowering::DAGCombinerInfo &DCI, 6524 const ARMSubtarget *Subtarget) { 6525 6526 // Only perform optimization if after legalize, and if NEON is available. We 6527 // also expected both operands to be BUILD_VECTORs. 6528 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 6529 || N0.getOpcode() != ISD::BUILD_VECTOR 6530 || N1.getOpcode() != ISD::BUILD_VECTOR) 6531 return SDValue(); 6532 6533 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 6534 EVT VT = N->getValueType(0); 6535 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 6536 return SDValue(); 6537 6538 // Check that the vector operands are of the right form. 6539 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 6540 // operands, where N is the size of the formed vector. 6541 // Each EXTRACT_VECTOR should have the same input vector and odd or even 6542 // index such that we have a pair wise add pattern. 6543 6544 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 6545 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6546 return SDValue(); 6547 SDValue Vec = N0->getOperand(0)->getOperand(0); 6548 SDNode *V = Vec.getNode(); 6549 unsigned nextIndex = 0; 6550 6551 // For each operands to the ADD which are BUILD_VECTORs, 6552 // check to see if each of their operands are an EXTRACT_VECTOR with 6553 // the same vector and appropriate index. 6554 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 6555 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 6556 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6557 6558 SDValue ExtVec0 = N0->getOperand(i); 6559 SDValue ExtVec1 = N1->getOperand(i); 6560 6561 // First operand is the vector, verify its the same. 6562 if (V != ExtVec0->getOperand(0).getNode() || 6563 V != ExtVec1->getOperand(0).getNode()) 6564 return SDValue(); 6565 6566 // Second is the constant, verify its correct. 6567 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 6568 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 6569 6570 // For the constant, we want to see all the even or all the odd. 6571 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 6572 || C1->getZExtValue() != nextIndex+1) 6573 return SDValue(); 6574 6575 // Increment index. 6576 nextIndex+=2; 6577 } else 6578 return SDValue(); 6579 } 6580 6581 // Create VPADDL node. 6582 SelectionDAG &DAG = DCI.DAG; 6583 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6584 6585 // Build operand list. 6586 SmallVector<SDValue, 8> Ops; 6587 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 6588 TLI.getPointerTy())); 6589 6590 // Input is the vector. 6591 Ops.push_back(Vec); 6592 6593 // Get widened type and narrowed type. 6594 MVT widenType; 6595 unsigned numElem = VT.getVectorNumElements(); 6596 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 6597 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 6598 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 6599 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 6600 default: 6601 assert(0 && "Invalid vector element type for padd optimization."); 6602 } 6603 6604 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6605 widenType, &Ops[0], Ops.size()); 6606 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 6607} 6608 6609/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 6610/// operands N0 and N1. This is a helper for PerformADDCombine that is 6611/// called with the default operands, and if that fails, with commuted 6612/// operands. 6613static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 6614 TargetLowering::DAGCombinerInfo &DCI, 6615 const ARMSubtarget *Subtarget){ 6616 6617 // Attempt to create vpaddl for this add. 6618 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 6619 if (Result.getNode()) 6620 return Result; 6621 6622 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 6623 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 6624 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 6625 if (Result.getNode()) return Result; 6626 } 6627 return SDValue(); 6628} 6629 6630/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 6631/// 6632static SDValue PerformADDCombine(SDNode *N, 6633 TargetLowering::DAGCombinerInfo &DCI, 6634 const ARMSubtarget *Subtarget) { 6635 SDValue N0 = N->getOperand(0); 6636 SDValue N1 = N->getOperand(1); 6637 6638 // First try with the default operand order. 6639 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 6640 if (Result.getNode()) 6641 return Result; 6642 6643 // If that didn't work, try again with the operands commuted. 6644 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 6645} 6646 6647/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 6648/// 6649static SDValue PerformSUBCombine(SDNode *N, 6650 TargetLowering::DAGCombinerInfo &DCI) { 6651 SDValue N0 = N->getOperand(0); 6652 SDValue N1 = N->getOperand(1); 6653 6654 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 6655 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 6656 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 6657 if (Result.getNode()) return Result; 6658 } 6659 6660 return SDValue(); 6661} 6662 6663/// PerformVMULCombine 6664/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 6665/// special multiplier accumulator forwarding. 6666/// vmul d3, d0, d2 6667/// vmla d3, d1, d2 6668/// is faster than 6669/// vadd d3, d0, d1 6670/// vmul d3, d3, d2 6671static SDValue PerformVMULCombine(SDNode *N, 6672 TargetLowering::DAGCombinerInfo &DCI, 6673 const ARMSubtarget *Subtarget) { 6674 if (!Subtarget->hasVMLxForwarding()) 6675 return SDValue(); 6676 6677 SelectionDAG &DAG = DCI.DAG; 6678 SDValue N0 = N->getOperand(0); 6679 SDValue N1 = N->getOperand(1); 6680 unsigned Opcode = N0.getOpcode(); 6681 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6682 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 6683 Opcode = N1.getOpcode(); 6684 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6685 Opcode != ISD::FADD && Opcode != ISD::FSUB) 6686 return SDValue(); 6687 std::swap(N0, N1); 6688 } 6689 6690 EVT VT = N->getValueType(0); 6691 DebugLoc DL = N->getDebugLoc(); 6692 SDValue N00 = N0->getOperand(0); 6693 SDValue N01 = N0->getOperand(1); 6694 return DAG.getNode(Opcode, DL, VT, 6695 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 6696 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 6697} 6698 6699static SDValue PerformMULCombine(SDNode *N, 6700 TargetLowering::DAGCombinerInfo &DCI, 6701 const ARMSubtarget *Subtarget) { 6702 SelectionDAG &DAG = DCI.DAG; 6703 6704 if (Subtarget->isThumb1Only()) 6705 return SDValue(); 6706 6707 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6708 return SDValue(); 6709 6710 EVT VT = N->getValueType(0); 6711 if (VT.is64BitVector() || VT.is128BitVector()) 6712 return PerformVMULCombine(N, DCI, Subtarget); 6713 if (VT != MVT::i32) 6714 return SDValue(); 6715 6716 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6717 if (!C) 6718 return SDValue(); 6719 6720 uint64_t MulAmt = C->getZExtValue(); 6721 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6722 ShiftAmt = ShiftAmt & (32 - 1); 6723 SDValue V = N->getOperand(0); 6724 DebugLoc DL = N->getDebugLoc(); 6725 6726 SDValue Res; 6727 MulAmt >>= ShiftAmt; 6728 if (isPowerOf2_32(MulAmt - 1)) { 6729 // (mul x, 2^N + 1) => (add (shl x, N), x) 6730 Res = DAG.getNode(ISD::ADD, DL, VT, 6731 V, DAG.getNode(ISD::SHL, DL, VT, 6732 V, DAG.getConstant(Log2_32(MulAmt-1), 6733 MVT::i32))); 6734 } else if (isPowerOf2_32(MulAmt + 1)) { 6735 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6736 Res = DAG.getNode(ISD::SUB, DL, VT, 6737 DAG.getNode(ISD::SHL, DL, VT, 6738 V, DAG.getConstant(Log2_32(MulAmt+1), 6739 MVT::i32)), 6740 V); 6741 } else 6742 return SDValue(); 6743 6744 if (ShiftAmt != 0) 6745 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6746 DAG.getConstant(ShiftAmt, MVT::i32)); 6747 6748 // Do not add new nodes to DAG combiner worklist. 6749 DCI.CombineTo(N, Res, false); 6750 return SDValue(); 6751} 6752 6753static SDValue PerformANDCombine(SDNode *N, 6754 TargetLowering::DAGCombinerInfo &DCI) { 6755 6756 // Attempt to use immediate-form VBIC 6757 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6758 DebugLoc dl = N->getDebugLoc(); 6759 EVT VT = N->getValueType(0); 6760 SelectionDAG &DAG = DCI.DAG; 6761 6762 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6763 return SDValue(); 6764 6765 APInt SplatBits, SplatUndef; 6766 unsigned SplatBitSize; 6767 bool HasAnyUndefs; 6768 if (BVN && 6769 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6770 if (SplatBitSize <= 64) { 6771 EVT VbicVT; 6772 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6773 SplatUndef.getZExtValue(), SplatBitSize, 6774 DAG, VbicVT, VT.is128BitVector(), 6775 OtherModImm); 6776 if (Val.getNode()) { 6777 SDValue Input = 6778 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6779 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6780 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6781 } 6782 } 6783 } 6784 6785 return SDValue(); 6786} 6787 6788/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6789static SDValue PerformORCombine(SDNode *N, 6790 TargetLowering::DAGCombinerInfo &DCI, 6791 const ARMSubtarget *Subtarget) { 6792 // Attempt to use immediate-form VORR 6793 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6794 DebugLoc dl = N->getDebugLoc(); 6795 EVT VT = N->getValueType(0); 6796 SelectionDAG &DAG = DCI.DAG; 6797 6798 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6799 return SDValue(); 6800 6801 APInt SplatBits, SplatUndef; 6802 unsigned SplatBitSize; 6803 bool HasAnyUndefs; 6804 if (BVN && Subtarget->hasNEON() && 6805 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6806 if (SplatBitSize <= 64) { 6807 EVT VorrVT; 6808 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6809 SplatUndef.getZExtValue(), SplatBitSize, 6810 DAG, VorrVT, VT.is128BitVector(), 6811 OtherModImm); 6812 if (Val.getNode()) { 6813 SDValue Input = 6814 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6815 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6816 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6817 } 6818 } 6819 } 6820 6821 SDValue N0 = N->getOperand(0); 6822 if (N0.getOpcode() != ISD::AND) 6823 return SDValue(); 6824 SDValue N1 = N->getOperand(1); 6825 6826 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6827 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6828 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6829 APInt SplatUndef; 6830 unsigned SplatBitSize; 6831 bool HasAnyUndefs; 6832 6833 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6834 APInt SplatBits0; 6835 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6836 HasAnyUndefs) && !HasAnyUndefs) { 6837 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6838 APInt SplatBits1; 6839 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6840 HasAnyUndefs) && !HasAnyUndefs && 6841 SplatBits0 == ~SplatBits1) { 6842 // Canonicalize the vector type to make instruction selection simpler. 6843 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 6844 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 6845 N0->getOperand(1), N0->getOperand(0), 6846 N1->getOperand(0)); 6847 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 6848 } 6849 } 6850 } 6851 6852 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 6853 // reasonable. 6854 6855 // BFI is only available on V6T2+ 6856 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 6857 return SDValue(); 6858 6859 DebugLoc DL = N->getDebugLoc(); 6860 // 1) or (and A, mask), val => ARMbfi A, val, mask 6861 // iff (val & mask) == val 6862 // 6863 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6864 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 6865 // && mask == ~mask2 6866 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 6867 // && ~mask == mask2 6868 // (i.e., copy a bitfield value into another bitfield of the same width) 6869 6870 if (VT != MVT::i32) 6871 return SDValue(); 6872 6873 SDValue N00 = N0.getOperand(0); 6874 6875 // The value and the mask need to be constants so we can verify this is 6876 // actually a bitfield set. If the mask is 0xffff, we can do better 6877 // via a movt instruction, so don't use BFI in that case. 6878 SDValue MaskOp = N0.getOperand(1); 6879 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 6880 if (!MaskC) 6881 return SDValue(); 6882 unsigned Mask = MaskC->getZExtValue(); 6883 if (Mask == 0xffff) 6884 return SDValue(); 6885 SDValue Res; 6886 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 6887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 6888 if (N1C) { 6889 unsigned Val = N1C->getZExtValue(); 6890 if ((Val & ~Mask) != Val) 6891 return SDValue(); 6892 6893 if (ARM::isBitFieldInvertedMask(Mask)) { 6894 Val >>= CountTrailingZeros_32(~Mask); 6895 6896 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 6897 DAG.getConstant(Val, MVT::i32), 6898 DAG.getConstant(Mask, MVT::i32)); 6899 6900 // Do not add new nodes to DAG combiner worklist. 6901 DCI.CombineTo(N, Res, false); 6902 return SDValue(); 6903 } 6904 } else if (N1.getOpcode() == ISD::AND) { 6905 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6906 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6907 if (!N11C) 6908 return SDValue(); 6909 unsigned Mask2 = N11C->getZExtValue(); 6910 6911 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 6912 // as is to match. 6913 if (ARM::isBitFieldInvertedMask(Mask) && 6914 (Mask == ~Mask2)) { 6915 // The pack halfword instruction works better for masks that fit it, 6916 // so use that when it's available. 6917 if (Subtarget->hasT2ExtractPack() && 6918 (Mask == 0xffff || Mask == 0xffff0000)) 6919 return SDValue(); 6920 // 2a 6921 unsigned amt = CountTrailingZeros_32(Mask2); 6922 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 6923 DAG.getConstant(amt, MVT::i32)); 6924 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 6925 DAG.getConstant(Mask, MVT::i32)); 6926 // Do not add new nodes to DAG combiner worklist. 6927 DCI.CombineTo(N, Res, false); 6928 return SDValue(); 6929 } else if (ARM::isBitFieldInvertedMask(~Mask) && 6930 (~Mask == Mask2)) { 6931 // The pack halfword instruction works better for masks that fit it, 6932 // so use that when it's available. 6933 if (Subtarget->hasT2ExtractPack() && 6934 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 6935 return SDValue(); 6936 // 2b 6937 unsigned lsb = CountTrailingZeros_32(Mask); 6938 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 6939 DAG.getConstant(lsb, MVT::i32)); 6940 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 6941 DAG.getConstant(Mask2, MVT::i32)); 6942 // Do not add new nodes to DAG combiner worklist. 6943 DCI.CombineTo(N, Res, false); 6944 return SDValue(); 6945 } 6946 } 6947 6948 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 6949 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 6950 ARM::isBitFieldInvertedMask(~Mask)) { 6951 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 6952 // where lsb(mask) == #shamt and masked bits of B are known zero. 6953 SDValue ShAmt = N00.getOperand(1); 6954 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 6955 unsigned LSB = CountTrailingZeros_32(Mask); 6956 if (ShAmtC != LSB) 6957 return SDValue(); 6958 6959 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 6960 DAG.getConstant(~Mask, MVT::i32)); 6961 6962 // Do not add new nodes to DAG combiner worklist. 6963 DCI.CombineTo(N, Res, false); 6964 } 6965 6966 return SDValue(); 6967} 6968 6969/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 6970/// the bits being cleared by the AND are not demanded by the BFI. 6971static SDValue PerformBFICombine(SDNode *N, 6972 TargetLowering::DAGCombinerInfo &DCI) { 6973 SDValue N1 = N->getOperand(1); 6974 if (N1.getOpcode() == ISD::AND) { 6975 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6976 if (!N11C) 6977 return SDValue(); 6978 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 6979 unsigned LSB = CountTrailingZeros_32(~InvMask); 6980 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 6981 unsigned Mask = (1 << Width)-1; 6982 unsigned Mask2 = N11C->getZExtValue(); 6983 if ((Mask & (~Mask2)) == 0) 6984 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 6985 N->getOperand(0), N1.getOperand(0), 6986 N->getOperand(2)); 6987 } 6988 return SDValue(); 6989} 6990 6991/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 6992/// ARMISD::VMOVRRD. 6993static SDValue PerformVMOVRRDCombine(SDNode *N, 6994 TargetLowering::DAGCombinerInfo &DCI) { 6995 // vmovrrd(vmovdrr x, y) -> x,y 6996 SDValue InDouble = N->getOperand(0); 6997 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 6998 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 6999 7000 // vmovrrd(load f64) -> (load i32), (load i32) 7001 SDNode *InNode = InDouble.getNode(); 7002 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 7003 InNode->getValueType(0) == MVT::f64 && 7004 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 7005 !cast<LoadSDNode>(InNode)->isVolatile()) { 7006 // TODO: Should this be done for non-FrameIndex operands? 7007 LoadSDNode *LD = cast<LoadSDNode>(InNode); 7008 7009 SelectionDAG &DAG = DCI.DAG; 7010 DebugLoc DL = LD->getDebugLoc(); 7011 SDValue BasePtr = LD->getBasePtr(); 7012 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 7013 LD->getPointerInfo(), LD->isVolatile(), 7014 LD->isNonTemporal(), LD->getAlignment()); 7015 7016 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 7017 DAG.getConstant(4, MVT::i32)); 7018 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 7019 LD->getPointerInfo(), LD->isVolatile(), 7020 LD->isNonTemporal(), 7021 std::min(4U, LD->getAlignment() / 2)); 7022 7023 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 7024 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 7025 DCI.RemoveFromWorklist(LD); 7026 DAG.DeleteNode(LD); 7027 return Result; 7028 } 7029 7030 return SDValue(); 7031} 7032 7033/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 7034/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 7035static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 7036 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 7037 SDValue Op0 = N->getOperand(0); 7038 SDValue Op1 = N->getOperand(1); 7039 if (Op0.getOpcode() == ISD::BITCAST) 7040 Op0 = Op0.getOperand(0); 7041 if (Op1.getOpcode() == ISD::BITCAST) 7042 Op1 = Op1.getOperand(0); 7043 if (Op0.getOpcode() == ARMISD::VMOVRRD && 7044 Op0.getNode() == Op1.getNode() && 7045 Op0.getResNo() == 0 && Op1.getResNo() == 1) 7046 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 7047 N->getValueType(0), Op0.getOperand(0)); 7048 return SDValue(); 7049} 7050 7051/// PerformSTORECombine - Target-specific dag combine xforms for 7052/// ISD::STORE. 7053static SDValue PerformSTORECombine(SDNode *N, 7054 TargetLowering::DAGCombinerInfo &DCI) { 7055 // Bitcast an i64 store extracted from a vector to f64. 7056 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7057 StoreSDNode *St = cast<StoreSDNode>(N); 7058 SDValue StVal = St->getValue(); 7059 if (!ISD::isNormalStore(St) || St->isVolatile()) 7060 return SDValue(); 7061 7062 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 7063 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 7064 SelectionDAG &DAG = DCI.DAG; 7065 DebugLoc DL = St->getDebugLoc(); 7066 SDValue BasePtr = St->getBasePtr(); 7067 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 7068 StVal.getNode()->getOperand(0), BasePtr, 7069 St->getPointerInfo(), St->isVolatile(), 7070 St->isNonTemporal(), St->getAlignment()); 7071 7072 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 7073 DAG.getConstant(4, MVT::i32)); 7074 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 7075 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 7076 St->isNonTemporal(), 7077 std::min(4U, St->getAlignment() / 2)); 7078 } 7079 7080 if (StVal.getValueType() != MVT::i64 || 7081 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 7082 return SDValue(); 7083 7084 SelectionDAG &DAG = DCI.DAG; 7085 DebugLoc dl = StVal.getDebugLoc(); 7086 SDValue IntVec = StVal.getOperand(0); 7087 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7088 IntVec.getValueType().getVectorNumElements()); 7089 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 7090 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7091 Vec, StVal.getOperand(1)); 7092 dl = N->getDebugLoc(); 7093 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 7094 // Make the DAGCombiner fold the bitcasts. 7095 DCI.AddToWorklist(Vec.getNode()); 7096 DCI.AddToWorklist(ExtElt.getNode()); 7097 DCI.AddToWorklist(V.getNode()); 7098 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 7099 St->getPointerInfo(), St->isVolatile(), 7100 St->isNonTemporal(), St->getAlignment(), 7101 St->getTBAAInfo()); 7102} 7103 7104/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 7105/// are normal, non-volatile loads. If so, it is profitable to bitcast an 7106/// i64 vector to have f64 elements, since the value can then be loaded 7107/// directly into a VFP register. 7108static bool hasNormalLoadOperand(SDNode *N) { 7109 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 7110 for (unsigned i = 0; i < NumElts; ++i) { 7111 SDNode *Elt = N->getOperand(i).getNode(); 7112 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 7113 return true; 7114 } 7115 return false; 7116} 7117 7118/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 7119/// ISD::BUILD_VECTOR. 7120static SDValue PerformBUILD_VECTORCombine(SDNode *N, 7121 TargetLowering::DAGCombinerInfo &DCI){ 7122 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 7123 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 7124 // into a pair of GPRs, which is fine when the value is used as a scalar, 7125 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 7126 SelectionDAG &DAG = DCI.DAG; 7127 if (N->getNumOperands() == 2) { 7128 SDValue RV = PerformVMOVDRRCombine(N, DAG); 7129 if (RV.getNode()) 7130 return RV; 7131 } 7132 7133 // Load i64 elements as f64 values so that type legalization does not split 7134 // them up into i32 values. 7135 EVT VT = N->getValueType(0); 7136 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 7137 return SDValue(); 7138 DebugLoc dl = N->getDebugLoc(); 7139 SmallVector<SDValue, 8> Ops; 7140 unsigned NumElts = VT.getVectorNumElements(); 7141 for (unsigned i = 0; i < NumElts; ++i) { 7142 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 7143 Ops.push_back(V); 7144 // Make the DAGCombiner fold the bitcast. 7145 DCI.AddToWorklist(V.getNode()); 7146 } 7147 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 7148 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 7149 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 7150} 7151 7152/// PerformInsertEltCombine - Target-specific dag combine xforms for 7153/// ISD::INSERT_VECTOR_ELT. 7154static SDValue PerformInsertEltCombine(SDNode *N, 7155 TargetLowering::DAGCombinerInfo &DCI) { 7156 // Bitcast an i64 load inserted into a vector to f64. 7157 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7158 EVT VT = N->getValueType(0); 7159 SDNode *Elt = N->getOperand(1).getNode(); 7160 if (VT.getVectorElementType() != MVT::i64 || 7161 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 7162 return SDValue(); 7163 7164 SelectionDAG &DAG = DCI.DAG; 7165 DebugLoc dl = N->getDebugLoc(); 7166 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7167 VT.getVectorNumElements()); 7168 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 7169 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 7170 // Make the DAGCombiner fold the bitcasts. 7171 DCI.AddToWorklist(Vec.getNode()); 7172 DCI.AddToWorklist(V.getNode()); 7173 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 7174 Vec, V, N->getOperand(2)); 7175 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 7176} 7177 7178/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 7179/// ISD::VECTOR_SHUFFLE. 7180static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 7181 // The LLVM shufflevector instruction does not require the shuffle mask 7182 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 7183 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 7184 // operands do not match the mask length, they are extended by concatenating 7185 // them with undef vectors. That is probably the right thing for other 7186 // targets, but for NEON it is better to concatenate two double-register 7187 // size vector operands into a single quad-register size vector. Do that 7188 // transformation here: 7189 // shuffle(concat(v1, undef), concat(v2, undef)) -> 7190 // shuffle(concat(v1, v2), undef) 7191 SDValue Op0 = N->getOperand(0); 7192 SDValue Op1 = N->getOperand(1); 7193 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 7194 Op1.getOpcode() != ISD::CONCAT_VECTORS || 7195 Op0.getNumOperands() != 2 || 7196 Op1.getNumOperands() != 2) 7197 return SDValue(); 7198 SDValue Concat0Op1 = Op0.getOperand(1); 7199 SDValue Concat1Op1 = Op1.getOperand(1); 7200 if (Concat0Op1.getOpcode() != ISD::UNDEF || 7201 Concat1Op1.getOpcode() != ISD::UNDEF) 7202 return SDValue(); 7203 // Skip the transformation if any of the types are illegal. 7204 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7205 EVT VT = N->getValueType(0); 7206 if (!TLI.isTypeLegal(VT) || 7207 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 7208 !TLI.isTypeLegal(Concat1Op1.getValueType())) 7209 return SDValue(); 7210 7211 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7212 Op0.getOperand(0), Op1.getOperand(0)); 7213 // Translate the shuffle mask. 7214 SmallVector<int, 16> NewMask; 7215 unsigned NumElts = VT.getVectorNumElements(); 7216 unsigned HalfElts = NumElts/2; 7217 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7218 for (unsigned n = 0; n < NumElts; ++n) { 7219 int MaskElt = SVN->getMaskElt(n); 7220 int NewElt = -1; 7221 if (MaskElt < (int)HalfElts) 7222 NewElt = MaskElt; 7223 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 7224 NewElt = HalfElts + MaskElt - NumElts; 7225 NewMask.push_back(NewElt); 7226 } 7227 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 7228 DAG.getUNDEF(VT), NewMask.data()); 7229} 7230 7231/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 7232/// NEON load/store intrinsics to merge base address updates. 7233static SDValue CombineBaseUpdate(SDNode *N, 7234 TargetLowering::DAGCombinerInfo &DCI) { 7235 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7236 return SDValue(); 7237 7238 SelectionDAG &DAG = DCI.DAG; 7239 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 7240 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 7241 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 7242 SDValue Addr = N->getOperand(AddrOpIdx); 7243 7244 // Search for a use of the address operand that is an increment. 7245 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7246 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7247 SDNode *User = *UI; 7248 if (User->getOpcode() != ISD::ADD || 7249 UI.getUse().getResNo() != Addr.getResNo()) 7250 continue; 7251 7252 // Check that the add is independent of the load/store. Otherwise, folding 7253 // it would create a cycle. 7254 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7255 continue; 7256 7257 // Find the new opcode for the updating load/store. 7258 bool isLoad = true; 7259 bool isLaneOp = false; 7260 unsigned NewOpc = 0; 7261 unsigned NumVecs = 0; 7262 if (isIntrinsic) { 7263 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7264 switch (IntNo) { 7265 default: assert(0 && "unexpected intrinsic for Neon base update"); 7266 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 7267 NumVecs = 1; break; 7268 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 7269 NumVecs = 2; break; 7270 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 7271 NumVecs = 3; break; 7272 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 7273 NumVecs = 4; break; 7274 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 7275 NumVecs = 2; isLaneOp = true; break; 7276 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 7277 NumVecs = 3; isLaneOp = true; break; 7278 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 7279 NumVecs = 4; isLaneOp = true; break; 7280 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 7281 NumVecs = 1; isLoad = false; break; 7282 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 7283 NumVecs = 2; isLoad = false; break; 7284 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 7285 NumVecs = 3; isLoad = false; break; 7286 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 7287 NumVecs = 4; isLoad = false; break; 7288 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 7289 NumVecs = 2; isLoad = false; isLaneOp = true; break; 7290 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 7291 NumVecs = 3; isLoad = false; isLaneOp = true; break; 7292 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 7293 NumVecs = 4; isLoad = false; isLaneOp = true; break; 7294 } 7295 } else { 7296 isLaneOp = true; 7297 switch (N->getOpcode()) { 7298 default: assert(0 && "unexpected opcode for Neon base update"); 7299 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 7300 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 7301 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 7302 } 7303 } 7304 7305 // Find the size of memory referenced by the load/store. 7306 EVT VecTy; 7307 if (isLoad) 7308 VecTy = N->getValueType(0); 7309 else 7310 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 7311 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7312 if (isLaneOp) 7313 NumBytes /= VecTy.getVectorNumElements(); 7314 7315 // If the increment is a constant, it must match the memory ref size. 7316 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7317 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7318 uint64_t IncVal = CInc->getZExtValue(); 7319 if (IncVal != NumBytes) 7320 continue; 7321 } else if (NumBytes >= 3 * 16) { 7322 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 7323 // separate instructions that make it harder to use a non-constant update. 7324 continue; 7325 } 7326 7327 // Create the new updating load/store node. 7328 EVT Tys[6]; 7329 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 7330 unsigned n; 7331 for (n = 0; n < NumResultVecs; ++n) 7332 Tys[n] = VecTy; 7333 Tys[n++] = MVT::i32; 7334 Tys[n] = MVT::Other; 7335 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 7336 SmallVector<SDValue, 8> Ops; 7337 Ops.push_back(N->getOperand(0)); // incoming chain 7338 Ops.push_back(N->getOperand(AddrOpIdx)); 7339 Ops.push_back(Inc); 7340 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 7341 Ops.push_back(N->getOperand(i)); 7342 } 7343 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7344 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 7345 Ops.data(), Ops.size(), 7346 MemInt->getMemoryVT(), 7347 MemInt->getMemOperand()); 7348 7349 // Update the uses. 7350 std::vector<SDValue> NewResults; 7351 for (unsigned i = 0; i < NumResultVecs; ++i) { 7352 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7353 } 7354 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 7355 DCI.CombineTo(N, NewResults); 7356 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7357 7358 break; 7359 } 7360 return SDValue(); 7361} 7362 7363/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 7364/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 7365/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 7366/// return true. 7367static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 7368 SelectionDAG &DAG = DCI.DAG; 7369 EVT VT = N->getValueType(0); 7370 // vldN-dup instructions only support 64-bit vectors for N > 1. 7371 if (!VT.is64BitVector()) 7372 return false; 7373 7374 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 7375 SDNode *VLD = N->getOperand(0).getNode(); 7376 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 7377 return false; 7378 unsigned NumVecs = 0; 7379 unsigned NewOpc = 0; 7380 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 7381 if (IntNo == Intrinsic::arm_neon_vld2lane) { 7382 NumVecs = 2; 7383 NewOpc = ARMISD::VLD2DUP; 7384 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 7385 NumVecs = 3; 7386 NewOpc = ARMISD::VLD3DUP; 7387 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 7388 NumVecs = 4; 7389 NewOpc = ARMISD::VLD4DUP; 7390 } else { 7391 return false; 7392 } 7393 7394 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 7395 // numbers match the load. 7396 unsigned VLDLaneNo = 7397 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 7398 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7399 UI != UE; ++UI) { 7400 // Ignore uses of the chain result. 7401 if (UI.getUse().getResNo() == NumVecs) 7402 continue; 7403 SDNode *User = *UI; 7404 if (User->getOpcode() != ARMISD::VDUPLANE || 7405 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 7406 return false; 7407 } 7408 7409 // Create the vldN-dup node. 7410 EVT Tys[5]; 7411 unsigned n; 7412 for (n = 0; n < NumVecs; ++n) 7413 Tys[n] = VT; 7414 Tys[n] = MVT::Other; 7415 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 7416 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 7417 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 7418 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 7419 Ops, 2, VLDMemInt->getMemoryVT(), 7420 VLDMemInt->getMemOperand()); 7421 7422 // Update the uses. 7423 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7424 UI != UE; ++UI) { 7425 unsigned ResNo = UI.getUse().getResNo(); 7426 // Ignore uses of the chain result. 7427 if (ResNo == NumVecs) 7428 continue; 7429 SDNode *User = *UI; 7430 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 7431 } 7432 7433 // Now the vldN-lane intrinsic is dead except for its chain result. 7434 // Update uses of the chain. 7435 std::vector<SDValue> VLDDupResults; 7436 for (unsigned n = 0; n < NumVecs; ++n) 7437 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 7438 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 7439 DCI.CombineTo(VLD, VLDDupResults); 7440 7441 return true; 7442} 7443 7444/// PerformVDUPLANECombine - Target-specific dag combine xforms for 7445/// ARMISD::VDUPLANE. 7446static SDValue PerformVDUPLANECombine(SDNode *N, 7447 TargetLowering::DAGCombinerInfo &DCI) { 7448 SDValue Op = N->getOperand(0); 7449 7450 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 7451 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 7452 if (CombineVLDDUP(N, DCI)) 7453 return SDValue(N, 0); 7454 7455 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 7456 // redundant. Ignore bit_converts for now; element sizes are checked below. 7457 while (Op.getOpcode() == ISD::BITCAST) 7458 Op = Op.getOperand(0); 7459 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 7460 return SDValue(); 7461 7462 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 7463 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 7464 // The canonical VMOV for a zero vector uses a 32-bit element size. 7465 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7466 unsigned EltBits; 7467 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 7468 EltSize = 8; 7469 EVT VT = N->getValueType(0); 7470 if (EltSize > VT.getVectorElementType().getSizeInBits()) 7471 return SDValue(); 7472 7473 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 7474} 7475 7476// isConstVecPow2 - Return true if each vector element is a power of 2, all 7477// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 7478static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 7479{ 7480 integerPart cN; 7481 integerPart c0 = 0; 7482 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 7483 I != E; I++) { 7484 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 7485 if (!C) 7486 return false; 7487 7488 bool isExact; 7489 APFloat APF = C->getValueAPF(); 7490 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 7491 != APFloat::opOK || !isExact) 7492 return false; 7493 7494 c0 = (I == 0) ? cN : c0; 7495 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 7496 return false; 7497 } 7498 C = c0; 7499 return true; 7500} 7501 7502/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 7503/// can replace combinations of VMUL and VCVT (floating-point to integer) 7504/// when the VMUL has a constant operand that is a power of 2. 7505/// 7506/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7507/// vmul.f32 d16, d17, d16 7508/// vcvt.s32.f32 d16, d16 7509/// becomes: 7510/// vcvt.s32.f32 d16, d16, #3 7511static SDValue PerformVCVTCombine(SDNode *N, 7512 TargetLowering::DAGCombinerInfo &DCI, 7513 const ARMSubtarget *Subtarget) { 7514 SelectionDAG &DAG = DCI.DAG; 7515 SDValue Op = N->getOperand(0); 7516 7517 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 7518 Op.getOpcode() != ISD::FMUL) 7519 return SDValue(); 7520 7521 uint64_t C; 7522 SDValue N0 = Op->getOperand(0); 7523 SDValue ConstVec = Op->getOperand(1); 7524 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 7525 7526 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7527 !isConstVecPow2(ConstVec, isSigned, C)) 7528 return SDValue(); 7529 7530 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 7531 Intrinsic::arm_neon_vcvtfp2fxu; 7532 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7533 N->getValueType(0), 7534 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 7535 DAG.getConstant(Log2_64(C), MVT::i32)); 7536} 7537 7538/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 7539/// can replace combinations of VCVT (integer to floating-point) and VDIV 7540/// when the VDIV has a constant operand that is a power of 2. 7541/// 7542/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7543/// vcvt.f32.s32 d16, d16 7544/// vdiv.f32 d16, d17, d16 7545/// becomes: 7546/// vcvt.f32.s32 d16, d16, #3 7547static SDValue PerformVDIVCombine(SDNode *N, 7548 TargetLowering::DAGCombinerInfo &DCI, 7549 const ARMSubtarget *Subtarget) { 7550 SelectionDAG &DAG = DCI.DAG; 7551 SDValue Op = N->getOperand(0); 7552 unsigned OpOpcode = Op.getNode()->getOpcode(); 7553 7554 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 7555 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 7556 return SDValue(); 7557 7558 uint64_t C; 7559 SDValue ConstVec = N->getOperand(1); 7560 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 7561 7562 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7563 !isConstVecPow2(ConstVec, isSigned, C)) 7564 return SDValue(); 7565 7566 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 7567 Intrinsic::arm_neon_vcvtfxu2fp; 7568 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7569 Op.getValueType(), 7570 DAG.getConstant(IntrinsicOpcode, MVT::i32), 7571 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 7572} 7573 7574/// Getvshiftimm - Check if this is a valid build_vector for the immediate 7575/// operand of a vector shift operation, where all the elements of the 7576/// build_vector must have the same constant integer value. 7577static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 7578 // Ignore bit_converts. 7579 while (Op.getOpcode() == ISD::BITCAST) 7580 Op = Op.getOperand(0); 7581 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 7582 APInt SplatBits, SplatUndef; 7583 unsigned SplatBitSize; 7584 bool HasAnyUndefs; 7585 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 7586 HasAnyUndefs, ElementBits) || 7587 SplatBitSize > ElementBits) 7588 return false; 7589 Cnt = SplatBits.getSExtValue(); 7590 return true; 7591} 7592 7593/// isVShiftLImm - Check if this is a valid build_vector for the immediate 7594/// operand of a vector shift left operation. That value must be in the range: 7595/// 0 <= Value < ElementBits for a left shift; or 7596/// 0 <= Value <= ElementBits for a long left shift. 7597static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 7598 assert(VT.isVector() && "vector shift count is not a vector type"); 7599 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7600 if (! getVShiftImm(Op, ElementBits, Cnt)) 7601 return false; 7602 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 7603} 7604 7605/// isVShiftRImm - Check if this is a valid build_vector for the immediate 7606/// operand of a vector shift right operation. For a shift opcode, the value 7607/// is positive, but for an intrinsic the value count must be negative. The 7608/// absolute value must be in the range: 7609/// 1 <= |Value| <= ElementBits for a right shift; or 7610/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 7611static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 7612 int64_t &Cnt) { 7613 assert(VT.isVector() && "vector shift count is not a vector type"); 7614 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7615 if (! getVShiftImm(Op, ElementBits, Cnt)) 7616 return false; 7617 if (isIntrinsic) 7618 Cnt = -Cnt; 7619 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 7620} 7621 7622/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 7623static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 7624 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 7625 switch (IntNo) { 7626 default: 7627 // Don't do anything for most intrinsics. 7628 break; 7629 7630 // Vector shifts: check for immediate versions and lower them. 7631 // Note: This is done during DAG combining instead of DAG legalizing because 7632 // the build_vectors for 64-bit vector element shift counts are generally 7633 // not legal, and it is hard to see their values after they get legalized to 7634 // loads from a constant pool. 7635 case Intrinsic::arm_neon_vshifts: 7636 case Intrinsic::arm_neon_vshiftu: 7637 case Intrinsic::arm_neon_vshiftls: 7638 case Intrinsic::arm_neon_vshiftlu: 7639 case Intrinsic::arm_neon_vshiftn: 7640 case Intrinsic::arm_neon_vrshifts: 7641 case Intrinsic::arm_neon_vrshiftu: 7642 case Intrinsic::arm_neon_vrshiftn: 7643 case Intrinsic::arm_neon_vqshifts: 7644 case Intrinsic::arm_neon_vqshiftu: 7645 case Intrinsic::arm_neon_vqshiftsu: 7646 case Intrinsic::arm_neon_vqshiftns: 7647 case Intrinsic::arm_neon_vqshiftnu: 7648 case Intrinsic::arm_neon_vqshiftnsu: 7649 case Intrinsic::arm_neon_vqrshiftns: 7650 case Intrinsic::arm_neon_vqrshiftnu: 7651 case Intrinsic::arm_neon_vqrshiftnsu: { 7652 EVT VT = N->getOperand(1).getValueType(); 7653 int64_t Cnt; 7654 unsigned VShiftOpc = 0; 7655 7656 switch (IntNo) { 7657 case Intrinsic::arm_neon_vshifts: 7658 case Intrinsic::arm_neon_vshiftu: 7659 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 7660 VShiftOpc = ARMISD::VSHL; 7661 break; 7662 } 7663 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 7664 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 7665 ARMISD::VSHRs : ARMISD::VSHRu); 7666 break; 7667 } 7668 return SDValue(); 7669 7670 case Intrinsic::arm_neon_vshiftls: 7671 case Intrinsic::arm_neon_vshiftlu: 7672 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 7673 break; 7674 llvm_unreachable("invalid shift count for vshll intrinsic"); 7675 7676 case Intrinsic::arm_neon_vrshifts: 7677 case Intrinsic::arm_neon_vrshiftu: 7678 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 7679 break; 7680 return SDValue(); 7681 7682 case Intrinsic::arm_neon_vqshifts: 7683 case Intrinsic::arm_neon_vqshiftu: 7684 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7685 break; 7686 return SDValue(); 7687 7688 case Intrinsic::arm_neon_vqshiftsu: 7689 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7690 break; 7691 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 7692 7693 case Intrinsic::arm_neon_vshiftn: 7694 case Intrinsic::arm_neon_vrshiftn: 7695 case Intrinsic::arm_neon_vqshiftns: 7696 case Intrinsic::arm_neon_vqshiftnu: 7697 case Intrinsic::arm_neon_vqshiftnsu: 7698 case Intrinsic::arm_neon_vqrshiftns: 7699 case Intrinsic::arm_neon_vqrshiftnu: 7700 case Intrinsic::arm_neon_vqrshiftnsu: 7701 // Narrowing shifts require an immediate right shift. 7702 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 7703 break; 7704 llvm_unreachable("invalid shift count for narrowing vector shift " 7705 "intrinsic"); 7706 7707 default: 7708 llvm_unreachable("unhandled vector shift"); 7709 } 7710 7711 switch (IntNo) { 7712 case Intrinsic::arm_neon_vshifts: 7713 case Intrinsic::arm_neon_vshiftu: 7714 // Opcode already set above. 7715 break; 7716 case Intrinsic::arm_neon_vshiftls: 7717 case Intrinsic::arm_neon_vshiftlu: 7718 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7719 VShiftOpc = ARMISD::VSHLLi; 7720 else 7721 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7722 ARMISD::VSHLLs : ARMISD::VSHLLu); 7723 break; 7724 case Intrinsic::arm_neon_vshiftn: 7725 VShiftOpc = ARMISD::VSHRN; break; 7726 case Intrinsic::arm_neon_vrshifts: 7727 VShiftOpc = ARMISD::VRSHRs; break; 7728 case Intrinsic::arm_neon_vrshiftu: 7729 VShiftOpc = ARMISD::VRSHRu; break; 7730 case Intrinsic::arm_neon_vrshiftn: 7731 VShiftOpc = ARMISD::VRSHRN; break; 7732 case Intrinsic::arm_neon_vqshifts: 7733 VShiftOpc = ARMISD::VQSHLs; break; 7734 case Intrinsic::arm_neon_vqshiftu: 7735 VShiftOpc = ARMISD::VQSHLu; break; 7736 case Intrinsic::arm_neon_vqshiftsu: 7737 VShiftOpc = ARMISD::VQSHLsu; break; 7738 case Intrinsic::arm_neon_vqshiftns: 7739 VShiftOpc = ARMISD::VQSHRNs; break; 7740 case Intrinsic::arm_neon_vqshiftnu: 7741 VShiftOpc = ARMISD::VQSHRNu; break; 7742 case Intrinsic::arm_neon_vqshiftnsu: 7743 VShiftOpc = ARMISD::VQSHRNsu; break; 7744 case Intrinsic::arm_neon_vqrshiftns: 7745 VShiftOpc = ARMISD::VQRSHRNs; break; 7746 case Intrinsic::arm_neon_vqrshiftnu: 7747 VShiftOpc = ARMISD::VQRSHRNu; break; 7748 case Intrinsic::arm_neon_vqrshiftnsu: 7749 VShiftOpc = ARMISD::VQRSHRNsu; break; 7750 } 7751 7752 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7753 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7754 } 7755 7756 case Intrinsic::arm_neon_vshiftins: { 7757 EVT VT = N->getOperand(1).getValueType(); 7758 int64_t Cnt; 7759 unsigned VShiftOpc = 0; 7760 7761 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7762 VShiftOpc = ARMISD::VSLI; 7763 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7764 VShiftOpc = ARMISD::VSRI; 7765 else { 7766 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7767 } 7768 7769 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7770 N->getOperand(1), N->getOperand(2), 7771 DAG.getConstant(Cnt, MVT::i32)); 7772 } 7773 7774 case Intrinsic::arm_neon_vqrshifts: 7775 case Intrinsic::arm_neon_vqrshiftu: 7776 // No immediate versions of these to check for. 7777 break; 7778 } 7779 7780 return SDValue(); 7781} 7782 7783/// PerformShiftCombine - Checks for immediate versions of vector shifts and 7784/// lowers them. As with the vector shift intrinsics, this is done during DAG 7785/// combining instead of DAG legalizing because the build_vectors for 64-bit 7786/// vector element shift counts are generally not legal, and it is hard to see 7787/// their values after they get legalized to loads from a constant pool. 7788static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7789 const ARMSubtarget *ST) { 7790 EVT VT = N->getValueType(0); 7791 7792 // Nothing to be done for scalar shifts. 7793 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7794 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7795 return SDValue(); 7796 7797 assert(ST->hasNEON() && "unexpected vector shift"); 7798 int64_t Cnt; 7799 7800 switch (N->getOpcode()) { 7801 default: llvm_unreachable("unexpected shift opcode"); 7802 7803 case ISD::SHL: 7804 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7805 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7806 DAG.getConstant(Cnt, MVT::i32)); 7807 break; 7808 7809 case ISD::SRA: 7810 case ISD::SRL: 7811 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7812 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7813 ARMISD::VSHRs : ARMISD::VSHRu); 7814 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7815 DAG.getConstant(Cnt, MVT::i32)); 7816 } 7817 } 7818 return SDValue(); 7819} 7820 7821/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7822/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7823static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 7824 const ARMSubtarget *ST) { 7825 SDValue N0 = N->getOperand(0); 7826 7827 // Check for sign- and zero-extensions of vector extract operations of 8- 7828 // and 16-bit vector elements. NEON supports these directly. They are 7829 // handled during DAG combining because type legalization will promote them 7830 // to 32-bit types and it is messy to recognize the operations after that. 7831 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7832 SDValue Vec = N0.getOperand(0); 7833 SDValue Lane = N0.getOperand(1); 7834 EVT VT = N->getValueType(0); 7835 EVT EltVT = N0.getValueType(); 7836 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7837 7838 if (VT == MVT::i32 && 7839 (EltVT == MVT::i8 || EltVT == MVT::i16) && 7840 TLI.isTypeLegal(Vec.getValueType()) && 7841 isa<ConstantSDNode>(Lane)) { 7842 7843 unsigned Opc = 0; 7844 switch (N->getOpcode()) { 7845 default: llvm_unreachable("unexpected opcode"); 7846 case ISD::SIGN_EXTEND: 7847 Opc = ARMISD::VGETLANEs; 7848 break; 7849 case ISD::ZERO_EXTEND: 7850 case ISD::ANY_EXTEND: 7851 Opc = ARMISD::VGETLANEu; 7852 break; 7853 } 7854 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 7855 } 7856 } 7857 7858 return SDValue(); 7859} 7860 7861/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 7862/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 7863static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 7864 const ARMSubtarget *ST) { 7865 // If the target supports NEON, try to use vmax/vmin instructions for f32 7866 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 7867 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 7868 // a NaN; only do the transformation when it matches that behavior. 7869 7870 // For now only do this when using NEON for FP operations; if using VFP, it 7871 // is not obvious that the benefit outweighs the cost of switching to the 7872 // NEON pipeline. 7873 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 7874 N->getValueType(0) != MVT::f32) 7875 return SDValue(); 7876 7877 SDValue CondLHS = N->getOperand(0); 7878 SDValue CondRHS = N->getOperand(1); 7879 SDValue LHS = N->getOperand(2); 7880 SDValue RHS = N->getOperand(3); 7881 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 7882 7883 unsigned Opcode = 0; 7884 bool IsReversed; 7885 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 7886 IsReversed = false; // x CC y ? x : y 7887 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 7888 IsReversed = true ; // x CC y ? y : x 7889 } else { 7890 return SDValue(); 7891 } 7892 7893 bool IsUnordered; 7894 switch (CC) { 7895 default: break; 7896 case ISD::SETOLT: 7897 case ISD::SETOLE: 7898 case ISD::SETLT: 7899 case ISD::SETLE: 7900 case ISD::SETULT: 7901 case ISD::SETULE: 7902 // If LHS is NaN, an ordered comparison will be false and the result will 7903 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 7904 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7905 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 7906 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7907 break; 7908 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 7909 // will return -0, so vmin can only be used for unsafe math or if one of 7910 // the operands is known to be nonzero. 7911 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 7912 !UnsafeFPMath && 7913 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7914 break; 7915 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 7916 break; 7917 7918 case ISD::SETOGT: 7919 case ISD::SETOGE: 7920 case ISD::SETGT: 7921 case ISD::SETGE: 7922 case ISD::SETUGT: 7923 case ISD::SETUGE: 7924 // If LHS is NaN, an ordered comparison will be false and the result will 7925 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 7926 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7927 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 7928 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7929 break; 7930 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 7931 // will return +0, so vmax can only be used for unsafe math or if one of 7932 // the operands is known to be nonzero. 7933 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 7934 !UnsafeFPMath && 7935 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7936 break; 7937 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 7938 break; 7939 } 7940 7941 if (!Opcode) 7942 return SDValue(); 7943 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 7944} 7945 7946/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 7947SDValue 7948ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 7949 SDValue Cmp = N->getOperand(4); 7950 if (Cmp.getOpcode() != ARMISD::CMPZ) 7951 // Only looking at EQ and NE cases. 7952 return SDValue(); 7953 7954 EVT VT = N->getValueType(0); 7955 DebugLoc dl = N->getDebugLoc(); 7956 SDValue LHS = Cmp.getOperand(0); 7957 SDValue RHS = Cmp.getOperand(1); 7958 SDValue FalseVal = N->getOperand(0); 7959 SDValue TrueVal = N->getOperand(1); 7960 SDValue ARMcc = N->getOperand(2); 7961 ARMCC::CondCodes CC = 7962 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 7963 7964 // Simplify 7965 // mov r1, r0 7966 // cmp r1, x 7967 // mov r0, y 7968 // moveq r0, x 7969 // to 7970 // cmp r0, x 7971 // movne r0, y 7972 // 7973 // mov r1, r0 7974 // cmp r1, x 7975 // mov r0, x 7976 // movne r0, y 7977 // to 7978 // cmp r0, x 7979 // movne r0, y 7980 /// FIXME: Turn this into a target neutral optimization? 7981 SDValue Res; 7982 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 7983 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 7984 N->getOperand(3), Cmp); 7985 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 7986 SDValue ARMcc; 7987 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 7988 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 7989 N->getOperand(3), NewCmp); 7990 } 7991 7992 if (Res.getNode()) { 7993 APInt KnownZero, KnownOne; 7994 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 7995 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 7996 // Capture demanded bits information that would be otherwise lost. 7997 if (KnownZero == 0xfffffffe) 7998 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7999 DAG.getValueType(MVT::i1)); 8000 else if (KnownZero == 0xffffff00) 8001 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8002 DAG.getValueType(MVT::i8)); 8003 else if (KnownZero == 0xffff0000) 8004 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8005 DAG.getValueType(MVT::i16)); 8006 } 8007 8008 return Res; 8009} 8010 8011SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 8012 DAGCombinerInfo &DCI) const { 8013 switch (N->getOpcode()) { 8014 default: break; 8015 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 8016 case ISD::SUB: return PerformSUBCombine(N, DCI); 8017 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 8018 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 8019 case ISD::AND: return PerformANDCombine(N, DCI); 8020 case ARMISD::BFI: return PerformBFICombine(N, DCI); 8021 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 8022 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 8023 case ISD::STORE: return PerformSTORECombine(N, DCI); 8024 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 8025 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 8026 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 8027 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 8028 case ISD::FP_TO_SINT: 8029 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 8030 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 8031 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 8032 case ISD::SHL: 8033 case ISD::SRA: 8034 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 8035 case ISD::SIGN_EXTEND: 8036 case ISD::ZERO_EXTEND: 8037 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 8038 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 8039 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 8040 case ARMISD::VLD2DUP: 8041 case ARMISD::VLD3DUP: 8042 case ARMISD::VLD4DUP: 8043 return CombineBaseUpdate(N, DCI); 8044 case ISD::INTRINSIC_VOID: 8045 case ISD::INTRINSIC_W_CHAIN: 8046 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 8047 case Intrinsic::arm_neon_vld1: 8048 case Intrinsic::arm_neon_vld2: 8049 case Intrinsic::arm_neon_vld3: 8050 case Intrinsic::arm_neon_vld4: 8051 case Intrinsic::arm_neon_vld2lane: 8052 case Intrinsic::arm_neon_vld3lane: 8053 case Intrinsic::arm_neon_vld4lane: 8054 case Intrinsic::arm_neon_vst1: 8055 case Intrinsic::arm_neon_vst2: 8056 case Intrinsic::arm_neon_vst3: 8057 case Intrinsic::arm_neon_vst4: 8058 case Intrinsic::arm_neon_vst2lane: 8059 case Intrinsic::arm_neon_vst3lane: 8060 case Intrinsic::arm_neon_vst4lane: 8061 return CombineBaseUpdate(N, DCI); 8062 default: break; 8063 } 8064 break; 8065 } 8066 return SDValue(); 8067} 8068 8069bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 8070 EVT VT) const { 8071 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 8072} 8073 8074bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 8075 if (!Subtarget->allowsUnalignedMem()) 8076 return false; 8077 8078 switch (VT.getSimpleVT().SimpleTy) { 8079 default: 8080 return false; 8081 case MVT::i8: 8082 case MVT::i16: 8083 case MVT::i32: 8084 return true; 8085 // FIXME: VLD1 etc with standard alignment is legal. 8086 } 8087} 8088 8089static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 8090 if (V < 0) 8091 return false; 8092 8093 unsigned Scale = 1; 8094 switch (VT.getSimpleVT().SimpleTy) { 8095 default: return false; 8096 case MVT::i1: 8097 case MVT::i8: 8098 // Scale == 1; 8099 break; 8100 case MVT::i16: 8101 // Scale == 2; 8102 Scale = 2; 8103 break; 8104 case MVT::i32: 8105 // Scale == 4; 8106 Scale = 4; 8107 break; 8108 } 8109 8110 if ((V & (Scale - 1)) != 0) 8111 return false; 8112 V /= Scale; 8113 return V == (V & ((1LL << 5) - 1)); 8114} 8115 8116static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 8117 const ARMSubtarget *Subtarget) { 8118 bool isNeg = false; 8119 if (V < 0) { 8120 isNeg = true; 8121 V = - V; 8122 } 8123 8124 switch (VT.getSimpleVT().SimpleTy) { 8125 default: return false; 8126 case MVT::i1: 8127 case MVT::i8: 8128 case MVT::i16: 8129 case MVT::i32: 8130 // + imm12 or - imm8 8131 if (isNeg) 8132 return V == (V & ((1LL << 8) - 1)); 8133 return V == (V & ((1LL << 12) - 1)); 8134 case MVT::f32: 8135 case MVT::f64: 8136 // Same as ARM mode. FIXME: NEON? 8137 if (!Subtarget->hasVFP2()) 8138 return false; 8139 if ((V & 3) != 0) 8140 return false; 8141 V >>= 2; 8142 return V == (V & ((1LL << 8) - 1)); 8143 } 8144} 8145 8146/// isLegalAddressImmediate - Return true if the integer value can be used 8147/// as the offset of the target addressing mode for load / store of the 8148/// given type. 8149static bool isLegalAddressImmediate(int64_t V, EVT VT, 8150 const ARMSubtarget *Subtarget) { 8151 if (V == 0) 8152 return true; 8153 8154 if (!VT.isSimple()) 8155 return false; 8156 8157 if (Subtarget->isThumb1Only()) 8158 return isLegalT1AddressImmediate(V, VT); 8159 else if (Subtarget->isThumb2()) 8160 return isLegalT2AddressImmediate(V, VT, Subtarget); 8161 8162 // ARM mode. 8163 if (V < 0) 8164 V = - V; 8165 switch (VT.getSimpleVT().SimpleTy) { 8166 default: return false; 8167 case MVT::i1: 8168 case MVT::i8: 8169 case MVT::i32: 8170 // +- imm12 8171 return V == (V & ((1LL << 12) - 1)); 8172 case MVT::i16: 8173 // +- imm8 8174 return V == (V & ((1LL << 8) - 1)); 8175 case MVT::f32: 8176 case MVT::f64: 8177 if (!Subtarget->hasVFP2()) // FIXME: NEON? 8178 return false; 8179 if ((V & 3) != 0) 8180 return false; 8181 V >>= 2; 8182 return V == (V & ((1LL << 8) - 1)); 8183 } 8184} 8185 8186bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 8187 EVT VT) const { 8188 int Scale = AM.Scale; 8189 if (Scale < 0) 8190 return false; 8191 8192 switch (VT.getSimpleVT().SimpleTy) { 8193 default: return false; 8194 case MVT::i1: 8195 case MVT::i8: 8196 case MVT::i16: 8197 case MVT::i32: 8198 if (Scale == 1) 8199 return true; 8200 // r + r << imm 8201 Scale = Scale & ~1; 8202 return Scale == 2 || Scale == 4 || Scale == 8; 8203 case MVT::i64: 8204 // r + r 8205 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8206 return true; 8207 return false; 8208 case MVT::isVoid: 8209 // Note, we allow "void" uses (basically, uses that aren't loads or 8210 // stores), because arm allows folding a scale into many arithmetic 8211 // operations. This should be made more precise and revisited later. 8212 8213 // Allow r << imm, but the imm has to be a multiple of two. 8214 if (Scale & 1) return false; 8215 return isPowerOf2_32(Scale); 8216 } 8217} 8218 8219/// isLegalAddressingMode - Return true if the addressing mode represented 8220/// by AM is legal for this target, for a load/store of the specified type. 8221bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 8222 Type *Ty) const { 8223 EVT VT = getValueType(Ty, true); 8224 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 8225 return false; 8226 8227 // Can never fold addr of global into load/store. 8228 if (AM.BaseGV) 8229 return false; 8230 8231 switch (AM.Scale) { 8232 case 0: // no scale reg, must be "r+i" or "r", or "i". 8233 break; 8234 case 1: 8235 if (Subtarget->isThumb1Only()) 8236 return false; 8237 // FALL THROUGH. 8238 default: 8239 // ARM doesn't support any R+R*scale+imm addr modes. 8240 if (AM.BaseOffs) 8241 return false; 8242 8243 if (!VT.isSimple()) 8244 return false; 8245 8246 if (Subtarget->isThumb2()) 8247 return isLegalT2ScaledAddressingMode(AM, VT); 8248 8249 int Scale = AM.Scale; 8250 switch (VT.getSimpleVT().SimpleTy) { 8251 default: return false; 8252 case MVT::i1: 8253 case MVT::i8: 8254 case MVT::i32: 8255 if (Scale < 0) Scale = -Scale; 8256 if (Scale == 1) 8257 return true; 8258 // r + r << imm 8259 return isPowerOf2_32(Scale & ~1); 8260 case MVT::i16: 8261 case MVT::i64: 8262 // r + r 8263 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8264 return true; 8265 return false; 8266 8267 case MVT::isVoid: 8268 // Note, we allow "void" uses (basically, uses that aren't loads or 8269 // stores), because arm allows folding a scale into many arithmetic 8270 // operations. This should be made more precise and revisited later. 8271 8272 // Allow r << imm, but the imm has to be a multiple of two. 8273 if (Scale & 1) return false; 8274 return isPowerOf2_32(Scale); 8275 } 8276 break; 8277 } 8278 return true; 8279} 8280 8281/// isLegalICmpImmediate - Return true if the specified immediate is legal 8282/// icmp immediate, that is the target has icmp instructions which can compare 8283/// a register against the immediate without having to materialize the 8284/// immediate into a register. 8285bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 8286 if (!Subtarget->isThumb()) 8287 return ARM_AM::getSOImmVal(Imm) != -1; 8288 if (Subtarget->isThumb2()) 8289 return ARM_AM::getT2SOImmVal(Imm) != -1; 8290 return Imm >= 0 && Imm <= 255; 8291} 8292 8293/// isLegalAddImmediate - Return true if the specified immediate is legal 8294/// add immediate, that is the target has add instructions which can add 8295/// a register with the immediate without having to materialize the 8296/// immediate into a register. 8297bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 8298 return ARM_AM::getSOImmVal(Imm) != -1; 8299} 8300 8301static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 8302 bool isSEXTLoad, SDValue &Base, 8303 SDValue &Offset, bool &isInc, 8304 SelectionDAG &DAG) { 8305 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8306 return false; 8307 8308 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8309 // AddressingMode 3 8310 Base = Ptr->getOperand(0); 8311 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8312 int RHSC = (int)RHS->getZExtValue(); 8313 if (RHSC < 0 && RHSC > -256) { 8314 assert(Ptr->getOpcode() == ISD::ADD); 8315 isInc = false; 8316 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8317 return true; 8318 } 8319 } 8320 isInc = (Ptr->getOpcode() == ISD::ADD); 8321 Offset = Ptr->getOperand(1); 8322 return true; 8323 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 8324 // AddressingMode 2 8325 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8326 int RHSC = (int)RHS->getZExtValue(); 8327 if (RHSC < 0 && RHSC > -0x1000) { 8328 assert(Ptr->getOpcode() == ISD::ADD); 8329 isInc = false; 8330 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8331 Base = Ptr->getOperand(0); 8332 return true; 8333 } 8334 } 8335 8336 if (Ptr->getOpcode() == ISD::ADD) { 8337 isInc = true; 8338 ARM_AM::ShiftOpc ShOpcVal= 8339 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 8340 if (ShOpcVal != ARM_AM::no_shift) { 8341 Base = Ptr->getOperand(1); 8342 Offset = Ptr->getOperand(0); 8343 } else { 8344 Base = Ptr->getOperand(0); 8345 Offset = Ptr->getOperand(1); 8346 } 8347 return true; 8348 } 8349 8350 isInc = (Ptr->getOpcode() == ISD::ADD); 8351 Base = Ptr->getOperand(0); 8352 Offset = Ptr->getOperand(1); 8353 return true; 8354 } 8355 8356 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 8357 return false; 8358} 8359 8360static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 8361 bool isSEXTLoad, SDValue &Base, 8362 SDValue &Offset, bool &isInc, 8363 SelectionDAG &DAG) { 8364 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8365 return false; 8366 8367 Base = Ptr->getOperand(0); 8368 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8369 int RHSC = (int)RHS->getZExtValue(); 8370 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 8371 assert(Ptr->getOpcode() == ISD::ADD); 8372 isInc = false; 8373 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8374 return true; 8375 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 8376 isInc = Ptr->getOpcode() == ISD::ADD; 8377 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 8378 return true; 8379 } 8380 } 8381 8382 return false; 8383} 8384 8385/// getPreIndexedAddressParts - returns true by value, base pointer and 8386/// offset pointer and addressing mode by reference if the node's address 8387/// can be legally represented as pre-indexed load / store address. 8388bool 8389ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8390 SDValue &Offset, 8391 ISD::MemIndexedMode &AM, 8392 SelectionDAG &DAG) const { 8393 if (Subtarget->isThumb1Only()) 8394 return false; 8395 8396 EVT VT; 8397 SDValue Ptr; 8398 bool isSEXTLoad = false; 8399 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8400 Ptr = LD->getBasePtr(); 8401 VT = LD->getMemoryVT(); 8402 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8403 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8404 Ptr = ST->getBasePtr(); 8405 VT = ST->getMemoryVT(); 8406 } else 8407 return false; 8408 8409 bool isInc; 8410 bool isLegal = false; 8411 if (Subtarget->isThumb2()) 8412 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8413 Offset, isInc, DAG); 8414 else 8415 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8416 Offset, isInc, DAG); 8417 if (!isLegal) 8418 return false; 8419 8420 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 8421 return true; 8422} 8423 8424/// getPostIndexedAddressParts - returns true by value, base pointer and 8425/// offset pointer and addressing mode by reference if this node can be 8426/// combined with a load / store to form a post-indexed load / store. 8427bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 8428 SDValue &Base, 8429 SDValue &Offset, 8430 ISD::MemIndexedMode &AM, 8431 SelectionDAG &DAG) const { 8432 if (Subtarget->isThumb1Only()) 8433 return false; 8434 8435 EVT VT; 8436 SDValue Ptr; 8437 bool isSEXTLoad = false; 8438 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8439 VT = LD->getMemoryVT(); 8440 Ptr = LD->getBasePtr(); 8441 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8442 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8443 VT = ST->getMemoryVT(); 8444 Ptr = ST->getBasePtr(); 8445 } else 8446 return false; 8447 8448 bool isInc; 8449 bool isLegal = false; 8450 if (Subtarget->isThumb2()) 8451 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8452 isInc, DAG); 8453 else 8454 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8455 isInc, DAG); 8456 if (!isLegal) 8457 return false; 8458 8459 if (Ptr != Base) { 8460 // Swap base ptr and offset to catch more post-index load / store when 8461 // it's legal. In Thumb2 mode, offset must be an immediate. 8462 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 8463 !Subtarget->isThumb2()) 8464 std::swap(Base, Offset); 8465 8466 // Post-indexed load / store update the base pointer. 8467 if (Ptr != Base) 8468 return false; 8469 } 8470 8471 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 8472 return true; 8473} 8474 8475void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8476 const APInt &Mask, 8477 APInt &KnownZero, 8478 APInt &KnownOne, 8479 const SelectionDAG &DAG, 8480 unsigned Depth) const { 8481 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 8482 switch (Op.getOpcode()) { 8483 default: break; 8484 case ARMISD::CMOV: { 8485 // Bits are known zero/one if known on the LHS and RHS. 8486 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 8487 if (KnownZero == 0 && KnownOne == 0) return; 8488 8489 APInt KnownZeroRHS, KnownOneRHS; 8490 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 8491 KnownZeroRHS, KnownOneRHS, Depth+1); 8492 KnownZero &= KnownZeroRHS; 8493 KnownOne &= KnownOneRHS; 8494 return; 8495 } 8496 } 8497} 8498 8499//===----------------------------------------------------------------------===// 8500// ARM Inline Assembly Support 8501//===----------------------------------------------------------------------===// 8502 8503bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 8504 // Looking for "rev" which is V6+. 8505 if (!Subtarget->hasV6Ops()) 8506 return false; 8507 8508 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8509 std::string AsmStr = IA->getAsmString(); 8510 SmallVector<StringRef, 4> AsmPieces; 8511 SplitString(AsmStr, AsmPieces, ";\n"); 8512 8513 switch (AsmPieces.size()) { 8514 default: return false; 8515 case 1: 8516 AsmStr = AsmPieces[0]; 8517 AsmPieces.clear(); 8518 SplitString(AsmStr, AsmPieces, " \t,"); 8519 8520 // rev $0, $1 8521 if (AsmPieces.size() == 3 && 8522 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 8523 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 8524 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8525 if (Ty && Ty->getBitWidth() == 32) 8526 return IntrinsicLowering::LowerToByteSwap(CI); 8527 } 8528 break; 8529 } 8530 8531 return false; 8532} 8533 8534/// getConstraintType - Given a constraint letter, return the type of 8535/// constraint it is for this target. 8536ARMTargetLowering::ConstraintType 8537ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 8538 if (Constraint.size() == 1) { 8539 switch (Constraint[0]) { 8540 default: break; 8541 case 'l': return C_RegisterClass; 8542 case 'w': return C_RegisterClass; 8543 case 'h': return C_RegisterClass; 8544 case 'x': return C_RegisterClass; 8545 case 't': return C_RegisterClass; 8546 case 'j': return C_Other; // Constant for movw. 8547 // An address with a single base register. Due to the way we 8548 // currently handle addresses it is the same as an 'r' memory constraint. 8549 case 'Q': return C_Memory; 8550 } 8551 } else if (Constraint.size() == 2) { 8552 switch (Constraint[0]) { 8553 default: break; 8554 // All 'U+' constraints are addresses. 8555 case 'U': return C_Memory; 8556 } 8557 } 8558 return TargetLowering::getConstraintType(Constraint); 8559} 8560 8561/// Examine constraint type and operand type and determine a weight value. 8562/// This object must already have been set up with the operand type 8563/// and the current alternative constraint selected. 8564TargetLowering::ConstraintWeight 8565ARMTargetLowering::getSingleConstraintMatchWeight( 8566 AsmOperandInfo &info, const char *constraint) const { 8567 ConstraintWeight weight = CW_Invalid; 8568 Value *CallOperandVal = info.CallOperandVal; 8569 // If we don't have a value, we can't do a match, 8570 // but allow it at the lowest weight. 8571 if (CallOperandVal == NULL) 8572 return CW_Default; 8573 Type *type = CallOperandVal->getType(); 8574 // Look at the constraint type. 8575 switch (*constraint) { 8576 default: 8577 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 8578 break; 8579 case 'l': 8580 if (type->isIntegerTy()) { 8581 if (Subtarget->isThumb()) 8582 weight = CW_SpecificReg; 8583 else 8584 weight = CW_Register; 8585 } 8586 break; 8587 case 'w': 8588 if (type->isFloatingPointTy()) 8589 weight = CW_Register; 8590 break; 8591 } 8592 return weight; 8593} 8594 8595typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 8596RCPair 8597ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8598 EVT VT) const { 8599 if (Constraint.size() == 1) { 8600 // GCC ARM Constraint Letters 8601 switch (Constraint[0]) { 8602 case 'l': // Low regs or general regs. 8603 if (Subtarget->isThumb()) 8604 return RCPair(0U, ARM::tGPRRegisterClass); 8605 else 8606 return RCPair(0U, ARM::GPRRegisterClass); 8607 case 'h': // High regs or no regs. 8608 if (Subtarget->isThumb()) 8609 return RCPair(0U, ARM::hGPRRegisterClass); 8610 break; 8611 case 'r': 8612 return RCPair(0U, ARM::GPRRegisterClass); 8613 case 'w': 8614 if (VT == MVT::f32) 8615 return RCPair(0U, ARM::SPRRegisterClass); 8616 if (VT.getSizeInBits() == 64) 8617 return RCPair(0U, ARM::DPRRegisterClass); 8618 if (VT.getSizeInBits() == 128) 8619 return RCPair(0U, ARM::QPRRegisterClass); 8620 break; 8621 case 'x': 8622 if (VT == MVT::f32) 8623 return RCPair(0U, ARM::SPR_8RegisterClass); 8624 if (VT.getSizeInBits() == 64) 8625 return RCPair(0U, ARM::DPR_8RegisterClass); 8626 if (VT.getSizeInBits() == 128) 8627 return RCPair(0U, ARM::QPR_8RegisterClass); 8628 break; 8629 case 't': 8630 if (VT == MVT::f32) 8631 return RCPair(0U, ARM::SPRRegisterClass); 8632 break; 8633 } 8634 } 8635 if (StringRef("{cc}").equals_lower(Constraint)) 8636 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 8637 8638 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8639} 8640 8641/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8642/// vector. If it is invalid, don't add anything to Ops. 8643void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8644 std::string &Constraint, 8645 std::vector<SDValue>&Ops, 8646 SelectionDAG &DAG) const { 8647 SDValue Result(0, 0); 8648 8649 // Currently only support length 1 constraints. 8650 if (Constraint.length() != 1) return; 8651 8652 char ConstraintLetter = Constraint[0]; 8653 switch (ConstraintLetter) { 8654 default: break; 8655 case 'j': 8656 case 'I': case 'J': case 'K': case 'L': 8657 case 'M': case 'N': case 'O': 8658 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 8659 if (!C) 8660 return; 8661 8662 int64_t CVal64 = C->getSExtValue(); 8663 int CVal = (int) CVal64; 8664 // None of these constraints allow values larger than 32 bits. Check 8665 // that the value fits in an int. 8666 if (CVal != CVal64) 8667 return; 8668 8669 switch (ConstraintLetter) { 8670 case 'j': 8671 // Constant suitable for movw, must be between 0 and 8672 // 65535. 8673 if (Subtarget->hasV6T2Ops()) 8674 if (CVal >= 0 && CVal <= 65535) 8675 break; 8676 return; 8677 case 'I': 8678 if (Subtarget->isThumb1Only()) { 8679 // This must be a constant between 0 and 255, for ADD 8680 // immediates. 8681 if (CVal >= 0 && CVal <= 255) 8682 break; 8683 } else if (Subtarget->isThumb2()) { 8684 // A constant that can be used as an immediate value in a 8685 // data-processing instruction. 8686 if (ARM_AM::getT2SOImmVal(CVal) != -1) 8687 break; 8688 } else { 8689 // A constant that can be used as an immediate value in a 8690 // data-processing instruction. 8691 if (ARM_AM::getSOImmVal(CVal) != -1) 8692 break; 8693 } 8694 return; 8695 8696 case 'J': 8697 if (Subtarget->isThumb()) { // FIXME thumb2 8698 // This must be a constant between -255 and -1, for negated ADD 8699 // immediates. This can be used in GCC with an "n" modifier that 8700 // prints the negated value, for use with SUB instructions. It is 8701 // not useful otherwise but is implemented for compatibility. 8702 if (CVal >= -255 && CVal <= -1) 8703 break; 8704 } else { 8705 // This must be a constant between -4095 and 4095. It is not clear 8706 // what this constraint is intended for. Implemented for 8707 // compatibility with GCC. 8708 if (CVal >= -4095 && CVal <= 4095) 8709 break; 8710 } 8711 return; 8712 8713 case 'K': 8714 if (Subtarget->isThumb1Only()) { 8715 // A 32-bit value where only one byte has a nonzero value. Exclude 8716 // zero to match GCC. This constraint is used by GCC internally for 8717 // constants that can be loaded with a move/shift combination. 8718 // It is not useful otherwise but is implemented for compatibility. 8719 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8720 break; 8721 } else if (Subtarget->isThumb2()) { 8722 // A constant whose bitwise inverse can be used as an immediate 8723 // value in a data-processing instruction. This can be used in GCC 8724 // with a "B" modifier that prints the inverted value, for use with 8725 // BIC and MVN instructions. It is not useful otherwise but is 8726 // implemented for compatibility. 8727 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8728 break; 8729 } else { 8730 // A constant whose bitwise inverse can be used as an immediate 8731 // value in a data-processing instruction. This can be used in GCC 8732 // with a "B" modifier that prints the inverted value, for use with 8733 // BIC and MVN instructions. It is not useful otherwise but is 8734 // implemented for compatibility. 8735 if (ARM_AM::getSOImmVal(~CVal) != -1) 8736 break; 8737 } 8738 return; 8739 8740 case 'L': 8741 if (Subtarget->isThumb1Only()) { 8742 // This must be a constant between -7 and 7, 8743 // for 3-operand ADD/SUB immediate instructions. 8744 if (CVal >= -7 && CVal < 7) 8745 break; 8746 } else if (Subtarget->isThumb2()) { 8747 // A constant whose negation can be used as an immediate value in a 8748 // data-processing instruction. This can be used in GCC with an "n" 8749 // modifier that prints the negated value, for use with SUB 8750 // instructions. It is not useful otherwise but is implemented for 8751 // compatibility. 8752 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8753 break; 8754 } else { 8755 // A constant whose negation can be used as an immediate value in a 8756 // data-processing instruction. This can be used in GCC with an "n" 8757 // modifier that prints the negated value, for use with SUB 8758 // instructions. It is not useful otherwise but is implemented for 8759 // compatibility. 8760 if (ARM_AM::getSOImmVal(-CVal) != -1) 8761 break; 8762 } 8763 return; 8764 8765 case 'M': 8766 if (Subtarget->isThumb()) { // FIXME thumb2 8767 // This must be a multiple of 4 between 0 and 1020, for 8768 // ADD sp + immediate. 8769 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8770 break; 8771 } else { 8772 // A power of two or a constant between 0 and 32. This is used in 8773 // GCC for the shift amount on shifted register operands, but it is 8774 // useful in general for any shift amounts. 8775 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8776 break; 8777 } 8778 return; 8779 8780 case 'N': 8781 if (Subtarget->isThumb()) { // FIXME thumb2 8782 // This must be a constant between 0 and 31, for shift amounts. 8783 if (CVal >= 0 && CVal <= 31) 8784 break; 8785 } 8786 return; 8787 8788 case 'O': 8789 if (Subtarget->isThumb()) { // FIXME thumb2 8790 // This must be a multiple of 4 between -508 and 508, for 8791 // ADD/SUB sp = sp + immediate. 8792 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 8793 break; 8794 } 8795 return; 8796 } 8797 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 8798 break; 8799 } 8800 8801 if (Result.getNode()) { 8802 Ops.push_back(Result); 8803 return; 8804 } 8805 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 8806} 8807 8808bool 8809ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 8810 // The ARM target isn't yet aware of offsets. 8811 return false; 8812} 8813 8814bool ARM::isBitFieldInvertedMask(unsigned v) { 8815 if (v == 0xffffffff) 8816 return 0; 8817 // there can be 1's on either or both "outsides", all the "inside" 8818 // bits must be 0's 8819 unsigned int lsb = 0, msb = 31; 8820 while (v & (1 << msb)) --msb; 8821 while (v & (1 << lsb)) ++lsb; 8822 for (unsigned int i = lsb; i <= msb; ++i) { 8823 if (v & (1 << i)) 8824 return 0; 8825 } 8826 return 1; 8827} 8828 8829/// isFPImmLegal - Returns true if the target can instruction select the 8830/// specified FP immediate natively. If false, the legalizer will 8831/// materialize the FP immediate as a load from a constant pool. 8832bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 8833 if (!Subtarget->hasVFP3()) 8834 return false; 8835 if (VT == MVT::f32) 8836 return ARM_AM::getFP32Imm(Imm) != -1; 8837 if (VT == MVT::f64) 8838 return ARM_AM::getFP64Imm(Imm) != -1; 8839 return false; 8840} 8841 8842/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 8843/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 8844/// specified in the intrinsic calls. 8845bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 8846 const CallInst &I, 8847 unsigned Intrinsic) const { 8848 switch (Intrinsic) { 8849 case Intrinsic::arm_neon_vld1: 8850 case Intrinsic::arm_neon_vld2: 8851 case Intrinsic::arm_neon_vld3: 8852 case Intrinsic::arm_neon_vld4: 8853 case Intrinsic::arm_neon_vld2lane: 8854 case Intrinsic::arm_neon_vld3lane: 8855 case Intrinsic::arm_neon_vld4lane: { 8856 Info.opc = ISD::INTRINSIC_W_CHAIN; 8857 // Conservatively set memVT to the entire set of vectors loaded. 8858 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 8859 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8860 Info.ptrVal = I.getArgOperand(0); 8861 Info.offset = 0; 8862 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8863 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8864 Info.vol = false; // volatile loads with NEON intrinsics not supported 8865 Info.readMem = true; 8866 Info.writeMem = false; 8867 return true; 8868 } 8869 case Intrinsic::arm_neon_vst1: 8870 case Intrinsic::arm_neon_vst2: 8871 case Intrinsic::arm_neon_vst3: 8872 case Intrinsic::arm_neon_vst4: 8873 case Intrinsic::arm_neon_vst2lane: 8874 case Intrinsic::arm_neon_vst3lane: 8875 case Intrinsic::arm_neon_vst4lane: { 8876 Info.opc = ISD::INTRINSIC_VOID; 8877 // Conservatively set memVT to the entire set of vectors stored. 8878 unsigned NumElts = 0; 8879 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 8880 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 8881 if (!ArgTy->isVectorTy()) 8882 break; 8883 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 8884 } 8885 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8886 Info.ptrVal = I.getArgOperand(0); 8887 Info.offset = 0; 8888 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8889 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8890 Info.vol = false; // volatile stores with NEON intrinsics not supported 8891 Info.readMem = false; 8892 Info.writeMem = true; 8893 return true; 8894 } 8895 case Intrinsic::arm_strexd: { 8896 Info.opc = ISD::INTRINSIC_W_CHAIN; 8897 Info.memVT = MVT::i64; 8898 Info.ptrVal = I.getArgOperand(2); 8899 Info.offset = 0; 8900 Info.align = 8; 8901 Info.vol = true; 8902 Info.readMem = false; 8903 Info.writeMem = true; 8904 return true; 8905 } 8906 case Intrinsic::arm_ldrexd: { 8907 Info.opc = ISD::INTRINSIC_W_CHAIN; 8908 Info.memVT = MVT::i64; 8909 Info.ptrVal = I.getArgOperand(0); 8910 Info.offset = 0; 8911 Info.align = 8; 8912 Info.vol = true; 8913 Info.readMem = true; 8914 Info.writeMem = false; 8915 return true; 8916 } 8917 default: 8918 break; 8919 } 8920 8921 return false; 8922} 8923