ARMISelLowering.cpp revision 907eebd5a6779e8539ef7bf63550a5b72de76ab2
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMPerfectShuffle.h" 21#include "ARMRegisterInfo.h" 22#include "ARMSubtarget.h" 23#include "ARMTargetMachine.h" 24#include "ARMTargetObjectFile.h" 25#include "llvm/CallingConv.h" 26#include "llvm/Constants.h" 27#include "llvm/Function.h" 28#include "llvm/GlobalValue.h" 29#include "llvm/Instruction.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Type.h" 32#include "llvm/CodeGen/CallingConvLower.h" 33#include "llvm/CodeGen/MachineBasicBlock.h" 34#include "llvm/CodeGen/MachineFrameInfo.h" 35#include "llvm/CodeGen/MachineFunction.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Target/TargetOptions.h" 41#include "llvm/ADT/VectorExtras.h" 42#include "llvm/Support/ErrorHandling.h" 43#include "llvm/Support/MathExtras.h" 44#include <sstream> 45using namespace llvm; 46 47static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 48 CCValAssign::LocInfo &LocInfo, 49 ISD::ArgFlagsTy &ArgFlags, 50 CCState &State); 51static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 56 CCValAssign::LocInfo &LocInfo, 57 ISD::ArgFlagsTy &ArgFlags, 58 CCState &State); 59static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 60 CCValAssign::LocInfo &LocInfo, 61 ISD::ArgFlagsTy &ArgFlags, 62 CCState &State); 63 64void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 65 EVT PromotedBitwiseVT) { 66 if (VT != PromotedLdStVT) { 67 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 68 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 69 PromotedLdStVT.getSimpleVT()); 70 71 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 72 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 73 PromotedLdStVT.getSimpleVT()); 74 } 75 76 EVT ElemTy = VT.getVectorElementType(); 77 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 78 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); 79 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) 80 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 81 if (ElemTy != MVT::i32) { 82 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 83 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 84 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 85 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 86 } 87 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 88 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 89 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom); 90 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); 91 if (VT.isInteger()) { 92 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 93 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 94 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 95 } 96 97 // Promote all bit-wise operations. 98 if (VT.isInteger() && VT != PromotedBitwiseVT) { 99 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 101 PromotedBitwiseVT.getSimpleVT()); 102 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 103 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 104 PromotedBitwiseVT.getSimpleVT()); 105 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 106 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 107 PromotedBitwiseVT.getSimpleVT()); 108 } 109 110 // Neon does not support vector divide/remainder operations. 111 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 112 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 113 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 117} 118 119void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 120 addRegisterClass(VT, ARM::DPRRegisterClass); 121 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 122} 123 124void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 125 addRegisterClass(VT, ARM::QPRRegisterClass); 126 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 127} 128 129static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 130 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 131 return new TargetLoweringObjectFileMachO(); 132 return new ARMElfTargetObjectFile(); 133} 134 135ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 136 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) { 137 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 138 139 if (Subtarget->isTargetDarwin()) { 140 // Uses VFP for Thumb libfuncs if available. 141 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 142 // Single-precision floating-point arithmetic. 143 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 144 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 145 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 146 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 147 148 // Double-precision floating-point arithmetic. 149 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 150 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 151 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 152 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 153 154 // Single-precision comparisons. 155 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 156 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 157 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 158 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 159 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 160 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 161 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 162 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 163 164 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 165 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 166 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 167 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 168 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 169 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 170 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 171 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 172 173 // Double-precision comparisons. 174 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 175 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 176 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 177 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 178 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 179 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 180 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 181 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 182 183 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 184 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 185 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 186 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 187 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 188 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 189 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 190 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 191 192 // Floating-point to integer conversions. 193 // i64 conversions are done via library routines even when generating VFP 194 // instructions, so use the same ones. 195 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 196 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 197 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 198 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 199 200 // Conversions between floating types. 201 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 202 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 203 204 // Integer to floating-point conversions. 205 // i64 conversions are done via library routines even when generating VFP 206 // instructions, so use the same ones. 207 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 208 // e.g., __floatunsidf vs. __floatunssidfvfp. 209 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 210 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 211 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 212 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 213 } 214 } 215 216 // These libcalls are not available in 32-bit. 217 setLibcallName(RTLIB::SHL_I128, 0); 218 setLibcallName(RTLIB::SRL_I128, 0); 219 setLibcallName(RTLIB::SRA_I128, 0); 220 221 // Libcalls should use the AAPCS base standard ABI, even if hard float 222 // is in effect, as per the ARM RTABI specification, section 4.1.2. 223 if (Subtarget->isAAPCS_ABI()) { 224 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 225 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i), 226 CallingConv::ARM_AAPCS); 227 } 228 } 229 230 if (Subtarget->isThumb1Only()) 231 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 232 else 233 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 234 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 235 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 236 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 237 238 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 239 } 240 241 if (Subtarget->hasNEON()) { 242 addDRTypeForNEON(MVT::v2f32); 243 addDRTypeForNEON(MVT::v8i8); 244 addDRTypeForNEON(MVT::v4i16); 245 addDRTypeForNEON(MVT::v2i32); 246 addDRTypeForNEON(MVT::v1i64); 247 248 addQRTypeForNEON(MVT::v4f32); 249 addQRTypeForNEON(MVT::v2f64); 250 addQRTypeForNEON(MVT::v16i8); 251 addQRTypeForNEON(MVT::v8i16); 252 addQRTypeForNEON(MVT::v4i32); 253 addQRTypeForNEON(MVT::v2i64); 254 255 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 256 // neither Neon nor VFP support any arithmetic operations on it. 257 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 258 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 259 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 260 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 261 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 262 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 263 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand); 264 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 265 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 266 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 267 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 268 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 269 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 270 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 271 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 272 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 273 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 274 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 275 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 276 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 277 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 278 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 279 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 280 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 281 282 // Neon does not support some operations on v1i64 and v2i64 types. 283 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 284 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 285 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); 286 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); 287 288 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 289 setTargetDAGCombine(ISD::SHL); 290 setTargetDAGCombine(ISD::SRL); 291 setTargetDAGCombine(ISD::SRA); 292 setTargetDAGCombine(ISD::SIGN_EXTEND); 293 setTargetDAGCombine(ISD::ZERO_EXTEND); 294 setTargetDAGCombine(ISD::ANY_EXTEND); 295 } 296 297 computeRegisterProperties(); 298 299 // ARM does not have f32 extending load. 300 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 301 302 // ARM does not have i1 sign extending load. 303 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 304 305 // ARM supports all 4 flavors of integer indexed load / store. 306 if (!Subtarget->isThumb1Only()) { 307 for (unsigned im = (unsigned)ISD::PRE_INC; 308 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 309 setIndexedLoadAction(im, MVT::i1, Legal); 310 setIndexedLoadAction(im, MVT::i8, Legal); 311 setIndexedLoadAction(im, MVT::i16, Legal); 312 setIndexedLoadAction(im, MVT::i32, Legal); 313 setIndexedStoreAction(im, MVT::i1, Legal); 314 setIndexedStoreAction(im, MVT::i8, Legal); 315 setIndexedStoreAction(im, MVT::i16, Legal); 316 setIndexedStoreAction(im, MVT::i32, Legal); 317 } 318 } 319 320 // i64 operation support. 321 if (Subtarget->isThumb1Only()) { 322 setOperationAction(ISD::MUL, MVT::i64, Expand); 323 setOperationAction(ISD::MULHU, MVT::i32, Expand); 324 setOperationAction(ISD::MULHS, MVT::i32, Expand); 325 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 326 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 327 } else { 328 setOperationAction(ISD::MUL, MVT::i64, Expand); 329 setOperationAction(ISD::MULHU, MVT::i32, Expand); 330 if (!Subtarget->hasV6Ops()) 331 setOperationAction(ISD::MULHS, MVT::i32, Expand); 332 } 333 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 334 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 335 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 336 setOperationAction(ISD::SRL, MVT::i64, Custom); 337 setOperationAction(ISD::SRA, MVT::i64, Custom); 338 339 // ARM does not have ROTL. 340 setOperationAction(ISD::ROTL, MVT::i32, Expand); 341 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 342 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 343 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 344 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 345 346 // Only ARMv6 has BSWAP. 347 if (!Subtarget->hasV6Ops()) 348 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 349 350 // These are expanded into libcalls. 351 setOperationAction(ISD::SDIV, MVT::i32, Expand); 352 setOperationAction(ISD::UDIV, MVT::i32, Expand); 353 setOperationAction(ISD::SREM, MVT::i32, Expand); 354 setOperationAction(ISD::UREM, MVT::i32, Expand); 355 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 356 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 357 358 // Support label based line numbers. 359 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 360 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 361 362 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 363 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 364 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 365 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 366 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 367 368 // Use the default implementation. 369 setOperationAction(ISD::VASTART, MVT::Other, Custom); 370 setOperationAction(ISD::VAARG, MVT::Other, Expand); 371 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 372 setOperationAction(ISD::VAEND, MVT::Other, Expand); 373 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 374 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 375 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 376 // FIXME: Shouldn't need this, since no register is used, but the legalizer 377 // doesn't yet know how to not do that for SjLj. 378 setExceptionSelectorRegister(ARM::R0); 379 if (Subtarget->isThumb()) 380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 381 else 382 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 383 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 384 385 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) { 386 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 388 } 389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 390 391 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) 392 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2. 393 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 394 395 // We want to custom lower some of our intrinsics. 396 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 397 398 setOperationAction(ISD::SETCC, MVT::i32, Expand); 399 setOperationAction(ISD::SETCC, MVT::f32, Expand); 400 setOperationAction(ISD::SETCC, MVT::f64, Expand); 401 setOperationAction(ISD::SELECT, MVT::i32, Expand); 402 setOperationAction(ISD::SELECT, MVT::f32, Expand); 403 setOperationAction(ISD::SELECT, MVT::f64, Expand); 404 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 405 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 406 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 407 408 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 409 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 410 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 411 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 412 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 413 414 // We don't support sin/cos/fmod/copysign/pow 415 setOperationAction(ISD::FSIN, MVT::f64, Expand); 416 setOperationAction(ISD::FSIN, MVT::f32, Expand); 417 setOperationAction(ISD::FCOS, MVT::f32, Expand); 418 setOperationAction(ISD::FCOS, MVT::f64, Expand); 419 setOperationAction(ISD::FREM, MVT::f64, Expand); 420 setOperationAction(ISD::FREM, MVT::f32, Expand); 421 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 422 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 423 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 424 } 425 setOperationAction(ISD::FPOW, MVT::f64, Expand); 426 setOperationAction(ISD::FPOW, MVT::f32, Expand); 427 428 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 429 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 430 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 431 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 432 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 433 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 434 } 435 436 // We have target-specific dag combine patterns for the following nodes: 437 // ARMISD::FMRRD - No need to call setTargetDAGCombine 438 setTargetDAGCombine(ISD::ADD); 439 setTargetDAGCombine(ISD::SUB); 440 441 setStackPointerRegisterToSaveRestore(ARM::SP); 442 setSchedulingPreference(SchedulingForRegPressure); 443 444 // FIXME: If-converter should use instruction latency to determine 445 // profitability rather than relying on fixed limits. 446 if (Subtarget->getCPUString() == "generic") { 447 // Generic (and overly aggressive) if-conversion limits. 448 setIfCvtBlockSizeLimit(10); 449 setIfCvtDupBlockSizeLimit(2); 450 } else if (Subtarget->hasV6Ops()) { 451 setIfCvtBlockSizeLimit(2); 452 setIfCvtDupBlockSizeLimit(1); 453 } else { 454 setIfCvtBlockSizeLimit(3); 455 setIfCvtDupBlockSizeLimit(2); 456 } 457 458 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 459 // Do not enable CodePlacementOpt for now: it currently runs after the 460 // ARMConstantIslandPass and messes up branch relaxation and placement 461 // of constant islands. 462 // benefitFromCodePlacementOpt = true; 463} 464 465const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 466 switch (Opcode) { 467 default: return 0; 468 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 469 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 470 case ARMISD::CALL: return "ARMISD::CALL"; 471 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 472 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 473 case ARMISD::tCALL: return "ARMISD::tCALL"; 474 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 475 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 476 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 477 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 478 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 479 case ARMISD::CMP: return "ARMISD::CMP"; 480 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 481 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 482 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 483 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 484 case ARMISD::CMOV: return "ARMISD::CMOV"; 485 case ARMISD::CNEG: return "ARMISD::CNEG"; 486 487 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 488 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 489 case ARMISD::SITOF: return "ARMISD::SITOF"; 490 case ARMISD::UITOF: return "ARMISD::UITOF"; 491 492 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 493 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 494 case ARMISD::RRX: return "ARMISD::RRX"; 495 496 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 497 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 498 499 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 500 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 501 502 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 503 504 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 505 506 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 507 case ARMISD::VCGE: return "ARMISD::VCGE"; 508 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 509 case ARMISD::VCGT: return "ARMISD::VCGT"; 510 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 511 case ARMISD::VTST: return "ARMISD::VTST"; 512 513 case ARMISD::VSHL: return "ARMISD::VSHL"; 514 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 515 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 516 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 517 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 518 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 519 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 520 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 521 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 522 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 523 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 524 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 525 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 526 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 527 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 528 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 529 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 530 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 531 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 532 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 533 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 534 case ARMISD::VDUP: return "ARMISD::VDUP"; 535 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 536 case ARMISD::VEXT: return "ARMISD::VEXT"; 537 case ARMISD::VREV64: return "ARMISD::VREV64"; 538 case ARMISD::VREV32: return "ARMISD::VREV32"; 539 case ARMISD::VREV16: return "ARMISD::VREV16"; 540 case ARMISD::VZIP: return "ARMISD::VZIP"; 541 case ARMISD::VUZP: return "ARMISD::VUZP"; 542 case ARMISD::VTRN: return "ARMISD::VTRN"; 543 } 544} 545 546/// getFunctionAlignment - Return the Log2 alignment of this function. 547unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { 548 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1; 549} 550 551//===----------------------------------------------------------------------===// 552// Lowering Code 553//===----------------------------------------------------------------------===// 554 555/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 556static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 557 switch (CC) { 558 default: llvm_unreachable("Unknown condition code!"); 559 case ISD::SETNE: return ARMCC::NE; 560 case ISD::SETEQ: return ARMCC::EQ; 561 case ISD::SETGT: return ARMCC::GT; 562 case ISD::SETGE: return ARMCC::GE; 563 case ISD::SETLT: return ARMCC::LT; 564 case ISD::SETLE: return ARMCC::LE; 565 case ISD::SETUGT: return ARMCC::HI; 566 case ISD::SETUGE: return ARMCC::HS; 567 case ISD::SETULT: return ARMCC::LO; 568 case ISD::SETULE: return ARMCC::LS; 569 } 570} 571 572/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 573static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 574 ARMCC::CondCodes &CondCode2) { 575 CondCode2 = ARMCC::AL; 576 switch (CC) { 577 default: llvm_unreachable("Unknown FP condition!"); 578 case ISD::SETEQ: 579 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 580 case ISD::SETGT: 581 case ISD::SETOGT: CondCode = ARMCC::GT; break; 582 case ISD::SETGE: 583 case ISD::SETOGE: CondCode = ARMCC::GE; break; 584 case ISD::SETOLT: CondCode = ARMCC::MI; break; 585 case ISD::SETOLE: CondCode = ARMCC::LS; break; 586 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 587 case ISD::SETO: CondCode = ARMCC::VC; break; 588 case ISD::SETUO: CondCode = ARMCC::VS; break; 589 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 590 case ISD::SETUGT: CondCode = ARMCC::HI; break; 591 case ISD::SETUGE: CondCode = ARMCC::PL; break; 592 case ISD::SETLT: 593 case ISD::SETULT: CondCode = ARMCC::LT; break; 594 case ISD::SETLE: 595 case ISD::SETULE: CondCode = ARMCC::LE; break; 596 case ISD::SETNE: 597 case ISD::SETUNE: CondCode = ARMCC::NE; break; 598 } 599} 600 601//===----------------------------------------------------------------------===// 602// Calling Convention Implementation 603//===----------------------------------------------------------------------===// 604 605#include "ARMGenCallingConv.inc" 606 607// APCS f64 is in register pairs, possibly split to stack 608static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 609 CCValAssign::LocInfo &LocInfo, 610 CCState &State, bool CanFail) { 611 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 612 613 // Try to get the first register. 614 if (unsigned Reg = State.AllocateReg(RegList, 4)) 615 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 616 else { 617 // For the 2nd half of a v2f64, do not fail. 618 if (CanFail) 619 return false; 620 621 // Put the whole thing on the stack. 622 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 623 State.AllocateStack(8, 4), 624 LocVT, LocInfo)); 625 return true; 626 } 627 628 // Try to get the second register. 629 if (unsigned Reg = State.AllocateReg(RegList, 4)) 630 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 631 else 632 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 633 State.AllocateStack(4, 4), 634 LocVT, LocInfo)); 635 return true; 636} 637 638static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 639 CCValAssign::LocInfo &LocInfo, 640 ISD::ArgFlagsTy &ArgFlags, 641 CCState &State) { 642 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 643 return false; 644 if (LocVT == MVT::v2f64 && 645 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 646 return false; 647 return true; // we handled it 648} 649 650// AAPCS f64 is in aligned register pairs 651static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 652 CCValAssign::LocInfo &LocInfo, 653 CCState &State, bool CanFail) { 654 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 655 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 656 657 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 658 if (Reg == 0) { 659 // For the 2nd half of a v2f64, do not just fail. 660 if (CanFail) 661 return false; 662 663 // Put the whole thing on the stack. 664 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 665 State.AllocateStack(8, 8), 666 LocVT, LocInfo)); 667 return true; 668 } 669 670 unsigned i; 671 for (i = 0; i < 2; ++i) 672 if (HiRegList[i] == Reg) 673 break; 674 675 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 676 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 677 LocVT, LocInfo)); 678 return true; 679} 680 681static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 682 CCValAssign::LocInfo &LocInfo, 683 ISD::ArgFlagsTy &ArgFlags, 684 CCState &State) { 685 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) 686 return false; 687 if (LocVT == MVT::v2f64 && 688 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) 689 return false; 690 return true; // we handled it 691} 692 693static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 694 CCValAssign::LocInfo &LocInfo, CCState &State) { 695 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 696 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 697 698 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 699 if (Reg == 0) 700 return false; // we didn't handle it 701 702 unsigned i; 703 for (i = 0; i < 2; ++i) 704 if (HiRegList[i] == Reg) 705 break; 706 707 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 708 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 709 LocVT, LocInfo)); 710 return true; 711} 712 713static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 714 CCValAssign::LocInfo &LocInfo, 715 ISD::ArgFlagsTy &ArgFlags, 716 CCState &State) { 717 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 718 return false; 719 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 720 return false; 721 return true; // we handled it 722} 723 724static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 725 CCValAssign::LocInfo &LocInfo, 726 ISD::ArgFlagsTy &ArgFlags, 727 CCState &State) { 728 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, 729 State); 730} 731 732/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 733/// given CallingConvention value. 734CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 735 bool Return, 736 bool isVarArg) const { 737 switch (CC) { 738 default: 739 llvm_unreachable("Unsupported calling convention"); 740 case CallingConv::C: 741 case CallingConv::Fast: 742 // Use target triple & subtarget features to do actual dispatch. 743 if (Subtarget->isAAPCS_ABI()) { 744 if (Subtarget->hasVFP2() && 745 FloatABIType == FloatABI::Hard && !isVarArg) 746 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 747 else 748 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 749 } else 750 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 751 case CallingConv::ARM_AAPCS_VFP: 752 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 753 case CallingConv::ARM_AAPCS: 754 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 755 case CallingConv::ARM_APCS: 756 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 757 } 758} 759 760/// LowerCallResult - Lower the result values of a call into the 761/// appropriate copies out of appropriate physical registers. 762SDValue 763ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 764 CallingConv::ID CallConv, bool isVarArg, 765 const SmallVectorImpl<ISD::InputArg> &Ins, 766 DebugLoc dl, SelectionDAG &DAG, 767 SmallVectorImpl<SDValue> &InVals) { 768 769 // Assign locations to each value returned by this call. 770 SmallVector<CCValAssign, 16> RVLocs; 771 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 772 RVLocs, *DAG.getContext()); 773 CCInfo.AnalyzeCallResult(Ins, 774 CCAssignFnForNode(CallConv, /* Return*/ true, 775 isVarArg)); 776 777 // Copy all of the result registers out of their specified physreg. 778 for (unsigned i = 0; i != RVLocs.size(); ++i) { 779 CCValAssign VA = RVLocs[i]; 780 781 SDValue Val; 782 if (VA.needsCustom()) { 783 // Handle f64 or half of a v2f64. 784 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 785 InFlag); 786 Chain = Lo.getValue(1); 787 InFlag = Lo.getValue(2); 788 VA = RVLocs[++i]; // skip ahead to next loc 789 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 790 InFlag); 791 Chain = Hi.getValue(1); 792 InFlag = Hi.getValue(2); 793 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); 794 795 if (VA.getLocVT() == MVT::v2f64) { 796 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 797 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 798 DAG.getConstant(0, MVT::i32)); 799 800 VA = RVLocs[++i]; // skip ahead to next loc 801 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 802 Chain = Lo.getValue(1); 803 InFlag = Lo.getValue(2); 804 VA = RVLocs[++i]; // skip ahead to next loc 805 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 806 Chain = Hi.getValue(1); 807 InFlag = Hi.getValue(2); 808 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); 809 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 810 DAG.getConstant(1, MVT::i32)); 811 } 812 } else { 813 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 814 InFlag); 815 Chain = Val.getValue(1); 816 InFlag = Val.getValue(2); 817 } 818 819 switch (VA.getLocInfo()) { 820 default: llvm_unreachable("Unknown loc info!"); 821 case CCValAssign::Full: break; 822 case CCValAssign::BCvt: 823 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); 824 break; 825 } 826 827 InVals.push_back(Val); 828 } 829 830 return Chain; 831} 832 833/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 834/// by "Src" to address "Dst" of size "Size". Alignment information is 835/// specified by the specific parameter attribute. The copy will be passed as 836/// a byval function parameter. 837/// Sometimes what we are copying is the end of a larger object, the part that 838/// does not fit in registers. 839static SDValue 840CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 841 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 842 DebugLoc dl) { 843 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 844 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 845 /*AlwaysInline=*/false, NULL, 0, NULL, 0); 846} 847 848/// LowerMemOpCallTo - Store the argument to the stack. 849SDValue 850ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 851 SDValue StackPtr, SDValue Arg, 852 DebugLoc dl, SelectionDAG &DAG, 853 const CCValAssign &VA, 854 ISD::ArgFlagsTy Flags) { 855 unsigned LocMemOffset = VA.getLocMemOffset(); 856 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 857 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 858 if (Flags.isByVal()) { 859 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 860 } 861 return DAG.getStore(Chain, dl, Arg, PtrOff, 862 PseudoSourceValue::getStack(), LocMemOffset); 863} 864 865void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 866 SDValue Chain, SDValue &Arg, 867 RegsToPassVector &RegsToPass, 868 CCValAssign &VA, CCValAssign &NextVA, 869 SDValue &StackPtr, 870 SmallVector<SDValue, 8> &MemOpChains, 871 ISD::ArgFlagsTy Flags) { 872 873 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, 874 DAG.getVTList(MVT::i32, MVT::i32), Arg); 875 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 876 877 if (NextVA.isRegLoc()) 878 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 879 else { 880 assert(NextVA.isMemLoc()); 881 if (StackPtr.getNode() == 0) 882 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 883 884 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 885 dl, DAG, NextVA, 886 Flags)); 887 } 888} 889 890/// LowerCall - Lowering a call into a callseq_start <- 891/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 892/// nodes. 893SDValue 894ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 895 CallingConv::ID CallConv, bool isVarArg, 896 bool isTailCall, 897 const SmallVectorImpl<ISD::OutputArg> &Outs, 898 const SmallVectorImpl<ISD::InputArg> &Ins, 899 DebugLoc dl, SelectionDAG &DAG, 900 SmallVectorImpl<SDValue> &InVals) { 901 902 // Analyze operands of the call, assigning locations to each operand. 903 SmallVector<CCValAssign, 16> ArgLocs; 904 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 905 *DAG.getContext()); 906 CCInfo.AnalyzeCallOperands(Outs, 907 CCAssignFnForNode(CallConv, /* Return*/ false, 908 isVarArg)); 909 910 // Get a count of how many bytes are to be pushed on the stack. 911 unsigned NumBytes = CCInfo.getNextStackOffset(); 912 913 // Adjust the stack pointer for the new arguments... 914 // These operations are automatically eliminated by the prolog/epilog pass 915 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 916 917 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 918 919 RegsToPassVector RegsToPass; 920 SmallVector<SDValue, 8> MemOpChains; 921 922 // Walk the register/memloc assignments, inserting copies/loads. In the case 923 // of tail call optimization, arguments are handled later. 924 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 925 i != e; 926 ++i, ++realArgIdx) { 927 CCValAssign &VA = ArgLocs[i]; 928 SDValue Arg = Outs[realArgIdx].Val; 929 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 930 931 // Promote the value if needed. 932 switch (VA.getLocInfo()) { 933 default: llvm_unreachable("Unknown loc info!"); 934 case CCValAssign::Full: break; 935 case CCValAssign::SExt: 936 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 937 break; 938 case CCValAssign::ZExt: 939 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 940 break; 941 case CCValAssign::AExt: 942 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 943 break; 944 case CCValAssign::BCvt: 945 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 946 break; 947 } 948 949 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 950 if (VA.needsCustom()) { 951 if (VA.getLocVT() == MVT::v2f64) { 952 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 953 DAG.getConstant(0, MVT::i32)); 954 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 955 DAG.getConstant(1, MVT::i32)); 956 957 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 958 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 959 960 VA = ArgLocs[++i]; // skip ahead to next loc 961 if (VA.isRegLoc()) { 962 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 963 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 964 } else { 965 assert(VA.isMemLoc()); 966 if (StackPtr.getNode() == 0) 967 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 968 969 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 970 dl, DAG, VA, Flags)); 971 } 972 } else { 973 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 974 StackPtr, MemOpChains, Flags); 975 } 976 } else if (VA.isRegLoc()) { 977 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 978 } else { 979 assert(VA.isMemLoc()); 980 if (StackPtr.getNode() == 0) 981 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 982 983 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 984 dl, DAG, VA, Flags)); 985 } 986 } 987 988 if (!MemOpChains.empty()) 989 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 990 &MemOpChains[0], MemOpChains.size()); 991 992 // Build a sequence of copy-to-reg nodes chained together with token chain 993 // and flag operands which copy the outgoing args into the appropriate regs. 994 SDValue InFlag; 995 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 996 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 997 RegsToPass[i].second, InFlag); 998 InFlag = Chain.getValue(1); 999 } 1000 1001 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1002 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1003 // node so that legalize doesn't hack it. 1004 bool isDirect = false; 1005 bool isARMFunc = false; 1006 bool isLocalARMFunc = false; 1007 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1008 GlobalValue *GV = G->getGlobal(); 1009 isDirect = true; 1010 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1011 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1012 getTargetMachine().getRelocationModel() != Reloc::Static; 1013 isARMFunc = !Subtarget->isThumb() || isStub; 1014 // ARM call to a local ARM function is predicable. 1015 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 1016 // tBX takes a register source operand. 1017 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1018 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1019 ARMPCLabelIndex, 1020 ARMCP::CPValue, 4); 1021 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1022 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1023 Callee = DAG.getLoad(getPointerTy(), dl, 1024 DAG.getEntryNode(), CPAddr, 1025 PseudoSourceValue::getConstantPool(), 0); 1026 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1027 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1028 getPointerTy(), Callee, PICLabel); 1029 } else 1030 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 1031 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1032 isDirect = true; 1033 bool isStub = Subtarget->isTargetDarwin() && 1034 getTargetMachine().getRelocationModel() != Reloc::Static; 1035 isARMFunc = !Subtarget->isThumb() || isStub; 1036 // tBX takes a register source operand. 1037 const char *Sym = S->getSymbol(); 1038 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1039 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1040 Sym, ARMPCLabelIndex, 4); 1041 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1042 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1043 Callee = DAG.getLoad(getPointerTy(), dl, 1044 DAG.getEntryNode(), CPAddr, 1045 PseudoSourceValue::getConstantPool(), 0); 1046 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1047 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1048 getPointerTy(), Callee, PICLabel); 1049 } else 1050 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 1051 } 1052 1053 // FIXME: handle tail calls differently. 1054 unsigned CallOpc; 1055 if (Subtarget->isThumb()) { 1056 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1057 CallOpc = ARMISD::CALL_NOLINK; 1058 else 1059 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1060 } else { 1061 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1062 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1063 : ARMISD::CALL_NOLINK; 1064 } 1065 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) { 1066 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 1067 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); 1068 InFlag = Chain.getValue(1); 1069 } 1070 1071 std::vector<SDValue> Ops; 1072 Ops.push_back(Chain); 1073 Ops.push_back(Callee); 1074 1075 // Add argument registers to the end of the list so that they are known live 1076 // into the call. 1077 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1078 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1079 RegsToPass[i].second.getValueType())); 1080 1081 if (InFlag.getNode()) 1082 Ops.push_back(InFlag); 1083 // Returns a chain and a flag for retval copy to use. 1084 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), 1085 &Ops[0], Ops.size()); 1086 InFlag = Chain.getValue(1); 1087 1088 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1089 DAG.getIntPtrConstant(0, true), InFlag); 1090 if (!Ins.empty()) 1091 InFlag = Chain.getValue(1); 1092 1093 // Handle result values, copying them out of physregs into vregs that we 1094 // return. 1095 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1096 dl, DAG, InVals); 1097} 1098 1099SDValue 1100ARMTargetLowering::LowerReturn(SDValue Chain, 1101 CallingConv::ID CallConv, bool isVarArg, 1102 const SmallVectorImpl<ISD::OutputArg> &Outs, 1103 DebugLoc dl, SelectionDAG &DAG) { 1104 1105 // CCValAssign - represent the assignment of the return value to a location. 1106 SmallVector<CCValAssign, 16> RVLocs; 1107 1108 // CCState - Info about the registers and stack slots. 1109 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 1110 *DAG.getContext()); 1111 1112 // Analyze outgoing return values. 1113 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1114 isVarArg)); 1115 1116 // If this is the first return lowered for this function, add 1117 // the regs to the liveout set for the function. 1118 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1119 for (unsigned i = 0; i != RVLocs.size(); ++i) 1120 if (RVLocs[i].isRegLoc()) 1121 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1122 } 1123 1124 SDValue Flag; 1125 1126 // Copy the result values into the output registers. 1127 for (unsigned i = 0, realRVLocIdx = 0; 1128 i != RVLocs.size(); 1129 ++i, ++realRVLocIdx) { 1130 CCValAssign &VA = RVLocs[i]; 1131 assert(VA.isRegLoc() && "Can only return in registers!"); 1132 1133 SDValue Arg = Outs[realRVLocIdx].Val; 1134 1135 switch (VA.getLocInfo()) { 1136 default: llvm_unreachable("Unknown loc info!"); 1137 case CCValAssign::Full: break; 1138 case CCValAssign::BCvt: 1139 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1140 break; 1141 } 1142 1143 if (VA.needsCustom()) { 1144 if (VA.getLocVT() == MVT::v2f64) { 1145 // Extract the first half and return it in two registers. 1146 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1147 DAG.getConstant(0, MVT::i32)); 1148 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl, 1149 DAG.getVTList(MVT::i32, MVT::i32), Half); 1150 1151 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1152 Flag = Chain.getValue(1); 1153 VA = RVLocs[++i]; // skip ahead to next loc 1154 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1155 HalfGPRs.getValue(1), Flag); 1156 Flag = Chain.getValue(1); 1157 VA = RVLocs[++i]; // skip ahead to next loc 1158 1159 // Extract the 2nd half and fall through to handle it as an f64 value. 1160 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1161 DAG.getConstant(1, MVT::i32)); 1162 } 1163 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1164 // available. 1165 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, 1166 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1167 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1168 Flag = Chain.getValue(1); 1169 VA = RVLocs[++i]; // skip ahead to next loc 1170 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1171 Flag); 1172 } else 1173 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1174 1175 // Guarantee that all emitted copies are 1176 // stuck together, avoiding something bad. 1177 Flag = Chain.getValue(1); 1178 } 1179 1180 SDValue result; 1181 if (Flag.getNode()) 1182 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1183 else // Return Void 1184 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1185 1186 return result; 1187} 1188 1189// ConstantPool, BlockAddress, JumpTable, GlobalAddress, and ExternalSymbol are 1190// lowered as their target counterpart wrapped in the ARMISD::Wrapper 1191// node. Suppose N is one of the above mentioned nodes. It has to be wrapped 1192// because otherwise Select(N) returns N. So the raw TargetGlobalAddress 1193// nodes, etc. can only be used to form addressing mode. These wrapped nodes 1194// will be selected into MOVi. 1195static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1196 EVT PtrVT = Op.getValueType(); 1197 // FIXME there is no actual debug info here 1198 DebugLoc dl = Op.getDebugLoc(); 1199 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1200 SDValue Res; 1201 if (CP->isMachineConstantPoolEntry()) 1202 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1203 CP->getAlignment()); 1204 else 1205 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1206 CP->getAlignment()); 1207 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1208} 1209 1210SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 1211 DebugLoc DL = Op.getDebugLoc(); 1212 EVT PtrVT = getPointerTy(); 1213 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1214 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1215 SDValue CPAddr; 1216 if (RelocM == Reloc::Static) { 1217 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1218 } else { 1219 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1220 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex, 1221 ARMCP::CPBlockAddress, 1222 PCAdj); 1223 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1224 } 1225 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1226 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1227 PseudoSourceValue::getConstantPool(), 0); 1228 if (RelocM == Reloc::Static) 1229 return Result; 1230 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1231 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1232} 1233 1234// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1235SDValue 1236ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1237 SelectionDAG &DAG) { 1238 DebugLoc dl = GA->getDebugLoc(); 1239 EVT PtrVT = getPointerTy(); 1240 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1241 ARMConstantPoolValue *CPV = 1242 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1243 ARMCP::CPValue, PCAdj, "tlsgd", true); 1244 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1245 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1246 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1247 PseudoSourceValue::getConstantPool(), 0); 1248 SDValue Chain = Argument.getValue(1); 1249 1250 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1251 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1252 1253 // call __tls_get_addr. 1254 ArgListTy Args; 1255 ArgListEntry Entry; 1256 Entry.Node = Argument; 1257 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext()); 1258 Args.push_back(Entry); 1259 // FIXME: is there useful debug info available here? 1260 std::pair<SDValue, SDValue> CallResult = 1261 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()), 1262 false, false, false, false, 1263 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 1264 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 1265 return CallResult.first; 1266} 1267 1268// Lower ISD::GlobalTLSAddress using the "initial exec" or 1269// "local exec" model. 1270SDValue 1271ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 1272 SelectionDAG &DAG) { 1273 GlobalValue *GV = GA->getGlobal(); 1274 DebugLoc dl = GA->getDebugLoc(); 1275 SDValue Offset; 1276 SDValue Chain = DAG.getEntryNode(); 1277 EVT PtrVT = getPointerTy(); 1278 // Get the Thread Pointer 1279 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1280 1281 if (GV->isDeclaration()) { 1282 // initial exec model 1283 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1284 ARMConstantPoolValue *CPV = 1285 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1286 ARMCP::CPValue, PCAdj, "gottpoff", true); 1287 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1288 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1289 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1290 PseudoSourceValue::getConstantPool(), 0); 1291 Chain = Offset.getValue(1); 1292 1293 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1294 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 1295 1296 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1297 PseudoSourceValue::getConstantPool(), 0); 1298 } else { 1299 // local exec model 1300 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff"); 1301 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1302 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1303 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1304 PseudoSourceValue::getConstantPool(), 0); 1305 } 1306 1307 // The address of the thread local variable is the add of the thread 1308 // pointer with the offset of the variable. 1309 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1310} 1311 1312SDValue 1313ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 1314 // TODO: implement the "local dynamic" model 1315 assert(Subtarget->isTargetELF() && 1316 "TLS not implemented for non-ELF targets"); 1317 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1318 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 1319 // otherwise use the "Local Exec" TLS Model 1320 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 1321 return LowerToTLSGeneralDynamicModel(GA, DAG); 1322 else 1323 return LowerToTLSExecModels(GA, DAG); 1324} 1325 1326SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 1327 SelectionDAG &DAG) { 1328 EVT PtrVT = getPointerTy(); 1329 DebugLoc dl = Op.getDebugLoc(); 1330 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1331 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1332 if (RelocM == Reloc::PIC_) { 1333 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 1334 ARMConstantPoolValue *CPV = 1335 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT"); 1336 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1337 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1338 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1339 CPAddr, 1340 PseudoSourceValue::getConstantPool(), 0); 1341 SDValue Chain = Result.getValue(1); 1342 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 1343 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 1344 if (!UseGOTOFF) 1345 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1346 PseudoSourceValue::getGOT(), 0); 1347 return Result; 1348 } else { 1349 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1350 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1351 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1352 PseudoSourceValue::getConstantPool(), 0); 1353 } 1354} 1355 1356SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 1357 SelectionDAG &DAG) { 1358 EVT PtrVT = getPointerTy(); 1359 DebugLoc dl = Op.getDebugLoc(); 1360 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1361 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1362 SDValue CPAddr; 1363 if (RelocM == Reloc::Static) 1364 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1365 else { 1366 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 1367 ARMConstantPoolValue *CPV = 1368 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj); 1369 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1370 } 1371 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1372 1373 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1374 PseudoSourceValue::getConstantPool(), 0); 1375 SDValue Chain = Result.getValue(1); 1376 1377 if (RelocM == Reloc::PIC_) { 1378 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1379 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1380 } 1381 1382 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 1383 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1384 PseudoSourceValue::getGOT(), 0); 1385 1386 return Result; 1387} 1388 1389SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 1390 SelectionDAG &DAG){ 1391 assert(Subtarget->isTargetELF() && 1392 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 1393 EVT PtrVT = getPointerTy(); 1394 DebugLoc dl = Op.getDebugLoc(); 1395 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1396 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1397 "_GLOBAL_OFFSET_TABLE_", 1398 ARMPCLabelIndex, PCAdj); 1399 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1400 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1401 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1402 PseudoSourceValue::getConstantPool(), 0); 1403 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1404 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1405} 1406 1407SDValue 1408ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 1409 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1410 DebugLoc dl = Op.getDebugLoc(); 1411 switch (IntNo) { 1412 default: return SDValue(); // Don't custom lower most intrinsics. 1413 case Intrinsic::arm_thread_pointer: { 1414 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1415 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1416 } 1417 case Intrinsic::eh_sjlj_lsda: { 1418 MachineFunction &MF = DAG.getMachineFunction(); 1419 EVT PtrVT = getPointerTy(); 1420 DebugLoc dl = Op.getDebugLoc(); 1421 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1422 SDValue CPAddr; 1423 unsigned PCAdj = (RelocM != Reloc::PIC_) 1424 ? 0 : (Subtarget->isThumb() ? 4 : 8); 1425 ARMConstantPoolValue *CPV = 1426 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex, 1427 ARMCP::CPLSDA, PCAdj); 1428 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1429 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1430 SDValue Result = 1431 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1432 PseudoSourceValue::getConstantPool(), 0); 1433 SDValue Chain = Result.getValue(1); 1434 1435 if (RelocM == Reloc::PIC_) { 1436 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1437 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1438 } 1439 return Result; 1440 } 1441 case Intrinsic::eh_sjlj_setjmp: 1442 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1)); 1443 } 1444} 1445 1446static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1447 unsigned VarArgsFrameIndex) { 1448 // vastart just stores the address of the VarArgsFrameIndex slot into the 1449 // memory location argument. 1450 DebugLoc dl = Op.getDebugLoc(); 1451 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1452 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1453 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1454 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 1455} 1456 1457SDValue 1458ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1459 SDNode *Node = Op.getNode(); 1460 DebugLoc dl = Node->getDebugLoc(); 1461 EVT VT = Node->getValueType(0); 1462 SDValue Chain = Op.getOperand(0); 1463 SDValue Size = Op.getOperand(1); 1464 SDValue Align = Op.getOperand(2); 1465 1466 // Chain the dynamic stack allocation so that it doesn't modify the stack 1467 // pointer when other instructions are using the stack. 1468 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1469 1470 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue(); 1471 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment(); 1472 if (AlignVal > StackAlign) 1473 // Do this now since selection pass cannot introduce new target 1474 // independent node. 1475 Align = DAG.getConstant(-(uint64_t)AlignVal, VT); 1476 1477 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up 1478 // using a "add r, sp, r" instead. Negate the size now so we don't have to 1479 // do even more horrible hack later. 1480 MachineFunction &MF = DAG.getMachineFunction(); 1481 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1482 if (AFI->isThumb1OnlyFunction()) { 1483 bool Negate = true; 1484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size); 1485 if (C) { 1486 uint32_t Val = C->getZExtValue(); 1487 if (Val <= 508 && ((Val & 3) == 0)) 1488 Negate = false; 1489 } 1490 if (Negate) 1491 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size); 1492 } 1493 1494 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1495 SDValue Ops1[] = { Chain, Size, Align }; 1496 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3); 1497 Chain = Res.getValue(1); 1498 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1499 DAG.getIntPtrConstant(0, true), SDValue()); 1500 SDValue Ops2[] = { Res, Chain }; 1501 return DAG.getMergeValues(Ops2, 2, dl); 1502} 1503 1504SDValue 1505ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 1506 SDValue &Root, SelectionDAG &DAG, 1507 DebugLoc dl) { 1508 MachineFunction &MF = DAG.getMachineFunction(); 1509 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1510 1511 TargetRegisterClass *RC; 1512 if (AFI->isThumb1OnlyFunction()) 1513 RC = ARM::tGPRRegisterClass; 1514 else 1515 RC = ARM::GPRRegisterClass; 1516 1517 // Transform the arguments stored in physical registers into virtual ones. 1518 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1519 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 1520 1521 SDValue ArgValue2; 1522 if (NextVA.isMemLoc()) { 1523 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8; 1524 MachineFrameInfo *MFI = MF.getFrameInfo(); 1525 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset()); 1526 1527 // Create load node to retrieve arguments from the stack. 1528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1529 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 1530 PseudoSourceValue::getFixedStack(FI), 0); 1531 } else { 1532 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 1533 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 1534 } 1535 1536 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); 1537} 1538 1539SDValue 1540ARMTargetLowering::LowerFormalArguments(SDValue Chain, 1541 CallingConv::ID CallConv, bool isVarArg, 1542 const SmallVectorImpl<ISD::InputArg> 1543 &Ins, 1544 DebugLoc dl, SelectionDAG &DAG, 1545 SmallVectorImpl<SDValue> &InVals) { 1546 1547 MachineFunction &MF = DAG.getMachineFunction(); 1548 MachineFrameInfo *MFI = MF.getFrameInfo(); 1549 1550 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1551 1552 // Assign locations to all of the incoming arguments. 1553 SmallVector<CCValAssign, 16> ArgLocs; 1554 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1555 *DAG.getContext()); 1556 CCInfo.AnalyzeFormalArguments(Ins, 1557 CCAssignFnForNode(CallConv, /* Return*/ false, 1558 isVarArg)); 1559 1560 SmallVector<SDValue, 16> ArgValues; 1561 1562 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1563 CCValAssign &VA = ArgLocs[i]; 1564 1565 // Arguments stored in registers. 1566 if (VA.isRegLoc()) { 1567 EVT RegVT = VA.getLocVT(); 1568 1569 SDValue ArgValue; 1570 if (VA.needsCustom()) { 1571 // f64 and vector types are split up into multiple registers or 1572 // combinations of registers and stack slots. 1573 RegVT = MVT::i32; 1574 1575 if (VA.getLocVT() == MVT::v2f64) { 1576 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 1577 Chain, DAG, dl); 1578 VA = ArgLocs[++i]; // skip ahead to next loc 1579 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 1580 Chain, DAG, dl); 1581 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1582 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 1583 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 1584 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 1585 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 1586 } else 1587 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 1588 1589 } else { 1590 TargetRegisterClass *RC; 1591 1592 if (RegVT == MVT::f32) 1593 RC = ARM::SPRRegisterClass; 1594 else if (RegVT == MVT::f64) 1595 RC = ARM::DPRRegisterClass; 1596 else if (RegVT == MVT::v2f64) 1597 RC = ARM::QPRRegisterClass; 1598 else if (RegVT == MVT::i32) 1599 RC = (AFI->isThumb1OnlyFunction() ? 1600 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 1601 else 1602 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 1603 1604 // Transform the arguments in physical registers into virtual ones. 1605 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1606 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1607 } 1608 1609 // If this is an 8 or 16-bit value, it is really passed promoted 1610 // to 32 bits. Insert an assert[sz]ext to capture this, then 1611 // truncate to the right size. 1612 switch (VA.getLocInfo()) { 1613 default: llvm_unreachable("Unknown loc info!"); 1614 case CCValAssign::Full: break; 1615 case CCValAssign::BCvt: 1616 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1617 break; 1618 case CCValAssign::SExt: 1619 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1620 DAG.getValueType(VA.getValVT())); 1621 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1622 break; 1623 case CCValAssign::ZExt: 1624 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1625 DAG.getValueType(VA.getValVT())); 1626 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1627 break; 1628 } 1629 1630 InVals.push_back(ArgValue); 1631 1632 } else { // VA.isRegLoc() 1633 1634 // sanity check 1635 assert(VA.isMemLoc()); 1636 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 1637 1638 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 1639 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset()); 1640 1641 // Create load nodes to retrieve arguments from the stack. 1642 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1643 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1644 PseudoSourceValue::getFixedStack(FI), 0)); 1645 } 1646 } 1647 1648 // varargs 1649 if (isVarArg) { 1650 static const unsigned GPRArgRegs[] = { 1651 ARM::R0, ARM::R1, ARM::R2, ARM::R3 1652 }; 1653 1654 unsigned NumGPRs = CCInfo.getFirstUnallocated 1655 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 1656 1657 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1658 unsigned VARegSize = (4 - NumGPRs) * 4; 1659 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 1660 unsigned ArgOffset = CCInfo.getNextStackOffset(); 1661 if (VARegSaveSize) { 1662 // If this function is vararg, store any remaining integer argument regs 1663 // to their spots on the stack so that they may be loaded by deferencing 1664 // the result of va_next. 1665 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1666 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1667 VARegSaveSize - VARegSize); 1668 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1669 1670 SmallVector<SDValue, 4> MemOps; 1671 for (; NumGPRs < 4; ++NumGPRs) { 1672 TargetRegisterClass *RC; 1673 if (AFI->isThumb1OnlyFunction()) 1674 RC = ARM::tGPRRegisterClass; 1675 else 1676 RC = ARM::GPRRegisterClass; 1677 1678 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); 1679 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1680 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1681 PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0); 1682 MemOps.push_back(Store); 1683 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1684 DAG.getConstant(4, getPointerTy())); 1685 } 1686 if (!MemOps.empty()) 1687 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1688 &MemOps[0], MemOps.size()); 1689 } else 1690 // This will point to the next argument passed via stack. 1691 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1692 } 1693 1694 return Chain; 1695} 1696 1697/// isFloatingPointZero - Return true if this is +0.0. 1698static bool isFloatingPointZero(SDValue Op) { 1699 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1700 return CFP->getValueAPF().isPosZero(); 1701 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 1702 // Maybe this has already been legalized into the constant pool? 1703 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1704 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 1705 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1706 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1707 return CFP->getValueAPF().isPosZero(); 1708 } 1709 } 1710 return false; 1711} 1712 1713static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) { 1714 return ( isThumb1Only && (C & ~255U) == 0) || 1715 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1); 1716} 1717 1718/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1719/// the given operands. 1720static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1721 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only, 1722 DebugLoc dl) { 1723 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1724 unsigned C = RHSC->getZExtValue(); 1725 if (!isLegalCmpImmediate(C, isThumb1Only)) { 1726 // Constant does not fit, try adjusting it by one? 1727 switch (CC) { 1728 default: break; 1729 case ISD::SETLT: 1730 case ISD::SETGE: 1731 if (isLegalCmpImmediate(C-1, isThumb1Only)) { 1732 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1733 RHS = DAG.getConstant(C-1, MVT::i32); 1734 } 1735 break; 1736 case ISD::SETULT: 1737 case ISD::SETUGE: 1738 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) { 1739 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1740 RHS = DAG.getConstant(C-1, MVT::i32); 1741 } 1742 break; 1743 case ISD::SETLE: 1744 case ISD::SETGT: 1745 if (isLegalCmpImmediate(C+1, isThumb1Only)) { 1746 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1747 RHS = DAG.getConstant(C+1, MVT::i32); 1748 } 1749 break; 1750 case ISD::SETULE: 1751 case ISD::SETUGT: 1752 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) { 1753 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1754 RHS = DAG.getConstant(C+1, MVT::i32); 1755 } 1756 break; 1757 } 1758 } 1759 } 1760 1761 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1762 ARMISD::NodeType CompareType; 1763 switch (CondCode) { 1764 default: 1765 CompareType = ARMISD::CMP; 1766 break; 1767 case ARMCC::EQ: 1768 case ARMCC::NE: 1769 // Uses only Z Flag 1770 CompareType = ARMISD::CMPZ; 1771 break; 1772 } 1773 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1774 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); 1775} 1776 1777/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1778static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 1779 DebugLoc dl) { 1780 SDValue Cmp; 1781 if (!isFloatingPointZero(RHS)) 1782 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); 1783 else 1784 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); 1785 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); 1786} 1787 1788static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 1789 const ARMSubtarget *ST) { 1790 EVT VT = Op.getValueType(); 1791 SDValue LHS = Op.getOperand(0); 1792 SDValue RHS = Op.getOperand(1); 1793 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1794 SDValue TrueVal = Op.getOperand(2); 1795 SDValue FalseVal = Op.getOperand(3); 1796 DebugLoc dl = Op.getDebugLoc(); 1797 1798 if (LHS.getValueType() == MVT::i32) { 1799 SDValue ARMCC; 1800 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1801 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl); 1802 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); 1803 } 1804 1805 ARMCC::CondCodes CondCode, CondCode2; 1806 FPCCToARMCC(CC, CondCode, CondCode2); 1807 1808 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1809 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1810 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 1811 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 1812 ARMCC, CCR, Cmp); 1813 if (CondCode2 != ARMCC::AL) { 1814 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1815 // FIXME: Needs another CMP because flag can have but one use. 1816 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 1817 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 1818 Result, TrueVal, ARMCC2, CCR, Cmp2); 1819 } 1820 return Result; 1821} 1822 1823static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 1824 const ARMSubtarget *ST) { 1825 SDValue Chain = Op.getOperand(0); 1826 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1827 SDValue LHS = Op.getOperand(2); 1828 SDValue RHS = Op.getOperand(3); 1829 SDValue Dest = Op.getOperand(4); 1830 DebugLoc dl = Op.getDebugLoc(); 1831 1832 if (LHS.getValueType() == MVT::i32) { 1833 SDValue ARMCC; 1834 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1835 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl); 1836 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 1837 Chain, Dest, ARMCC, CCR,Cmp); 1838 } 1839 1840 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1841 ARMCC::CondCodes CondCode, CondCode2; 1842 FPCCToARMCC(CC, CondCode, CondCode2); 1843 1844 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 1845 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1846 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1847 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1848 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1849 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 1850 if (CondCode2 != ARMCC::AL) { 1851 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1852 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1853 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 1854 } 1855 return Res; 1856} 1857 1858SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { 1859 SDValue Chain = Op.getOperand(0); 1860 SDValue Table = Op.getOperand(1); 1861 SDValue Index = Op.getOperand(2); 1862 DebugLoc dl = Op.getDebugLoc(); 1863 1864 EVT PTy = getPointerTy(); 1865 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1866 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1867 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1868 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1869 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 1870 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 1871 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 1872 if (Subtarget->isThumb2()) { 1873 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 1874 // which does another jump to the destination. This also makes it easier 1875 // to translate it to TBB / TBH later. 1876 // FIXME: This might not work if the function is extremely large. 1877 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 1878 Addr, Op.getOperand(2), JTI, UId); 1879 } 1880 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1881 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 1882 PseudoSourceValue::getJumpTable(), 0); 1883 Chain = Addr.getValue(1); 1884 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 1885 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 1886 } else { 1887 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 1888 PseudoSourceValue::getJumpTable(), 0); 1889 Chain = Addr.getValue(1); 1890 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 1891 } 1892} 1893 1894static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1895 DebugLoc dl = Op.getDebugLoc(); 1896 unsigned Opc = 1897 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1898 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 1899 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 1900} 1901 1902static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1903 EVT VT = Op.getValueType(); 1904 DebugLoc dl = Op.getDebugLoc(); 1905 unsigned Opc = 1906 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1907 1908 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 1909 return DAG.getNode(Opc, dl, VT, Op); 1910} 1911 1912static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 1913 // Implement fcopysign with a fabs and a conditional fneg. 1914 SDValue Tmp0 = Op.getOperand(0); 1915 SDValue Tmp1 = Op.getOperand(1); 1916 DebugLoc dl = Op.getDebugLoc(); 1917 EVT VT = Op.getValueType(); 1918 EVT SrcVT = Tmp1.getValueType(); 1919 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); 1920 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); 1921 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1922 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1923 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1924} 1925 1926SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1927 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1928 MFI->setFrameAddressIsTaken(true); 1929 EVT VT = Op.getValueType(); 1930 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 1931 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1932 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 1933 ? ARM::R7 : ARM::R11; 1934 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1935 while (Depth--) 1936 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 1937 return FrameAddr; 1938} 1939 1940SDValue 1941ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1942 SDValue Chain, 1943 SDValue Dst, SDValue Src, 1944 SDValue Size, unsigned Align, 1945 bool AlwaysInline, 1946 const Value *DstSV, uint64_t DstSVOff, 1947 const Value *SrcSV, uint64_t SrcSVOff){ 1948 // Do repeated 4-byte loads and stores. To be improved. 1949 // This requires 4-byte alignment. 1950 if ((Align & 3) != 0) 1951 return SDValue(); 1952 // This requires the copy size to be a constant, preferrably 1953 // within a subtarget-specific limit. 1954 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 1955 if (!ConstantSize) 1956 return SDValue(); 1957 uint64_t SizeVal = ConstantSize->getZExtValue(); 1958 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 1959 return SDValue(); 1960 1961 unsigned BytesLeft = SizeVal & 3; 1962 unsigned NumMemOps = SizeVal >> 2; 1963 unsigned EmittedNumMemOps = 0; 1964 EVT VT = MVT::i32; 1965 unsigned VTSize = 4; 1966 unsigned i = 0; 1967 const unsigned MAX_LOADS_IN_LDM = 6; 1968 SDValue TFOps[MAX_LOADS_IN_LDM]; 1969 SDValue Loads[MAX_LOADS_IN_LDM]; 1970 uint64_t SrcOff = 0, DstOff = 0; 1971 1972 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1973 // same number of stores. The loads and stores will get combined into 1974 // ldm/stm later on. 1975 while (EmittedNumMemOps < NumMemOps) { 1976 for (i = 0; 1977 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1978 Loads[i] = DAG.getLoad(VT, dl, Chain, 1979 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 1980 DAG.getConstant(SrcOff, MVT::i32)), 1981 SrcSV, SrcSVOff + SrcOff); 1982 TFOps[i] = Loads[i].getValue(1); 1983 SrcOff += VTSize; 1984 } 1985 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1986 1987 for (i = 0; 1988 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1989 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 1990 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 1991 DAG.getConstant(DstOff, MVT::i32)), 1992 DstSV, DstSVOff + DstOff); 1993 DstOff += VTSize; 1994 } 1995 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1996 1997 EmittedNumMemOps += i; 1998 } 1999 2000 if (BytesLeft == 0) 2001 return Chain; 2002 2003 // Issue loads / stores for the trailing (1 - 3) bytes. 2004 unsigned BytesLeftSave = BytesLeft; 2005 i = 0; 2006 while (BytesLeft) { 2007 if (BytesLeft >= 2) { 2008 VT = MVT::i16; 2009 VTSize = 2; 2010 } else { 2011 VT = MVT::i8; 2012 VTSize = 1; 2013 } 2014 2015 Loads[i] = DAG.getLoad(VT, dl, Chain, 2016 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 2017 DAG.getConstant(SrcOff, MVT::i32)), 2018 SrcSV, SrcSVOff + SrcOff); 2019 TFOps[i] = Loads[i].getValue(1); 2020 ++i; 2021 SrcOff += VTSize; 2022 BytesLeft -= VTSize; 2023 } 2024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 2025 2026 i = 0; 2027 BytesLeft = BytesLeftSave; 2028 while (BytesLeft) { 2029 if (BytesLeft >= 2) { 2030 VT = MVT::i16; 2031 VTSize = 2; 2032 } else { 2033 VT = MVT::i8; 2034 VTSize = 1; 2035 } 2036 2037 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 2038 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 2039 DAG.getConstant(DstOff, MVT::i32)), 2040 DstSV, DstSVOff + DstOff); 2041 ++i; 2042 DstOff += VTSize; 2043 BytesLeft -= VTSize; 2044 } 2045 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 2046} 2047 2048static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 2049 SDValue Op = N->getOperand(0); 2050 DebugLoc dl = N->getDebugLoc(); 2051 if (N->getValueType(0) == MVT::f64) { 2052 // Turn i64->f64 into FMDRR. 2053 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2054 DAG.getConstant(0, MVT::i32)); 2055 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2056 DAG.getConstant(1, MVT::i32)); 2057 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); 2058 } 2059 2060 // Turn f64->i64 into FMRRD. 2061 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, 2062 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 2063 2064 // Merge the pieces into a single i64 value. 2065 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 2066} 2067 2068/// getZeroVector - Returns a vector of specified type with all zero elements. 2069/// 2070static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2071 assert(VT.isVector() && "Expected a vector type"); 2072 2073 // Zero vectors are used to represent vector negation and in those cases 2074 // will be implemented with the NEON VNEG instruction. However, VNEG does 2075 // not support i64 elements, so sometimes the zero vectors will need to be 2076 // explicitly constructed. For those cases, and potentially other uses in 2077 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted 2078 // to their dest type. This ensures they get CSE'd. 2079 SDValue Vec; 2080 SDValue Cst = DAG.getTargetConstant(0, MVT::i8); 2081 SmallVector<SDValue, 8> Ops; 2082 MVT TVT; 2083 2084 if (VT.getSizeInBits() == 64) { 2085 Ops.assign(8, Cst); TVT = MVT::v8i8; 2086 } else { 2087 Ops.assign(16, Cst); TVT = MVT::v16i8; 2088 } 2089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2090 2091 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2092} 2093 2094/// getOnesVector - Returns a vector of specified type with all bits set. 2095/// 2096static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2097 assert(VT.isVector() && "Expected a vector type"); 2098 2099 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their 2100 // dest type. This ensures they get CSE'd. 2101 SDValue Vec; 2102 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8); 2103 SmallVector<SDValue, 8> Ops; 2104 MVT TVT; 2105 2106 if (VT.getSizeInBits() == 64) { 2107 Ops.assign(8, Cst); TVT = MVT::v8i8; 2108 } else { 2109 Ops.assign(16, Cst); TVT = MVT::v16i8; 2110 } 2111 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); 2112 2113 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2114} 2115 2116/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 2117/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2118static SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2119 const ARMSubtarget *ST) { 2120 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2121 EVT VT = Op.getValueType(); 2122 unsigned VTBits = VT.getSizeInBits(); 2123 DebugLoc dl = Op.getDebugLoc(); 2124 SDValue ShOpLo = Op.getOperand(0); 2125 SDValue ShOpHi = Op.getOperand(1); 2126 SDValue ShAmt = Op.getOperand(2); 2127 SDValue ARMCC; 2128 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 2129 2130 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 2131 2132 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2133 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2134 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 2135 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2136 DAG.getConstant(VTBits, MVT::i32)); 2137 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 2138 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2139 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 2140 2141 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2142 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2143 ARMCC, DAG, ST->isThumb1Only(), dl); 2144 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 2145 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, 2146 CCR, Cmp); 2147 2148 SDValue Ops[2] = { Lo, Hi }; 2149 return DAG.getMergeValues(Ops, 2, dl); 2150} 2151 2152/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 2153/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2154static SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG, 2155 const ARMSubtarget *ST) { 2156 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2157 EVT VT = Op.getValueType(); 2158 unsigned VTBits = VT.getSizeInBits(); 2159 DebugLoc dl = Op.getDebugLoc(); 2160 SDValue ShOpLo = Op.getOperand(0); 2161 SDValue ShOpHi = Op.getOperand(1); 2162 SDValue ShAmt = Op.getOperand(2); 2163 SDValue ARMCC; 2164 2165 assert(Op.getOpcode() == ISD::SHL_PARTS); 2166 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2167 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2168 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 2169 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2170 DAG.getConstant(VTBits, MVT::i32)); 2171 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 2172 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 2173 2174 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2175 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2176 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2177 ARMCC, DAG, ST->isThumb1Only(), dl); 2178 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 2179 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC, 2180 CCR, Cmp); 2181 2182 SDValue Ops[2] = { Lo, Hi }; 2183 return DAG.getMergeValues(Ops, 2, dl); 2184} 2185 2186static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 2187 const ARMSubtarget *ST) { 2188 EVT VT = N->getValueType(0); 2189 DebugLoc dl = N->getDebugLoc(); 2190 2191 // Lower vector shifts on NEON to use VSHL. 2192 if (VT.isVector()) { 2193 assert(ST->hasNEON() && "unexpected vector shift"); 2194 2195 // Left shifts translate directly to the vshiftu intrinsic. 2196 if (N->getOpcode() == ISD::SHL) 2197 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2198 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 2199 N->getOperand(0), N->getOperand(1)); 2200 2201 assert((N->getOpcode() == ISD::SRA || 2202 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 2203 2204 // NEON uses the same intrinsics for both left and right shifts. For 2205 // right shifts, the shift amounts are negative, so negate the vector of 2206 // shift amounts. 2207 EVT ShiftVT = N->getOperand(1).getValueType(); 2208 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 2209 getZeroVector(ShiftVT, DAG, dl), 2210 N->getOperand(1)); 2211 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 2212 Intrinsic::arm_neon_vshifts : 2213 Intrinsic::arm_neon_vshiftu); 2214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2215 DAG.getConstant(vshiftInt, MVT::i32), 2216 N->getOperand(0), NegatedCount); 2217 } 2218 2219 // We can get here for a node like i32 = ISD::SHL i32, i64 2220 if (VT != MVT::i64) 2221 return SDValue(); 2222 2223 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 2224 "Unknown shift to lower!"); 2225 2226 // We only lower SRA, SRL of 1 here, all others use generic lowering. 2227 if (!isa<ConstantSDNode>(N->getOperand(1)) || 2228 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 2229 return SDValue(); 2230 2231 // If we are in thumb mode, we don't have RRX. 2232 if (ST->isThumb1Only()) return SDValue(); 2233 2234 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 2235 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2236 DAG.getConstant(0, MVT::i32)); 2237 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2238 DAG.getConstant(1, MVT::i32)); 2239 2240 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 2241 // captures the result into a carry flag. 2242 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 2243 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 2244 2245 // The low part is an ARMISD::RRX operand, which shifts the carry in. 2246 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 2247 2248 // Merge the pieces into a single i64 value. 2249 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 2250} 2251 2252static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 2253 SDValue TmpOp0, TmpOp1; 2254 bool Invert = false; 2255 bool Swap = false; 2256 unsigned Opc = 0; 2257 2258 SDValue Op0 = Op.getOperand(0); 2259 SDValue Op1 = Op.getOperand(1); 2260 SDValue CC = Op.getOperand(2); 2261 EVT VT = Op.getValueType(); 2262 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 2263 DebugLoc dl = Op.getDebugLoc(); 2264 2265 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 2266 switch (SetCCOpcode) { 2267 default: llvm_unreachable("Illegal FP comparison"); break; 2268 case ISD::SETUNE: 2269 case ISD::SETNE: Invert = true; // Fallthrough 2270 case ISD::SETOEQ: 2271 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2272 case ISD::SETOLT: 2273 case ISD::SETLT: Swap = true; // Fallthrough 2274 case ISD::SETOGT: 2275 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2276 case ISD::SETOLE: 2277 case ISD::SETLE: Swap = true; // Fallthrough 2278 case ISD::SETOGE: 2279 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2280 case ISD::SETUGE: Swap = true; // Fallthrough 2281 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 2282 case ISD::SETUGT: Swap = true; // Fallthrough 2283 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 2284 case ISD::SETUEQ: Invert = true; // Fallthrough 2285 case ISD::SETONE: 2286 // Expand this to (OLT | OGT). 2287 TmpOp0 = Op0; 2288 TmpOp1 = Op1; 2289 Opc = ISD::OR; 2290 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2291 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 2292 break; 2293 case ISD::SETUO: Invert = true; // Fallthrough 2294 case ISD::SETO: 2295 // Expand this to (OLT | OGE). 2296 TmpOp0 = Op0; 2297 TmpOp1 = Op1; 2298 Opc = ISD::OR; 2299 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2300 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 2301 break; 2302 } 2303 } else { 2304 // Integer comparisons. 2305 switch (SetCCOpcode) { 2306 default: llvm_unreachable("Illegal integer comparison"); break; 2307 case ISD::SETNE: Invert = true; 2308 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2309 case ISD::SETLT: Swap = true; 2310 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2311 case ISD::SETLE: Swap = true; 2312 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2313 case ISD::SETULT: Swap = true; 2314 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 2315 case ISD::SETULE: Swap = true; 2316 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 2317 } 2318 2319 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 2320 if (Opc == ARMISD::VCEQ) { 2321 2322 SDValue AndOp; 2323 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 2324 AndOp = Op0; 2325 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 2326 AndOp = Op1; 2327 2328 // Ignore bitconvert. 2329 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) 2330 AndOp = AndOp.getOperand(0); 2331 2332 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 2333 Opc = ARMISD::VTST; 2334 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); 2335 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); 2336 Invert = !Invert; 2337 } 2338 } 2339 } 2340 2341 if (Swap) 2342 std::swap(Op0, Op1); 2343 2344 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 2345 2346 if (Invert) 2347 Result = DAG.getNOT(dl, Result, VT); 2348 2349 return Result; 2350} 2351 2352/// isVMOVSplat - Check if the specified splat value corresponds to an immediate 2353/// VMOV instruction, and if so, return the constant being splatted. 2354static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, 2355 unsigned SplatBitSize, SelectionDAG &DAG) { 2356 switch (SplatBitSize) { 2357 case 8: 2358 // Any 1-byte value is OK. 2359 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 2360 return DAG.getTargetConstant(SplatBits, MVT::i8); 2361 2362 case 16: 2363 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 2364 if ((SplatBits & ~0xff) == 0 || 2365 (SplatBits & ~0xff00) == 0) 2366 return DAG.getTargetConstant(SplatBits, MVT::i16); 2367 break; 2368 2369 case 32: 2370 // NEON's 32-bit VMOV supports splat values where: 2371 // * only one byte is nonzero, or 2372 // * the least significant byte is 0xff and the second byte is nonzero, or 2373 // * the least significant 2 bytes are 0xff and the third is nonzero. 2374 if ((SplatBits & ~0xff) == 0 || 2375 (SplatBits & ~0xff00) == 0 || 2376 (SplatBits & ~0xff0000) == 0 || 2377 (SplatBits & ~0xff000000) == 0) 2378 return DAG.getTargetConstant(SplatBits, MVT::i32); 2379 2380 if ((SplatBits & ~0xffff) == 0 && 2381 ((SplatBits | SplatUndef) & 0xff) == 0xff) 2382 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32); 2383 2384 if ((SplatBits & ~0xffffff) == 0 && 2385 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) 2386 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32); 2387 2388 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 2389 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 2390 // VMOV.I32. A (very) minor optimization would be to replicate the value 2391 // and fall through here to test for a valid 64-bit splat. But, then the 2392 // caller would also need to check and handle the change in size. 2393 break; 2394 2395 case 64: { 2396 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 2397 uint64_t BitMask = 0xff; 2398 uint64_t Val = 0; 2399 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 2400 if (((SplatBits | SplatUndef) & BitMask) == BitMask) 2401 Val |= BitMask; 2402 else if ((SplatBits & BitMask) != 0) 2403 return SDValue(); 2404 BitMask <<= 8; 2405 } 2406 return DAG.getTargetConstant(Val, MVT::i64); 2407 } 2408 2409 default: 2410 llvm_unreachable("unexpected size for isVMOVSplat"); 2411 break; 2412 } 2413 2414 return SDValue(); 2415} 2416 2417/// getVMOVImm - If this is a build_vector of constants which can be 2418/// formed by using a VMOV instruction of the specified element size, 2419/// return the constant being splatted. The ByteSize field indicates the 2420/// number of bytes of each element [1248]. 2421SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 2422 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 2423 APInt SplatBits, SplatUndef; 2424 unsigned SplatBitSize; 2425 bool HasAnyUndefs; 2426 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 2427 HasAnyUndefs, ByteSize * 8)) 2428 return SDValue(); 2429 2430 if (SplatBitSize > ByteSize * 8) 2431 return SDValue(); 2432 2433 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), 2434 SplatBitSize, DAG); 2435} 2436 2437static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 2438 bool &ReverseVEXT, unsigned &Imm) { 2439 unsigned NumElts = VT.getVectorNumElements(); 2440 ReverseVEXT = false; 2441 Imm = M[0]; 2442 2443 // If this is a VEXT shuffle, the immediate value is the index of the first 2444 // element. The other shuffle indices must be the successive elements after 2445 // the first one. 2446 unsigned ExpectedElt = Imm; 2447 for (unsigned i = 1; i < NumElts; ++i) { 2448 // Increment the expected index. If it wraps around, it may still be 2449 // a VEXT but the source vectors must be swapped. 2450 ExpectedElt += 1; 2451 if (ExpectedElt == NumElts * 2) { 2452 ExpectedElt = 0; 2453 ReverseVEXT = true; 2454 } 2455 2456 if (ExpectedElt != static_cast<unsigned>(M[i])) 2457 return false; 2458 } 2459 2460 // Adjust the index value if the source operands will be swapped. 2461 if (ReverseVEXT) 2462 Imm -= NumElts; 2463 2464 return true; 2465} 2466 2467/// isVREVMask - Check if a vector shuffle corresponds to a VREV 2468/// instruction with the specified blocksize. (The order of the elements 2469/// within each block of the vector is reversed.) 2470static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 2471 unsigned BlockSize) { 2472 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 2473 "Only possible block sizes for VREV are: 16, 32, 64"); 2474 2475 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 2476 if (EltSz == 64) 2477 return false; 2478 2479 unsigned NumElts = VT.getVectorNumElements(); 2480 unsigned BlockElts = M[0] + 1; 2481 2482 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 2483 return false; 2484 2485 for (unsigned i = 0; i < NumElts; ++i) { 2486 if ((unsigned) M[i] != 2487 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 2488 return false; 2489 } 2490 2491 return true; 2492} 2493 2494static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 2495 unsigned &WhichResult) { 2496 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 2497 if (EltSz == 64) 2498 return false; 2499 2500 unsigned NumElts = VT.getVectorNumElements(); 2501 WhichResult = (M[0] == 0 ? 0 : 1); 2502 for (unsigned i = 0; i < NumElts; i += 2) { 2503 if ((unsigned) M[i] != i + WhichResult || 2504 (unsigned) M[i+1] != i + NumElts + WhichResult) 2505 return false; 2506 } 2507 return true; 2508} 2509 2510static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 2511 unsigned &WhichResult) { 2512 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 2513 if (EltSz == 64) 2514 return false; 2515 2516 unsigned NumElts = VT.getVectorNumElements(); 2517 WhichResult = (M[0] == 0 ? 0 : 1); 2518 for (unsigned i = 0; i != NumElts; ++i) { 2519 if ((unsigned) M[i] != 2 * i + WhichResult) 2520 return false; 2521 } 2522 2523 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 2524 if (VT.is64BitVector() && EltSz == 32) 2525 return false; 2526 2527 return true; 2528} 2529 2530static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 2531 unsigned &WhichResult) { 2532 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 2533 if (EltSz == 64) 2534 return false; 2535 2536 unsigned NumElts = VT.getVectorNumElements(); 2537 WhichResult = (M[0] == 0 ? 0 : 1); 2538 unsigned Idx = WhichResult * NumElts / 2; 2539 for (unsigned i = 0; i != NumElts; i += 2) { 2540 if ((unsigned) M[i] != Idx || 2541 (unsigned) M[i+1] != Idx + NumElts) 2542 return false; 2543 Idx += 1; 2544 } 2545 2546 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 2547 if (VT.is64BitVector() && EltSz == 32) 2548 return false; 2549 2550 return true; 2551} 2552 2553static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2554 // Canonicalize all-zeros and all-ones vectors. 2555 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode()); 2556 if (ConstVal->isNullValue()) 2557 return getZeroVector(VT, DAG, dl); 2558 if (ConstVal->isAllOnesValue()) 2559 return getOnesVector(VT, DAG, dl); 2560 2561 EVT CanonicalVT; 2562 if (VT.is64BitVector()) { 2563 switch (Val.getValueType().getSizeInBits()) { 2564 case 8: CanonicalVT = MVT::v8i8; break; 2565 case 16: CanonicalVT = MVT::v4i16; break; 2566 case 32: CanonicalVT = MVT::v2i32; break; 2567 case 64: CanonicalVT = MVT::v1i64; break; 2568 default: llvm_unreachable("unexpected splat element type"); break; 2569 } 2570 } else { 2571 assert(VT.is128BitVector() && "unknown splat vector size"); 2572 switch (Val.getValueType().getSizeInBits()) { 2573 case 8: CanonicalVT = MVT::v16i8; break; 2574 case 16: CanonicalVT = MVT::v8i16; break; 2575 case 32: CanonicalVT = MVT::v4i32; break; 2576 case 64: CanonicalVT = MVT::v2i64; break; 2577 default: llvm_unreachable("unexpected splat element type"); break; 2578 } 2579 } 2580 2581 // Build a canonical splat for this value. 2582 SmallVector<SDValue, 8> Ops; 2583 Ops.assign(CanonicalVT.getVectorNumElements(), Val); 2584 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], 2585 Ops.size()); 2586 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res); 2587} 2588 2589// If this is a case we can't handle, return null and let the default 2590// expansion code take care of it. 2591static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 2592 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 2593 DebugLoc dl = Op.getDebugLoc(); 2594 EVT VT = Op.getValueType(); 2595 2596 APInt SplatBits, SplatUndef; 2597 unsigned SplatBitSize; 2598 bool HasAnyUndefs; 2599 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 2600 if (SplatBitSize <= 64) { 2601 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(), 2602 SplatUndef.getZExtValue(), SplatBitSize, DAG); 2603 if (Val.getNode()) 2604 return BuildSplat(Val, VT, DAG, dl); 2605 } 2606 } 2607 2608 // If there are only 2 elements in a 128-bit vector, insert them into an 2609 // undef vector. This handles the common case for 128-bit vector argument 2610 // passing, where the insertions should be translated to subreg accesses 2611 // with no real instructions. 2612 if (VT.is128BitVector() && Op.getNumOperands() == 2) { 2613 SDValue Val = DAG.getUNDEF(VT); 2614 SDValue Op0 = Op.getOperand(0); 2615 SDValue Op1 = Op.getOperand(1); 2616 if (Op0.getOpcode() != ISD::UNDEF) 2617 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0, 2618 DAG.getIntPtrConstant(0)); 2619 if (Op1.getOpcode() != ISD::UNDEF) 2620 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1, 2621 DAG.getIntPtrConstant(1)); 2622 return Val; 2623 } 2624 2625 return SDValue(); 2626} 2627 2628/// isShuffleMaskLegal - Targets can use this to indicate that they only 2629/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 2630/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 2631/// are assumed to be legal. 2632bool 2633ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 2634 EVT VT) const { 2635 if (VT.getVectorNumElements() == 4 && 2636 (VT.is128BitVector() || VT.is64BitVector())) { 2637 unsigned PFIndexes[4]; 2638 for (unsigned i = 0; i != 4; ++i) { 2639 if (M[i] < 0) 2640 PFIndexes[i] = 8; 2641 else 2642 PFIndexes[i] = M[i]; 2643 } 2644 2645 // Compute the index in the perfect shuffle table. 2646 unsigned PFTableIndex = 2647 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2648 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2649 unsigned Cost = (PFEntry >> 30); 2650 2651 if (Cost <= 4) 2652 return true; 2653 } 2654 2655 bool ReverseVEXT; 2656 unsigned Imm, WhichResult; 2657 2658 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 2659 isVREVMask(M, VT, 64) || 2660 isVREVMask(M, VT, 32) || 2661 isVREVMask(M, VT, 16) || 2662 isVEXTMask(M, VT, ReverseVEXT, Imm) || 2663 isVTRNMask(M, VT, WhichResult) || 2664 isVUZPMask(M, VT, WhichResult) || 2665 isVZIPMask(M, VT, WhichResult)); 2666} 2667 2668/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2669/// the specified operations to build the shuffle. 2670static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 2671 SDValue RHS, SelectionDAG &DAG, 2672 DebugLoc dl) { 2673 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2674 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2675 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2676 2677 enum { 2678 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2679 OP_VREV, 2680 OP_VDUP0, 2681 OP_VDUP1, 2682 OP_VDUP2, 2683 OP_VDUP3, 2684 OP_VEXT1, 2685 OP_VEXT2, 2686 OP_VEXT3, 2687 OP_VUZPL, // VUZP, left result 2688 OP_VUZPR, // VUZP, right result 2689 OP_VZIPL, // VZIP, left result 2690 OP_VZIPR, // VZIP, right result 2691 OP_VTRNL, // VTRN, left result 2692 OP_VTRNR // VTRN, right result 2693 }; 2694 2695 if (OpNum == OP_COPY) { 2696 if (LHSID == (1*9+2)*9+3) return LHS; 2697 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2698 return RHS; 2699 } 2700 2701 SDValue OpLHS, OpRHS; 2702 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 2703 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 2704 EVT VT = OpLHS.getValueType(); 2705 2706 switch (OpNum) { 2707 default: llvm_unreachable("Unknown shuffle opcode!"); 2708 case OP_VREV: 2709 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 2710 case OP_VDUP0: 2711 case OP_VDUP1: 2712 case OP_VDUP2: 2713 case OP_VDUP3: 2714 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 2715 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 2716 case OP_VEXT1: 2717 case OP_VEXT2: 2718 case OP_VEXT3: 2719 return DAG.getNode(ARMISD::VEXT, dl, VT, 2720 OpLHS, OpRHS, 2721 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 2722 case OP_VUZPL: 2723 case OP_VUZPR: 2724 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 2725 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 2726 case OP_VZIPL: 2727 case OP_VZIPR: 2728 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 2729 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 2730 case OP_VTRNL: 2731 case OP_VTRNR: 2732 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 2733 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 2734 } 2735} 2736 2737static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 2738 SDValue V1 = Op.getOperand(0); 2739 SDValue V2 = Op.getOperand(1); 2740 DebugLoc dl = Op.getDebugLoc(); 2741 EVT VT = Op.getValueType(); 2742 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 2743 SmallVector<int, 8> ShuffleMask; 2744 2745 // Convert shuffles that are directly supported on NEON to target-specific 2746 // DAG nodes, instead of keeping them as shuffles and matching them again 2747 // during code selection. This is more efficient and avoids the possibility 2748 // of inconsistencies between legalization and selection. 2749 // FIXME: floating-point vectors should be canonicalized to integer vectors 2750 // of the same time so that they get CSEd properly. 2751 SVN->getMask(ShuffleMask); 2752 2753 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 2754 int Lane = SVN->getSplatIndex(); 2755 // If this is undef splat, generate it via "just" vdup, if possible. 2756 if (Lane == -1) Lane = 0; 2757 2758 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 2759 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 2760 } 2761 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 2762 DAG.getConstant(Lane, MVT::i32)); 2763 } 2764 2765 bool ReverseVEXT; 2766 unsigned Imm; 2767 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 2768 if (ReverseVEXT) 2769 std::swap(V1, V2); 2770 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 2771 DAG.getConstant(Imm, MVT::i32)); 2772 } 2773 2774 if (isVREVMask(ShuffleMask, VT, 64)) 2775 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 2776 if (isVREVMask(ShuffleMask, VT, 32)) 2777 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 2778 if (isVREVMask(ShuffleMask, VT, 16)) 2779 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 2780 2781 // Check for Neon shuffles that modify both input vectors in place. 2782 // If both results are used, i.e., if there are two shuffles with the same 2783 // source operands and with masks corresponding to both results of one of 2784 // these operations, DAG memoization will ensure that a single node is 2785 // used for both shuffles. 2786 unsigned WhichResult; 2787 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 2788 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 2789 V1, V2).getValue(WhichResult); 2790 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 2791 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 2792 V1, V2).getValue(WhichResult); 2793 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 2794 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 2795 V1, V2).getValue(WhichResult); 2796 2797 // If the shuffle is not directly supported and it has 4 elements, use 2798 // the PerfectShuffle-generated table to synthesize it from other shuffles. 2799 if (VT.getVectorNumElements() == 4 && 2800 (VT.is128BitVector() || VT.is64BitVector())) { 2801 unsigned PFIndexes[4]; 2802 for (unsigned i = 0; i != 4; ++i) { 2803 if (ShuffleMask[i] < 0) 2804 PFIndexes[i] = 8; 2805 else 2806 PFIndexes[i] = ShuffleMask[i]; 2807 } 2808 2809 // Compute the index in the perfect shuffle table. 2810 unsigned PFTableIndex = 2811 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2812 2813 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2814 unsigned Cost = (PFEntry >> 30); 2815 2816 if (Cost <= 4) 2817 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 2818 } 2819 2820 return SDValue(); 2821} 2822 2823static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 2824 EVT VT = Op.getValueType(); 2825 DebugLoc dl = Op.getDebugLoc(); 2826 SDValue Vec = Op.getOperand(0); 2827 SDValue Lane = Op.getOperand(1); 2828 assert(VT == MVT::i32 && 2829 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && 2830 "unexpected type for custom-lowering vector extract"); 2831 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 2832} 2833 2834static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 2835 // The only time a CONCAT_VECTORS operation can have legal types is when 2836 // two 64-bit vectors are concatenated to a 128-bit vector. 2837 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 2838 "unexpected CONCAT_VECTORS"); 2839 DebugLoc dl = Op.getDebugLoc(); 2840 SDValue Val = DAG.getUNDEF(MVT::v2f64); 2841 SDValue Op0 = Op.getOperand(0); 2842 SDValue Op1 = Op.getOperand(1); 2843 if (Op0.getOpcode() != ISD::UNDEF) 2844 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 2845 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), 2846 DAG.getIntPtrConstant(0)); 2847 if (Op1.getOpcode() != ISD::UNDEF) 2848 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 2849 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), 2850 DAG.getIntPtrConstant(1)); 2851 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); 2852} 2853 2854SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 2855 switch (Op.getOpcode()) { 2856 default: llvm_unreachable("Don't know how to custom lower this!"); 2857 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2858 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 2859 case ISD::GlobalAddress: 2860 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 2861 LowerGlobalAddressELF(Op, DAG); 2862 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2863 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 2864 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 2865 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 2866 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 2867 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 2868 case ISD::SINT_TO_FP: 2869 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 2870 case ISD::FP_TO_SINT: 2871 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 2872 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 2873 case ISD::RETURNADDR: break; 2874 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 2875 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 2876 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2877 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 2878 case ISD::SHL: 2879 case ISD::SRL: 2880 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 2881 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG, Subtarget); 2882 case ISD::SRL_PARTS: 2883 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, Subtarget); 2884 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 2885 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2886 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2887 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 2888 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 2889 } 2890 return SDValue(); 2891} 2892 2893/// ReplaceNodeResults - Replace the results of node with an illegal result 2894/// type with new values built out of custom code. 2895void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 2896 SmallVectorImpl<SDValue>&Results, 2897 SelectionDAG &DAG) { 2898 switch (N->getOpcode()) { 2899 default: 2900 llvm_unreachable("Don't know how to custom expand this!"); 2901 return; 2902 case ISD::BIT_CONVERT: 2903 Results.push_back(ExpandBIT_CONVERT(N, DAG)); 2904 return; 2905 case ISD::SRL: 2906 case ISD::SRA: { 2907 SDValue Res = LowerShift(N, DAG, Subtarget); 2908 if (Res.getNode()) 2909 Results.push_back(Res); 2910 return; 2911 } 2912 } 2913} 2914 2915//===----------------------------------------------------------------------===// 2916// ARM Scheduler Hooks 2917//===----------------------------------------------------------------------===// 2918 2919MachineBasicBlock * 2920ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 2921 MachineBasicBlock *BB, 2922 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 2923 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2924 DebugLoc dl = MI->getDebugLoc(); 2925 switch (MI->getOpcode()) { 2926 default: 2927 llvm_unreachable("Unexpected instr type to insert"); 2928 case ARM::tMOVCCr_pseudo: { 2929 // To "insert" a SELECT_CC instruction, we actually have to insert the 2930 // diamond control-flow pattern. The incoming instruction knows the 2931 // destination vreg to set, the condition code register to branch on, the 2932 // true/false values to select between, and a branch opcode to use. 2933 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2934 MachineFunction::iterator It = BB; 2935 ++It; 2936 2937 // thisMBB: 2938 // ... 2939 // TrueVal = ... 2940 // cmpTY ccX, r1, r2 2941 // bCC copy1MBB 2942 // fallthrough --> copy0MBB 2943 MachineBasicBlock *thisMBB = BB; 2944 MachineFunction *F = BB->getParent(); 2945 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 2946 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 2947 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 2948 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 2949 F->insert(It, copy0MBB); 2950 F->insert(It, sinkMBB); 2951 // Update machine-CFG edges by first adding all successors of the current 2952 // block to the new block which will contain the Phi node for the select. 2953 // Also inform sdisel of the edge changes. 2954 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 2955 E = BB->succ_end(); I != E; ++I) { 2956 EM->insert(std::make_pair(*I, sinkMBB)); 2957 sinkMBB->addSuccessor(*I); 2958 } 2959 // Next, remove all successors of the current block, and add the true 2960 // and fallthrough blocks as its successors. 2961 while (!BB->succ_empty()) 2962 BB->removeSuccessor(BB->succ_begin()); 2963 BB->addSuccessor(copy0MBB); 2964 BB->addSuccessor(sinkMBB); 2965 2966 // copy0MBB: 2967 // %FalseValue = ... 2968 // # fallthrough to sinkMBB 2969 BB = copy0MBB; 2970 2971 // Update machine-CFG edges 2972 BB->addSuccessor(sinkMBB); 2973 2974 // sinkMBB: 2975 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2976 // ... 2977 BB = sinkMBB; 2978 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 2979 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 2980 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2981 2982 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 2983 return BB; 2984 } 2985 2986 case ARM::tANDsp: 2987 case ARM::tADDspr_: 2988 case ARM::tSUBspi_: 2989 case ARM::t2SUBrSPi_: 2990 case ARM::t2SUBrSPi12_: 2991 case ARM::t2SUBrSPs_: { 2992 MachineFunction *MF = BB->getParent(); 2993 unsigned DstReg = MI->getOperand(0).getReg(); 2994 unsigned SrcReg = MI->getOperand(1).getReg(); 2995 bool DstIsDead = MI->getOperand(0).isDead(); 2996 bool SrcIsKill = MI->getOperand(1).isKill(); 2997 2998 if (SrcReg != ARM::SP) { 2999 // Copy the source to SP from virtual register. 3000 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg); 3001 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 3002 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr; 3003 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP) 3004 .addReg(SrcReg, getKillRegState(SrcIsKill)); 3005 } 3006 3007 unsigned OpOpc = 0; 3008 bool NeedPred = false, NeedCC = false, NeedOp3 = false; 3009 switch (MI->getOpcode()) { 3010 default: 3011 llvm_unreachable("Unexpected pseudo instruction!"); 3012 case ARM::tANDsp: 3013 OpOpc = ARM::tAND; 3014 NeedPred = true; 3015 break; 3016 case ARM::tADDspr_: 3017 OpOpc = ARM::tADDspr; 3018 break; 3019 case ARM::tSUBspi_: 3020 OpOpc = ARM::tSUBspi; 3021 break; 3022 case ARM::t2SUBrSPi_: 3023 OpOpc = ARM::t2SUBrSPi; 3024 NeedPred = true; NeedCC = true; 3025 break; 3026 case ARM::t2SUBrSPi12_: 3027 OpOpc = ARM::t2SUBrSPi12; 3028 NeedPred = true; 3029 break; 3030 case ARM::t2SUBrSPs_: 3031 OpOpc = ARM::t2SUBrSPs; 3032 NeedPred = true; NeedCC = true; NeedOp3 = true; 3033 break; 3034 } 3035 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP); 3036 if (OpOpc == ARM::tAND) 3037 AddDefaultT1CC(MIB); 3038 MIB.addReg(ARM::SP); 3039 MIB.addOperand(MI->getOperand(2)); 3040 if (NeedOp3) 3041 MIB.addOperand(MI->getOperand(3)); 3042 if (NeedPred) 3043 AddDefaultPred(MIB); 3044 if (NeedCC) 3045 AddDefaultCC(MIB); 3046 3047 // Copy the result from SP to virtual register. 3048 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg); 3049 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) 3050 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr; 3051 BuildMI(BB, dl, TII->get(CopyOpc)) 3052 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) 3053 .addReg(ARM::SP); 3054 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 3055 return BB; 3056 } 3057 } 3058} 3059 3060//===----------------------------------------------------------------------===// 3061// ARM Optimization Hooks 3062//===----------------------------------------------------------------------===// 3063 3064static 3065SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 3066 TargetLowering::DAGCombinerInfo &DCI) { 3067 SelectionDAG &DAG = DCI.DAG; 3068 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3069 EVT VT = N->getValueType(0); 3070 unsigned Opc = N->getOpcode(); 3071 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 3072 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 3073 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 3074 ISD::CondCode CC = ISD::SETCC_INVALID; 3075 3076 if (isSlctCC) { 3077 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 3078 } else { 3079 SDValue CCOp = Slct.getOperand(0); 3080 if (CCOp.getOpcode() == ISD::SETCC) 3081 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 3082 } 3083 3084 bool DoXform = false; 3085 bool InvCC = false; 3086 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 3087 "Bad input!"); 3088 3089 if (LHS.getOpcode() == ISD::Constant && 3090 cast<ConstantSDNode>(LHS)->isNullValue()) { 3091 DoXform = true; 3092 } else if (CC != ISD::SETCC_INVALID && 3093 RHS.getOpcode() == ISD::Constant && 3094 cast<ConstantSDNode>(RHS)->isNullValue()) { 3095 std::swap(LHS, RHS); 3096 SDValue Op0 = Slct.getOperand(0); 3097 EVT OpVT = isSlctCC ? Op0.getValueType() : 3098 Op0.getOperand(0).getValueType(); 3099 bool isInt = OpVT.isInteger(); 3100 CC = ISD::getSetCCInverse(CC, isInt); 3101 3102 if (!TLI.isCondCodeLegal(CC, OpVT)) 3103 return SDValue(); // Inverse operator isn't legal. 3104 3105 DoXform = true; 3106 InvCC = true; 3107 } 3108 3109 if (DoXform) { 3110 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 3111 if (isSlctCC) 3112 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 3113 Slct.getOperand(0), Slct.getOperand(1), CC); 3114 SDValue CCOp = Slct.getOperand(0); 3115 if (InvCC) 3116 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 3117 CCOp.getOperand(0), CCOp.getOperand(1), CC); 3118 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3119 CCOp, OtherOp, Result); 3120 } 3121 return SDValue(); 3122} 3123 3124/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 3125static SDValue PerformADDCombine(SDNode *N, 3126 TargetLowering::DAGCombinerInfo &DCI) { 3127 // added by evan in r37685 with no testcase. 3128 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 3129 3130 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 3131 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 3132 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 3133 if (Result.getNode()) return Result; 3134 } 3135 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 3136 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 3137 if (Result.getNode()) return Result; 3138 } 3139 3140 return SDValue(); 3141} 3142 3143/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 3144static SDValue PerformSUBCombine(SDNode *N, 3145 TargetLowering::DAGCombinerInfo &DCI) { 3146 // added by evan in r37685 with no testcase. 3147 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 3148 3149 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 3150 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 3151 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 3152 if (Result.getNode()) return Result; 3153 } 3154 3155 return SDValue(); 3156} 3157 3158/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 3159static SDValue PerformFMRRDCombine(SDNode *N, 3160 TargetLowering::DAGCombinerInfo &DCI) { 3161 // fmrrd(fmdrr x, y) -> x,y 3162 SDValue InDouble = N->getOperand(0); 3163 if (InDouble.getOpcode() == ARMISD::FMDRR) 3164 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 3165 return SDValue(); 3166} 3167 3168/// getVShiftImm - Check if this is a valid build_vector for the immediate 3169/// operand of a vector shift operation, where all the elements of the 3170/// build_vector must have the same constant integer value. 3171static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 3172 // Ignore bit_converts. 3173 while (Op.getOpcode() == ISD::BIT_CONVERT) 3174 Op = Op.getOperand(0); 3175 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3176 APInt SplatBits, SplatUndef; 3177 unsigned SplatBitSize; 3178 bool HasAnyUndefs; 3179 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 3180 HasAnyUndefs, ElementBits) || 3181 SplatBitSize > ElementBits) 3182 return false; 3183 Cnt = SplatBits.getSExtValue(); 3184 return true; 3185} 3186 3187/// isVShiftLImm - Check if this is a valid build_vector for the immediate 3188/// operand of a vector shift left operation. That value must be in the range: 3189/// 0 <= Value < ElementBits for a left shift; or 3190/// 0 <= Value <= ElementBits for a long left shift. 3191static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 3192 assert(VT.isVector() && "vector shift count is not a vector type"); 3193 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 3194 if (! getVShiftImm(Op, ElementBits, Cnt)) 3195 return false; 3196 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 3197} 3198 3199/// isVShiftRImm - Check if this is a valid build_vector for the immediate 3200/// operand of a vector shift right operation. For a shift opcode, the value 3201/// is positive, but for an intrinsic the value count must be negative. The 3202/// absolute value must be in the range: 3203/// 1 <= |Value| <= ElementBits for a right shift; or 3204/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 3205static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 3206 int64_t &Cnt) { 3207 assert(VT.isVector() && "vector shift count is not a vector type"); 3208 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 3209 if (! getVShiftImm(Op, ElementBits, Cnt)) 3210 return false; 3211 if (isIntrinsic) 3212 Cnt = -Cnt; 3213 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 3214} 3215 3216/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 3217static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 3218 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 3219 switch (IntNo) { 3220 default: 3221 // Don't do anything for most intrinsics. 3222 break; 3223 3224 // Vector shifts: check for immediate versions and lower them. 3225 // Note: This is done during DAG combining instead of DAG legalizing because 3226 // the build_vectors for 64-bit vector element shift counts are generally 3227 // not legal, and it is hard to see their values after they get legalized to 3228 // loads from a constant pool. 3229 case Intrinsic::arm_neon_vshifts: 3230 case Intrinsic::arm_neon_vshiftu: 3231 case Intrinsic::arm_neon_vshiftls: 3232 case Intrinsic::arm_neon_vshiftlu: 3233 case Intrinsic::arm_neon_vshiftn: 3234 case Intrinsic::arm_neon_vrshifts: 3235 case Intrinsic::arm_neon_vrshiftu: 3236 case Intrinsic::arm_neon_vrshiftn: 3237 case Intrinsic::arm_neon_vqshifts: 3238 case Intrinsic::arm_neon_vqshiftu: 3239 case Intrinsic::arm_neon_vqshiftsu: 3240 case Intrinsic::arm_neon_vqshiftns: 3241 case Intrinsic::arm_neon_vqshiftnu: 3242 case Intrinsic::arm_neon_vqshiftnsu: 3243 case Intrinsic::arm_neon_vqrshiftns: 3244 case Intrinsic::arm_neon_vqrshiftnu: 3245 case Intrinsic::arm_neon_vqrshiftnsu: { 3246 EVT VT = N->getOperand(1).getValueType(); 3247 int64_t Cnt; 3248 unsigned VShiftOpc = 0; 3249 3250 switch (IntNo) { 3251 case Intrinsic::arm_neon_vshifts: 3252 case Intrinsic::arm_neon_vshiftu: 3253 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 3254 VShiftOpc = ARMISD::VSHL; 3255 break; 3256 } 3257 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 3258 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 3259 ARMISD::VSHRs : ARMISD::VSHRu); 3260 break; 3261 } 3262 return SDValue(); 3263 3264 case Intrinsic::arm_neon_vshiftls: 3265 case Intrinsic::arm_neon_vshiftlu: 3266 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 3267 break; 3268 llvm_unreachable("invalid shift count for vshll intrinsic"); 3269 3270 case Intrinsic::arm_neon_vrshifts: 3271 case Intrinsic::arm_neon_vrshiftu: 3272 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 3273 break; 3274 return SDValue(); 3275 3276 case Intrinsic::arm_neon_vqshifts: 3277 case Intrinsic::arm_neon_vqshiftu: 3278 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 3279 break; 3280 return SDValue(); 3281 3282 case Intrinsic::arm_neon_vqshiftsu: 3283 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 3284 break; 3285 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 3286 3287 case Intrinsic::arm_neon_vshiftn: 3288 case Intrinsic::arm_neon_vrshiftn: 3289 case Intrinsic::arm_neon_vqshiftns: 3290 case Intrinsic::arm_neon_vqshiftnu: 3291 case Intrinsic::arm_neon_vqshiftnsu: 3292 case Intrinsic::arm_neon_vqrshiftns: 3293 case Intrinsic::arm_neon_vqrshiftnu: 3294 case Intrinsic::arm_neon_vqrshiftnsu: 3295 // Narrowing shifts require an immediate right shift. 3296 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 3297 break; 3298 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic"); 3299 3300 default: 3301 llvm_unreachable("unhandled vector shift"); 3302 } 3303 3304 switch (IntNo) { 3305 case Intrinsic::arm_neon_vshifts: 3306 case Intrinsic::arm_neon_vshiftu: 3307 // Opcode already set above. 3308 break; 3309 case Intrinsic::arm_neon_vshiftls: 3310 case Intrinsic::arm_neon_vshiftlu: 3311 if (Cnt == VT.getVectorElementType().getSizeInBits()) 3312 VShiftOpc = ARMISD::VSHLLi; 3313 else 3314 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 3315 ARMISD::VSHLLs : ARMISD::VSHLLu); 3316 break; 3317 case Intrinsic::arm_neon_vshiftn: 3318 VShiftOpc = ARMISD::VSHRN; break; 3319 case Intrinsic::arm_neon_vrshifts: 3320 VShiftOpc = ARMISD::VRSHRs; break; 3321 case Intrinsic::arm_neon_vrshiftu: 3322 VShiftOpc = ARMISD::VRSHRu; break; 3323 case Intrinsic::arm_neon_vrshiftn: 3324 VShiftOpc = ARMISD::VRSHRN; break; 3325 case Intrinsic::arm_neon_vqshifts: 3326 VShiftOpc = ARMISD::VQSHLs; break; 3327 case Intrinsic::arm_neon_vqshiftu: 3328 VShiftOpc = ARMISD::VQSHLu; break; 3329 case Intrinsic::arm_neon_vqshiftsu: 3330 VShiftOpc = ARMISD::VQSHLsu; break; 3331 case Intrinsic::arm_neon_vqshiftns: 3332 VShiftOpc = ARMISD::VQSHRNs; break; 3333 case Intrinsic::arm_neon_vqshiftnu: 3334 VShiftOpc = ARMISD::VQSHRNu; break; 3335 case Intrinsic::arm_neon_vqshiftnsu: 3336 VShiftOpc = ARMISD::VQSHRNsu; break; 3337 case Intrinsic::arm_neon_vqrshiftns: 3338 VShiftOpc = ARMISD::VQRSHRNs; break; 3339 case Intrinsic::arm_neon_vqrshiftnu: 3340 VShiftOpc = ARMISD::VQRSHRNu; break; 3341 case Intrinsic::arm_neon_vqrshiftnsu: 3342 VShiftOpc = ARMISD::VQRSHRNsu; break; 3343 } 3344 3345 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 3346 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 3347 } 3348 3349 case Intrinsic::arm_neon_vshiftins: { 3350 EVT VT = N->getOperand(1).getValueType(); 3351 int64_t Cnt; 3352 unsigned VShiftOpc = 0; 3353 3354 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 3355 VShiftOpc = ARMISD::VSLI; 3356 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 3357 VShiftOpc = ARMISD::VSRI; 3358 else { 3359 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 3360 } 3361 3362 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 3363 N->getOperand(1), N->getOperand(2), 3364 DAG.getConstant(Cnt, MVT::i32)); 3365 } 3366 3367 case Intrinsic::arm_neon_vqrshifts: 3368 case Intrinsic::arm_neon_vqrshiftu: 3369 // No immediate versions of these to check for. 3370 break; 3371 } 3372 3373 return SDValue(); 3374} 3375 3376/// PerformShiftCombine - Checks for immediate versions of vector shifts and 3377/// lowers them. As with the vector shift intrinsics, this is done during DAG 3378/// combining instead of DAG legalizing because the build_vectors for 64-bit 3379/// vector element shift counts are generally not legal, and it is hard to see 3380/// their values after they get legalized to loads from a constant pool. 3381static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 3382 const ARMSubtarget *ST) { 3383 EVT VT = N->getValueType(0); 3384 3385 // Nothing to be done for scalar shifts. 3386 if (! VT.isVector()) 3387 return SDValue(); 3388 3389 assert(ST->hasNEON() && "unexpected vector shift"); 3390 int64_t Cnt; 3391 3392 switch (N->getOpcode()) { 3393 default: llvm_unreachable("unexpected shift opcode"); 3394 3395 case ISD::SHL: 3396 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 3397 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 3398 DAG.getConstant(Cnt, MVT::i32)); 3399 break; 3400 3401 case ISD::SRA: 3402 case ISD::SRL: 3403 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 3404 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 3405 ARMISD::VSHRs : ARMISD::VSHRu); 3406 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 3407 DAG.getConstant(Cnt, MVT::i32)); 3408 } 3409 } 3410 return SDValue(); 3411} 3412 3413/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 3414/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 3415static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 3416 const ARMSubtarget *ST) { 3417 SDValue N0 = N->getOperand(0); 3418 3419 // Check for sign- and zero-extensions of vector extract operations of 8- 3420 // and 16-bit vector elements. NEON supports these directly. They are 3421 // handled during DAG combining because type legalization will promote them 3422 // to 32-bit types and it is messy to recognize the operations after that. 3423 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 3424 SDValue Vec = N0.getOperand(0); 3425 SDValue Lane = N0.getOperand(1); 3426 EVT VT = N->getValueType(0); 3427 EVT EltVT = N0.getValueType(); 3428 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3429 3430 if (VT == MVT::i32 && 3431 (EltVT == MVT::i8 || EltVT == MVT::i16) && 3432 TLI.isTypeLegal(Vec.getValueType())) { 3433 3434 unsigned Opc = 0; 3435 switch (N->getOpcode()) { 3436 default: llvm_unreachable("unexpected opcode"); 3437 case ISD::SIGN_EXTEND: 3438 Opc = ARMISD::VGETLANEs; 3439 break; 3440 case ISD::ZERO_EXTEND: 3441 case ISD::ANY_EXTEND: 3442 Opc = ARMISD::VGETLANEu; 3443 break; 3444 } 3445 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 3446 } 3447 } 3448 3449 return SDValue(); 3450} 3451 3452SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 3453 DAGCombinerInfo &DCI) const { 3454 switch (N->getOpcode()) { 3455 default: break; 3456 case ISD::ADD: return PerformADDCombine(N, DCI); 3457 case ISD::SUB: return PerformSUBCombine(N, DCI); 3458 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 3459 case ISD::INTRINSIC_WO_CHAIN: 3460 return PerformIntrinsicCombine(N, DCI.DAG); 3461 case ISD::SHL: 3462 case ISD::SRA: 3463 case ISD::SRL: 3464 return PerformShiftCombine(N, DCI.DAG, Subtarget); 3465 case ISD::SIGN_EXTEND: 3466 case ISD::ZERO_EXTEND: 3467 case ISD::ANY_EXTEND: 3468 return PerformExtendCombine(N, DCI.DAG, Subtarget); 3469 } 3470 return SDValue(); 3471} 3472 3473bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 3474 if (!Subtarget->hasV6Ops()) 3475 // Pre-v6 does not support unaligned mem access. 3476 return false; 3477 else if (!Subtarget->hasV6Ops()) { 3478 // v6 may or may not support unaligned mem access. 3479 if (!Subtarget->isTargetDarwin()) 3480 return false; 3481 } 3482 3483 switch (VT.getSimpleVT().SimpleTy) { 3484 default: 3485 return false; 3486 case MVT::i8: 3487 case MVT::i16: 3488 case MVT::i32: 3489 return true; 3490 // FIXME: VLD1 etc with standard alignment is legal. 3491 } 3492} 3493 3494static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 3495 if (V < 0) 3496 return false; 3497 3498 unsigned Scale = 1; 3499 switch (VT.getSimpleVT().SimpleTy) { 3500 default: return false; 3501 case MVT::i1: 3502 case MVT::i8: 3503 // Scale == 1; 3504 break; 3505 case MVT::i16: 3506 // Scale == 2; 3507 Scale = 2; 3508 break; 3509 case MVT::i32: 3510 // Scale == 4; 3511 Scale = 4; 3512 break; 3513 } 3514 3515 if ((V & (Scale - 1)) != 0) 3516 return false; 3517 V /= Scale; 3518 return V == (V & ((1LL << 5) - 1)); 3519} 3520 3521static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 3522 const ARMSubtarget *Subtarget) { 3523 bool isNeg = false; 3524 if (V < 0) { 3525 isNeg = true; 3526 V = - V; 3527 } 3528 3529 switch (VT.getSimpleVT().SimpleTy) { 3530 default: return false; 3531 case MVT::i1: 3532 case MVT::i8: 3533 case MVT::i16: 3534 case MVT::i32: 3535 // + imm12 or - imm8 3536 if (isNeg) 3537 return V == (V & ((1LL << 8) - 1)); 3538 return V == (V & ((1LL << 12) - 1)); 3539 case MVT::f32: 3540 case MVT::f64: 3541 // Same as ARM mode. FIXME: NEON? 3542 if (!Subtarget->hasVFP2()) 3543 return false; 3544 if ((V & 3) != 0) 3545 return false; 3546 V >>= 2; 3547 return V == (V & ((1LL << 8) - 1)); 3548 } 3549} 3550 3551/// isLegalAddressImmediate - Return true if the integer value can be used 3552/// as the offset of the target addressing mode for load / store of the 3553/// given type. 3554static bool isLegalAddressImmediate(int64_t V, EVT VT, 3555 const ARMSubtarget *Subtarget) { 3556 if (V == 0) 3557 return true; 3558 3559 if (!VT.isSimple()) 3560 return false; 3561 3562 if (Subtarget->isThumb1Only()) 3563 return isLegalT1AddressImmediate(V, VT); 3564 else if (Subtarget->isThumb2()) 3565 return isLegalT2AddressImmediate(V, VT, Subtarget); 3566 3567 // ARM mode. 3568 if (V < 0) 3569 V = - V; 3570 switch (VT.getSimpleVT().SimpleTy) { 3571 default: return false; 3572 case MVT::i1: 3573 case MVT::i8: 3574 case MVT::i32: 3575 // +- imm12 3576 return V == (V & ((1LL << 12) - 1)); 3577 case MVT::i16: 3578 // +- imm8 3579 return V == (V & ((1LL << 8) - 1)); 3580 case MVT::f32: 3581 case MVT::f64: 3582 if (!Subtarget->hasVFP2()) // FIXME: NEON? 3583 return false; 3584 if ((V & 3) != 0) 3585 return false; 3586 V >>= 2; 3587 return V == (V & ((1LL << 8) - 1)); 3588 } 3589} 3590 3591bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 3592 EVT VT) const { 3593 int Scale = AM.Scale; 3594 if (Scale < 0) 3595 return false; 3596 3597 switch (VT.getSimpleVT().SimpleTy) { 3598 default: return false; 3599 case MVT::i1: 3600 case MVT::i8: 3601 case MVT::i16: 3602 case MVT::i32: 3603 if (Scale == 1) 3604 return true; 3605 // r + r << imm 3606 Scale = Scale & ~1; 3607 return Scale == 2 || Scale == 4 || Scale == 8; 3608 case MVT::i64: 3609 // r + r 3610 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 3611 return true; 3612 return false; 3613 case MVT::isVoid: 3614 // Note, we allow "void" uses (basically, uses that aren't loads or 3615 // stores), because arm allows folding a scale into many arithmetic 3616 // operations. This should be made more precise and revisited later. 3617 3618 // Allow r << imm, but the imm has to be a multiple of two. 3619 if (Scale & 1) return false; 3620 return isPowerOf2_32(Scale); 3621 } 3622} 3623 3624/// isLegalAddressingMode - Return true if the addressing mode represented 3625/// by AM is legal for this target, for a load/store of the specified type. 3626bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3627 const Type *Ty) const { 3628 EVT VT = getValueType(Ty, true); 3629 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 3630 return false; 3631 3632 // Can never fold addr of global into load/store. 3633 if (AM.BaseGV) 3634 return false; 3635 3636 switch (AM.Scale) { 3637 case 0: // no scale reg, must be "r+i" or "r", or "i". 3638 break; 3639 case 1: 3640 if (Subtarget->isThumb1Only()) 3641 return false; 3642 // FALL THROUGH. 3643 default: 3644 // ARM doesn't support any R+R*scale+imm addr modes. 3645 if (AM.BaseOffs) 3646 return false; 3647 3648 if (!VT.isSimple()) 3649 return false; 3650 3651 if (Subtarget->isThumb2()) 3652 return isLegalT2ScaledAddressingMode(AM, VT); 3653 3654 int Scale = AM.Scale; 3655 switch (VT.getSimpleVT().SimpleTy) { 3656 default: return false; 3657 case MVT::i1: 3658 case MVT::i8: 3659 case MVT::i32: 3660 if (Scale < 0) Scale = -Scale; 3661 if (Scale == 1) 3662 return true; 3663 // r + r << imm 3664 return isPowerOf2_32(Scale & ~1); 3665 case MVT::i16: 3666 case MVT::i64: 3667 // r + r 3668 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 3669 return true; 3670 return false; 3671 3672 case MVT::isVoid: 3673 // Note, we allow "void" uses (basically, uses that aren't loads or 3674 // stores), because arm allows folding a scale into many arithmetic 3675 // operations. This should be made more precise and revisited later. 3676 3677 // Allow r << imm, but the imm has to be a multiple of two. 3678 if (Scale & 1) return false; 3679 return isPowerOf2_32(Scale); 3680 } 3681 break; 3682 } 3683 return true; 3684} 3685 3686static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 3687 bool isSEXTLoad, SDValue &Base, 3688 SDValue &Offset, bool &isInc, 3689 SelectionDAG &DAG) { 3690 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 3691 return false; 3692 3693 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 3694 // AddressingMode 3 3695 Base = Ptr->getOperand(0); 3696 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 3697 int RHSC = (int)RHS->getZExtValue(); 3698 if (RHSC < 0 && RHSC > -256) { 3699 assert(Ptr->getOpcode() == ISD::ADD); 3700 isInc = false; 3701 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 3702 return true; 3703 } 3704 } 3705 isInc = (Ptr->getOpcode() == ISD::ADD); 3706 Offset = Ptr->getOperand(1); 3707 return true; 3708 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 3709 // AddressingMode 2 3710 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 3711 int RHSC = (int)RHS->getZExtValue(); 3712 if (RHSC < 0 && RHSC > -0x1000) { 3713 assert(Ptr->getOpcode() == ISD::ADD); 3714 isInc = false; 3715 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 3716 Base = Ptr->getOperand(0); 3717 return true; 3718 } 3719 } 3720 3721 if (Ptr->getOpcode() == ISD::ADD) { 3722 isInc = true; 3723 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 3724 if (ShOpcVal != ARM_AM::no_shift) { 3725 Base = Ptr->getOperand(1); 3726 Offset = Ptr->getOperand(0); 3727 } else { 3728 Base = Ptr->getOperand(0); 3729 Offset = Ptr->getOperand(1); 3730 } 3731 return true; 3732 } 3733 3734 isInc = (Ptr->getOpcode() == ISD::ADD); 3735 Base = Ptr->getOperand(0); 3736 Offset = Ptr->getOperand(1); 3737 return true; 3738 } 3739 3740 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 3741 return false; 3742} 3743 3744static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 3745 bool isSEXTLoad, SDValue &Base, 3746 SDValue &Offset, bool &isInc, 3747 SelectionDAG &DAG) { 3748 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 3749 return false; 3750 3751 Base = Ptr->getOperand(0); 3752 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 3753 int RHSC = (int)RHS->getZExtValue(); 3754 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 3755 assert(Ptr->getOpcode() == ISD::ADD); 3756 isInc = false; 3757 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 3758 return true; 3759 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 3760 isInc = Ptr->getOpcode() == ISD::ADD; 3761 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 3762 return true; 3763 } 3764 } 3765 3766 return false; 3767} 3768 3769/// getPreIndexedAddressParts - returns true by value, base pointer and 3770/// offset pointer and addressing mode by reference if the node's address 3771/// can be legally represented as pre-indexed load / store address. 3772bool 3773ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 3774 SDValue &Offset, 3775 ISD::MemIndexedMode &AM, 3776 SelectionDAG &DAG) const { 3777 if (Subtarget->isThumb1Only()) 3778 return false; 3779 3780 EVT VT; 3781 SDValue Ptr; 3782 bool isSEXTLoad = false; 3783 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3784 Ptr = LD->getBasePtr(); 3785 VT = LD->getMemoryVT(); 3786 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 3787 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3788 Ptr = ST->getBasePtr(); 3789 VT = ST->getMemoryVT(); 3790 } else 3791 return false; 3792 3793 bool isInc; 3794 bool isLegal = false; 3795 if (Subtarget->isThumb2()) 3796 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 3797 Offset, isInc, DAG); 3798 else 3799 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 3800 Offset, isInc, DAG); 3801 if (!isLegal) 3802 return false; 3803 3804 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 3805 return true; 3806} 3807 3808/// getPostIndexedAddressParts - returns true by value, base pointer and 3809/// offset pointer and addressing mode by reference if this node can be 3810/// combined with a load / store to form a post-indexed load / store. 3811bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 3812 SDValue &Base, 3813 SDValue &Offset, 3814 ISD::MemIndexedMode &AM, 3815 SelectionDAG &DAG) const { 3816 if (Subtarget->isThumb1Only()) 3817 return false; 3818 3819 EVT VT; 3820 SDValue Ptr; 3821 bool isSEXTLoad = false; 3822 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3823 VT = LD->getMemoryVT(); 3824 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 3825 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3826 VT = ST->getMemoryVT(); 3827 } else 3828 return false; 3829 3830 bool isInc; 3831 bool isLegal = false; 3832 if (Subtarget->isThumb2()) 3833 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 3834 isInc, DAG); 3835 else 3836 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 3837 isInc, DAG); 3838 if (!isLegal) 3839 return false; 3840 3841 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 3842 return true; 3843} 3844 3845void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 3846 const APInt &Mask, 3847 APInt &KnownZero, 3848 APInt &KnownOne, 3849 const SelectionDAG &DAG, 3850 unsigned Depth) const { 3851 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 3852 switch (Op.getOpcode()) { 3853 default: break; 3854 case ARMISD::CMOV: { 3855 // Bits are known zero/one if known on the LHS and RHS. 3856 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 3857 if (KnownZero == 0 && KnownOne == 0) return; 3858 3859 APInt KnownZeroRHS, KnownOneRHS; 3860 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 3861 KnownZeroRHS, KnownOneRHS, Depth+1); 3862 KnownZero &= KnownZeroRHS; 3863 KnownOne &= KnownOneRHS; 3864 return; 3865 } 3866 } 3867} 3868 3869//===----------------------------------------------------------------------===// 3870// ARM Inline Assembly Support 3871//===----------------------------------------------------------------------===// 3872 3873/// getConstraintType - Given a constraint letter, return the type of 3874/// constraint it is for this target. 3875ARMTargetLowering::ConstraintType 3876ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 3877 if (Constraint.size() == 1) { 3878 switch (Constraint[0]) { 3879 default: break; 3880 case 'l': return C_RegisterClass; 3881 case 'w': return C_RegisterClass; 3882 } 3883 } 3884 return TargetLowering::getConstraintType(Constraint); 3885} 3886 3887std::pair<unsigned, const TargetRegisterClass*> 3888ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3889 EVT VT) const { 3890 if (Constraint.size() == 1) { 3891 // GCC RS6000 Constraint Letters 3892 switch (Constraint[0]) { 3893 case 'l': 3894 if (Subtarget->isThumb1Only()) 3895 return std::make_pair(0U, ARM::tGPRRegisterClass); 3896 else 3897 return std::make_pair(0U, ARM::GPRRegisterClass); 3898 case 'r': 3899 return std::make_pair(0U, ARM::GPRRegisterClass); 3900 case 'w': 3901 if (VT == MVT::f32) 3902 return std::make_pair(0U, ARM::SPRRegisterClass); 3903 if (VT == MVT::f64) 3904 return std::make_pair(0U, ARM::DPRRegisterClass); 3905 break; 3906 } 3907 } 3908 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3909} 3910 3911std::vector<unsigned> ARMTargetLowering:: 3912getRegClassForInlineAsmConstraint(const std::string &Constraint, 3913 EVT VT) const { 3914 if (Constraint.size() != 1) 3915 return std::vector<unsigned>(); 3916 3917 switch (Constraint[0]) { // GCC ARM Constraint Letters 3918 default: break; 3919 case 'l': 3920 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 3921 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 3922 0); 3923 case 'r': 3924 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 3925 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 3926 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 3927 ARM::R12, ARM::LR, 0); 3928 case 'w': 3929 if (VT == MVT::f32) 3930 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 3931 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 3932 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 3933 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 3934 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 3935 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 3936 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 3937 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 3938 if (VT == MVT::f64) 3939 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 3940 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 3941 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 3942 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 3943 break; 3944 } 3945 3946 return std::vector<unsigned>(); 3947} 3948 3949/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3950/// vector. If it is invalid, don't add anything to Ops. 3951void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3952 char Constraint, 3953 bool hasMemory, 3954 std::vector<SDValue>&Ops, 3955 SelectionDAG &DAG) const { 3956 SDValue Result(0, 0); 3957 3958 switch (Constraint) { 3959 default: break; 3960 case 'I': case 'J': case 'K': case 'L': 3961 case 'M': case 'N': case 'O': 3962 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 3963 if (!C) 3964 return; 3965 3966 int64_t CVal64 = C->getSExtValue(); 3967 int CVal = (int) CVal64; 3968 // None of these constraints allow values larger than 32 bits. Check 3969 // that the value fits in an int. 3970 if (CVal != CVal64) 3971 return; 3972 3973 switch (Constraint) { 3974 case 'I': 3975 if (Subtarget->isThumb1Only()) { 3976 // This must be a constant between 0 and 255, for ADD 3977 // immediates. 3978 if (CVal >= 0 && CVal <= 255) 3979 break; 3980 } else if (Subtarget->isThumb2()) { 3981 // A constant that can be used as an immediate value in a 3982 // data-processing instruction. 3983 if (ARM_AM::getT2SOImmVal(CVal) != -1) 3984 break; 3985 } else { 3986 // A constant that can be used as an immediate value in a 3987 // data-processing instruction. 3988 if (ARM_AM::getSOImmVal(CVal) != -1) 3989 break; 3990 } 3991 return; 3992 3993 case 'J': 3994 if (Subtarget->isThumb()) { // FIXME thumb2 3995 // This must be a constant between -255 and -1, for negated ADD 3996 // immediates. This can be used in GCC with an "n" modifier that 3997 // prints the negated value, for use with SUB instructions. It is 3998 // not useful otherwise but is implemented for compatibility. 3999 if (CVal >= -255 && CVal <= -1) 4000 break; 4001 } else { 4002 // This must be a constant between -4095 and 4095. It is not clear 4003 // what this constraint is intended for. Implemented for 4004 // compatibility with GCC. 4005 if (CVal >= -4095 && CVal <= 4095) 4006 break; 4007 } 4008 return; 4009 4010 case 'K': 4011 if (Subtarget->isThumb1Only()) { 4012 // A 32-bit value where only one byte has a nonzero value. Exclude 4013 // zero to match GCC. This constraint is used by GCC internally for 4014 // constants that can be loaded with a move/shift combination. 4015 // It is not useful otherwise but is implemented for compatibility. 4016 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 4017 break; 4018 } else if (Subtarget->isThumb2()) { 4019 // A constant whose bitwise inverse can be used as an immediate 4020 // value in a data-processing instruction. This can be used in GCC 4021 // with a "B" modifier that prints the inverted value, for use with 4022 // BIC and MVN instructions. It is not useful otherwise but is 4023 // implemented for compatibility. 4024 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 4025 break; 4026 } else { 4027 // A constant whose bitwise inverse can be used as an immediate 4028 // value in a data-processing instruction. This can be used in GCC 4029 // with a "B" modifier that prints the inverted value, for use with 4030 // BIC and MVN instructions. It is not useful otherwise but is 4031 // implemented for compatibility. 4032 if (ARM_AM::getSOImmVal(~CVal) != -1) 4033 break; 4034 } 4035 return; 4036 4037 case 'L': 4038 if (Subtarget->isThumb1Only()) { 4039 // This must be a constant between -7 and 7, 4040 // for 3-operand ADD/SUB immediate instructions. 4041 if (CVal >= -7 && CVal < 7) 4042 break; 4043 } else if (Subtarget->isThumb2()) { 4044 // A constant whose negation can be used as an immediate value in a 4045 // data-processing instruction. This can be used in GCC with an "n" 4046 // modifier that prints the negated value, for use with SUB 4047 // instructions. It is not useful otherwise but is implemented for 4048 // compatibility. 4049 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 4050 break; 4051 } else { 4052 // A constant whose negation can be used as an immediate value in a 4053 // data-processing instruction. This can be used in GCC with an "n" 4054 // modifier that prints the negated value, for use with SUB 4055 // instructions. It is not useful otherwise but is implemented for 4056 // compatibility. 4057 if (ARM_AM::getSOImmVal(-CVal) != -1) 4058 break; 4059 } 4060 return; 4061 4062 case 'M': 4063 if (Subtarget->isThumb()) { // FIXME thumb2 4064 // This must be a multiple of 4 between 0 and 1020, for 4065 // ADD sp + immediate. 4066 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 4067 break; 4068 } else { 4069 // A power of two or a constant between 0 and 32. This is used in 4070 // GCC for the shift amount on shifted register operands, but it is 4071 // useful in general for any shift amounts. 4072 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 4073 break; 4074 } 4075 return; 4076 4077 case 'N': 4078 if (Subtarget->isThumb()) { // FIXME thumb2 4079 // This must be a constant between 0 and 31, for shift amounts. 4080 if (CVal >= 0 && CVal <= 31) 4081 break; 4082 } 4083 return; 4084 4085 case 'O': 4086 if (Subtarget->isThumb()) { // FIXME thumb2 4087 // This must be a multiple of 4 between -508 and 508, for 4088 // ADD/SUB sp = sp + immediate. 4089 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 4090 break; 4091 } 4092 return; 4093 } 4094 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 4095 break; 4096 } 4097 4098 if (Result.getNode()) { 4099 Ops.push_back(Result); 4100 return; 4101 } 4102 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 4103 Ops, DAG); 4104} 4105 4106bool 4107ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4108 // The ARM target isn't yet aware of offsets. 4109 return false; 4110} 4111 4112int ARM::getVFPf32Imm(const APFloat &FPImm) { 4113 APInt Imm = FPImm.bitcastToAPInt(); 4114 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 4115 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 4116 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 4117 4118 // We can handle 4 bits of mantissa. 4119 // mantissa = (16+UInt(e:f:g:h))/16. 4120 if (Mantissa & 0x7ffff) 4121 return -1; 4122 Mantissa >>= 19; 4123 if ((Mantissa & 0xf) != Mantissa) 4124 return -1; 4125 4126 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 4127 if (Exp < -3 || Exp > 4) 4128 return -1; 4129 Exp = ((Exp+3) & 0x7) ^ 4; 4130 4131 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 4132} 4133 4134int ARM::getVFPf64Imm(const APFloat &FPImm) { 4135 APInt Imm = FPImm.bitcastToAPInt(); 4136 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 4137 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 4138 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL; 4139 4140 // We can handle 4 bits of mantissa. 4141 // mantissa = (16+UInt(e:f:g:h))/16. 4142 if (Mantissa & 0xffffffffffffLL) 4143 return -1; 4144 Mantissa >>= 48; 4145 if ((Mantissa & 0xf) != Mantissa) 4146 return -1; 4147 4148 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 4149 if (Exp < -3 || Exp > 4) 4150 return -1; 4151 Exp = ((Exp+3) & 0x7) ^ 4; 4152 4153 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 4154} 4155 4156/// isFPImmLegal - Returns true if the target can instruction select the 4157/// specified FP immediate natively. If false, the legalizer will 4158/// materialize the FP immediate as a load from a constant pool. 4159bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4160 if (!Subtarget->hasVFP3()) 4161 return false; 4162 if (VT == MVT::f32) 4163 return ARM::getVFPf32Imm(Imm) != -1; 4164 if (VT == MVT::f64) 4165 return ARM::getVFPf64Imm(Imm) != -1; 4166 return false; 4167} 4168