ARMISelLowering.cpp revision 575cd148cedec66af0adc266c5d7ecdbe1641d7e
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMCallingConv.h" 19#include "ARMConstantPoolValue.h" 20#include "ARMISelLowering.h" 21#include "ARMMachineFunctionInfo.h" 22#include "ARMPerfectShuffle.h" 23#include "ARMRegisterInfo.h" 24#include "ARMSubtarget.h" 25#include "ARMTargetMachine.h" 26#include "ARMTargetObjectFile.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/MachineBasicBlock.h" 37#include "llvm/CodeGen/MachineFrameInfo.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/PseudoSourceValue.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/MC/MCSectionMachO.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/ADT/Statistic.h" 47#include "llvm/Support/CommandLine.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Support/raw_ostream.h" 51#include <sstream> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// This option should go away when tail calls fully work. 57static cl::opt<bool> 58EnableARMTailCalls("arm-tail-calls", cl::Hidden, 59 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 60 cl::init(false)); 61 62static cl::opt<bool> 63EnableARMLongCalls("arm-long-calls", cl::Hidden, 64 cl::desc("Generate calls via indirect call instructions"), 65 cl::init(false)); 66 67static cl::opt<bool> 68ARMInterworking("arm-interworking", cl::Hidden, 69 cl::desc("Enable / disable ARM interworking (for debugging only)"), 70 cl::init(true)); 71 72void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 73 EVT PromotedBitwiseVT) { 74 if (VT != PromotedLdStVT) { 75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 77 PromotedLdStVT.getSimpleVT()); 78 79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 81 PromotedLdStVT.getSimpleVT()); 82 } 83 84 EVT ElemTy = VT.getVectorElementType(); 85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); 87 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) 88 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 89 if (ElemTy != MVT::i32) { 90 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 91 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 92 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 93 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 94 } 95 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 96 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 97 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 98 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); 99 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 100 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 101 if (VT.isInteger()) { 102 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 103 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 104 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 105 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 106 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 107 } 108 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 109 110 // Promote all bit-wise operations. 111 if (VT.isInteger() && VT != PromotedBitwiseVT) { 112 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 113 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 114 PromotedBitwiseVT.getSimpleVT()); 115 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 116 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 117 PromotedBitwiseVT.getSimpleVT()); 118 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 119 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 120 PromotedBitwiseVT.getSimpleVT()); 121 } 122 123 // Neon does not support vector divide/remainder operations. 124 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 125 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 126 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 127 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 128 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 129 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 130} 131 132void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 133 addRegisterClass(VT, ARM::DPRRegisterClass); 134 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 135} 136 137void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 138 addRegisterClass(VT, ARM::QPRRegisterClass); 139 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 140} 141 142static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 143 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 144 return new TargetLoweringObjectFileMachO(); 145 146 return new ARMElfTargetObjectFile(); 147} 148 149ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 150 : TargetLowering(TM, createTLOF(TM)) { 151 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 152 RegInfo = TM.getRegisterInfo(); 153 Itins = TM.getInstrItineraryData(); 154 155 if (Subtarget->isTargetDarwin()) { 156 // Uses VFP for Thumb libfuncs if available. 157 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 158 // Single-precision floating-point arithmetic. 159 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 160 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 161 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 162 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 163 164 // Double-precision floating-point arithmetic. 165 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 166 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 167 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 168 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 169 170 // Single-precision comparisons. 171 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 172 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 173 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 174 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 175 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 176 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 177 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 178 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 179 180 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 181 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 182 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 183 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 184 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 185 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 186 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 187 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 188 189 // Double-precision comparisons. 190 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 191 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 192 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 193 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 194 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 195 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 196 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 197 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 198 199 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 200 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 201 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 202 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 203 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 204 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 205 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 206 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 207 208 // Floating-point to integer conversions. 209 // i64 conversions are done via library routines even when generating VFP 210 // instructions, so use the same ones. 211 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 212 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 213 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 214 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 215 216 // Conversions between floating types. 217 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 218 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 219 220 // Integer to floating-point conversions. 221 // i64 conversions are done via library routines even when generating VFP 222 // instructions, so use the same ones. 223 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 224 // e.g., __floatunsidf vs. __floatunssidfvfp. 225 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 226 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 227 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 228 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 229 } 230 } 231 232 // These libcalls are not available in 32-bit. 233 setLibcallName(RTLIB::SHL_I128, 0); 234 setLibcallName(RTLIB::SRL_I128, 0); 235 setLibcallName(RTLIB::SRA_I128, 0); 236 237 if (Subtarget->isAAPCS_ABI()) { 238 // Double-precision floating-point arithmetic helper functions 239 // RTABI chapter 4.1.2, Table 2 240 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 241 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 242 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 243 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 244 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 245 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 246 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 247 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 248 249 // Double-precision floating-point comparison helper functions 250 // RTABI chapter 4.1.2, Table 3 251 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 252 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 253 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 254 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 255 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 256 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 257 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 258 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 259 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 260 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 261 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 262 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 263 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 264 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 265 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 266 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 267 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 268 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 269 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 270 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 271 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 272 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 273 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 275 276 // Single-precision floating-point arithmetic helper functions 277 // RTABI chapter 4.1.2, Table 4 278 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 279 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 280 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 281 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 282 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 283 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 284 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 285 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 286 287 // Single-precision floating-point comparison helper functions 288 // RTABI chapter 4.1.2, Table 5 289 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 290 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 291 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 292 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 293 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 294 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 295 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 296 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 297 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 298 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 299 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 300 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 301 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 302 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 303 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 304 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 305 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 306 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 307 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 308 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 309 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 310 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 311 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 313 314 // Floating-point to integer conversions. 315 // RTABI chapter 4.1.2, Table 6 316 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 317 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 318 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 319 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 320 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 321 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 322 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 323 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 324 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 325 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 326 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 327 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 328 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 329 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 330 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 331 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 332 333 // Conversions between floating types. 334 // RTABI chapter 4.1.2, Table 7 335 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 336 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 337 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 339 340 // Integer to floating-point conversions. 341 // RTABI chapter 4.1.2, Table 8 342 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 343 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 344 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 345 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 346 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 347 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 348 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 349 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 350 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 351 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 352 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 353 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 358 359 // Long long helper functions 360 // RTABI chapter 4.2, Table 9 361 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 362 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 363 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 364 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 365 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 366 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 367 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 368 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 369 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 370 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 371 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 372 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 373 374 // Integer division functions 375 // RTABI chapter 4.3.1 376 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 377 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 378 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 379 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 380 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 381 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 382 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 387 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 388 } 389 390 if (Subtarget->isThumb1Only()) 391 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 392 else 393 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 394 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 395 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 396 if (!Subtarget->isFPOnlySP()) 397 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 398 399 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 400 } 401 402 if (Subtarget->hasNEON()) { 403 addDRTypeForNEON(MVT::v2f32); 404 addDRTypeForNEON(MVT::v8i8); 405 addDRTypeForNEON(MVT::v4i16); 406 addDRTypeForNEON(MVT::v2i32); 407 addDRTypeForNEON(MVT::v1i64); 408 409 addQRTypeForNEON(MVT::v4f32); 410 addQRTypeForNEON(MVT::v2f64); 411 addQRTypeForNEON(MVT::v16i8); 412 addQRTypeForNEON(MVT::v8i16); 413 addQRTypeForNEON(MVT::v4i32); 414 addQRTypeForNEON(MVT::v2i64); 415 416 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 417 // neither Neon nor VFP support any arithmetic operations on it. 418 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 419 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 420 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 421 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 422 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 423 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 424 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand); 425 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 426 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 427 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 428 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 429 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 430 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 431 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 432 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 433 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 434 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 435 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 436 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 437 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 438 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 439 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 440 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 441 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 442 443 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 444 445 // Neon does not support some operations on v1i64 and v2i64 types. 446 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 447 // Custom handling for some quad-vector types to detect VMULL. 448 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 449 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 450 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 451 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); 452 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); 453 454 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 455 setTargetDAGCombine(ISD::SHL); 456 setTargetDAGCombine(ISD::SRL); 457 setTargetDAGCombine(ISD::SRA); 458 setTargetDAGCombine(ISD::SIGN_EXTEND); 459 setTargetDAGCombine(ISD::ZERO_EXTEND); 460 setTargetDAGCombine(ISD::ANY_EXTEND); 461 setTargetDAGCombine(ISD::SELECT_CC); 462 setTargetDAGCombine(ISD::BUILD_VECTOR); 463 } 464 465 computeRegisterProperties(); 466 467 // ARM does not have f32 extending load. 468 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 469 470 // ARM does not have i1 sign extending load. 471 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 472 473 // ARM supports all 4 flavors of integer indexed load / store. 474 if (!Subtarget->isThumb1Only()) { 475 for (unsigned im = (unsigned)ISD::PRE_INC; 476 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 477 setIndexedLoadAction(im, MVT::i1, Legal); 478 setIndexedLoadAction(im, MVT::i8, Legal); 479 setIndexedLoadAction(im, MVT::i16, Legal); 480 setIndexedLoadAction(im, MVT::i32, Legal); 481 setIndexedStoreAction(im, MVT::i1, Legal); 482 setIndexedStoreAction(im, MVT::i8, Legal); 483 setIndexedStoreAction(im, MVT::i16, Legal); 484 setIndexedStoreAction(im, MVT::i32, Legal); 485 } 486 } 487 488 // i64 operation support. 489 if (Subtarget->isThumb1Only()) { 490 setOperationAction(ISD::MUL, MVT::i64, Expand); 491 setOperationAction(ISD::MULHU, MVT::i32, Expand); 492 setOperationAction(ISD::MULHS, MVT::i32, Expand); 493 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 494 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 495 } else { 496 setOperationAction(ISD::MUL, MVT::i64, Expand); 497 setOperationAction(ISD::MULHU, MVT::i32, Expand); 498 if (!Subtarget->hasV6Ops()) 499 setOperationAction(ISD::MULHS, MVT::i32, Expand); 500 } 501 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 502 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 503 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 504 setOperationAction(ISD::SRL, MVT::i64, Custom); 505 setOperationAction(ISD::SRA, MVT::i64, Custom); 506 507 // ARM does not have ROTL. 508 setOperationAction(ISD::ROTL, MVT::i32, Expand); 509 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 510 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 511 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 512 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 513 514 // Only ARMv6 has BSWAP. 515 if (!Subtarget->hasV6Ops()) 516 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 517 518 // These are expanded into libcalls. 519 if (!Subtarget->hasDivide()) { 520 // v7M has a hardware divider 521 setOperationAction(ISD::SDIV, MVT::i32, Expand); 522 setOperationAction(ISD::UDIV, MVT::i32, Expand); 523 } 524 setOperationAction(ISD::SREM, MVT::i32, Expand); 525 setOperationAction(ISD::UREM, MVT::i32, Expand); 526 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 527 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 528 529 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 530 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 531 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 532 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 533 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 534 535 setOperationAction(ISD::TRAP, MVT::Other, Legal); 536 537 // Use the default implementation. 538 setOperationAction(ISD::VASTART, MVT::Other, Custom); 539 setOperationAction(ISD::VAARG, MVT::Other, Expand); 540 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 541 setOperationAction(ISD::VAEND, MVT::Other, Expand); 542 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 543 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 545 // FIXME: Shouldn't need this, since no register is used, but the legalizer 546 // doesn't yet know how to not do that for SjLj. 547 setExceptionSelectorRegister(ARM::R0); 548 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 549 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 550 // the default expansion. 551 if (Subtarget->hasDataBarrier() || 552 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) { 553 // membarrier needs custom lowering; the rest are legal and handled 554 // normally. 555 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 556 } else { 557 // Set them all for expansion, which will force libcalls. 558 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 559 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand); 560 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand); 561 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 562 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand); 563 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand); 564 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 565 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand); 566 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand); 567 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 568 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand); 569 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand); 570 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 571 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand); 572 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand); 573 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 574 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand); 575 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand); 576 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 577 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand); 578 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand); 579 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 580 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand); 581 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand); 582 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 583 // Since the libcalls include locking, fold in the fences 584 setShouldFoldAtomicFences(true); 585 } 586 // 64-bit versions are always libcalls (for now) 587 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand); 588 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand); 589 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand); 590 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand); 591 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand); 592 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand); 593 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); 594 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); 595 596 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 597 if (!Subtarget->hasV6Ops()) { 598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 599 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 600 } 601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 602 603 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 604 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 605 // iff target supports vfp2. 606 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 607 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 608 } 609 610 // We want to custom lower some of our intrinsics. 611 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 612 if (Subtarget->isTargetDarwin()) { 613 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 614 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 615 } 616 617 setOperationAction(ISD::SETCC, MVT::i32, Expand); 618 setOperationAction(ISD::SETCC, MVT::f32, Expand); 619 setOperationAction(ISD::SETCC, MVT::f64, Expand); 620 setOperationAction(ISD::SELECT, MVT::i32, Custom); 621 setOperationAction(ISD::SELECT, MVT::f32, Custom); 622 setOperationAction(ISD::SELECT, MVT::f64, Custom); 623 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 624 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 625 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 626 627 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 628 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 629 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 630 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 631 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 632 633 // We don't support sin/cos/fmod/copysign/pow 634 setOperationAction(ISD::FSIN, MVT::f64, Expand); 635 setOperationAction(ISD::FSIN, MVT::f32, Expand); 636 setOperationAction(ISD::FCOS, MVT::f32, Expand); 637 setOperationAction(ISD::FCOS, MVT::f64, Expand); 638 setOperationAction(ISD::FREM, MVT::f64, Expand); 639 setOperationAction(ISD::FREM, MVT::f32, Expand); 640 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 643 } 644 setOperationAction(ISD::FPOW, MVT::f64, Expand); 645 setOperationAction(ISD::FPOW, MVT::f32, Expand); 646 647 // Various VFP goodness 648 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 649 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 650 if (Subtarget->hasVFP2()) { 651 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 652 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 653 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 654 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 655 } 656 // Special handling for half-precision FP. 657 if (!Subtarget->hasFP16()) { 658 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 659 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 660 } 661 } 662 663 // We have target-specific dag combine patterns for the following nodes: 664 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 665 setTargetDAGCombine(ISD::ADD); 666 setTargetDAGCombine(ISD::SUB); 667 setTargetDAGCombine(ISD::MUL); 668 669 if (Subtarget->hasV6T2Ops()) 670 setTargetDAGCombine(ISD::OR); 671 672 setStackPointerRegisterToSaveRestore(ARM::SP); 673 674 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 675 setSchedulingPreference(Sched::RegPressure); 676 else 677 setSchedulingPreference(Sched::Hybrid); 678 679 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 680 681 // On ARM arguments smaller than 4 bytes are extended, so all arguments 682 // are at least 4 bytes aligned. 683 setMinStackArgumentAlignment(4); 684 685 benefitFromCodePlacementOpt = true; 686} 687 688std::pair<const TargetRegisterClass*, uint8_t> 689ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 690 const TargetRegisterClass *RRC = 0; 691 uint8_t Cost = 1; 692 switch (VT.getSimpleVT().SimpleTy) { 693 default: 694 return TargetLowering::findRepresentativeClass(VT); 695 // Use DPR as representative register class for all floating point 696 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 697 // the cost is 1 for both f32 and f64. 698 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 699 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 700 RRC = ARM::DPRRegisterClass; 701 break; 702 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 703 case MVT::v4f32: case MVT::v2f64: 704 RRC = ARM::DPRRegisterClass; 705 Cost = 2; 706 break; 707 case MVT::v4i64: 708 RRC = ARM::DPRRegisterClass; 709 Cost = 4; 710 break; 711 case MVT::v8i64: 712 RRC = ARM::DPRRegisterClass; 713 Cost = 8; 714 break; 715 } 716 return std::make_pair(RRC, Cost); 717} 718 719const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 720 switch (Opcode) { 721 default: return 0; 722 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 723 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 724 case ARMISD::CALL: return "ARMISD::CALL"; 725 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 726 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 727 case ARMISD::tCALL: return "ARMISD::tCALL"; 728 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 729 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 730 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 731 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 732 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 733 case ARMISD::CMP: return "ARMISD::CMP"; 734 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 735 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 736 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 737 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 738 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 739 case ARMISD::CMOV: return "ARMISD::CMOV"; 740 case ARMISD::CNEG: return "ARMISD::CNEG"; 741 742 case ARMISD::RBIT: return "ARMISD::RBIT"; 743 744 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 745 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 746 case ARMISD::SITOF: return "ARMISD::SITOF"; 747 case ARMISD::UITOF: return "ARMISD::UITOF"; 748 749 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 750 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 751 case ARMISD::RRX: return "ARMISD::RRX"; 752 753 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 754 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 755 756 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 757 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 758 759 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 760 761 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 762 763 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 764 765 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 766 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER"; 767 768 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 769 case ARMISD::VCGE: return "ARMISD::VCGE"; 770 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 771 case ARMISD::VCGT: return "ARMISD::VCGT"; 772 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 773 case ARMISD::VTST: return "ARMISD::VTST"; 774 775 case ARMISD::VSHL: return "ARMISD::VSHL"; 776 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 777 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 778 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 779 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 780 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 781 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 782 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 783 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 784 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 785 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 786 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 787 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 788 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 789 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 790 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 791 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 792 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 793 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 794 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 795 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 796 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 797 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 798 case ARMISD::VDUP: return "ARMISD::VDUP"; 799 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 800 case ARMISD::VEXT: return "ARMISD::VEXT"; 801 case ARMISD::VREV64: return "ARMISD::VREV64"; 802 case ARMISD::VREV32: return "ARMISD::VREV32"; 803 case ARMISD::VREV16: return "ARMISD::VREV16"; 804 case ARMISD::VZIP: return "ARMISD::VZIP"; 805 case ARMISD::VUZP: return "ARMISD::VUZP"; 806 case ARMISD::VTRN: return "ARMISD::VTRN"; 807 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 808 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 809 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 810 case ARMISD::FMAX: return "ARMISD::FMAX"; 811 case ARMISD::FMIN: return "ARMISD::FMIN"; 812 case ARMISD::BFI: return "ARMISD::BFI"; 813 } 814} 815 816/// getRegClassFor - Return the register class that should be used for the 817/// specified value type. 818TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 819 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 820 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 821 // load / store 4 to 8 consecutive D registers. 822 if (Subtarget->hasNEON()) { 823 if (VT == MVT::v4i64) 824 return ARM::QQPRRegisterClass; 825 else if (VT == MVT::v8i64) 826 return ARM::QQQQPRRegisterClass; 827 } 828 return TargetLowering::getRegClassFor(VT); 829} 830 831// Create a fast isel object. 832FastISel * 833ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 834 return ARM::createFastISel(funcInfo); 835} 836 837/// getFunctionAlignment - Return the Log2 alignment of this function. 838unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { 839 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2; 840} 841 842/// getMaximalGlobalOffset - Returns the maximal possible offset which can 843/// be used for loads / stores from the global. 844unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 845 return (Subtarget->isThumb1Only() ? 127 : 4095); 846} 847 848Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 849 unsigned NumVals = N->getNumValues(); 850 if (!NumVals) 851 return Sched::RegPressure; 852 853 for (unsigned i = 0; i != NumVals; ++i) { 854 EVT VT = N->getValueType(i); 855 if (VT.isFloatingPoint() || VT.isVector()) 856 return Sched::Latency; 857 } 858 859 if (!N->isMachineOpcode()) 860 return Sched::RegPressure; 861 862 // Load are scheduled for latency even if there instruction itinerary 863 // is not available. 864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 865 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 866 if (TID.mayLoad()) 867 return Sched::Latency; 868 869 if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2) 870 return Sched::Latency; 871 return Sched::RegPressure; 872} 873 874unsigned 875ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, 876 MachineFunction &MF) const { 877 switch (RC->getID()) { 878 default: 879 return 0; 880 case ARM::tGPRRegClassID: 881 return RegInfo->hasFP(MF) ? 4 : 5; 882 case ARM::GPRRegClassID: { 883 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0; 884 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0); 885 } 886 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 887 case ARM::DPRRegClassID: 888 return 32 - 10; 889 } 890} 891 892//===----------------------------------------------------------------------===// 893// Lowering Code 894//===----------------------------------------------------------------------===// 895 896/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 897static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 898 switch (CC) { 899 default: llvm_unreachable("Unknown condition code!"); 900 case ISD::SETNE: return ARMCC::NE; 901 case ISD::SETEQ: return ARMCC::EQ; 902 case ISD::SETGT: return ARMCC::GT; 903 case ISD::SETGE: return ARMCC::GE; 904 case ISD::SETLT: return ARMCC::LT; 905 case ISD::SETLE: return ARMCC::LE; 906 case ISD::SETUGT: return ARMCC::HI; 907 case ISD::SETUGE: return ARMCC::HS; 908 case ISD::SETULT: return ARMCC::LO; 909 case ISD::SETULE: return ARMCC::LS; 910 } 911} 912 913/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 914static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 915 ARMCC::CondCodes &CondCode2) { 916 CondCode2 = ARMCC::AL; 917 switch (CC) { 918 default: llvm_unreachable("Unknown FP condition!"); 919 case ISD::SETEQ: 920 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 921 case ISD::SETGT: 922 case ISD::SETOGT: CondCode = ARMCC::GT; break; 923 case ISD::SETGE: 924 case ISD::SETOGE: CondCode = ARMCC::GE; break; 925 case ISD::SETOLT: CondCode = ARMCC::MI; break; 926 case ISD::SETOLE: CondCode = ARMCC::LS; break; 927 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 928 case ISD::SETO: CondCode = ARMCC::VC; break; 929 case ISD::SETUO: CondCode = ARMCC::VS; break; 930 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 931 case ISD::SETUGT: CondCode = ARMCC::HI; break; 932 case ISD::SETUGE: CondCode = ARMCC::PL; break; 933 case ISD::SETLT: 934 case ISD::SETULT: CondCode = ARMCC::LT; break; 935 case ISD::SETLE: 936 case ISD::SETULE: CondCode = ARMCC::LE; break; 937 case ISD::SETNE: 938 case ISD::SETUNE: CondCode = ARMCC::NE; break; 939 } 940} 941 942//===----------------------------------------------------------------------===// 943// Calling Convention Implementation 944//===----------------------------------------------------------------------===// 945 946#include "ARMGenCallingConv.inc" 947 948/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 949/// given CallingConvention value. 950CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 951 bool Return, 952 bool isVarArg) const { 953 switch (CC) { 954 default: 955 llvm_unreachable("Unsupported calling convention"); 956 case CallingConv::C: 957 case CallingConv::Fast: 958 // Use target triple & subtarget features to do actual dispatch. 959 if (Subtarget->isAAPCS_ABI()) { 960 if (Subtarget->hasVFP2() && 961 FloatABIType == FloatABI::Hard && !isVarArg) 962 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 963 else 964 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 965 } else 966 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 967 case CallingConv::ARM_AAPCS_VFP: 968 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 969 case CallingConv::ARM_AAPCS: 970 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 971 case CallingConv::ARM_APCS: 972 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 973 } 974} 975 976/// LowerCallResult - Lower the result values of a call into the 977/// appropriate copies out of appropriate physical registers. 978SDValue 979ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 980 CallingConv::ID CallConv, bool isVarArg, 981 const SmallVectorImpl<ISD::InputArg> &Ins, 982 DebugLoc dl, SelectionDAG &DAG, 983 SmallVectorImpl<SDValue> &InVals) const { 984 985 // Assign locations to each value returned by this call. 986 SmallVector<CCValAssign, 16> RVLocs; 987 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 988 RVLocs, *DAG.getContext()); 989 CCInfo.AnalyzeCallResult(Ins, 990 CCAssignFnForNode(CallConv, /* Return*/ true, 991 isVarArg)); 992 993 // Copy all of the result registers out of their specified physreg. 994 for (unsigned i = 0; i != RVLocs.size(); ++i) { 995 CCValAssign VA = RVLocs[i]; 996 997 SDValue Val; 998 if (VA.needsCustom()) { 999 // Handle f64 or half of a v2f64. 1000 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1001 InFlag); 1002 Chain = Lo.getValue(1); 1003 InFlag = Lo.getValue(2); 1004 VA = RVLocs[++i]; // skip ahead to next loc 1005 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1006 InFlag); 1007 Chain = Hi.getValue(1); 1008 InFlag = Hi.getValue(2); 1009 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1010 1011 if (VA.getLocVT() == MVT::v2f64) { 1012 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1013 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1014 DAG.getConstant(0, MVT::i32)); 1015 1016 VA = RVLocs[++i]; // skip ahead to next loc 1017 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1018 Chain = Lo.getValue(1); 1019 InFlag = Lo.getValue(2); 1020 VA = RVLocs[++i]; // skip ahead to next loc 1021 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1022 Chain = Hi.getValue(1); 1023 InFlag = Hi.getValue(2); 1024 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1025 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1026 DAG.getConstant(1, MVT::i32)); 1027 } 1028 } else { 1029 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1030 InFlag); 1031 Chain = Val.getValue(1); 1032 InFlag = Val.getValue(2); 1033 } 1034 1035 switch (VA.getLocInfo()) { 1036 default: llvm_unreachable("Unknown loc info!"); 1037 case CCValAssign::Full: break; 1038 case CCValAssign::BCvt: 1039 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); 1040 break; 1041 } 1042 1043 InVals.push_back(Val); 1044 } 1045 1046 return Chain; 1047} 1048 1049/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1050/// by "Src" to address "Dst" of size "Size". Alignment information is 1051/// specified by the specific parameter attribute. The copy will be passed as 1052/// a byval function parameter. 1053/// Sometimes what we are copying is the end of a larger object, the part that 1054/// does not fit in registers. 1055static SDValue 1056CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1057 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1058 DebugLoc dl) { 1059 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1060 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1061 /*isVolatile=*/false, /*AlwaysInline=*/false, 1062 MachinePointerInfo(0), MachinePointerInfo(0)); 1063} 1064 1065/// LowerMemOpCallTo - Store the argument to the stack. 1066SDValue 1067ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1068 SDValue StackPtr, SDValue Arg, 1069 DebugLoc dl, SelectionDAG &DAG, 1070 const CCValAssign &VA, 1071 ISD::ArgFlagsTy Flags) const { 1072 unsigned LocMemOffset = VA.getLocMemOffset(); 1073 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1074 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1075 if (Flags.isByVal()) 1076 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1077 1078 return DAG.getStore(Chain, dl, Arg, PtrOff, 1079 MachinePointerInfo::getStack(LocMemOffset), 1080 false, false, 0); 1081} 1082 1083void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1084 SDValue Chain, SDValue &Arg, 1085 RegsToPassVector &RegsToPass, 1086 CCValAssign &VA, CCValAssign &NextVA, 1087 SDValue &StackPtr, 1088 SmallVector<SDValue, 8> &MemOpChains, 1089 ISD::ArgFlagsTy Flags) const { 1090 1091 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1092 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1093 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1094 1095 if (NextVA.isRegLoc()) 1096 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1097 else { 1098 assert(NextVA.isMemLoc()); 1099 if (StackPtr.getNode() == 0) 1100 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1101 1102 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1103 dl, DAG, NextVA, 1104 Flags)); 1105 } 1106} 1107 1108/// LowerCall - Lowering a call into a callseq_start <- 1109/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1110/// nodes. 1111SDValue 1112ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1113 CallingConv::ID CallConv, bool isVarArg, 1114 bool &isTailCall, 1115 const SmallVectorImpl<ISD::OutputArg> &Outs, 1116 const SmallVectorImpl<SDValue> &OutVals, 1117 const SmallVectorImpl<ISD::InputArg> &Ins, 1118 DebugLoc dl, SelectionDAG &DAG, 1119 SmallVectorImpl<SDValue> &InVals) const { 1120 MachineFunction &MF = DAG.getMachineFunction(); 1121 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1122 bool IsSibCall = false; 1123 // Temporarily disable tail calls so things don't break. 1124 if (!EnableARMTailCalls) 1125 isTailCall = false; 1126 if (isTailCall) { 1127 // Check if it's really possible to do a tail call. 1128 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1129 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1130 Outs, OutVals, Ins, DAG); 1131 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1132 // detected sibcalls. 1133 if (isTailCall) { 1134 ++NumTailCalls; 1135 IsSibCall = true; 1136 } 1137 } 1138 1139 // Analyze operands of the call, assigning locations to each operand. 1140 SmallVector<CCValAssign, 16> ArgLocs; 1141 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1142 *DAG.getContext()); 1143 CCInfo.AnalyzeCallOperands(Outs, 1144 CCAssignFnForNode(CallConv, /* Return*/ false, 1145 isVarArg)); 1146 1147 // Get a count of how many bytes are to be pushed on the stack. 1148 unsigned NumBytes = CCInfo.getNextStackOffset(); 1149 1150 // For tail calls, memory operands are available in our caller's stack. 1151 if (IsSibCall) 1152 NumBytes = 0; 1153 1154 // Adjust the stack pointer for the new arguments... 1155 // These operations are automatically eliminated by the prolog/epilog pass 1156 if (!IsSibCall) 1157 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1158 1159 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1160 1161 RegsToPassVector RegsToPass; 1162 SmallVector<SDValue, 8> MemOpChains; 1163 1164 // Walk the register/memloc assignments, inserting copies/loads. In the case 1165 // of tail call optimization, arguments are handled later. 1166 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1167 i != e; 1168 ++i, ++realArgIdx) { 1169 CCValAssign &VA = ArgLocs[i]; 1170 SDValue Arg = OutVals[realArgIdx]; 1171 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1172 1173 // Promote the value if needed. 1174 switch (VA.getLocInfo()) { 1175 default: llvm_unreachable("Unknown loc info!"); 1176 case CCValAssign::Full: break; 1177 case CCValAssign::SExt: 1178 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1179 break; 1180 case CCValAssign::ZExt: 1181 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1182 break; 1183 case CCValAssign::AExt: 1184 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1185 break; 1186 case CCValAssign::BCvt: 1187 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1188 break; 1189 } 1190 1191 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1192 if (VA.needsCustom()) { 1193 if (VA.getLocVT() == MVT::v2f64) { 1194 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1195 DAG.getConstant(0, MVT::i32)); 1196 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1197 DAG.getConstant(1, MVT::i32)); 1198 1199 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1200 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1201 1202 VA = ArgLocs[++i]; // skip ahead to next loc 1203 if (VA.isRegLoc()) { 1204 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1205 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1206 } else { 1207 assert(VA.isMemLoc()); 1208 1209 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1210 dl, DAG, VA, Flags)); 1211 } 1212 } else { 1213 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1214 StackPtr, MemOpChains, Flags); 1215 } 1216 } else if (VA.isRegLoc()) { 1217 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1218 } else if (!IsSibCall) { 1219 assert(VA.isMemLoc()); 1220 1221 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1222 dl, DAG, VA, Flags)); 1223 } 1224 } 1225 1226 if (!MemOpChains.empty()) 1227 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1228 &MemOpChains[0], MemOpChains.size()); 1229 1230 // Build a sequence of copy-to-reg nodes chained together with token chain 1231 // and flag operands which copy the outgoing args into the appropriate regs. 1232 SDValue InFlag; 1233 // Tail call byval lowering might overwrite argument registers so in case of 1234 // tail call optimization the copies to registers are lowered later. 1235 if (!isTailCall) 1236 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1237 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1238 RegsToPass[i].second, InFlag); 1239 InFlag = Chain.getValue(1); 1240 } 1241 1242 // For tail calls lower the arguments to the 'real' stack slot. 1243 if (isTailCall) { 1244 // Force all the incoming stack arguments to be loaded from the stack 1245 // before any new outgoing arguments are stored to the stack, because the 1246 // outgoing stack slots may alias the incoming argument stack slots, and 1247 // the alias isn't otherwise explicit. This is slightly more conservative 1248 // than necessary, because it means that each store effectively depends 1249 // on every argument instead of just those arguments it would clobber. 1250 1251 // Do not flag preceeding copytoreg stuff together with the following stuff. 1252 InFlag = SDValue(); 1253 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1254 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1255 RegsToPass[i].second, InFlag); 1256 InFlag = Chain.getValue(1); 1257 } 1258 InFlag =SDValue(); 1259 } 1260 1261 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1262 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1263 // node so that legalize doesn't hack it. 1264 bool isDirect = false; 1265 bool isARMFunc = false; 1266 bool isLocalARMFunc = false; 1267 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1268 1269 if (EnableARMLongCalls) { 1270 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1271 && "long-calls with non-static relocation model!"); 1272 // Handle a global address or an external symbol. If it's not one of 1273 // those, the target's already in a register, so we don't need to do 1274 // anything extra. 1275 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1276 const GlobalValue *GV = G->getGlobal(); 1277 // Create a constant pool entry for the callee address 1278 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1279 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1280 ARMPCLabelIndex, 1281 ARMCP::CPValue, 0); 1282 // Get the address of the callee into a register 1283 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1284 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1285 Callee = DAG.getLoad(getPointerTy(), dl, 1286 DAG.getEntryNode(), CPAddr, 1287 MachinePointerInfo::getConstantPool(), 1288 false, false, 0); 1289 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1290 const char *Sym = S->getSymbol(); 1291 1292 // Create a constant pool entry for the callee address 1293 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1294 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1295 Sym, ARMPCLabelIndex, 0); 1296 // Get the address of the callee into a register 1297 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1298 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1299 Callee = DAG.getLoad(getPointerTy(), dl, 1300 DAG.getEntryNode(), CPAddr, 1301 MachinePointerInfo::getConstantPool(), 1302 false, false, 0); 1303 } 1304 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1305 const GlobalValue *GV = G->getGlobal(); 1306 isDirect = true; 1307 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1308 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1309 getTargetMachine().getRelocationModel() != Reloc::Static; 1310 isARMFunc = !Subtarget->isThumb() || isStub; 1311 // ARM call to a local ARM function is predicable. 1312 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1313 // tBX takes a register source operand. 1314 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1315 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1316 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, 1317 ARMPCLabelIndex, 1318 ARMCP::CPValue, 4); 1319 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1320 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1321 Callee = DAG.getLoad(getPointerTy(), dl, 1322 DAG.getEntryNode(), CPAddr, 1323 MachinePointerInfo::getConstantPool(), 1324 false, false, 0); 1325 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1326 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1327 getPointerTy(), Callee, PICLabel); 1328 } else { 1329 // On ELF targets for PIC code, direct calls should go through the PLT 1330 unsigned OpFlags = 0; 1331 if (Subtarget->isTargetELF() && 1332 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1333 OpFlags = ARMII::MO_PLT; 1334 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1335 } 1336 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1337 isDirect = true; 1338 bool isStub = Subtarget->isTargetDarwin() && 1339 getTargetMachine().getRelocationModel() != Reloc::Static; 1340 isARMFunc = !Subtarget->isThumb() || isStub; 1341 // tBX takes a register source operand. 1342 const char *Sym = S->getSymbol(); 1343 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1344 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1345 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1346 Sym, ARMPCLabelIndex, 4); 1347 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1348 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1349 Callee = DAG.getLoad(getPointerTy(), dl, 1350 DAG.getEntryNode(), CPAddr, 1351 MachinePointerInfo::getConstantPool(), 1352 false, false, 0); 1353 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1354 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1355 getPointerTy(), Callee, PICLabel); 1356 } else { 1357 unsigned OpFlags = 0; 1358 // On ELF targets for PIC code, direct calls should go through the PLT 1359 if (Subtarget->isTargetELF() && 1360 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1361 OpFlags = ARMII::MO_PLT; 1362 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1363 } 1364 } 1365 1366 // FIXME: handle tail calls differently. 1367 unsigned CallOpc; 1368 if (Subtarget->isThumb()) { 1369 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1370 CallOpc = ARMISD::CALL_NOLINK; 1371 else 1372 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1373 } else { 1374 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1375 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1376 : ARMISD::CALL_NOLINK; 1377 } 1378 1379 std::vector<SDValue> Ops; 1380 Ops.push_back(Chain); 1381 Ops.push_back(Callee); 1382 1383 // Add argument registers to the end of the list so that they are known live 1384 // into the call. 1385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1386 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1387 RegsToPass[i].second.getValueType())); 1388 1389 if (InFlag.getNode()) 1390 Ops.push_back(InFlag); 1391 1392 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1393 if (isTailCall) 1394 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1395 1396 // Returns a chain and a flag for retval copy to use. 1397 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1398 InFlag = Chain.getValue(1); 1399 1400 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1401 DAG.getIntPtrConstant(0, true), InFlag); 1402 if (!Ins.empty()) 1403 InFlag = Chain.getValue(1); 1404 1405 // Handle result values, copying them out of physregs into vregs that we 1406 // return. 1407 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1408 dl, DAG, InVals); 1409} 1410 1411/// MatchingStackOffset - Return true if the given stack call argument is 1412/// already available in the same position (relatively) of the caller's 1413/// incoming argument stack. 1414static 1415bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1416 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1417 const ARMInstrInfo *TII) { 1418 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1419 int FI = INT_MAX; 1420 if (Arg.getOpcode() == ISD::CopyFromReg) { 1421 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1422 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 1423 return false; 1424 MachineInstr *Def = MRI->getVRegDef(VR); 1425 if (!Def) 1426 return false; 1427 if (!Flags.isByVal()) { 1428 if (!TII->isLoadFromStackSlot(Def, FI)) 1429 return false; 1430 } else { 1431 return false; 1432 } 1433 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1434 if (Flags.isByVal()) 1435 // ByVal argument is passed in as a pointer but it's now being 1436 // dereferenced. e.g. 1437 // define @foo(%struct.X* %A) { 1438 // tail call @bar(%struct.X* byval %A) 1439 // } 1440 return false; 1441 SDValue Ptr = Ld->getBasePtr(); 1442 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1443 if (!FINode) 1444 return false; 1445 FI = FINode->getIndex(); 1446 } else 1447 return false; 1448 1449 assert(FI != INT_MAX); 1450 if (!MFI->isFixedObjectIndex(FI)) 1451 return false; 1452 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1453} 1454 1455/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1456/// for tail call optimization. Targets which want to do tail call 1457/// optimization should implement this function. 1458bool 1459ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1460 CallingConv::ID CalleeCC, 1461 bool isVarArg, 1462 bool isCalleeStructRet, 1463 bool isCallerStructRet, 1464 const SmallVectorImpl<ISD::OutputArg> &Outs, 1465 const SmallVectorImpl<SDValue> &OutVals, 1466 const SmallVectorImpl<ISD::InputArg> &Ins, 1467 SelectionDAG& DAG) const { 1468 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1469 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1470 bool CCMatch = CallerCC == CalleeCC; 1471 1472 // Look for obvious safe cases to perform tail call optimization that do not 1473 // require ABI changes. This is what gcc calls sibcall. 1474 1475 // Do not sibcall optimize vararg calls unless the call site is not passing 1476 // any arguments. 1477 if (isVarArg && !Outs.empty()) 1478 return false; 1479 1480 // Also avoid sibcall optimization if either caller or callee uses struct 1481 // return semantics. 1482 if (isCalleeStructRet || isCallerStructRet) 1483 return false; 1484 1485 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1486 // emitEpilogue is not ready for them. 1487 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1488 // LR. This means if we need to reload LR, it takes an extra instructions, 1489 // which outweighs the value of the tail call; but here we don't know yet 1490 // whether LR is going to be used. Probably the right approach is to 1491 // generate the tail call here and turn it back into CALL/RET in 1492 // emitEpilogue if LR is used. 1493 if (Subtarget->isThumb1Only()) 1494 return false; 1495 1496 // For the moment, we can only do this to functions defined in this 1497 // compilation, or to indirect calls. A Thumb B to an ARM function, 1498 // or vice versa, is not easily fixed up in the linker unlike BL. 1499 // (We could do this by loading the address of the callee into a register; 1500 // that is an extra instruction over the direct call and burns a register 1501 // as well, so is not likely to be a win.) 1502 1503 // It might be safe to remove this restriction on non-Darwin. 1504 1505 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1506 // but we need to make sure there are enough registers; the only valid 1507 // registers are the 4 used for parameters. We don't currently do this 1508 // case. 1509 if (isa<ExternalSymbolSDNode>(Callee)) 1510 return false; 1511 1512 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1513 const GlobalValue *GV = G->getGlobal(); 1514 if (GV->isDeclaration() || GV->isWeakForLinker()) 1515 return false; 1516 } 1517 1518 // If the calling conventions do not match, then we'd better make sure the 1519 // results are returned in the same way as what the caller expects. 1520 if (!CCMatch) { 1521 SmallVector<CCValAssign, 16> RVLocs1; 1522 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 1523 RVLocs1, *DAG.getContext()); 1524 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1525 1526 SmallVector<CCValAssign, 16> RVLocs2; 1527 CCState CCInfo2(CallerCC, false, getTargetMachine(), 1528 RVLocs2, *DAG.getContext()); 1529 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1530 1531 if (RVLocs1.size() != RVLocs2.size()) 1532 return false; 1533 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1534 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1535 return false; 1536 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1537 return false; 1538 if (RVLocs1[i].isRegLoc()) { 1539 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1540 return false; 1541 } else { 1542 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1543 return false; 1544 } 1545 } 1546 } 1547 1548 // If the callee takes no arguments then go on to check the results of the 1549 // call. 1550 if (!Outs.empty()) { 1551 // Check if stack adjustment is needed. For now, do not do this if any 1552 // argument is passed on the stack. 1553 SmallVector<CCValAssign, 16> ArgLocs; 1554 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 1555 ArgLocs, *DAG.getContext()); 1556 CCInfo.AnalyzeCallOperands(Outs, 1557 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1558 if (CCInfo.getNextStackOffset()) { 1559 MachineFunction &MF = DAG.getMachineFunction(); 1560 1561 // Check if the arguments are already laid out in the right way as 1562 // the caller's fixed stack objects. 1563 MachineFrameInfo *MFI = MF.getFrameInfo(); 1564 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1565 const ARMInstrInfo *TII = 1566 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1567 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1568 i != e; 1569 ++i, ++realArgIdx) { 1570 CCValAssign &VA = ArgLocs[i]; 1571 EVT RegVT = VA.getLocVT(); 1572 SDValue Arg = OutVals[realArgIdx]; 1573 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1574 if (VA.getLocInfo() == CCValAssign::Indirect) 1575 return false; 1576 if (VA.needsCustom()) { 1577 // f64 and vector types are split into multiple registers or 1578 // register/stack-slot combinations. The types will not match 1579 // the registers; give up on memory f64 refs until we figure 1580 // out what to do about this. 1581 if (!VA.isRegLoc()) 1582 return false; 1583 if (!ArgLocs[++i].isRegLoc()) 1584 return false; 1585 if (RegVT == MVT::v2f64) { 1586 if (!ArgLocs[++i].isRegLoc()) 1587 return false; 1588 if (!ArgLocs[++i].isRegLoc()) 1589 return false; 1590 } 1591 } else if (!VA.isRegLoc()) { 1592 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1593 MFI, MRI, TII)) 1594 return false; 1595 } 1596 } 1597 } 1598 } 1599 1600 return true; 1601} 1602 1603SDValue 1604ARMTargetLowering::LowerReturn(SDValue Chain, 1605 CallingConv::ID CallConv, bool isVarArg, 1606 const SmallVectorImpl<ISD::OutputArg> &Outs, 1607 const SmallVectorImpl<SDValue> &OutVals, 1608 DebugLoc dl, SelectionDAG &DAG) const { 1609 1610 // CCValAssign - represent the assignment of the return value to a location. 1611 SmallVector<CCValAssign, 16> RVLocs; 1612 1613 // CCState - Info about the registers and stack slots. 1614 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 1615 *DAG.getContext()); 1616 1617 // Analyze outgoing return values. 1618 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1619 isVarArg)); 1620 1621 // If this is the first return lowered for this function, add 1622 // the regs to the liveout set for the function. 1623 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1624 for (unsigned i = 0; i != RVLocs.size(); ++i) 1625 if (RVLocs[i].isRegLoc()) 1626 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1627 } 1628 1629 SDValue Flag; 1630 1631 // Copy the result values into the output registers. 1632 for (unsigned i = 0, realRVLocIdx = 0; 1633 i != RVLocs.size(); 1634 ++i, ++realRVLocIdx) { 1635 CCValAssign &VA = RVLocs[i]; 1636 assert(VA.isRegLoc() && "Can only return in registers!"); 1637 1638 SDValue Arg = OutVals[realRVLocIdx]; 1639 1640 switch (VA.getLocInfo()) { 1641 default: llvm_unreachable("Unknown loc info!"); 1642 case CCValAssign::Full: break; 1643 case CCValAssign::BCvt: 1644 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 1645 break; 1646 } 1647 1648 if (VA.needsCustom()) { 1649 if (VA.getLocVT() == MVT::v2f64) { 1650 // Extract the first half and return it in two registers. 1651 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1652 DAG.getConstant(0, MVT::i32)); 1653 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1654 DAG.getVTList(MVT::i32, MVT::i32), Half); 1655 1656 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1657 Flag = Chain.getValue(1); 1658 VA = RVLocs[++i]; // skip ahead to next loc 1659 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1660 HalfGPRs.getValue(1), Flag); 1661 Flag = Chain.getValue(1); 1662 VA = RVLocs[++i]; // skip ahead to next loc 1663 1664 // Extract the 2nd half and fall through to handle it as an f64 value. 1665 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1666 DAG.getConstant(1, MVT::i32)); 1667 } 1668 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1669 // available. 1670 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1671 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1672 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1673 Flag = Chain.getValue(1); 1674 VA = RVLocs[++i]; // skip ahead to next loc 1675 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1676 Flag); 1677 } else 1678 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1679 1680 // Guarantee that all emitted copies are 1681 // stuck together, avoiding something bad. 1682 Flag = Chain.getValue(1); 1683 } 1684 1685 SDValue result; 1686 if (Flag.getNode()) 1687 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1688 else // Return Void 1689 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1690 1691 return result; 1692} 1693 1694// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1695// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1696// one of the above mentioned nodes. It has to be wrapped because otherwise 1697// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1698// be used to form addressing mode. These wrapped nodes will be selected 1699// into MOVi. 1700static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1701 EVT PtrVT = Op.getValueType(); 1702 // FIXME there is no actual debug info here 1703 DebugLoc dl = Op.getDebugLoc(); 1704 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1705 SDValue Res; 1706 if (CP->isMachineConstantPoolEntry()) 1707 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1708 CP->getAlignment()); 1709 else 1710 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1711 CP->getAlignment()); 1712 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1713} 1714 1715unsigned ARMTargetLowering::getJumpTableEncoding() const { 1716 return MachineJumpTableInfo::EK_Inline; 1717} 1718 1719SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1720 SelectionDAG &DAG) const { 1721 MachineFunction &MF = DAG.getMachineFunction(); 1722 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1723 unsigned ARMPCLabelIndex = 0; 1724 DebugLoc DL = Op.getDebugLoc(); 1725 EVT PtrVT = getPointerTy(); 1726 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1727 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1728 SDValue CPAddr; 1729 if (RelocM == Reloc::Static) { 1730 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1731 } else { 1732 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1733 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1734 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex, 1735 ARMCP::CPBlockAddress, 1736 PCAdj); 1737 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1738 } 1739 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1740 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1741 MachinePointerInfo::getConstantPool(), 1742 false, false, 0); 1743 if (RelocM == Reloc::Static) 1744 return Result; 1745 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1746 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1747} 1748 1749// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1750SDValue 1751ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1752 SelectionDAG &DAG) const { 1753 DebugLoc dl = GA->getDebugLoc(); 1754 EVT PtrVT = getPointerTy(); 1755 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1756 MachineFunction &MF = DAG.getMachineFunction(); 1757 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1758 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1759 ARMConstantPoolValue *CPV = 1760 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1761 ARMCP::CPValue, PCAdj, "tlsgd", true); 1762 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1763 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1764 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1765 MachinePointerInfo::getConstantPool(), 1766 false, false, 0); 1767 SDValue Chain = Argument.getValue(1); 1768 1769 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1770 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1771 1772 // call __tls_get_addr. 1773 ArgListTy Args; 1774 ArgListEntry Entry; 1775 Entry.Node = Argument; 1776 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext()); 1777 Args.push_back(Entry); 1778 // FIXME: is there useful debug info available here? 1779 std::pair<SDValue, SDValue> CallResult = 1780 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()), 1781 false, false, false, false, 1782 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 1783 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 1784 return CallResult.first; 1785} 1786 1787// Lower ISD::GlobalTLSAddress using the "initial exec" or 1788// "local exec" model. 1789SDValue 1790ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 1791 SelectionDAG &DAG) const { 1792 const GlobalValue *GV = GA->getGlobal(); 1793 DebugLoc dl = GA->getDebugLoc(); 1794 SDValue Offset; 1795 SDValue Chain = DAG.getEntryNode(); 1796 EVT PtrVT = getPointerTy(); 1797 // Get the Thread Pointer 1798 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1799 1800 if (GV->isDeclaration()) { 1801 MachineFunction &MF = DAG.getMachineFunction(); 1802 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1803 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1804 // Initial exec model. 1805 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1806 ARMConstantPoolValue *CPV = 1807 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, 1808 ARMCP::CPValue, PCAdj, "gottpoff", true); 1809 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1810 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1811 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1812 MachinePointerInfo::getConstantPool(), 1813 false, false, 0); 1814 Chain = Offset.getValue(1); 1815 1816 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1817 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 1818 1819 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1820 MachinePointerInfo::getConstantPool(), 1821 false, false, 0); 1822 } else { 1823 // local exec model 1824 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff"); 1825 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1826 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 1827 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 1828 MachinePointerInfo::getConstantPool(), 1829 false, false, 0); 1830 } 1831 1832 // The address of the thread local variable is the add of the thread 1833 // pointer with the offset of the variable. 1834 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1835} 1836 1837SDValue 1838ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 1839 // TODO: implement the "local dynamic" model 1840 assert(Subtarget->isTargetELF() && 1841 "TLS not implemented for non-ELF targets"); 1842 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1843 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 1844 // otherwise use the "Local Exec" TLS Model 1845 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 1846 return LowerToTLSGeneralDynamicModel(GA, DAG); 1847 else 1848 return LowerToTLSExecModels(GA, DAG); 1849} 1850 1851SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 1852 SelectionDAG &DAG) const { 1853 EVT PtrVT = getPointerTy(); 1854 DebugLoc dl = Op.getDebugLoc(); 1855 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1856 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1857 if (RelocM == Reloc::PIC_) { 1858 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 1859 ARMConstantPoolValue *CPV = 1860 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT"); 1861 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1862 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1863 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1864 CPAddr, 1865 MachinePointerInfo::getConstantPool(), 1866 false, false, 0); 1867 SDValue Chain = Result.getValue(1); 1868 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 1869 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 1870 if (!UseGOTOFF) 1871 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 1872 MachinePointerInfo::getGOT(), false, false, 0); 1873 return Result; 1874 } else { 1875 // If we have T2 ops, we can materialize the address directly via movt/movw 1876 // pair. This is always cheaper. 1877 if (Subtarget->useMovt()) { 1878 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 1879 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 1880 } else { 1881 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1882 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1883 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1884 MachinePointerInfo::getConstantPool(), 1885 false, false, 0); 1886 } 1887 } 1888} 1889 1890SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 1891 SelectionDAG &DAG) const { 1892 MachineFunction &MF = DAG.getMachineFunction(); 1893 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1894 unsigned ARMPCLabelIndex = 0; 1895 EVT PtrVT = getPointerTy(); 1896 DebugLoc dl = Op.getDebugLoc(); 1897 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1898 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1899 SDValue CPAddr; 1900 if (RelocM == Reloc::Static) 1901 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1902 else { 1903 ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1904 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 1905 ARMConstantPoolValue *CPV = 1906 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj); 1907 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1908 } 1909 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1910 1911 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1912 MachinePointerInfo::getConstantPool(), 1913 false, false, 0); 1914 SDValue Chain = Result.getValue(1); 1915 1916 if (RelocM == Reloc::PIC_) { 1917 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1918 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1919 } 1920 1921 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 1922 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 1923 false, false, 0); 1924 1925 return Result; 1926} 1927 1928SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 1929 SelectionDAG &DAG) const { 1930 assert(Subtarget->isTargetELF() && 1931 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 1932 MachineFunction &MF = DAG.getMachineFunction(); 1933 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1934 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1935 EVT PtrVT = getPointerTy(); 1936 DebugLoc dl = Op.getDebugLoc(); 1937 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1938 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(), 1939 "_GLOBAL_OFFSET_TABLE_", 1940 ARMPCLabelIndex, PCAdj); 1941 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1942 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1943 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1944 MachinePointerInfo::getConstantPool(), 1945 false, false, 0); 1946 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1947 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1948} 1949 1950SDValue 1951ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 1952 DebugLoc dl = Op.getDebugLoc(); 1953 SDValue Val = DAG.getConstant(0, MVT::i32); 1954 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), 1955 Op.getOperand(1), Val); 1956} 1957 1958SDValue 1959ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 1960 DebugLoc dl = Op.getDebugLoc(); 1961 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 1962 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 1963} 1964 1965SDValue 1966ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 1967 const ARMSubtarget *Subtarget) const { 1968 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1969 DebugLoc dl = Op.getDebugLoc(); 1970 switch (IntNo) { 1971 default: return SDValue(); // Don't custom lower most intrinsics. 1972 case Intrinsic::arm_thread_pointer: { 1973 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1974 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1975 } 1976 case Intrinsic::eh_sjlj_lsda: { 1977 MachineFunction &MF = DAG.getMachineFunction(); 1978 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1979 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); 1980 EVT PtrVT = getPointerTy(); 1981 DebugLoc dl = Op.getDebugLoc(); 1982 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1983 SDValue CPAddr; 1984 unsigned PCAdj = (RelocM != Reloc::PIC_) 1985 ? 0 : (Subtarget->isThumb() ? 4 : 8); 1986 ARMConstantPoolValue *CPV = 1987 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex, 1988 ARMCP::CPLSDA, PCAdj); 1989 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1990 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1991 SDValue Result = 1992 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 1993 MachinePointerInfo::getConstantPool(), 1994 false, false, 0); 1995 1996 if (RelocM == Reloc::PIC_) { 1997 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1998 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1999 } 2000 return Result; 2001 } 2002 } 2003} 2004 2005static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2006 const ARMSubtarget *Subtarget) { 2007 DebugLoc dl = Op.getDebugLoc(); 2008 SDValue Op5 = Op.getOperand(5); 2009 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue(); 2010 // Some subtargets which have dmb and dsb instructions can handle barriers 2011 // directly. Some ARMv6 cpus can support them with the help of mcr 2012 // instruction. Thumb1 and pre-v6 ARM mode use a libcall instead and should 2013 // never get here. 2014 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER; 2015 if (Subtarget->hasDataBarrier()) 2016 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0)); 2017 else { 2018 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() && 2019 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2020 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0), 2021 DAG.getConstant(0, MVT::i32)); 2022 } 2023} 2024 2025static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2026 MachineFunction &MF = DAG.getMachineFunction(); 2027 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2028 2029 // vastart just stores the address of the VarArgsFrameIndex slot into the 2030 // memory location argument. 2031 DebugLoc dl = Op.getDebugLoc(); 2032 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2033 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2034 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2035 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2036 MachinePointerInfo(SV), false, false, 0); 2037} 2038 2039SDValue 2040ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2041 SDValue &Root, SelectionDAG &DAG, 2042 DebugLoc dl) const { 2043 MachineFunction &MF = DAG.getMachineFunction(); 2044 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2045 2046 TargetRegisterClass *RC; 2047 if (AFI->isThumb1OnlyFunction()) 2048 RC = ARM::tGPRRegisterClass; 2049 else 2050 RC = ARM::GPRRegisterClass; 2051 2052 // Transform the arguments stored in physical registers into virtual ones. 2053 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2054 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2055 2056 SDValue ArgValue2; 2057 if (NextVA.isMemLoc()) { 2058 MachineFrameInfo *MFI = MF.getFrameInfo(); 2059 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2060 2061 // Create load node to retrieve arguments from the stack. 2062 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2063 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2064 MachinePointerInfo::getFixedStack(FI), 2065 false, false, 0); 2066 } else { 2067 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2068 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2069 } 2070 2071 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2072} 2073 2074SDValue 2075ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2076 CallingConv::ID CallConv, bool isVarArg, 2077 const SmallVectorImpl<ISD::InputArg> 2078 &Ins, 2079 DebugLoc dl, SelectionDAG &DAG, 2080 SmallVectorImpl<SDValue> &InVals) 2081 const { 2082 2083 MachineFunction &MF = DAG.getMachineFunction(); 2084 MachineFrameInfo *MFI = MF.getFrameInfo(); 2085 2086 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2087 2088 // Assign locations to all of the incoming arguments. 2089 SmallVector<CCValAssign, 16> ArgLocs; 2090 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 2091 *DAG.getContext()); 2092 CCInfo.AnalyzeFormalArguments(Ins, 2093 CCAssignFnForNode(CallConv, /* Return*/ false, 2094 isVarArg)); 2095 2096 SmallVector<SDValue, 16> ArgValues; 2097 2098 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2099 CCValAssign &VA = ArgLocs[i]; 2100 2101 // Arguments stored in registers. 2102 if (VA.isRegLoc()) { 2103 EVT RegVT = VA.getLocVT(); 2104 2105 SDValue ArgValue; 2106 if (VA.needsCustom()) { 2107 // f64 and vector types are split up into multiple registers or 2108 // combinations of registers and stack slots. 2109 if (VA.getLocVT() == MVT::v2f64) { 2110 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2111 Chain, DAG, dl); 2112 VA = ArgLocs[++i]; // skip ahead to next loc 2113 SDValue ArgValue2; 2114 if (VA.isMemLoc()) { 2115 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2116 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2117 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2118 MachinePointerInfo::getFixedStack(FI), 2119 false, false, 0); 2120 } else { 2121 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2122 Chain, DAG, dl); 2123 } 2124 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2125 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2126 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2127 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2128 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2129 } else 2130 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2131 2132 } else { 2133 TargetRegisterClass *RC; 2134 2135 if (RegVT == MVT::f32) 2136 RC = ARM::SPRRegisterClass; 2137 else if (RegVT == MVT::f64) 2138 RC = ARM::DPRRegisterClass; 2139 else if (RegVT == MVT::v2f64) 2140 RC = ARM::QPRRegisterClass; 2141 else if (RegVT == MVT::i32) 2142 RC = (AFI->isThumb1OnlyFunction() ? 2143 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2144 else 2145 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2146 2147 // Transform the arguments in physical registers into virtual ones. 2148 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2149 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2150 } 2151 2152 // If this is an 8 or 16-bit value, it is really passed promoted 2153 // to 32 bits. Insert an assert[sz]ext to capture this, then 2154 // truncate to the right size. 2155 switch (VA.getLocInfo()) { 2156 default: llvm_unreachable("Unknown loc info!"); 2157 case CCValAssign::Full: break; 2158 case CCValAssign::BCvt: 2159 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 2160 break; 2161 case CCValAssign::SExt: 2162 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2163 DAG.getValueType(VA.getValVT())); 2164 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2165 break; 2166 case CCValAssign::ZExt: 2167 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2168 DAG.getValueType(VA.getValVT())); 2169 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2170 break; 2171 } 2172 2173 InVals.push_back(ArgValue); 2174 2175 } else { // VA.isRegLoc() 2176 2177 // sanity check 2178 assert(VA.isMemLoc()); 2179 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2180 2181 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 2182 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true); 2183 2184 // Create load nodes to retrieve arguments from the stack. 2185 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2186 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2187 MachinePointerInfo::getFixedStack(FI), 2188 false, false, 0)); 2189 } 2190 } 2191 2192 // varargs 2193 if (isVarArg) { 2194 static const unsigned GPRArgRegs[] = { 2195 ARM::R0, ARM::R1, ARM::R2, ARM::R3 2196 }; 2197 2198 unsigned NumGPRs = CCInfo.getFirstUnallocated 2199 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2200 2201 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 2202 unsigned VARegSize = (4 - NumGPRs) * 4; 2203 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2204 unsigned ArgOffset = CCInfo.getNextStackOffset(); 2205 if (VARegSaveSize) { 2206 // If this function is vararg, store any remaining integer argument regs 2207 // to their spots on the stack so that they may be loaded by deferencing 2208 // the result of va_next. 2209 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2210 AFI->setVarArgsFrameIndex( 2211 MFI->CreateFixedObject(VARegSaveSize, 2212 ArgOffset + VARegSaveSize - VARegSize, 2213 false)); 2214 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2215 getPointerTy()); 2216 2217 SmallVector<SDValue, 4> MemOps; 2218 for (; NumGPRs < 4; ++NumGPRs) { 2219 TargetRegisterClass *RC; 2220 if (AFI->isThumb1OnlyFunction()) 2221 RC = ARM::tGPRRegisterClass; 2222 else 2223 RC = ARM::GPRRegisterClass; 2224 2225 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); 2226 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2227 SDValue Store = 2228 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2229 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2230 false, false, 0); 2231 MemOps.push_back(Store); 2232 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2233 DAG.getConstant(4, getPointerTy())); 2234 } 2235 if (!MemOps.empty()) 2236 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2237 &MemOps[0], MemOps.size()); 2238 } else 2239 // This will point to the next argument passed via stack. 2240 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2241 } 2242 2243 return Chain; 2244} 2245 2246/// isFloatingPointZero - Return true if this is +0.0. 2247static bool isFloatingPointZero(SDValue Op) { 2248 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2249 return CFP->getValueAPF().isPosZero(); 2250 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2251 // Maybe this has already been legalized into the constant pool? 2252 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2253 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2254 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2255 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2256 return CFP->getValueAPF().isPosZero(); 2257 } 2258 } 2259 return false; 2260} 2261 2262/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2263/// the given operands. 2264SDValue 2265ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2266 SDValue &ARMcc, SelectionDAG &DAG, 2267 DebugLoc dl) const { 2268 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2269 unsigned C = RHSC->getZExtValue(); 2270 if (!isLegalICmpImmediate(C)) { 2271 // Constant does not fit, try adjusting it by one? 2272 switch (CC) { 2273 default: break; 2274 case ISD::SETLT: 2275 case ISD::SETGE: 2276 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2277 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2278 RHS = DAG.getConstant(C-1, MVT::i32); 2279 } 2280 break; 2281 case ISD::SETULT: 2282 case ISD::SETUGE: 2283 if (C != 0 && isLegalICmpImmediate(C-1)) { 2284 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2285 RHS = DAG.getConstant(C-1, MVT::i32); 2286 } 2287 break; 2288 case ISD::SETLE: 2289 case ISD::SETGT: 2290 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2291 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2292 RHS = DAG.getConstant(C+1, MVT::i32); 2293 } 2294 break; 2295 case ISD::SETULE: 2296 case ISD::SETUGT: 2297 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2298 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2299 RHS = DAG.getConstant(C+1, MVT::i32); 2300 } 2301 break; 2302 } 2303 } 2304 } 2305 2306 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2307 ARMISD::NodeType CompareType; 2308 switch (CondCode) { 2309 default: 2310 CompareType = ARMISD::CMP; 2311 break; 2312 case ARMCC::EQ: 2313 case ARMCC::NE: 2314 // Uses only Z Flag 2315 CompareType = ARMISD::CMPZ; 2316 break; 2317 } 2318 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2319 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); 2320} 2321 2322/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2323SDValue 2324ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2325 DebugLoc dl) const { 2326 SDValue Cmp; 2327 if (!isFloatingPointZero(RHS)) 2328 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); 2329 else 2330 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); 2331 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); 2332} 2333 2334SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2335 SDValue Cond = Op.getOperand(0); 2336 SDValue SelectTrue = Op.getOperand(1); 2337 SDValue SelectFalse = Op.getOperand(2); 2338 DebugLoc dl = Op.getDebugLoc(); 2339 2340 // Convert: 2341 // 2342 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2343 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2344 // 2345 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2346 const ConstantSDNode *CMOVTrue = 2347 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2348 const ConstantSDNode *CMOVFalse = 2349 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2350 2351 if (CMOVTrue && CMOVFalse) { 2352 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2353 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2354 2355 SDValue True; 2356 SDValue False; 2357 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2358 True = SelectTrue; 2359 False = SelectFalse; 2360 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2361 True = SelectFalse; 2362 False = SelectTrue; 2363 } 2364 2365 if (True.getNode() && False.getNode()) { 2366 EVT VT = Cond.getValueType(); 2367 SDValue ARMcc = Cond.getOperand(2); 2368 SDValue CCR = Cond.getOperand(3); 2369 SDValue Cmp = Cond.getOperand(4); 2370 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2371 } 2372 } 2373 } 2374 2375 return DAG.getSelectCC(dl, Cond, 2376 DAG.getConstant(0, Cond.getValueType()), 2377 SelectTrue, SelectFalse, ISD::SETNE); 2378} 2379 2380SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2381 EVT VT = Op.getValueType(); 2382 SDValue LHS = Op.getOperand(0); 2383 SDValue RHS = Op.getOperand(1); 2384 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2385 SDValue TrueVal = Op.getOperand(2); 2386 SDValue FalseVal = Op.getOperand(3); 2387 DebugLoc dl = Op.getDebugLoc(); 2388 2389 if (LHS.getValueType() == MVT::i32) { 2390 SDValue ARMcc; 2391 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2392 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2393 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2394 } 2395 2396 ARMCC::CondCodes CondCode, CondCode2; 2397 FPCCToARMCC(CC, CondCode, CondCode2); 2398 2399 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2400 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2401 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2402 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2403 ARMcc, CCR, Cmp); 2404 if (CondCode2 != ARMCC::AL) { 2405 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2406 // FIXME: Needs another CMP because flag can have but one use. 2407 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2408 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2409 Result, TrueVal, ARMcc2, CCR, Cmp2); 2410 } 2411 return Result; 2412} 2413 2414/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2415/// to morph to an integer compare sequence. 2416static bool canChangeToInt(SDValue Op, bool &SeenZero, 2417 const ARMSubtarget *Subtarget) { 2418 SDNode *N = Op.getNode(); 2419 if (!N->hasOneUse()) 2420 // Otherwise it requires moving the value from fp to integer registers. 2421 return false; 2422 if (!N->getNumValues()) 2423 return false; 2424 EVT VT = Op.getValueType(); 2425 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2426 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2427 // vmrs are very slow, e.g. cortex-a8. 2428 return false; 2429 2430 if (isFloatingPointZero(Op)) { 2431 SeenZero = true; 2432 return true; 2433 } 2434 return ISD::isNormalLoad(N); 2435} 2436 2437static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2438 if (isFloatingPointZero(Op)) 2439 return DAG.getConstant(0, MVT::i32); 2440 2441 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2442 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2443 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2444 Ld->isVolatile(), Ld->isNonTemporal(), 2445 Ld->getAlignment()); 2446 2447 llvm_unreachable("Unknown VFP cmp argument!"); 2448} 2449 2450static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2451 SDValue &RetVal1, SDValue &RetVal2) { 2452 if (isFloatingPointZero(Op)) { 2453 RetVal1 = DAG.getConstant(0, MVT::i32); 2454 RetVal2 = DAG.getConstant(0, MVT::i32); 2455 return; 2456 } 2457 2458 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2459 SDValue Ptr = Ld->getBasePtr(); 2460 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2461 Ld->getChain(), Ptr, 2462 Ld->getPointerInfo(), 2463 Ld->isVolatile(), Ld->isNonTemporal(), 2464 Ld->getAlignment()); 2465 2466 EVT PtrType = Ptr.getValueType(); 2467 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2468 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2469 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2470 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2471 Ld->getChain(), NewPtr, 2472 Ld->getPointerInfo().getWithOffset(4), 2473 Ld->isVolatile(), Ld->isNonTemporal(), 2474 NewAlign); 2475 return; 2476 } 2477 2478 llvm_unreachable("Unknown VFP cmp argument!"); 2479} 2480 2481/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2482/// f32 and even f64 comparisons to integer ones. 2483SDValue 2484ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2485 SDValue Chain = Op.getOperand(0); 2486 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2487 SDValue LHS = Op.getOperand(2); 2488 SDValue RHS = Op.getOperand(3); 2489 SDValue Dest = Op.getOperand(4); 2490 DebugLoc dl = Op.getDebugLoc(); 2491 2492 bool SeenZero = false; 2493 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2494 canChangeToInt(RHS, SeenZero, Subtarget) && 2495 // If one of the operand is zero, it's safe to ignore the NaN case since 2496 // we only care about equality comparisons. 2497 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2498 // If unsafe fp math optimization is enabled and there are no othter uses of 2499 // the CMP operands, and the condition code is EQ oe NE, we can optimize it 2500 // to an integer comparison. 2501 if (CC == ISD::SETOEQ) 2502 CC = ISD::SETEQ; 2503 else if (CC == ISD::SETUNE) 2504 CC = ISD::SETNE; 2505 2506 SDValue ARMcc; 2507 if (LHS.getValueType() == MVT::f32) { 2508 LHS = bitcastf32Toi32(LHS, DAG); 2509 RHS = bitcastf32Toi32(RHS, DAG); 2510 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2511 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2512 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2513 Chain, Dest, ARMcc, CCR, Cmp); 2514 } 2515 2516 SDValue LHS1, LHS2; 2517 SDValue RHS1, RHS2; 2518 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2519 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2520 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2521 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2522 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 2523 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2524 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2525 } 2526 2527 return SDValue(); 2528} 2529 2530SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2531 SDValue Chain = Op.getOperand(0); 2532 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2533 SDValue LHS = Op.getOperand(2); 2534 SDValue RHS = Op.getOperand(3); 2535 SDValue Dest = Op.getOperand(4); 2536 DebugLoc dl = Op.getDebugLoc(); 2537 2538 if (LHS.getValueType() == MVT::i32) { 2539 SDValue ARMcc; 2540 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2541 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2542 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2543 Chain, Dest, ARMcc, CCR, Cmp); 2544 } 2545 2546 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2547 2548 if (UnsafeFPMath && 2549 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2550 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2551 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2552 if (Result.getNode()) 2553 return Result; 2554 } 2555 2556 ARMCC::CondCodes CondCode, CondCode2; 2557 FPCCToARMCC(CC, CondCode, CondCode2); 2558 2559 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2560 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2561 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2562 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 2563 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2564 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2565 if (CondCode2 != ARMCC::AL) { 2566 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2567 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2568 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2569 } 2570 return Res; 2571} 2572 2573SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2574 SDValue Chain = Op.getOperand(0); 2575 SDValue Table = Op.getOperand(1); 2576 SDValue Index = Op.getOperand(2); 2577 DebugLoc dl = Op.getDebugLoc(); 2578 2579 EVT PTy = getPointerTy(); 2580 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2581 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2582 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2583 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2584 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2585 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2586 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2587 if (Subtarget->isThumb2()) { 2588 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2589 // which does another jump to the destination. This also makes it easier 2590 // to translate it to TBB / TBH later. 2591 // FIXME: This might not work if the function is extremely large. 2592 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2593 Addr, Op.getOperand(2), JTI, UId); 2594 } 2595 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2596 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 2597 MachinePointerInfo::getJumpTable(), 2598 false, false, 0); 2599 Chain = Addr.getValue(1); 2600 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 2601 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2602 } else { 2603 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 2604 MachinePointerInfo::getJumpTable(), false, false, 0); 2605 Chain = Addr.getValue(1); 2606 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 2607 } 2608} 2609 2610static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 2611 DebugLoc dl = Op.getDebugLoc(); 2612 unsigned Opc; 2613 2614 switch (Op.getOpcode()) { 2615 default: 2616 assert(0 && "Invalid opcode!"); 2617 case ISD::FP_TO_SINT: 2618 Opc = ARMISD::FTOSI; 2619 break; 2620 case ISD::FP_TO_UINT: 2621 Opc = ARMISD::FTOUI; 2622 break; 2623 } 2624 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 2625 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 2626} 2627 2628static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2629 EVT VT = Op.getValueType(); 2630 DebugLoc dl = Op.getDebugLoc(); 2631 unsigned Opc; 2632 2633 switch (Op.getOpcode()) { 2634 default: 2635 assert(0 && "Invalid opcode!"); 2636 case ISD::SINT_TO_FP: 2637 Opc = ARMISD::SITOF; 2638 break; 2639 case ISD::UINT_TO_FP: 2640 Opc = ARMISD::UITOF; 2641 break; 2642 } 2643 2644 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 2645 return DAG.getNode(Opc, dl, VT, Op); 2646} 2647 2648SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2649 // Implement fcopysign with a fabs and a conditional fneg. 2650 SDValue Tmp0 = Op.getOperand(0); 2651 SDValue Tmp1 = Op.getOperand(1); 2652 DebugLoc dl = Op.getDebugLoc(); 2653 EVT VT = Op.getValueType(); 2654 EVT SrcVT = Tmp1.getValueType(); 2655 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); 2656 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32); 2657 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT); 2658 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl); 2659 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2660 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp); 2661} 2662 2663SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 2664 MachineFunction &MF = DAG.getMachineFunction(); 2665 MachineFrameInfo *MFI = MF.getFrameInfo(); 2666 MFI->setReturnAddressIsTaken(true); 2667 2668 EVT VT = Op.getValueType(); 2669 DebugLoc dl = Op.getDebugLoc(); 2670 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2671 if (Depth) { 2672 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 2673 SDValue Offset = DAG.getConstant(4, MVT::i32); 2674 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 2675 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 2676 MachinePointerInfo(), false, false, 0); 2677 } 2678 2679 // Return LR, which contains the return address. Mark it an implicit live-in. 2680 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 2681 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 2682} 2683 2684SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2685 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2686 MFI->setFrameAddressIsTaken(true); 2687 2688 EVT VT = Op.getValueType(); 2689 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 2690 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2691 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 2692 ? ARM::R7 : ARM::R11; 2693 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2694 while (Depth--) 2695 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 2696 MachinePointerInfo(), 2697 false, false, 0); 2698 return FrameAddr; 2699} 2700 2701/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to 2702/// expand a bit convert where either the source or destination type is i64 to 2703/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 2704/// operand type is illegal (e.g., v2f32 for a target that doesn't support 2705/// vectors), since the legalizer won't know what to do with that. 2706static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 2707 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2708 DebugLoc dl = N->getDebugLoc(); 2709 SDValue Op = N->getOperand(0); 2710 2711 // This function is only supposed to be called for i64 types, either as the 2712 // source or destination of the bit convert. 2713 EVT SrcVT = Op.getValueType(); 2714 EVT DstVT = N->getValueType(0); 2715 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 2716 "ExpandBIT_CONVERT called for non-i64 type"); 2717 2718 // Turn i64->f64 into VMOVDRR. 2719 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 2720 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2721 DAG.getConstant(0, MVT::i32)); 2722 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 2723 DAG.getConstant(1, MVT::i32)); 2724 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT, 2725 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 2726 } 2727 2728 // Turn f64->i64 into VMOVRRD. 2729 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 2730 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 2731 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 2732 // Merge the pieces into a single i64 value. 2733 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 2734 } 2735 2736 return SDValue(); 2737} 2738 2739/// getZeroVector - Returns a vector of specified type with all zero elements. 2740/// Zero vectors are used to represent vector negation and in those cases 2741/// will be implemented with the NEON VNEG instruction. However, VNEG does 2742/// not support i64 elements, so sometimes the zero vectors will need to be 2743/// explicitly constructed. Regardless, use a canonical VMOV to create the 2744/// zero vector. 2745static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2746 assert(VT.isVector() && "Expected a vector type"); 2747 // The canonical modified immediate encoding of a zero vector is....0! 2748 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 2749 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 2750 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 2751 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); 2752} 2753 2754/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 2755/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2756SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 2757 SelectionDAG &DAG) const { 2758 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2759 EVT VT = Op.getValueType(); 2760 unsigned VTBits = VT.getSizeInBits(); 2761 DebugLoc dl = Op.getDebugLoc(); 2762 SDValue ShOpLo = Op.getOperand(0); 2763 SDValue ShOpHi = Op.getOperand(1); 2764 SDValue ShAmt = Op.getOperand(2); 2765 SDValue ARMcc; 2766 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 2767 2768 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 2769 2770 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2771 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2772 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 2773 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2774 DAG.getConstant(VTBits, MVT::i32)); 2775 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 2776 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2777 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 2778 2779 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2780 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2781 ARMcc, DAG, dl); 2782 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 2783 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 2784 CCR, Cmp); 2785 2786 SDValue Ops[2] = { Lo, Hi }; 2787 return DAG.getMergeValues(Ops, 2, dl); 2788} 2789 2790/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 2791/// i32 values and take a 2 x i32 value to shift plus a shift amount. 2792SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 2793 SelectionDAG &DAG) const { 2794 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 2795 EVT VT = Op.getValueType(); 2796 unsigned VTBits = VT.getSizeInBits(); 2797 DebugLoc dl = Op.getDebugLoc(); 2798 SDValue ShOpLo = Op.getOperand(0); 2799 SDValue ShOpHi = Op.getOperand(1); 2800 SDValue ShAmt = Op.getOperand(2); 2801 SDValue ARMcc; 2802 2803 assert(Op.getOpcode() == ISD::SHL_PARTS); 2804 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 2805 DAG.getConstant(VTBits, MVT::i32), ShAmt); 2806 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 2807 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 2808 DAG.getConstant(VTBits, MVT::i32)); 2809 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 2810 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 2811 2812 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2813 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2814 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 2815 ARMcc, DAG, dl); 2816 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 2817 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 2818 CCR, Cmp); 2819 2820 SDValue Ops[2] = { Lo, Hi }; 2821 return DAG.getMergeValues(Ops, 2, dl); 2822} 2823 2824SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 2825 SelectionDAG &DAG) const { 2826 // The rounding mode is in bits 23:22 of the FPSCR. 2827 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 2828 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 2829 // so that the shift + and get folded into a bitfield extract. 2830 DebugLoc dl = Op.getDebugLoc(); 2831 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 2832 DAG.getConstant(Intrinsic::arm_get_fpscr, 2833 MVT::i32)); 2834 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 2835 DAG.getConstant(1U << 22, MVT::i32)); 2836 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 2837 DAG.getConstant(22, MVT::i32)); 2838 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 2839 DAG.getConstant(3, MVT::i32)); 2840} 2841 2842static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 2843 const ARMSubtarget *ST) { 2844 EVT VT = N->getValueType(0); 2845 DebugLoc dl = N->getDebugLoc(); 2846 2847 if (!ST->hasV6T2Ops()) 2848 return SDValue(); 2849 2850 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 2851 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 2852} 2853 2854static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 2855 const ARMSubtarget *ST) { 2856 EVT VT = N->getValueType(0); 2857 DebugLoc dl = N->getDebugLoc(); 2858 2859 // Lower vector shifts on NEON to use VSHL. 2860 if (VT.isVector()) { 2861 assert(ST->hasNEON() && "unexpected vector shift"); 2862 2863 // Left shifts translate directly to the vshiftu intrinsic. 2864 if (N->getOpcode() == ISD::SHL) 2865 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2866 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 2867 N->getOperand(0), N->getOperand(1)); 2868 2869 assert((N->getOpcode() == ISD::SRA || 2870 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 2871 2872 // NEON uses the same intrinsics for both left and right shifts. For 2873 // right shifts, the shift amounts are negative, so negate the vector of 2874 // shift amounts. 2875 EVT ShiftVT = N->getOperand(1).getValueType(); 2876 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 2877 getZeroVector(ShiftVT, DAG, dl), 2878 N->getOperand(1)); 2879 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 2880 Intrinsic::arm_neon_vshifts : 2881 Intrinsic::arm_neon_vshiftu); 2882 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 2883 DAG.getConstant(vshiftInt, MVT::i32), 2884 N->getOperand(0), NegatedCount); 2885 } 2886 2887 // We can get here for a node like i32 = ISD::SHL i32, i64 2888 if (VT != MVT::i64) 2889 return SDValue(); 2890 2891 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 2892 "Unknown shift to lower!"); 2893 2894 // We only lower SRA, SRL of 1 here, all others use generic lowering. 2895 if (!isa<ConstantSDNode>(N->getOperand(1)) || 2896 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 2897 return SDValue(); 2898 2899 // If we are in thumb mode, we don't have RRX. 2900 if (ST->isThumb1Only()) return SDValue(); 2901 2902 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 2903 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2904 DAG.getConstant(0, MVT::i32)); 2905 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 2906 DAG.getConstant(1, MVT::i32)); 2907 2908 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 2909 // captures the result into a carry flag. 2910 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 2911 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 2912 2913 // The low part is an ARMISD::RRX operand, which shifts the carry in. 2914 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 2915 2916 // Merge the pieces into a single i64 value. 2917 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 2918} 2919 2920static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 2921 SDValue TmpOp0, TmpOp1; 2922 bool Invert = false; 2923 bool Swap = false; 2924 unsigned Opc = 0; 2925 2926 SDValue Op0 = Op.getOperand(0); 2927 SDValue Op1 = Op.getOperand(1); 2928 SDValue CC = Op.getOperand(2); 2929 EVT VT = Op.getValueType(); 2930 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 2931 DebugLoc dl = Op.getDebugLoc(); 2932 2933 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 2934 switch (SetCCOpcode) { 2935 default: llvm_unreachable("Illegal FP comparison"); break; 2936 case ISD::SETUNE: 2937 case ISD::SETNE: Invert = true; // Fallthrough 2938 case ISD::SETOEQ: 2939 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2940 case ISD::SETOLT: 2941 case ISD::SETLT: Swap = true; // Fallthrough 2942 case ISD::SETOGT: 2943 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2944 case ISD::SETOLE: 2945 case ISD::SETLE: Swap = true; // Fallthrough 2946 case ISD::SETOGE: 2947 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2948 case ISD::SETUGE: Swap = true; // Fallthrough 2949 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 2950 case ISD::SETUGT: Swap = true; // Fallthrough 2951 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 2952 case ISD::SETUEQ: Invert = true; // Fallthrough 2953 case ISD::SETONE: 2954 // Expand this to (OLT | OGT). 2955 TmpOp0 = Op0; 2956 TmpOp1 = Op1; 2957 Opc = ISD::OR; 2958 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2959 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 2960 break; 2961 case ISD::SETUO: Invert = true; // Fallthrough 2962 case ISD::SETO: 2963 // Expand this to (OLT | OGE). 2964 TmpOp0 = Op0; 2965 TmpOp1 = Op1; 2966 Opc = ISD::OR; 2967 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 2968 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 2969 break; 2970 } 2971 } else { 2972 // Integer comparisons. 2973 switch (SetCCOpcode) { 2974 default: llvm_unreachable("Illegal integer comparison"); break; 2975 case ISD::SETNE: Invert = true; 2976 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 2977 case ISD::SETLT: Swap = true; 2978 case ISD::SETGT: Opc = ARMISD::VCGT; break; 2979 case ISD::SETLE: Swap = true; 2980 case ISD::SETGE: Opc = ARMISD::VCGE; break; 2981 case ISD::SETULT: Swap = true; 2982 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 2983 case ISD::SETULE: Swap = true; 2984 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 2985 } 2986 2987 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 2988 if (Opc == ARMISD::VCEQ) { 2989 2990 SDValue AndOp; 2991 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 2992 AndOp = Op0; 2993 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 2994 AndOp = Op1; 2995 2996 // Ignore bitconvert. 2997 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) 2998 AndOp = AndOp.getOperand(0); 2999 3000 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3001 Opc = ARMISD::VTST; 3002 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); 3003 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); 3004 Invert = !Invert; 3005 } 3006 } 3007 } 3008 3009 if (Swap) 3010 std::swap(Op0, Op1); 3011 3012 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3013 3014 if (Invert) 3015 Result = DAG.getNOT(dl, Result, VT); 3016 3017 return Result; 3018} 3019 3020/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3021/// valid vector constant for a NEON instruction with a "modified immediate" 3022/// operand (e.g., VMOV). If so, return the encoded value. 3023static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3024 unsigned SplatBitSize, SelectionDAG &DAG, 3025 EVT &VT, bool is128Bits, bool isVMOV) { 3026 unsigned OpCmode, Imm; 3027 3028 // SplatBitSize is set to the smallest size that splats the vector, so a 3029 // zero vector will always have SplatBitSize == 8. However, NEON modified 3030 // immediate instructions others than VMOV do not support the 8-bit encoding 3031 // of a zero vector, and the default encoding of zero is supposed to be the 3032 // 32-bit version. 3033 if (SplatBits == 0) 3034 SplatBitSize = 32; 3035 3036 switch (SplatBitSize) { 3037 case 8: 3038 if (!isVMOV) 3039 return SDValue(); 3040 // Any 1-byte value is OK. Op=0, Cmode=1110. 3041 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3042 OpCmode = 0xe; 3043 Imm = SplatBits; 3044 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3045 break; 3046 3047 case 16: 3048 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3049 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3050 if ((SplatBits & ~0xff) == 0) { 3051 // Value = 0x00nn: Op=x, Cmode=100x. 3052 OpCmode = 0x8; 3053 Imm = SplatBits; 3054 break; 3055 } 3056 if ((SplatBits & ~0xff00) == 0) { 3057 // Value = 0xnn00: Op=x, Cmode=101x. 3058 OpCmode = 0xa; 3059 Imm = SplatBits >> 8; 3060 break; 3061 } 3062 return SDValue(); 3063 3064 case 32: 3065 // NEON's 32-bit VMOV supports splat values where: 3066 // * only one byte is nonzero, or 3067 // * the least significant byte is 0xff and the second byte is nonzero, or 3068 // * the least significant 2 bytes are 0xff and the third is nonzero. 3069 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3070 if ((SplatBits & ~0xff) == 0) { 3071 // Value = 0x000000nn: Op=x, Cmode=000x. 3072 OpCmode = 0; 3073 Imm = SplatBits; 3074 break; 3075 } 3076 if ((SplatBits & ~0xff00) == 0) { 3077 // Value = 0x0000nn00: Op=x, Cmode=001x. 3078 OpCmode = 0x2; 3079 Imm = SplatBits >> 8; 3080 break; 3081 } 3082 if ((SplatBits & ~0xff0000) == 0) { 3083 // Value = 0x00nn0000: Op=x, Cmode=010x. 3084 OpCmode = 0x4; 3085 Imm = SplatBits >> 16; 3086 break; 3087 } 3088 if ((SplatBits & ~0xff000000) == 0) { 3089 // Value = 0xnn000000: Op=x, Cmode=011x. 3090 OpCmode = 0x6; 3091 Imm = SplatBits >> 24; 3092 break; 3093 } 3094 3095 if ((SplatBits & ~0xffff) == 0 && 3096 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3097 // Value = 0x0000nnff: Op=x, Cmode=1100. 3098 OpCmode = 0xc; 3099 Imm = SplatBits >> 8; 3100 SplatBits |= 0xff; 3101 break; 3102 } 3103 3104 if ((SplatBits & ~0xffffff) == 0 && 3105 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3106 // Value = 0x00nnffff: Op=x, Cmode=1101. 3107 OpCmode = 0xd; 3108 Imm = SplatBits >> 16; 3109 SplatBits |= 0xffff; 3110 break; 3111 } 3112 3113 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3114 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3115 // VMOV.I32. A (very) minor optimization would be to replicate the value 3116 // and fall through here to test for a valid 64-bit splat. But, then the 3117 // caller would also need to check and handle the change in size. 3118 return SDValue(); 3119 3120 case 64: { 3121 if (!isVMOV) 3122 return SDValue(); 3123 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3124 uint64_t BitMask = 0xff; 3125 uint64_t Val = 0; 3126 unsigned ImmMask = 1; 3127 Imm = 0; 3128 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3129 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3130 Val |= BitMask; 3131 Imm |= ImmMask; 3132 } else if ((SplatBits & BitMask) != 0) { 3133 return SDValue(); 3134 } 3135 BitMask <<= 8; 3136 ImmMask <<= 1; 3137 } 3138 // Op=1, Cmode=1110. 3139 OpCmode = 0x1e; 3140 SplatBits = Val; 3141 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3142 break; 3143 } 3144 3145 default: 3146 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3147 return SDValue(); 3148 } 3149 3150 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3151 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3152} 3153 3154static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3155 bool &ReverseVEXT, unsigned &Imm) { 3156 unsigned NumElts = VT.getVectorNumElements(); 3157 ReverseVEXT = false; 3158 3159 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3160 if (M[0] < 0) 3161 return false; 3162 3163 Imm = M[0]; 3164 3165 // If this is a VEXT shuffle, the immediate value is the index of the first 3166 // element. The other shuffle indices must be the successive elements after 3167 // the first one. 3168 unsigned ExpectedElt = Imm; 3169 for (unsigned i = 1; i < NumElts; ++i) { 3170 // Increment the expected index. If it wraps around, it may still be 3171 // a VEXT but the source vectors must be swapped. 3172 ExpectedElt += 1; 3173 if (ExpectedElt == NumElts * 2) { 3174 ExpectedElt = 0; 3175 ReverseVEXT = true; 3176 } 3177 3178 if (M[i] < 0) continue; // ignore UNDEF indices 3179 if (ExpectedElt != static_cast<unsigned>(M[i])) 3180 return false; 3181 } 3182 3183 // Adjust the index value if the source operands will be swapped. 3184 if (ReverseVEXT) 3185 Imm -= NumElts; 3186 3187 return true; 3188} 3189 3190/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3191/// instruction with the specified blocksize. (The order of the elements 3192/// within each block of the vector is reversed.) 3193static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3194 unsigned BlockSize) { 3195 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3196 "Only possible block sizes for VREV are: 16, 32, 64"); 3197 3198 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3199 if (EltSz == 64) 3200 return false; 3201 3202 unsigned NumElts = VT.getVectorNumElements(); 3203 unsigned BlockElts = M[0] + 1; 3204 // If the first shuffle index is UNDEF, be optimistic. 3205 if (M[0] < 0) 3206 BlockElts = BlockSize / EltSz; 3207 3208 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3209 return false; 3210 3211 for (unsigned i = 0; i < NumElts; ++i) { 3212 if (M[i] < 0) continue; // ignore UNDEF indices 3213 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3214 return false; 3215 } 3216 3217 return true; 3218} 3219 3220static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3221 unsigned &WhichResult) { 3222 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3223 if (EltSz == 64) 3224 return false; 3225 3226 unsigned NumElts = VT.getVectorNumElements(); 3227 WhichResult = (M[0] == 0 ? 0 : 1); 3228 for (unsigned i = 0; i < NumElts; i += 2) { 3229 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3230 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3231 return false; 3232 } 3233 return true; 3234} 3235 3236/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3237/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3238/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3239static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3240 unsigned &WhichResult) { 3241 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3242 if (EltSz == 64) 3243 return false; 3244 3245 unsigned NumElts = VT.getVectorNumElements(); 3246 WhichResult = (M[0] == 0 ? 0 : 1); 3247 for (unsigned i = 0; i < NumElts; i += 2) { 3248 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3249 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3250 return false; 3251 } 3252 return true; 3253} 3254 3255static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3256 unsigned &WhichResult) { 3257 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3258 if (EltSz == 64) 3259 return false; 3260 3261 unsigned NumElts = VT.getVectorNumElements(); 3262 WhichResult = (M[0] == 0 ? 0 : 1); 3263 for (unsigned i = 0; i != NumElts; ++i) { 3264 if (M[i] < 0) continue; // ignore UNDEF indices 3265 if ((unsigned) M[i] != 2 * i + WhichResult) 3266 return false; 3267 } 3268 3269 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3270 if (VT.is64BitVector() && EltSz == 32) 3271 return false; 3272 3273 return true; 3274} 3275 3276/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3277/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3278/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3279static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3280 unsigned &WhichResult) { 3281 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3282 if (EltSz == 64) 3283 return false; 3284 3285 unsigned Half = VT.getVectorNumElements() / 2; 3286 WhichResult = (M[0] == 0 ? 0 : 1); 3287 for (unsigned j = 0; j != 2; ++j) { 3288 unsigned Idx = WhichResult; 3289 for (unsigned i = 0; i != Half; ++i) { 3290 int MIdx = M[i + j * Half]; 3291 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3292 return false; 3293 Idx += 2; 3294 } 3295 } 3296 3297 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3298 if (VT.is64BitVector() && EltSz == 32) 3299 return false; 3300 3301 return true; 3302} 3303 3304static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3305 unsigned &WhichResult) { 3306 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3307 if (EltSz == 64) 3308 return false; 3309 3310 unsigned NumElts = VT.getVectorNumElements(); 3311 WhichResult = (M[0] == 0 ? 0 : 1); 3312 unsigned Idx = WhichResult * NumElts / 2; 3313 for (unsigned i = 0; i != NumElts; i += 2) { 3314 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3315 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3316 return false; 3317 Idx += 1; 3318 } 3319 3320 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3321 if (VT.is64BitVector() && EltSz == 32) 3322 return false; 3323 3324 return true; 3325} 3326 3327/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3328/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3329/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3330static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3331 unsigned &WhichResult) { 3332 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3333 if (EltSz == 64) 3334 return false; 3335 3336 unsigned NumElts = VT.getVectorNumElements(); 3337 WhichResult = (M[0] == 0 ? 0 : 1); 3338 unsigned Idx = WhichResult * NumElts / 2; 3339 for (unsigned i = 0; i != NumElts; i += 2) { 3340 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3341 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3342 return false; 3343 Idx += 1; 3344 } 3345 3346 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3347 if (VT.is64BitVector() && EltSz == 32) 3348 return false; 3349 3350 return true; 3351} 3352 3353// If N is an integer constant that can be moved into a register in one 3354// instruction, return an SDValue of such a constant (will become a MOV 3355// instruction). Otherwise return null. 3356static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3357 const ARMSubtarget *ST, DebugLoc dl) { 3358 uint64_t Val; 3359 if (!isa<ConstantSDNode>(N)) 3360 return SDValue(); 3361 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3362 3363 if (ST->isThumb1Only()) { 3364 if (Val <= 255 || ~Val <= 255) 3365 return DAG.getConstant(Val, MVT::i32); 3366 } else { 3367 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3368 return DAG.getConstant(Val, MVT::i32); 3369 } 3370 return SDValue(); 3371} 3372 3373// If this is a case we can't handle, return null and let the default 3374// expansion code take care of it. 3375static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3376 const ARMSubtarget *ST) { 3377 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3378 DebugLoc dl = Op.getDebugLoc(); 3379 EVT VT = Op.getValueType(); 3380 3381 APInt SplatBits, SplatUndef; 3382 unsigned SplatBitSize; 3383 bool HasAnyUndefs; 3384 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3385 if (SplatBitSize <= 64) { 3386 // Check if an immediate VMOV works. 3387 EVT VmovVT; 3388 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3389 SplatUndef.getZExtValue(), SplatBitSize, 3390 DAG, VmovVT, VT.is128BitVector(), true); 3391 if (Val.getNode()) { 3392 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3393 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); 3394 } 3395 3396 // Try an immediate VMVN. 3397 uint64_t NegatedImm = (SplatBits.getZExtValue() ^ 3398 ((1LL << SplatBitSize) - 1)); 3399 Val = isNEONModifiedImm(NegatedImm, 3400 SplatUndef.getZExtValue(), SplatBitSize, 3401 DAG, VmovVT, VT.is128BitVector(), false); 3402 if (Val.getNode()) { 3403 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3404 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); 3405 } 3406 } 3407 } 3408 3409 // Scan through the operands to see if only one value is used. 3410 unsigned NumElts = VT.getVectorNumElements(); 3411 bool isOnlyLowElement = true; 3412 bool usesOnlyOneValue = true; 3413 bool isConstant = true; 3414 SDValue Value; 3415 for (unsigned i = 0; i < NumElts; ++i) { 3416 SDValue V = Op.getOperand(i); 3417 if (V.getOpcode() == ISD::UNDEF) 3418 continue; 3419 if (i > 0) 3420 isOnlyLowElement = false; 3421 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3422 isConstant = false; 3423 3424 if (!Value.getNode()) 3425 Value = V; 3426 else if (V != Value) 3427 usesOnlyOneValue = false; 3428 } 3429 3430 if (!Value.getNode()) 3431 return DAG.getUNDEF(VT); 3432 3433 if (isOnlyLowElement) 3434 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3435 3436 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3437 3438 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3439 // i32 and try again. 3440 if (usesOnlyOneValue && EltSize <= 32) { 3441 if (!isConstant) 3442 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3443 if (VT.getVectorElementType().isFloatingPoint()) { 3444 SmallVector<SDValue, 8> Ops; 3445 for (unsigned i = 0; i < NumElts; ++i) 3446 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 3447 Op.getOperand(i))); 3448 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0], 3449 NumElts); 3450 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3451 LowerBUILD_VECTOR(Val, DAG, ST)); 3452 } 3453 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 3454 if (Val.getNode()) 3455 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 3456 } 3457 3458 // If all elements are constants and the case above didn't get hit, fall back 3459 // to the default expansion, which will generate a load from the constant 3460 // pool. 3461 if (isConstant) 3462 return SDValue(); 3463 3464 // Vectors with 32- or 64-bit elements can be built by directly assigning 3465 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 3466 // will be legalized. 3467 if (EltSize >= 32) { 3468 // Do the expansion with floating-point types, since that is what the VFP 3469 // registers are defined to use, and since i64 is not legal. 3470 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3471 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3472 SmallVector<SDValue, 8> Ops; 3473 for (unsigned i = 0; i < NumElts; ++i) 3474 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i))); 3475 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3476 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3477 } 3478 3479 return SDValue(); 3480} 3481 3482/// isShuffleMaskLegal - Targets can use this to indicate that they only 3483/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 3484/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 3485/// are assumed to be legal. 3486bool 3487ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 3488 EVT VT) const { 3489 if (VT.getVectorNumElements() == 4 && 3490 (VT.is128BitVector() || VT.is64BitVector())) { 3491 unsigned PFIndexes[4]; 3492 for (unsigned i = 0; i != 4; ++i) { 3493 if (M[i] < 0) 3494 PFIndexes[i] = 8; 3495 else 3496 PFIndexes[i] = M[i]; 3497 } 3498 3499 // Compute the index in the perfect shuffle table. 3500 unsigned PFTableIndex = 3501 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3502 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3503 unsigned Cost = (PFEntry >> 30); 3504 3505 if (Cost <= 4) 3506 return true; 3507 } 3508 3509 bool ReverseVEXT; 3510 unsigned Imm, WhichResult; 3511 3512 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3513 return (EltSize >= 32 || 3514 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 3515 isVREVMask(M, VT, 64) || 3516 isVREVMask(M, VT, 32) || 3517 isVREVMask(M, VT, 16) || 3518 isVEXTMask(M, VT, ReverseVEXT, Imm) || 3519 isVTRNMask(M, VT, WhichResult) || 3520 isVUZPMask(M, VT, WhichResult) || 3521 isVZIPMask(M, VT, WhichResult) || 3522 isVTRN_v_undef_Mask(M, VT, WhichResult) || 3523 isVUZP_v_undef_Mask(M, VT, WhichResult) || 3524 isVZIP_v_undef_Mask(M, VT, WhichResult)); 3525} 3526 3527/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3528/// the specified operations to build the shuffle. 3529static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3530 SDValue RHS, SelectionDAG &DAG, 3531 DebugLoc dl) { 3532 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3533 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3534 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3535 3536 enum { 3537 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3538 OP_VREV, 3539 OP_VDUP0, 3540 OP_VDUP1, 3541 OP_VDUP2, 3542 OP_VDUP3, 3543 OP_VEXT1, 3544 OP_VEXT2, 3545 OP_VEXT3, 3546 OP_VUZPL, // VUZP, left result 3547 OP_VUZPR, // VUZP, right result 3548 OP_VZIPL, // VZIP, left result 3549 OP_VZIPR, // VZIP, right result 3550 OP_VTRNL, // VTRN, left result 3551 OP_VTRNR // VTRN, right result 3552 }; 3553 3554 if (OpNum == OP_COPY) { 3555 if (LHSID == (1*9+2)*9+3) return LHS; 3556 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3557 return RHS; 3558 } 3559 3560 SDValue OpLHS, OpRHS; 3561 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 3562 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 3563 EVT VT = OpLHS.getValueType(); 3564 3565 switch (OpNum) { 3566 default: llvm_unreachable("Unknown shuffle opcode!"); 3567 case OP_VREV: 3568 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 3569 case OP_VDUP0: 3570 case OP_VDUP1: 3571 case OP_VDUP2: 3572 case OP_VDUP3: 3573 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 3574 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 3575 case OP_VEXT1: 3576 case OP_VEXT2: 3577 case OP_VEXT3: 3578 return DAG.getNode(ARMISD::VEXT, dl, VT, 3579 OpLHS, OpRHS, 3580 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 3581 case OP_VUZPL: 3582 case OP_VUZPR: 3583 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3584 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 3585 case OP_VZIPL: 3586 case OP_VZIPR: 3587 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3588 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 3589 case OP_VTRNL: 3590 case OP_VTRNR: 3591 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3592 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 3593 } 3594} 3595 3596static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 3597 SDValue V1 = Op.getOperand(0); 3598 SDValue V2 = Op.getOperand(1); 3599 DebugLoc dl = Op.getDebugLoc(); 3600 EVT VT = Op.getValueType(); 3601 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 3602 SmallVector<int, 8> ShuffleMask; 3603 3604 // Convert shuffles that are directly supported on NEON to target-specific 3605 // DAG nodes, instead of keeping them as shuffles and matching them again 3606 // during code selection. This is more efficient and avoids the possibility 3607 // of inconsistencies between legalization and selection. 3608 // FIXME: floating-point vectors should be canonicalized to integer vectors 3609 // of the same time so that they get CSEd properly. 3610 SVN->getMask(ShuffleMask); 3611 3612 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3613 if (EltSize <= 32) { 3614 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 3615 int Lane = SVN->getSplatIndex(); 3616 // If this is undef splat, generate it via "just" vdup, if possible. 3617 if (Lane == -1) Lane = 0; 3618 3619 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3620 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 3621 } 3622 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 3623 DAG.getConstant(Lane, MVT::i32)); 3624 } 3625 3626 bool ReverseVEXT; 3627 unsigned Imm; 3628 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 3629 if (ReverseVEXT) 3630 std::swap(V1, V2); 3631 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 3632 DAG.getConstant(Imm, MVT::i32)); 3633 } 3634 3635 if (isVREVMask(ShuffleMask, VT, 64)) 3636 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 3637 if (isVREVMask(ShuffleMask, VT, 32)) 3638 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 3639 if (isVREVMask(ShuffleMask, VT, 16)) 3640 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 3641 3642 // Check for Neon shuffles that modify both input vectors in place. 3643 // If both results are used, i.e., if there are two shuffles with the same 3644 // source operands and with masks corresponding to both results of one of 3645 // these operations, DAG memoization will ensure that a single node is 3646 // used for both shuffles. 3647 unsigned WhichResult; 3648 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 3649 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3650 V1, V2).getValue(WhichResult); 3651 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 3652 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3653 V1, V2).getValue(WhichResult); 3654 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 3655 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3656 V1, V2).getValue(WhichResult); 3657 3658 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3659 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 3660 V1, V1).getValue(WhichResult); 3661 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3662 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 3663 V1, V1).getValue(WhichResult); 3664 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 3665 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 3666 V1, V1).getValue(WhichResult); 3667 } 3668 3669 // If the shuffle is not directly supported and it has 4 elements, use 3670 // the PerfectShuffle-generated table to synthesize it from other shuffles. 3671 unsigned NumElts = VT.getVectorNumElements(); 3672 if (NumElts == 4) { 3673 unsigned PFIndexes[4]; 3674 for (unsigned i = 0; i != 4; ++i) { 3675 if (ShuffleMask[i] < 0) 3676 PFIndexes[i] = 8; 3677 else 3678 PFIndexes[i] = ShuffleMask[i]; 3679 } 3680 3681 // Compute the index in the perfect shuffle table. 3682 unsigned PFTableIndex = 3683 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3684 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3685 unsigned Cost = (PFEntry >> 30); 3686 3687 if (Cost <= 4) 3688 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 3689 } 3690 3691 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 3692 if (EltSize >= 32) { 3693 // Do the expansion with floating-point types, since that is what the VFP 3694 // registers are defined to use, and since i64 is not legal. 3695 EVT EltVT = EVT::getFloatingPointVT(EltSize); 3696 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 3697 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1); 3698 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2); 3699 SmallVector<SDValue, 8> Ops; 3700 for (unsigned i = 0; i < NumElts; ++i) { 3701 if (ShuffleMask[i] < 0) 3702 Ops.push_back(DAG.getUNDEF(EltVT)); 3703 else 3704 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3705 ShuffleMask[i] < (int)NumElts ? V1 : V2, 3706 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 3707 MVT::i32))); 3708 } 3709 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 3710 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); 3711 } 3712 3713 return SDValue(); 3714} 3715 3716static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 3717 EVT VT = Op.getValueType(); 3718 DebugLoc dl = Op.getDebugLoc(); 3719 SDValue Vec = Op.getOperand(0); 3720 SDValue Lane = Op.getOperand(1); 3721 assert(VT == MVT::i32 && 3722 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && 3723 "unexpected type for custom-lowering vector extract"); 3724 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 3725} 3726 3727static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3728 // The only time a CONCAT_VECTORS operation can have legal types is when 3729 // two 64-bit vectors are concatenated to a 128-bit vector. 3730 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 3731 "unexpected CONCAT_VECTORS"); 3732 DebugLoc dl = Op.getDebugLoc(); 3733 SDValue Val = DAG.getUNDEF(MVT::v2f64); 3734 SDValue Op0 = Op.getOperand(0); 3735 SDValue Op1 = Op.getOperand(1); 3736 if (Op0.getOpcode() != ISD::UNDEF) 3737 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3738 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), 3739 DAG.getIntPtrConstant(0)); 3740 if (Op1.getOpcode() != ISD::UNDEF) 3741 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 3742 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), 3743 DAG.getIntPtrConstant(1)); 3744 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); 3745} 3746 3747/// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or 3748/// an extending load, return the unextended value. 3749static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 3750 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 3751 return N->getOperand(0); 3752 LoadSDNode *LD = cast<LoadSDNode>(N); 3753 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 3754 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 3755 LD->isNonTemporal(), LD->getAlignment()); 3756} 3757 3758static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 3759 // Multiplications are only custom-lowered for 128-bit vectors so that 3760 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 3761 EVT VT = Op.getValueType(); 3762 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 3763 SDNode *N0 = Op.getOperand(0).getNode(); 3764 SDNode *N1 = Op.getOperand(1).getNode(); 3765 unsigned NewOpc = 0; 3766 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) && 3767 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) { 3768 NewOpc = ARMISD::VMULLs; 3769 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) && 3770 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) { 3771 NewOpc = ARMISD::VMULLu; 3772 } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) { 3773 // Fall through to expand this. It is not legal. 3774 return SDValue(); 3775 } else { 3776 // Other vector multiplications are legal. 3777 return Op; 3778 } 3779 3780 // Legalize to a VMULL instruction. 3781 DebugLoc DL = Op.getDebugLoc(); 3782 SDValue Op0 = SkipExtension(N0, DAG); 3783 SDValue Op1 = SkipExtension(N1, DAG); 3784 3785 assert(Op0.getValueType().is64BitVector() && 3786 Op1.getValueType().is64BitVector() && 3787 "unexpected types for extended operands to VMULL"); 3788 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 3789} 3790 3791SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 3792 switch (Op.getOpcode()) { 3793 default: llvm_unreachable("Don't know how to custom lower this!"); 3794 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3795 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 3796 case ISD::GlobalAddress: 3797 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 3798 LowerGlobalAddressELF(Op, DAG); 3799 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3800 case ISD::SELECT: return LowerSELECT(Op, DAG); 3801 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3802 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 3803 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 3804 case ISD::VASTART: return LowerVASTART(Op, DAG); 3805 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 3806 case ISD::SINT_TO_FP: 3807 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 3808 case ISD::FP_TO_SINT: 3809 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 3810 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 3811 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3812 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3813 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 3814 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 3815 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 3816 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 3817 Subtarget); 3818 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 3819 case ISD::SHL: 3820 case ISD::SRL: 3821 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 3822 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 3823 case ISD::SRL_PARTS: 3824 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 3825 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 3826 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 3827 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 3828 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3829 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 3830 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 3831 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3832 case ISD::MUL: return LowerMUL(Op, DAG); 3833 } 3834 return SDValue(); 3835} 3836 3837/// ReplaceNodeResults - Replace the results of node with an illegal result 3838/// type with new values built out of custom code. 3839void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 3840 SmallVectorImpl<SDValue>&Results, 3841 SelectionDAG &DAG) const { 3842 SDValue Res; 3843 switch (N->getOpcode()) { 3844 default: 3845 llvm_unreachable("Don't know how to custom expand this!"); 3846 break; 3847 case ISD::BIT_CONVERT: 3848 Res = ExpandBIT_CONVERT(N, DAG); 3849 break; 3850 case ISD::SRL: 3851 case ISD::SRA: 3852 Res = LowerShift(N, DAG, Subtarget); 3853 break; 3854 } 3855 if (Res.getNode()) 3856 Results.push_back(Res); 3857} 3858 3859//===----------------------------------------------------------------------===// 3860// ARM Scheduler Hooks 3861//===----------------------------------------------------------------------===// 3862 3863MachineBasicBlock * 3864ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 3865 MachineBasicBlock *BB, 3866 unsigned Size) const { 3867 unsigned dest = MI->getOperand(0).getReg(); 3868 unsigned ptr = MI->getOperand(1).getReg(); 3869 unsigned oldval = MI->getOperand(2).getReg(); 3870 unsigned newval = MI->getOperand(3).getReg(); 3871 unsigned scratch = BB->getParent()->getRegInfo() 3872 .createVirtualRegister(ARM::GPRRegisterClass); 3873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3874 DebugLoc dl = MI->getDebugLoc(); 3875 bool isThumb2 = Subtarget->isThumb2(); 3876 3877 unsigned ldrOpc, strOpc; 3878 switch (Size) { 3879 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3880 case 1: 3881 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3882 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB; 3883 break; 3884 case 2: 3885 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3886 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3887 break; 3888 case 4: 3889 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3890 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3891 break; 3892 } 3893 3894 MachineFunction *MF = BB->getParent(); 3895 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3896 MachineFunction::iterator It = BB; 3897 ++It; // insert the new blocks after the current block 3898 3899 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3900 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 3901 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3902 MF->insert(It, loop1MBB); 3903 MF->insert(It, loop2MBB); 3904 MF->insert(It, exitMBB); 3905 3906 // Transfer the remainder of BB and its successor edges to exitMBB. 3907 exitMBB->splice(exitMBB->begin(), BB, 3908 llvm::next(MachineBasicBlock::iterator(MI)), 3909 BB->end()); 3910 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3911 3912 // thisMBB: 3913 // ... 3914 // fallthrough --> loop1MBB 3915 BB->addSuccessor(loop1MBB); 3916 3917 // loop1MBB: 3918 // ldrex dest, [ptr] 3919 // cmp dest, oldval 3920 // bne exitMBB 3921 BB = loop1MBB; 3922 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 3923 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 3924 .addReg(dest).addReg(oldval)); 3925 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3926 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3927 BB->addSuccessor(loop2MBB); 3928 BB->addSuccessor(exitMBB); 3929 3930 // loop2MBB: 3931 // strex scratch, newval, [ptr] 3932 // cmp scratch, #0 3933 // bne loop1MBB 3934 BB = loop2MBB; 3935 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval) 3936 .addReg(ptr)); 3937 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 3938 .addReg(scratch).addImm(0)); 3939 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 3940 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 3941 BB->addSuccessor(loop1MBB); 3942 BB->addSuccessor(exitMBB); 3943 3944 // exitMBB: 3945 // ... 3946 BB = exitMBB; 3947 3948 MI->eraseFromParent(); // The instruction is gone now. 3949 3950 return BB; 3951} 3952 3953MachineBasicBlock * 3954ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 3955 unsigned Size, unsigned BinOpcode) const { 3956 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3958 3959 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3960 MachineFunction *MF = BB->getParent(); 3961 MachineFunction::iterator It = BB; 3962 ++It; 3963 3964 unsigned dest = MI->getOperand(0).getReg(); 3965 unsigned ptr = MI->getOperand(1).getReg(); 3966 unsigned incr = MI->getOperand(2).getReg(); 3967 DebugLoc dl = MI->getDebugLoc(); 3968 3969 bool isThumb2 = Subtarget->isThumb2(); 3970 unsigned ldrOpc, strOpc; 3971 switch (Size) { 3972 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 3973 case 1: 3974 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 3975 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 3976 break; 3977 case 2: 3978 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 3979 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 3980 break; 3981 case 4: 3982 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 3983 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 3984 break; 3985 } 3986 3987 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3988 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3989 MF->insert(It, loopMBB); 3990 MF->insert(It, exitMBB); 3991 3992 // Transfer the remainder of BB and its successor edges to exitMBB. 3993 exitMBB->splice(exitMBB->begin(), BB, 3994 llvm::next(MachineBasicBlock::iterator(MI)), 3995 BB->end()); 3996 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 3997 3998 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3999 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 4000 unsigned scratch2 = (!BinOpcode) ? incr : 4001 RegInfo.createVirtualRegister(ARM::GPRRegisterClass); 4002 4003 // thisMBB: 4004 // ... 4005 // fallthrough --> loopMBB 4006 BB->addSuccessor(loopMBB); 4007 4008 // loopMBB: 4009 // ldrex dest, ptr 4010 // <binop> scratch2, dest, incr 4011 // strex scratch, scratch2, ptr 4012 // cmp scratch, #0 4013 // bne- loopMBB 4014 // fallthrough --> exitMBB 4015 BB = loopMBB; 4016 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr)); 4017 if (BinOpcode) { 4018 // operand order needs to go the other way for NAND 4019 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 4020 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 4021 addReg(incr).addReg(dest)).addReg(0); 4022 else 4023 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 4024 addReg(dest).addReg(incr)).addReg(0); 4025 } 4026 4027 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2) 4028 .addReg(ptr)); 4029 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 4030 .addReg(scratch).addImm(0)); 4031 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 4032 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 4033 4034 BB->addSuccessor(loopMBB); 4035 BB->addSuccessor(exitMBB); 4036 4037 // exitMBB: 4038 // ... 4039 BB = exitMBB; 4040 4041 MI->eraseFromParent(); // The instruction is gone now. 4042 4043 return BB; 4044} 4045 4046static 4047MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 4048 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 4049 E = MBB->succ_end(); I != E; ++I) 4050 if (*I != Succ) 4051 return *I; 4052 llvm_unreachable("Expecting a BB with two successors!"); 4053} 4054 4055MachineBasicBlock * 4056ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4057 MachineBasicBlock *BB) const { 4058 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4059 DebugLoc dl = MI->getDebugLoc(); 4060 bool isThumb2 = Subtarget->isThumb2(); 4061 switch (MI->getOpcode()) { 4062 default: 4063 MI->dump(); 4064 llvm_unreachable("Unexpected instr type to insert"); 4065 4066 case ARM::ATOMIC_LOAD_ADD_I8: 4067 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 4068 case ARM::ATOMIC_LOAD_ADD_I16: 4069 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 4070 case ARM::ATOMIC_LOAD_ADD_I32: 4071 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 4072 4073 case ARM::ATOMIC_LOAD_AND_I8: 4074 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 4075 case ARM::ATOMIC_LOAD_AND_I16: 4076 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 4077 case ARM::ATOMIC_LOAD_AND_I32: 4078 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 4079 4080 case ARM::ATOMIC_LOAD_OR_I8: 4081 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 4082 case ARM::ATOMIC_LOAD_OR_I16: 4083 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 4084 case ARM::ATOMIC_LOAD_OR_I32: 4085 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 4086 4087 case ARM::ATOMIC_LOAD_XOR_I8: 4088 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 4089 case ARM::ATOMIC_LOAD_XOR_I16: 4090 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 4091 case ARM::ATOMIC_LOAD_XOR_I32: 4092 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 4093 4094 case ARM::ATOMIC_LOAD_NAND_I8: 4095 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 4096 case ARM::ATOMIC_LOAD_NAND_I16: 4097 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 4098 case ARM::ATOMIC_LOAD_NAND_I32: 4099 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 4100 4101 case ARM::ATOMIC_LOAD_SUB_I8: 4102 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 4103 case ARM::ATOMIC_LOAD_SUB_I16: 4104 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 4105 case ARM::ATOMIC_LOAD_SUB_I32: 4106 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 4107 4108 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 4109 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 4110 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 4111 4112 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 4113 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 4114 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 4115 4116 case ARM::tMOVCCr_pseudo: { 4117 // To "insert" a SELECT_CC instruction, we actually have to insert the 4118 // diamond control-flow pattern. The incoming instruction knows the 4119 // destination vreg to set, the condition code register to branch on, the 4120 // true/false values to select between, and a branch opcode to use. 4121 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4122 MachineFunction::iterator It = BB; 4123 ++It; 4124 4125 // thisMBB: 4126 // ... 4127 // TrueVal = ... 4128 // cmpTY ccX, r1, r2 4129 // bCC copy1MBB 4130 // fallthrough --> copy0MBB 4131 MachineBasicBlock *thisMBB = BB; 4132 MachineFunction *F = BB->getParent(); 4133 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4134 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4135 F->insert(It, copy0MBB); 4136 F->insert(It, sinkMBB); 4137 4138 // Transfer the remainder of BB and its successor edges to sinkMBB. 4139 sinkMBB->splice(sinkMBB->begin(), BB, 4140 llvm::next(MachineBasicBlock::iterator(MI)), 4141 BB->end()); 4142 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4143 4144 BB->addSuccessor(copy0MBB); 4145 BB->addSuccessor(sinkMBB); 4146 4147 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 4148 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 4149 4150 // copy0MBB: 4151 // %FalseValue = ... 4152 // # fallthrough to sinkMBB 4153 BB = copy0MBB; 4154 4155 // Update machine-CFG edges 4156 BB->addSuccessor(sinkMBB); 4157 4158 // sinkMBB: 4159 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4160 // ... 4161 BB = sinkMBB; 4162 BuildMI(*BB, BB->begin(), dl, 4163 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 4164 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 4165 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4166 4167 MI->eraseFromParent(); // The pseudo instruction is gone now. 4168 return BB; 4169 } 4170 4171 case ARM::BCCi64: 4172 case ARM::BCCZi64: { 4173 // Compare both parts that make up the double comparison separately for 4174 // equality. 4175 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 4176 4177 unsigned LHS1 = MI->getOperand(1).getReg(); 4178 unsigned LHS2 = MI->getOperand(2).getReg(); 4179 if (RHSisZero) { 4180 AddDefaultPred(BuildMI(BB, dl, 4181 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 4182 .addReg(LHS1).addImm(0)); 4183 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 4184 .addReg(LHS2).addImm(0) 4185 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 4186 } else { 4187 unsigned RHS1 = MI->getOperand(3).getReg(); 4188 unsigned RHS2 = MI->getOperand(4).getReg(); 4189 AddDefaultPred(BuildMI(BB, dl, 4190 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 4191 .addReg(LHS1).addReg(RHS1)); 4192 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 4193 .addReg(LHS2).addReg(RHS2) 4194 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 4195 } 4196 4197 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 4198 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 4199 if (MI->getOperand(0).getImm() == ARMCC::NE) 4200 std::swap(destMBB, exitMBB); 4201 4202 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 4203 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 4204 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B)) 4205 .addMBB(exitMBB); 4206 4207 MI->eraseFromParent(); // The pseudo instruction is gone now. 4208 return BB; 4209 } 4210 } 4211} 4212 4213//===----------------------------------------------------------------------===// 4214// ARM Optimization Hooks 4215//===----------------------------------------------------------------------===// 4216 4217static 4218SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 4219 TargetLowering::DAGCombinerInfo &DCI) { 4220 SelectionDAG &DAG = DCI.DAG; 4221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4222 EVT VT = N->getValueType(0); 4223 unsigned Opc = N->getOpcode(); 4224 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 4225 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 4226 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 4227 ISD::CondCode CC = ISD::SETCC_INVALID; 4228 4229 if (isSlctCC) { 4230 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 4231 } else { 4232 SDValue CCOp = Slct.getOperand(0); 4233 if (CCOp.getOpcode() == ISD::SETCC) 4234 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 4235 } 4236 4237 bool DoXform = false; 4238 bool InvCC = false; 4239 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 4240 "Bad input!"); 4241 4242 if (LHS.getOpcode() == ISD::Constant && 4243 cast<ConstantSDNode>(LHS)->isNullValue()) { 4244 DoXform = true; 4245 } else if (CC != ISD::SETCC_INVALID && 4246 RHS.getOpcode() == ISD::Constant && 4247 cast<ConstantSDNode>(RHS)->isNullValue()) { 4248 std::swap(LHS, RHS); 4249 SDValue Op0 = Slct.getOperand(0); 4250 EVT OpVT = isSlctCC ? Op0.getValueType() : 4251 Op0.getOperand(0).getValueType(); 4252 bool isInt = OpVT.isInteger(); 4253 CC = ISD::getSetCCInverse(CC, isInt); 4254 4255 if (!TLI.isCondCodeLegal(CC, OpVT)) 4256 return SDValue(); // Inverse operator isn't legal. 4257 4258 DoXform = true; 4259 InvCC = true; 4260 } 4261 4262 if (DoXform) { 4263 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 4264 if (isSlctCC) 4265 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 4266 Slct.getOperand(0), Slct.getOperand(1), CC); 4267 SDValue CCOp = Slct.getOperand(0); 4268 if (InvCC) 4269 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 4270 CCOp.getOperand(0), CCOp.getOperand(1), CC); 4271 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4272 CCOp, OtherOp, Result); 4273 } 4274 return SDValue(); 4275} 4276 4277/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 4278/// operands N0 and N1. This is a helper for PerformADDCombine that is 4279/// called with the default operands, and if that fails, with commuted 4280/// operands. 4281static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 4282 TargetLowering::DAGCombinerInfo &DCI) { 4283 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 4284 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 4285 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 4286 if (Result.getNode()) return Result; 4287 } 4288 return SDValue(); 4289} 4290 4291/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 4292/// 4293static SDValue PerformADDCombine(SDNode *N, 4294 TargetLowering::DAGCombinerInfo &DCI) { 4295 SDValue N0 = N->getOperand(0); 4296 SDValue N1 = N->getOperand(1); 4297 4298 // First try with the default operand order. 4299 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI); 4300 if (Result.getNode()) 4301 return Result; 4302 4303 // If that didn't work, try again with the operands commuted. 4304 return PerformADDCombineWithOperands(N, N1, N0, DCI); 4305} 4306 4307/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 4308/// 4309static SDValue PerformSUBCombine(SDNode *N, 4310 TargetLowering::DAGCombinerInfo &DCI) { 4311 SDValue N0 = N->getOperand(0); 4312 SDValue N1 = N->getOperand(1); 4313 4314 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 4315 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 4316 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 4317 if (Result.getNode()) return Result; 4318 } 4319 4320 return SDValue(); 4321} 4322 4323static SDValue PerformMULCombine(SDNode *N, 4324 TargetLowering::DAGCombinerInfo &DCI, 4325 const ARMSubtarget *Subtarget) { 4326 SelectionDAG &DAG = DCI.DAG; 4327 4328 if (Subtarget->isThumb1Only()) 4329 return SDValue(); 4330 4331 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 4332 return SDValue(); 4333 4334 EVT VT = N->getValueType(0); 4335 if (VT != MVT::i32) 4336 return SDValue(); 4337 4338 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 4339 if (!C) 4340 return SDValue(); 4341 4342 uint64_t MulAmt = C->getZExtValue(); 4343 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 4344 ShiftAmt = ShiftAmt & (32 - 1); 4345 SDValue V = N->getOperand(0); 4346 DebugLoc DL = N->getDebugLoc(); 4347 4348 SDValue Res; 4349 MulAmt >>= ShiftAmt; 4350 if (isPowerOf2_32(MulAmt - 1)) { 4351 // (mul x, 2^N + 1) => (add (shl x, N), x) 4352 Res = DAG.getNode(ISD::ADD, DL, VT, 4353 V, DAG.getNode(ISD::SHL, DL, VT, 4354 V, DAG.getConstant(Log2_32(MulAmt-1), 4355 MVT::i32))); 4356 } else if (isPowerOf2_32(MulAmt + 1)) { 4357 // (mul x, 2^N - 1) => (sub (shl x, N), x) 4358 Res = DAG.getNode(ISD::SUB, DL, VT, 4359 DAG.getNode(ISD::SHL, DL, VT, 4360 V, DAG.getConstant(Log2_32(MulAmt+1), 4361 MVT::i32)), 4362 V); 4363 } else 4364 return SDValue(); 4365 4366 if (ShiftAmt != 0) 4367 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 4368 DAG.getConstant(ShiftAmt, MVT::i32)); 4369 4370 // Do not add new nodes to DAG combiner worklist. 4371 DCI.CombineTo(N, Res, false); 4372 return SDValue(); 4373} 4374 4375/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 4376static SDValue PerformORCombine(SDNode *N, 4377 TargetLowering::DAGCombinerInfo &DCI, 4378 const ARMSubtarget *Subtarget) { 4379 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 4380 // reasonable. 4381 4382 // BFI is only available on V6T2+ 4383 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 4384 return SDValue(); 4385 4386 SelectionDAG &DAG = DCI.DAG; 4387 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 4388 DebugLoc DL = N->getDebugLoc(); 4389 // 1) or (and A, mask), val => ARMbfi A, val, mask 4390 // iff (val & mask) == val 4391 // 4392 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 4393 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 4394 // && CountPopulation_32(mask) == CountPopulation_32(~mask2) 4395 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 4396 // && CountPopulation_32(mask) == CountPopulation_32(~mask2) 4397 // (i.e., copy a bitfield value into another bitfield of the same width) 4398 if (N0.getOpcode() != ISD::AND) 4399 return SDValue(); 4400 4401 EVT VT = N->getValueType(0); 4402 if (VT != MVT::i32) 4403 return SDValue(); 4404 4405 4406 // The value and the mask need to be constants so we can verify this is 4407 // actually a bitfield set. If the mask is 0xffff, we can do better 4408 // via a movt instruction, so don't use BFI in that case. 4409 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4410 if (!C) 4411 return SDValue(); 4412 unsigned Mask = C->getZExtValue(); 4413 if (Mask == 0xffff) 4414 return SDValue(); 4415 SDValue Res; 4416 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 4417 if ((C = dyn_cast<ConstantSDNode>(N1))) { 4418 unsigned Val = C->getZExtValue(); 4419 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val) 4420 return SDValue(); 4421 Val >>= CountTrailingZeros_32(~Mask); 4422 4423 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), 4424 DAG.getConstant(Val, MVT::i32), 4425 DAG.getConstant(Mask, MVT::i32)); 4426 4427 // Do not add new nodes to DAG combiner worklist. 4428 DCI.CombineTo(N, Res, false); 4429 } else if (N1.getOpcode() == ISD::AND) { 4430 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 4431 C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 4432 if (!C) 4433 return SDValue(); 4434 unsigned Mask2 = C->getZExtValue(); 4435 4436 if (ARM::isBitFieldInvertedMask(Mask) && 4437 ARM::isBitFieldInvertedMask(~Mask2) && 4438 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) { 4439 // The pack halfword instruction works better for masks that fit it, 4440 // so use that when it's available. 4441 if (Subtarget->hasT2ExtractPack() && 4442 (Mask == 0xffff || Mask == 0xffff0000)) 4443 return SDValue(); 4444 // 2a 4445 unsigned lsb = CountTrailingZeros_32(Mask2); 4446 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 4447 DAG.getConstant(lsb, MVT::i32)); 4448 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res, 4449 DAG.getConstant(Mask, MVT::i32)); 4450 // Do not add new nodes to DAG combiner worklist. 4451 DCI.CombineTo(N, Res, false); 4452 } else if (ARM::isBitFieldInvertedMask(~Mask) && 4453 ARM::isBitFieldInvertedMask(Mask2) && 4454 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) { 4455 // The pack halfword instruction works better for masks that fit it, 4456 // so use that when it's available. 4457 if (Subtarget->hasT2ExtractPack() && 4458 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 4459 return SDValue(); 4460 // 2b 4461 unsigned lsb = CountTrailingZeros_32(Mask); 4462 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), 4463 DAG.getConstant(lsb, MVT::i32)); 4464 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 4465 DAG.getConstant(Mask2, MVT::i32)); 4466 // Do not add new nodes to DAG combiner worklist. 4467 DCI.CombineTo(N, Res, false); 4468 } 4469 } 4470 4471 return SDValue(); 4472} 4473 4474/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 4475/// ARMISD::VMOVRRD. 4476static SDValue PerformVMOVRRDCombine(SDNode *N, 4477 TargetLowering::DAGCombinerInfo &DCI) { 4478 // vmovrrd(vmovdrr x, y) -> x,y 4479 SDValue InDouble = N->getOperand(0); 4480 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 4481 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 4482 return SDValue(); 4483} 4484 4485/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 4486/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 4487static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 4488 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 4489 SDValue Op0 = N->getOperand(0); 4490 SDValue Op1 = N->getOperand(1); 4491 if (Op0.getOpcode() == ISD::BIT_CONVERT) 4492 Op0 = Op0.getOperand(0); 4493 if (Op1.getOpcode() == ISD::BIT_CONVERT) 4494 Op1 = Op1.getOperand(0); 4495 if (Op0.getOpcode() == ARMISD::VMOVRRD && 4496 Op0.getNode() == Op1.getNode() && 4497 Op0.getResNo() == 0 && Op1.getResNo() == 1) 4498 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4499 N->getValueType(0), Op0.getOperand(0)); 4500 return SDValue(); 4501} 4502 4503/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 4504/// ISD::BUILD_VECTOR. 4505static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) { 4506 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 4507 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 4508 // into a pair of GPRs, which is fine when the value is used as a scalar, 4509 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 4510 if (N->getNumOperands() == 2) 4511 return PerformVMOVDRRCombine(N, DAG); 4512 4513 return SDValue(); 4514} 4515 4516/// PerformVDUPLANECombine - Target-specific dag combine xforms for 4517/// ARMISD::VDUPLANE. 4518static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) { 4519 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 4520 // redundant. 4521 SDValue Op = N->getOperand(0); 4522 EVT VT = N->getValueType(0); 4523 4524 // Ignore bit_converts. 4525 while (Op.getOpcode() == ISD::BIT_CONVERT) 4526 Op = Op.getOperand(0); 4527 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 4528 return SDValue(); 4529 4530 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 4531 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 4532 // The canonical VMOV for a zero vector uses a 32-bit element size. 4533 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 4534 unsigned EltBits; 4535 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 4536 EltSize = 8; 4537 if (EltSize > VT.getVectorElementType().getSizeInBits()) 4538 return SDValue(); 4539 4540 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 4541} 4542 4543/// getVShiftImm - Check if this is a valid build_vector for the immediate 4544/// operand of a vector shift operation, where all the elements of the 4545/// build_vector must have the same constant integer value. 4546static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 4547 // Ignore bit_converts. 4548 while (Op.getOpcode() == ISD::BIT_CONVERT) 4549 Op = Op.getOperand(0); 4550 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4551 APInt SplatBits, SplatUndef; 4552 unsigned SplatBitSize; 4553 bool HasAnyUndefs; 4554 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 4555 HasAnyUndefs, ElementBits) || 4556 SplatBitSize > ElementBits) 4557 return false; 4558 Cnt = SplatBits.getSExtValue(); 4559 return true; 4560} 4561 4562/// isVShiftLImm - Check if this is a valid build_vector for the immediate 4563/// operand of a vector shift left operation. That value must be in the range: 4564/// 0 <= Value < ElementBits for a left shift; or 4565/// 0 <= Value <= ElementBits for a long left shift. 4566static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 4567 assert(VT.isVector() && "vector shift count is not a vector type"); 4568 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4569 if (! getVShiftImm(Op, ElementBits, Cnt)) 4570 return false; 4571 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 4572} 4573 4574/// isVShiftRImm - Check if this is a valid build_vector for the immediate 4575/// operand of a vector shift right operation. For a shift opcode, the value 4576/// is positive, but for an intrinsic the value count must be negative. The 4577/// absolute value must be in the range: 4578/// 1 <= |Value| <= ElementBits for a right shift; or 4579/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 4580static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 4581 int64_t &Cnt) { 4582 assert(VT.isVector() && "vector shift count is not a vector type"); 4583 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 4584 if (! getVShiftImm(Op, ElementBits, Cnt)) 4585 return false; 4586 if (isIntrinsic) 4587 Cnt = -Cnt; 4588 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 4589} 4590 4591/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 4592static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 4593 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 4594 switch (IntNo) { 4595 default: 4596 // Don't do anything for most intrinsics. 4597 break; 4598 4599 // Vector shifts: check for immediate versions and lower them. 4600 // Note: This is done during DAG combining instead of DAG legalizing because 4601 // the build_vectors for 64-bit vector element shift counts are generally 4602 // not legal, and it is hard to see their values after they get legalized to 4603 // loads from a constant pool. 4604 case Intrinsic::arm_neon_vshifts: 4605 case Intrinsic::arm_neon_vshiftu: 4606 case Intrinsic::arm_neon_vshiftls: 4607 case Intrinsic::arm_neon_vshiftlu: 4608 case Intrinsic::arm_neon_vshiftn: 4609 case Intrinsic::arm_neon_vrshifts: 4610 case Intrinsic::arm_neon_vrshiftu: 4611 case Intrinsic::arm_neon_vrshiftn: 4612 case Intrinsic::arm_neon_vqshifts: 4613 case Intrinsic::arm_neon_vqshiftu: 4614 case Intrinsic::arm_neon_vqshiftsu: 4615 case Intrinsic::arm_neon_vqshiftns: 4616 case Intrinsic::arm_neon_vqshiftnu: 4617 case Intrinsic::arm_neon_vqshiftnsu: 4618 case Intrinsic::arm_neon_vqrshiftns: 4619 case Intrinsic::arm_neon_vqrshiftnu: 4620 case Intrinsic::arm_neon_vqrshiftnsu: { 4621 EVT VT = N->getOperand(1).getValueType(); 4622 int64_t Cnt; 4623 unsigned VShiftOpc = 0; 4624 4625 switch (IntNo) { 4626 case Intrinsic::arm_neon_vshifts: 4627 case Intrinsic::arm_neon_vshiftu: 4628 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 4629 VShiftOpc = ARMISD::VSHL; 4630 break; 4631 } 4632 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 4633 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 4634 ARMISD::VSHRs : ARMISD::VSHRu); 4635 break; 4636 } 4637 return SDValue(); 4638 4639 case Intrinsic::arm_neon_vshiftls: 4640 case Intrinsic::arm_neon_vshiftlu: 4641 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 4642 break; 4643 llvm_unreachable("invalid shift count for vshll intrinsic"); 4644 4645 case Intrinsic::arm_neon_vrshifts: 4646 case Intrinsic::arm_neon_vrshiftu: 4647 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 4648 break; 4649 return SDValue(); 4650 4651 case Intrinsic::arm_neon_vqshifts: 4652 case Intrinsic::arm_neon_vqshiftu: 4653 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4654 break; 4655 return SDValue(); 4656 4657 case Intrinsic::arm_neon_vqshiftsu: 4658 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 4659 break; 4660 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 4661 4662 case Intrinsic::arm_neon_vshiftn: 4663 case Intrinsic::arm_neon_vrshiftn: 4664 case Intrinsic::arm_neon_vqshiftns: 4665 case Intrinsic::arm_neon_vqshiftnu: 4666 case Intrinsic::arm_neon_vqshiftnsu: 4667 case Intrinsic::arm_neon_vqrshiftns: 4668 case Intrinsic::arm_neon_vqrshiftnu: 4669 case Intrinsic::arm_neon_vqrshiftnsu: 4670 // Narrowing shifts require an immediate right shift. 4671 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 4672 break; 4673 llvm_unreachable("invalid shift count for narrowing vector shift " 4674 "intrinsic"); 4675 4676 default: 4677 llvm_unreachable("unhandled vector shift"); 4678 } 4679 4680 switch (IntNo) { 4681 case Intrinsic::arm_neon_vshifts: 4682 case Intrinsic::arm_neon_vshiftu: 4683 // Opcode already set above. 4684 break; 4685 case Intrinsic::arm_neon_vshiftls: 4686 case Intrinsic::arm_neon_vshiftlu: 4687 if (Cnt == VT.getVectorElementType().getSizeInBits()) 4688 VShiftOpc = ARMISD::VSHLLi; 4689 else 4690 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 4691 ARMISD::VSHLLs : ARMISD::VSHLLu); 4692 break; 4693 case Intrinsic::arm_neon_vshiftn: 4694 VShiftOpc = ARMISD::VSHRN; break; 4695 case Intrinsic::arm_neon_vrshifts: 4696 VShiftOpc = ARMISD::VRSHRs; break; 4697 case Intrinsic::arm_neon_vrshiftu: 4698 VShiftOpc = ARMISD::VRSHRu; break; 4699 case Intrinsic::arm_neon_vrshiftn: 4700 VShiftOpc = ARMISD::VRSHRN; break; 4701 case Intrinsic::arm_neon_vqshifts: 4702 VShiftOpc = ARMISD::VQSHLs; break; 4703 case Intrinsic::arm_neon_vqshiftu: 4704 VShiftOpc = ARMISD::VQSHLu; break; 4705 case Intrinsic::arm_neon_vqshiftsu: 4706 VShiftOpc = ARMISD::VQSHLsu; break; 4707 case Intrinsic::arm_neon_vqshiftns: 4708 VShiftOpc = ARMISD::VQSHRNs; break; 4709 case Intrinsic::arm_neon_vqshiftnu: 4710 VShiftOpc = ARMISD::VQSHRNu; break; 4711 case Intrinsic::arm_neon_vqshiftnsu: 4712 VShiftOpc = ARMISD::VQSHRNsu; break; 4713 case Intrinsic::arm_neon_vqrshiftns: 4714 VShiftOpc = ARMISD::VQRSHRNs; break; 4715 case Intrinsic::arm_neon_vqrshiftnu: 4716 VShiftOpc = ARMISD::VQRSHRNu; break; 4717 case Intrinsic::arm_neon_vqrshiftnsu: 4718 VShiftOpc = ARMISD::VQRSHRNsu; break; 4719 } 4720 4721 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4722 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 4723 } 4724 4725 case Intrinsic::arm_neon_vshiftins: { 4726 EVT VT = N->getOperand(1).getValueType(); 4727 int64_t Cnt; 4728 unsigned VShiftOpc = 0; 4729 4730 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 4731 VShiftOpc = ARMISD::VSLI; 4732 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 4733 VShiftOpc = ARMISD::VSRI; 4734 else { 4735 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 4736 } 4737 4738 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 4739 N->getOperand(1), N->getOperand(2), 4740 DAG.getConstant(Cnt, MVT::i32)); 4741 } 4742 4743 case Intrinsic::arm_neon_vqrshifts: 4744 case Intrinsic::arm_neon_vqrshiftu: 4745 // No immediate versions of these to check for. 4746 break; 4747 } 4748 4749 return SDValue(); 4750} 4751 4752/// PerformShiftCombine - Checks for immediate versions of vector shifts and 4753/// lowers them. As with the vector shift intrinsics, this is done during DAG 4754/// combining instead of DAG legalizing because the build_vectors for 64-bit 4755/// vector element shift counts are generally not legal, and it is hard to see 4756/// their values after they get legalized to loads from a constant pool. 4757static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 4758 const ARMSubtarget *ST) { 4759 EVT VT = N->getValueType(0); 4760 4761 // Nothing to be done for scalar shifts. 4762 if (! VT.isVector()) 4763 return SDValue(); 4764 4765 assert(ST->hasNEON() && "unexpected vector shift"); 4766 int64_t Cnt; 4767 4768 switch (N->getOpcode()) { 4769 default: llvm_unreachable("unexpected shift opcode"); 4770 4771 case ISD::SHL: 4772 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 4773 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 4774 DAG.getConstant(Cnt, MVT::i32)); 4775 break; 4776 4777 case ISD::SRA: 4778 case ISD::SRL: 4779 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 4780 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 4781 ARMISD::VSHRs : ARMISD::VSHRu); 4782 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 4783 DAG.getConstant(Cnt, MVT::i32)); 4784 } 4785 } 4786 return SDValue(); 4787} 4788 4789/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 4790/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 4791static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 4792 const ARMSubtarget *ST) { 4793 SDValue N0 = N->getOperand(0); 4794 4795 // Check for sign- and zero-extensions of vector extract operations of 8- 4796 // and 16-bit vector elements. NEON supports these directly. They are 4797 // handled during DAG combining because type legalization will promote them 4798 // to 32-bit types and it is messy to recognize the operations after that. 4799 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 4800 SDValue Vec = N0.getOperand(0); 4801 SDValue Lane = N0.getOperand(1); 4802 EVT VT = N->getValueType(0); 4803 EVT EltVT = N0.getValueType(); 4804 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4805 4806 if (VT == MVT::i32 && 4807 (EltVT == MVT::i8 || EltVT == MVT::i16) && 4808 TLI.isTypeLegal(Vec.getValueType())) { 4809 4810 unsigned Opc = 0; 4811 switch (N->getOpcode()) { 4812 default: llvm_unreachable("unexpected opcode"); 4813 case ISD::SIGN_EXTEND: 4814 Opc = ARMISD::VGETLANEs; 4815 break; 4816 case ISD::ZERO_EXTEND: 4817 case ISD::ANY_EXTEND: 4818 Opc = ARMISD::VGETLANEu; 4819 break; 4820 } 4821 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 4822 } 4823 } 4824 4825 return SDValue(); 4826} 4827 4828/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 4829/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 4830static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 4831 const ARMSubtarget *ST) { 4832 // If the target supports NEON, try to use vmax/vmin instructions for f32 4833 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 4834 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 4835 // a NaN; only do the transformation when it matches that behavior. 4836 4837 // For now only do this when using NEON for FP operations; if using VFP, it 4838 // is not obvious that the benefit outweighs the cost of switching to the 4839 // NEON pipeline. 4840 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 4841 N->getValueType(0) != MVT::f32) 4842 return SDValue(); 4843 4844 SDValue CondLHS = N->getOperand(0); 4845 SDValue CondRHS = N->getOperand(1); 4846 SDValue LHS = N->getOperand(2); 4847 SDValue RHS = N->getOperand(3); 4848 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 4849 4850 unsigned Opcode = 0; 4851 bool IsReversed; 4852 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 4853 IsReversed = false; // x CC y ? x : y 4854 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 4855 IsReversed = true ; // x CC y ? y : x 4856 } else { 4857 return SDValue(); 4858 } 4859 4860 bool IsUnordered; 4861 switch (CC) { 4862 default: break; 4863 case ISD::SETOLT: 4864 case ISD::SETOLE: 4865 case ISD::SETLT: 4866 case ISD::SETLE: 4867 case ISD::SETULT: 4868 case ISD::SETULE: 4869 // If LHS is NaN, an ordered comparison will be false and the result will 4870 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 4871 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4872 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 4873 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4874 break; 4875 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 4876 // will return -0, so vmin can only be used for unsafe math or if one of 4877 // the operands is known to be nonzero. 4878 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 4879 !UnsafeFPMath && 4880 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4881 break; 4882 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 4883 break; 4884 4885 case ISD::SETOGT: 4886 case ISD::SETOGE: 4887 case ISD::SETGT: 4888 case ISD::SETGE: 4889 case ISD::SETUGT: 4890 case ISD::SETUGE: 4891 // If LHS is NaN, an ordered comparison will be false and the result will 4892 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 4893 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 4894 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 4895 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 4896 break; 4897 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 4898 // will return +0, so vmax can only be used for unsafe math or if one of 4899 // the operands is known to be nonzero. 4900 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 4901 !UnsafeFPMath && 4902 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 4903 break; 4904 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 4905 break; 4906 } 4907 4908 if (!Opcode) 4909 return SDValue(); 4910 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 4911} 4912 4913SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 4914 DAGCombinerInfo &DCI) const { 4915 switch (N->getOpcode()) { 4916 default: break; 4917 case ISD::ADD: return PerformADDCombine(N, DCI); 4918 case ISD::SUB: return PerformSUBCombine(N, DCI); 4919 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 4920 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 4921 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 4922 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 4923 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); 4924 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG); 4925 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 4926 case ISD::SHL: 4927 case ISD::SRA: 4928 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 4929 case ISD::SIGN_EXTEND: 4930 case ISD::ZERO_EXTEND: 4931 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 4932 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 4933 } 4934 return SDValue(); 4935} 4936 4937bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 4938 if (!Subtarget->allowsUnalignedMem()) 4939 return false; 4940 4941 switch (VT.getSimpleVT().SimpleTy) { 4942 default: 4943 return false; 4944 case MVT::i8: 4945 case MVT::i16: 4946 case MVT::i32: 4947 return true; 4948 // FIXME: VLD1 etc with standard alignment is legal. 4949 } 4950} 4951 4952static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 4953 if (V < 0) 4954 return false; 4955 4956 unsigned Scale = 1; 4957 switch (VT.getSimpleVT().SimpleTy) { 4958 default: return false; 4959 case MVT::i1: 4960 case MVT::i8: 4961 // Scale == 1; 4962 break; 4963 case MVT::i16: 4964 // Scale == 2; 4965 Scale = 2; 4966 break; 4967 case MVT::i32: 4968 // Scale == 4; 4969 Scale = 4; 4970 break; 4971 } 4972 4973 if ((V & (Scale - 1)) != 0) 4974 return false; 4975 V /= Scale; 4976 return V == (V & ((1LL << 5) - 1)); 4977} 4978 4979static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 4980 const ARMSubtarget *Subtarget) { 4981 bool isNeg = false; 4982 if (V < 0) { 4983 isNeg = true; 4984 V = - V; 4985 } 4986 4987 switch (VT.getSimpleVT().SimpleTy) { 4988 default: return false; 4989 case MVT::i1: 4990 case MVT::i8: 4991 case MVT::i16: 4992 case MVT::i32: 4993 // + imm12 or - imm8 4994 if (isNeg) 4995 return V == (V & ((1LL << 8) - 1)); 4996 return V == (V & ((1LL << 12) - 1)); 4997 case MVT::f32: 4998 case MVT::f64: 4999 // Same as ARM mode. FIXME: NEON? 5000 if (!Subtarget->hasVFP2()) 5001 return false; 5002 if ((V & 3) != 0) 5003 return false; 5004 V >>= 2; 5005 return V == (V & ((1LL << 8) - 1)); 5006 } 5007} 5008 5009/// isLegalAddressImmediate - Return true if the integer value can be used 5010/// as the offset of the target addressing mode for load / store of the 5011/// given type. 5012static bool isLegalAddressImmediate(int64_t V, EVT VT, 5013 const ARMSubtarget *Subtarget) { 5014 if (V == 0) 5015 return true; 5016 5017 if (!VT.isSimple()) 5018 return false; 5019 5020 if (Subtarget->isThumb1Only()) 5021 return isLegalT1AddressImmediate(V, VT); 5022 else if (Subtarget->isThumb2()) 5023 return isLegalT2AddressImmediate(V, VT, Subtarget); 5024 5025 // ARM mode. 5026 if (V < 0) 5027 V = - V; 5028 switch (VT.getSimpleVT().SimpleTy) { 5029 default: return false; 5030 case MVT::i1: 5031 case MVT::i8: 5032 case MVT::i32: 5033 // +- imm12 5034 return V == (V & ((1LL << 12) - 1)); 5035 case MVT::i16: 5036 // +- imm8 5037 return V == (V & ((1LL << 8) - 1)); 5038 case MVT::f32: 5039 case MVT::f64: 5040 if (!Subtarget->hasVFP2()) // FIXME: NEON? 5041 return false; 5042 if ((V & 3) != 0) 5043 return false; 5044 V >>= 2; 5045 return V == (V & ((1LL << 8) - 1)); 5046 } 5047} 5048 5049bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 5050 EVT VT) const { 5051 int Scale = AM.Scale; 5052 if (Scale < 0) 5053 return false; 5054 5055 switch (VT.getSimpleVT().SimpleTy) { 5056 default: return false; 5057 case MVT::i1: 5058 case MVT::i8: 5059 case MVT::i16: 5060 case MVT::i32: 5061 if (Scale == 1) 5062 return true; 5063 // r + r << imm 5064 Scale = Scale & ~1; 5065 return Scale == 2 || Scale == 4 || Scale == 8; 5066 case MVT::i64: 5067 // r + r 5068 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 5069 return true; 5070 return false; 5071 case MVT::isVoid: 5072 // Note, we allow "void" uses (basically, uses that aren't loads or 5073 // stores), because arm allows folding a scale into many arithmetic 5074 // operations. This should be made more precise and revisited later. 5075 5076 // Allow r << imm, but the imm has to be a multiple of two. 5077 if (Scale & 1) return false; 5078 return isPowerOf2_32(Scale); 5079 } 5080} 5081 5082/// isLegalAddressingMode - Return true if the addressing mode represented 5083/// by AM is legal for this target, for a load/store of the specified type. 5084bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5085 const Type *Ty) const { 5086 EVT VT = getValueType(Ty, true); 5087 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 5088 return false; 5089 5090 // Can never fold addr of global into load/store. 5091 if (AM.BaseGV) 5092 return false; 5093 5094 switch (AM.Scale) { 5095 case 0: // no scale reg, must be "r+i" or "r", or "i". 5096 break; 5097 case 1: 5098 if (Subtarget->isThumb1Only()) 5099 return false; 5100 // FALL THROUGH. 5101 default: 5102 // ARM doesn't support any R+R*scale+imm addr modes. 5103 if (AM.BaseOffs) 5104 return false; 5105 5106 if (!VT.isSimple()) 5107 return false; 5108 5109 if (Subtarget->isThumb2()) 5110 return isLegalT2ScaledAddressingMode(AM, VT); 5111 5112 int Scale = AM.Scale; 5113 switch (VT.getSimpleVT().SimpleTy) { 5114 default: return false; 5115 case MVT::i1: 5116 case MVT::i8: 5117 case MVT::i32: 5118 if (Scale < 0) Scale = -Scale; 5119 if (Scale == 1) 5120 return true; 5121 // r + r << imm 5122 return isPowerOf2_32(Scale & ~1); 5123 case MVT::i16: 5124 case MVT::i64: 5125 // r + r 5126 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 5127 return true; 5128 return false; 5129 5130 case MVT::isVoid: 5131 // Note, we allow "void" uses (basically, uses that aren't loads or 5132 // stores), because arm allows folding a scale into many arithmetic 5133 // operations. This should be made more precise and revisited later. 5134 5135 // Allow r << imm, but the imm has to be a multiple of two. 5136 if (Scale & 1) return false; 5137 return isPowerOf2_32(Scale); 5138 } 5139 break; 5140 } 5141 return true; 5142} 5143 5144/// isLegalICmpImmediate - Return true if the specified immediate is legal 5145/// icmp immediate, that is the target has icmp instructions which can compare 5146/// a register against the immediate without having to materialize the 5147/// immediate into a register. 5148bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 5149 if (!Subtarget->isThumb()) 5150 return ARM_AM::getSOImmVal(Imm) != -1; 5151 if (Subtarget->isThumb2()) 5152 return ARM_AM::getT2SOImmVal(Imm) != -1; 5153 return Imm >= 0 && Imm <= 255; 5154} 5155 5156static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 5157 bool isSEXTLoad, SDValue &Base, 5158 SDValue &Offset, bool &isInc, 5159 SelectionDAG &DAG) { 5160 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 5161 return false; 5162 5163 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 5164 // AddressingMode 3 5165 Base = Ptr->getOperand(0); 5166 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 5167 int RHSC = (int)RHS->getZExtValue(); 5168 if (RHSC < 0 && RHSC > -256) { 5169 assert(Ptr->getOpcode() == ISD::ADD); 5170 isInc = false; 5171 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 5172 return true; 5173 } 5174 } 5175 isInc = (Ptr->getOpcode() == ISD::ADD); 5176 Offset = Ptr->getOperand(1); 5177 return true; 5178 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 5179 // AddressingMode 2 5180 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 5181 int RHSC = (int)RHS->getZExtValue(); 5182 if (RHSC < 0 && RHSC > -0x1000) { 5183 assert(Ptr->getOpcode() == ISD::ADD); 5184 isInc = false; 5185 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 5186 Base = Ptr->getOperand(0); 5187 return true; 5188 } 5189 } 5190 5191 if (Ptr->getOpcode() == ISD::ADD) { 5192 isInc = true; 5193 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 5194 if (ShOpcVal != ARM_AM::no_shift) { 5195 Base = Ptr->getOperand(1); 5196 Offset = Ptr->getOperand(0); 5197 } else { 5198 Base = Ptr->getOperand(0); 5199 Offset = Ptr->getOperand(1); 5200 } 5201 return true; 5202 } 5203 5204 isInc = (Ptr->getOpcode() == ISD::ADD); 5205 Base = Ptr->getOperand(0); 5206 Offset = Ptr->getOperand(1); 5207 return true; 5208 } 5209 5210 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 5211 return false; 5212} 5213 5214static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 5215 bool isSEXTLoad, SDValue &Base, 5216 SDValue &Offset, bool &isInc, 5217 SelectionDAG &DAG) { 5218 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 5219 return false; 5220 5221 Base = Ptr->getOperand(0); 5222 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 5223 int RHSC = (int)RHS->getZExtValue(); 5224 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 5225 assert(Ptr->getOpcode() == ISD::ADD); 5226 isInc = false; 5227 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 5228 return true; 5229 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 5230 isInc = Ptr->getOpcode() == ISD::ADD; 5231 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 5232 return true; 5233 } 5234 } 5235 5236 return false; 5237} 5238 5239/// getPreIndexedAddressParts - returns true by value, base pointer and 5240/// offset pointer and addressing mode by reference if the node's address 5241/// can be legally represented as pre-indexed load / store address. 5242bool 5243ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 5244 SDValue &Offset, 5245 ISD::MemIndexedMode &AM, 5246 SelectionDAG &DAG) const { 5247 if (Subtarget->isThumb1Only()) 5248 return false; 5249 5250 EVT VT; 5251 SDValue Ptr; 5252 bool isSEXTLoad = false; 5253 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5254 Ptr = LD->getBasePtr(); 5255 VT = LD->getMemoryVT(); 5256 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 5257 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5258 Ptr = ST->getBasePtr(); 5259 VT = ST->getMemoryVT(); 5260 } else 5261 return false; 5262 5263 bool isInc; 5264 bool isLegal = false; 5265 if (Subtarget->isThumb2()) 5266 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 5267 Offset, isInc, DAG); 5268 else 5269 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 5270 Offset, isInc, DAG); 5271 if (!isLegal) 5272 return false; 5273 5274 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 5275 return true; 5276} 5277 5278/// getPostIndexedAddressParts - returns true by value, base pointer and 5279/// offset pointer and addressing mode by reference if this node can be 5280/// combined with a load / store to form a post-indexed load / store. 5281bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 5282 SDValue &Base, 5283 SDValue &Offset, 5284 ISD::MemIndexedMode &AM, 5285 SelectionDAG &DAG) const { 5286 if (Subtarget->isThumb1Only()) 5287 return false; 5288 5289 EVT VT; 5290 SDValue Ptr; 5291 bool isSEXTLoad = false; 5292 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5293 VT = LD->getMemoryVT(); 5294 Ptr = LD->getBasePtr(); 5295 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 5296 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5297 VT = ST->getMemoryVT(); 5298 Ptr = ST->getBasePtr(); 5299 } else 5300 return false; 5301 5302 bool isInc; 5303 bool isLegal = false; 5304 if (Subtarget->isThumb2()) 5305 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 5306 isInc, DAG); 5307 else 5308 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 5309 isInc, DAG); 5310 if (!isLegal) 5311 return false; 5312 5313 if (Ptr != Base) { 5314 // Swap base ptr and offset to catch more post-index load / store when 5315 // it's legal. In Thumb2 mode, offset must be an immediate. 5316 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 5317 !Subtarget->isThumb2()) 5318 std::swap(Base, Offset); 5319 5320 // Post-indexed load / store update the base pointer. 5321 if (Ptr != Base) 5322 return false; 5323 } 5324 5325 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 5326 return true; 5327} 5328 5329void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5330 const APInt &Mask, 5331 APInt &KnownZero, 5332 APInt &KnownOne, 5333 const SelectionDAG &DAG, 5334 unsigned Depth) const { 5335 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5336 switch (Op.getOpcode()) { 5337 default: break; 5338 case ARMISD::CMOV: { 5339 // Bits are known zero/one if known on the LHS and RHS. 5340 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 5341 if (KnownZero == 0 && KnownOne == 0) return; 5342 5343 APInt KnownZeroRHS, KnownOneRHS; 5344 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 5345 KnownZeroRHS, KnownOneRHS, Depth+1); 5346 KnownZero &= KnownZeroRHS; 5347 KnownOne &= KnownOneRHS; 5348 return; 5349 } 5350 } 5351} 5352 5353//===----------------------------------------------------------------------===// 5354// ARM Inline Assembly Support 5355//===----------------------------------------------------------------------===// 5356 5357/// getConstraintType - Given a constraint letter, return the type of 5358/// constraint it is for this target. 5359ARMTargetLowering::ConstraintType 5360ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 5361 if (Constraint.size() == 1) { 5362 switch (Constraint[0]) { 5363 default: break; 5364 case 'l': return C_RegisterClass; 5365 case 'w': return C_RegisterClass; 5366 } 5367 } 5368 return TargetLowering::getConstraintType(Constraint); 5369} 5370 5371std::pair<unsigned, const TargetRegisterClass*> 5372ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5373 EVT VT) const { 5374 if (Constraint.size() == 1) { 5375 // GCC ARM Constraint Letters 5376 switch (Constraint[0]) { 5377 case 'l': 5378 if (Subtarget->isThumb()) 5379 return std::make_pair(0U, ARM::tGPRRegisterClass); 5380 else 5381 return std::make_pair(0U, ARM::GPRRegisterClass); 5382 case 'r': 5383 return std::make_pair(0U, ARM::GPRRegisterClass); 5384 case 'w': 5385 if (VT == MVT::f32) 5386 return std::make_pair(0U, ARM::SPRRegisterClass); 5387 if (VT.getSizeInBits() == 64) 5388 return std::make_pair(0U, ARM::DPRRegisterClass); 5389 if (VT.getSizeInBits() == 128) 5390 return std::make_pair(0U, ARM::QPRRegisterClass); 5391 break; 5392 } 5393 } 5394 if (StringRef("{cc}").equals_lower(Constraint)) 5395 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 5396 5397 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5398} 5399 5400std::vector<unsigned> ARMTargetLowering:: 5401getRegClassForInlineAsmConstraint(const std::string &Constraint, 5402 EVT VT) const { 5403 if (Constraint.size() != 1) 5404 return std::vector<unsigned>(); 5405 5406 switch (Constraint[0]) { // GCC ARM Constraint Letters 5407 default: break; 5408 case 'l': 5409 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5410 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5411 0); 5412 case 'r': 5413 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 5414 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 5415 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 5416 ARM::R12, ARM::LR, 0); 5417 case 'w': 5418 if (VT == MVT::f32) 5419 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 5420 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 5421 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 5422 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 5423 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 5424 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 5425 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 5426 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 5427 if (VT.getSizeInBits() == 64) 5428 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 5429 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 5430 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 5431 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 5432 if (VT.getSizeInBits() == 128) 5433 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 5434 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0); 5435 break; 5436 } 5437 5438 return std::vector<unsigned>(); 5439} 5440 5441/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5442/// vector. If it is invalid, don't add anything to Ops. 5443void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5444 char Constraint, 5445 std::vector<SDValue>&Ops, 5446 SelectionDAG &DAG) const { 5447 SDValue Result(0, 0); 5448 5449 switch (Constraint) { 5450 default: break; 5451 case 'I': case 'J': case 'K': case 'L': 5452 case 'M': case 'N': case 'O': 5453 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 5454 if (!C) 5455 return; 5456 5457 int64_t CVal64 = C->getSExtValue(); 5458 int CVal = (int) CVal64; 5459 // None of these constraints allow values larger than 32 bits. Check 5460 // that the value fits in an int. 5461 if (CVal != CVal64) 5462 return; 5463 5464 switch (Constraint) { 5465 case 'I': 5466 if (Subtarget->isThumb1Only()) { 5467 // This must be a constant between 0 and 255, for ADD 5468 // immediates. 5469 if (CVal >= 0 && CVal <= 255) 5470 break; 5471 } else if (Subtarget->isThumb2()) { 5472 // A constant that can be used as an immediate value in a 5473 // data-processing instruction. 5474 if (ARM_AM::getT2SOImmVal(CVal) != -1) 5475 break; 5476 } else { 5477 // A constant that can be used as an immediate value in a 5478 // data-processing instruction. 5479 if (ARM_AM::getSOImmVal(CVal) != -1) 5480 break; 5481 } 5482 return; 5483 5484 case 'J': 5485 if (Subtarget->isThumb()) { // FIXME thumb2 5486 // This must be a constant between -255 and -1, for negated ADD 5487 // immediates. This can be used in GCC with an "n" modifier that 5488 // prints the negated value, for use with SUB instructions. It is 5489 // not useful otherwise but is implemented for compatibility. 5490 if (CVal >= -255 && CVal <= -1) 5491 break; 5492 } else { 5493 // This must be a constant between -4095 and 4095. It is not clear 5494 // what this constraint is intended for. Implemented for 5495 // compatibility with GCC. 5496 if (CVal >= -4095 && CVal <= 4095) 5497 break; 5498 } 5499 return; 5500 5501 case 'K': 5502 if (Subtarget->isThumb1Only()) { 5503 // A 32-bit value where only one byte has a nonzero value. Exclude 5504 // zero to match GCC. This constraint is used by GCC internally for 5505 // constants that can be loaded with a move/shift combination. 5506 // It is not useful otherwise but is implemented for compatibility. 5507 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 5508 break; 5509 } else if (Subtarget->isThumb2()) { 5510 // A constant whose bitwise inverse can be used as an immediate 5511 // value in a data-processing instruction. This can be used in GCC 5512 // with a "B" modifier that prints the inverted value, for use with 5513 // BIC and MVN instructions. It is not useful otherwise but is 5514 // implemented for compatibility. 5515 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 5516 break; 5517 } else { 5518 // A constant whose bitwise inverse can be used as an immediate 5519 // value in a data-processing instruction. This can be used in GCC 5520 // with a "B" modifier that prints the inverted value, for use with 5521 // BIC and MVN instructions. It is not useful otherwise but is 5522 // implemented for compatibility. 5523 if (ARM_AM::getSOImmVal(~CVal) != -1) 5524 break; 5525 } 5526 return; 5527 5528 case 'L': 5529 if (Subtarget->isThumb1Only()) { 5530 // This must be a constant between -7 and 7, 5531 // for 3-operand ADD/SUB immediate instructions. 5532 if (CVal >= -7 && CVal < 7) 5533 break; 5534 } else if (Subtarget->isThumb2()) { 5535 // A constant whose negation can be used as an immediate value in a 5536 // data-processing instruction. This can be used in GCC with an "n" 5537 // modifier that prints the negated value, for use with SUB 5538 // instructions. It is not useful otherwise but is implemented for 5539 // compatibility. 5540 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 5541 break; 5542 } else { 5543 // A constant whose negation can be used as an immediate value in a 5544 // data-processing instruction. This can be used in GCC with an "n" 5545 // modifier that prints the negated value, for use with SUB 5546 // instructions. It is not useful otherwise but is implemented for 5547 // compatibility. 5548 if (ARM_AM::getSOImmVal(-CVal) != -1) 5549 break; 5550 } 5551 return; 5552 5553 case 'M': 5554 if (Subtarget->isThumb()) { // FIXME thumb2 5555 // This must be a multiple of 4 between 0 and 1020, for 5556 // ADD sp + immediate. 5557 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 5558 break; 5559 } else { 5560 // A power of two or a constant between 0 and 32. This is used in 5561 // GCC for the shift amount on shifted register operands, but it is 5562 // useful in general for any shift amounts. 5563 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 5564 break; 5565 } 5566 return; 5567 5568 case 'N': 5569 if (Subtarget->isThumb()) { // FIXME thumb2 5570 // This must be a constant between 0 and 31, for shift amounts. 5571 if (CVal >= 0 && CVal <= 31) 5572 break; 5573 } 5574 return; 5575 5576 case 'O': 5577 if (Subtarget->isThumb()) { // FIXME thumb2 5578 // This must be a multiple of 4 between -508 and 508, for 5579 // ADD/SUB sp = sp + immediate. 5580 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 5581 break; 5582 } 5583 return; 5584 } 5585 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 5586 break; 5587 } 5588 5589 if (Result.getNode()) { 5590 Ops.push_back(Result); 5591 return; 5592 } 5593 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5594} 5595 5596bool 5597ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5598 // The ARM target isn't yet aware of offsets. 5599 return false; 5600} 5601 5602int ARM::getVFPf32Imm(const APFloat &FPImm) { 5603 APInt Imm = FPImm.bitcastToAPInt(); 5604 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 5605 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 5606 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 5607 5608 // We can handle 4 bits of mantissa. 5609 // mantissa = (16+UInt(e:f:g:h))/16. 5610 if (Mantissa & 0x7ffff) 5611 return -1; 5612 Mantissa >>= 19; 5613 if ((Mantissa & 0xf) != Mantissa) 5614 return -1; 5615 5616 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5617 if (Exp < -3 || Exp > 4) 5618 return -1; 5619 Exp = ((Exp+3) & 0x7) ^ 4; 5620 5621 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5622} 5623 5624int ARM::getVFPf64Imm(const APFloat &FPImm) { 5625 APInt Imm = FPImm.bitcastToAPInt(); 5626 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 5627 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 5628 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL; 5629 5630 // We can handle 4 bits of mantissa. 5631 // mantissa = (16+UInt(e:f:g:h))/16. 5632 if (Mantissa & 0xffffffffffffLL) 5633 return -1; 5634 Mantissa >>= 48; 5635 if ((Mantissa & 0xf) != Mantissa) 5636 return -1; 5637 5638 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 5639 if (Exp < -3 || Exp > 4) 5640 return -1; 5641 Exp = ((Exp+3) & 0x7) ^ 4; 5642 5643 return ((int)Sign << 7) | (Exp << 4) | Mantissa; 5644} 5645 5646bool ARM::isBitFieldInvertedMask(unsigned v) { 5647 if (v == 0xffffffff) 5648 return 0; 5649 // there can be 1's on either or both "outsides", all the "inside" 5650 // bits must be 0's 5651 unsigned int lsb = 0, msb = 31; 5652 while (v & (1 << msb)) --msb; 5653 while (v & (1 << lsb)) ++lsb; 5654 for (unsigned int i = lsb; i <= msb; ++i) { 5655 if (v & (1 << i)) 5656 return 0; 5657 } 5658 return 1; 5659} 5660 5661/// isFPImmLegal - Returns true if the target can instruction select the 5662/// specified FP immediate natively. If false, the legalizer will 5663/// materialize the FP immediate as a load from a constant pool. 5664bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 5665 if (!Subtarget->hasVFP3()) 5666 return false; 5667 if (VT == MVT::f32) 5668 return ARM::getVFPf32Imm(Imm) != -1; 5669 if (VT == MVT::f64) 5670 return ARM::getVFPf64Imm(Imm) != -1; 5671 return false; 5672} 5673 5674/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 5675/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 5676/// specified in the intrinsic calls. 5677bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 5678 const CallInst &I, 5679 unsigned Intrinsic) const { 5680 switch (Intrinsic) { 5681 case Intrinsic::arm_neon_vld1: 5682 case Intrinsic::arm_neon_vld2: 5683 case Intrinsic::arm_neon_vld3: 5684 case Intrinsic::arm_neon_vld4: 5685 case Intrinsic::arm_neon_vld2lane: 5686 case Intrinsic::arm_neon_vld3lane: 5687 case Intrinsic::arm_neon_vld4lane: { 5688 Info.opc = ISD::INTRINSIC_W_CHAIN; 5689 // Conservatively set memVT to the entire set of vectors loaded. 5690 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 5691 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 5692 Info.ptrVal = I.getArgOperand(0); 5693 Info.offset = 0; 5694 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 5695 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 5696 Info.vol = false; // volatile loads with NEON intrinsics not supported 5697 Info.readMem = true; 5698 Info.writeMem = false; 5699 return true; 5700 } 5701 case Intrinsic::arm_neon_vst1: 5702 case Intrinsic::arm_neon_vst2: 5703 case Intrinsic::arm_neon_vst3: 5704 case Intrinsic::arm_neon_vst4: 5705 case Intrinsic::arm_neon_vst2lane: 5706 case Intrinsic::arm_neon_vst3lane: 5707 case Intrinsic::arm_neon_vst4lane: { 5708 Info.opc = ISD::INTRINSIC_VOID; 5709 // Conservatively set memVT to the entire set of vectors stored. 5710 unsigned NumElts = 0; 5711 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 5712 const Type *ArgTy = I.getArgOperand(ArgI)->getType(); 5713 if (!ArgTy->isVectorTy()) 5714 break; 5715 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 5716 } 5717 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 5718 Info.ptrVal = I.getArgOperand(0); 5719 Info.offset = 0; 5720 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 5721 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 5722 Info.vol = false; // volatile stores with NEON intrinsics not supported 5723 Info.readMem = false; 5724 Info.writeMem = true; 5725 return true; 5726 } 5727 default: 5728 break; 5729 } 5730 5731 return false; 5732} 5733