ARMISelLowering.cpp revision 2fef4573df6fd645f4401302d21c16e72418e3a8
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMCallingConv.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "MCTargetDesc/ARMAddressingModes.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/IntrinsicLowering.h" 37#include "llvm/CodeGen/MachineBasicBlock.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/MC/MCSectionMachO.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/ADT/StringExtras.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/Support/CommandLine.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include <sstream> 55using namespace llvm; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 59 60// This option should go away when tail calls fully work. 61static cl::opt<bool> 62EnableARMTailCalls("arm-tail-calls", cl::Hidden, 63 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 64 cl::init(false)); 65 66cl::opt<bool> 67EnableARMLongCalls("arm-long-calls", cl::Hidden, 68 cl::desc("Generate calls via indirect call instructions"), 69 cl::init(false)); 70 71static cl::opt<bool> 72ARMInterworking("arm-interworking", cl::Hidden, 73 cl::desc("Enable / disable ARM interworking (for debugging only)"), 74 cl::init(true)); 75 76namespace llvm { 77 class ARMCCState : public CCState { 78 public: 79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 81 LLVMContext &C, ParmContext PC) 82 : CCState(CC, isVarArg, MF, TM, locs, C) { 83 assert(((PC == Call) || (PC == Prologue)) && 84 "ARMCCState users must specify whether their context is call" 85 "or prologue generation."); 86 CallOrPrologue = PC; 87 } 88 }; 89} 90 91// The APCS parameter registers. 92static const unsigned GPRArgRegs[] = { 93 ARM::R0, ARM::R1, ARM::R2, ARM::R3 94}; 95 96void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 97 EVT PromotedBitwiseVT) { 98 if (VT != PromotedLdStVT) { 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 105 PromotedLdStVT.getSimpleVT()); 106 } 107 108 EVT ElemTy = VT.getVectorElementType(); 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 112 if (ElemTy != MVT::i32) { 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 117 } 118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 124 if (VT.isInteger()) { 125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 132 setTruncStoreAction(VT.getSimpleVT(), 133 (MVT::SimpleValueType)InnerVT, Expand); 134 } 135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 136 137 // Promote all bit-wise operations. 138 if (VT.isInteger() && VT != PromotedBitwiseVT) { 139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 140 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 141 PromotedBitwiseVT.getSimpleVT()); 142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 143 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 144 PromotedBitwiseVT.getSimpleVT()); 145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 147 PromotedBitwiseVT.getSimpleVT()); 148 } 149 150 // Neon does not support vector divide/remainder operations. 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 157} 158 159void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 160 addRegisterClass(VT, ARM::DPRRegisterClass); 161 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 162} 163 164void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 165 addRegisterClass(VT, ARM::QPRRegisterClass); 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 167} 168 169static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 171 return new TargetLoweringObjectFileMachO(); 172 173 return new ARMElfTargetObjectFile(); 174} 175 176ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 177 : TargetLowering(TM, createTLOF(TM)) { 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 179 RegInfo = TM.getRegisterInfo(); 180 Itins = TM.getInstrItineraryData(); 181 182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 183 184 if (Subtarget->isTargetDarwin()) { 185 // Uses VFP for Thumb libfuncs if available. 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 187 // Single-precision floating-point arithmetic. 188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 192 193 // Double-precision floating-point arithmetic. 194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 198 199 // Single-precision comparisons. 200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 208 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 217 218 // Double-precision comparisons. 219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 227 228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 236 237 // Floating-point to integer conversions. 238 // i64 conversions are done via library routines even when generating VFP 239 // instructions, so use the same ones. 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 244 245 // Conversions between floating types. 246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 248 249 // Integer to floating-point conversions. 250 // i64 conversions are done via library routines even when generating VFP 251 // instructions, so use the same ones. 252 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 253 // e.g., __floatunsidf vs. __floatunssidfvfp. 254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 258 } 259 } 260 261 // These libcalls are not available in 32-bit. 262 setLibcallName(RTLIB::SHL_I128, 0); 263 setLibcallName(RTLIB::SRL_I128, 0); 264 setLibcallName(RTLIB::SRA_I128, 0); 265 266 if (Subtarget->isAAPCS_ABI()) { 267 // Double-precision floating-point arithmetic helper functions 268 // RTABI chapter 4.1.2, Table 2 269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 277 278 // Double-precision floating-point comparison helper functions 279 // RTABI chapter 4.1.2, Table 3 280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 304 305 // Single-precision floating-point arithmetic helper functions 306 // RTABI chapter 4.1.2, Table 4 307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 315 316 // Single-precision floating-point comparison helper functions 317 // RTABI chapter 4.1.2, Table 5 318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 342 343 // Floating-point to integer conversions. 344 // RTABI chapter 4.1.2, Table 6 345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 361 362 // Conversions between floating types. 363 // RTABI chapter 4.1.2, Table 7 364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 368 369 // Integer to floating-point conversions. 370 // RTABI chapter 4.1.2, Table 8 371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 387 388 // Long long helper functions 389 // RTABI chapter 4.2, Table 9 390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 402 403 // Integer division functions 404 // RTABI chapter 4.3.1 405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 } 424 425 // Use divmod compiler-rt calls for iOS 5.0 and later. 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 430 } 431 432 if (Subtarget->isThumb1Only()) 433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 434 else 435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 438 if (!Subtarget->isFPOnlySP()) 439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 440 441 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 442 } 443 444 if (Subtarget->hasNEON()) { 445 addDRTypeForNEON(MVT::v2f32); 446 addDRTypeForNEON(MVT::v8i8); 447 addDRTypeForNEON(MVT::v4i16); 448 addDRTypeForNEON(MVT::v2i32); 449 addDRTypeForNEON(MVT::v1i64); 450 451 addQRTypeForNEON(MVT::v4f32); 452 addQRTypeForNEON(MVT::v2f64); 453 addQRTypeForNEON(MVT::v16i8); 454 addQRTypeForNEON(MVT::v8i16); 455 addQRTypeForNEON(MVT::v4i32); 456 addQRTypeForNEON(MVT::v2i64); 457 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 459 // neither Neon nor VFP support any arithmetic operations on it. 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 468 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 484 485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 486 487 // Neon does not support some operations on v1i64 and v2i64 types. 488 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 489 // Custom handling for some quad-vector types to detect VMULL. 490 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 491 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 492 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 493 // Custom handling for some vector types to avoid expensive expansions 494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 501 // a destination type that is wider than the source. 502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 504 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); 506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 508 setTargetDAGCombine(ISD::SHL); 509 setTargetDAGCombine(ISD::SRL); 510 setTargetDAGCombine(ISD::SRA); 511 setTargetDAGCombine(ISD::SIGN_EXTEND); 512 setTargetDAGCombine(ISD::ZERO_EXTEND); 513 setTargetDAGCombine(ISD::ANY_EXTEND); 514 setTargetDAGCombine(ISD::SELECT_CC); 515 setTargetDAGCombine(ISD::BUILD_VECTOR); 516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 518 setTargetDAGCombine(ISD::STORE); 519 setTargetDAGCombine(ISD::FP_TO_SINT); 520 setTargetDAGCombine(ISD::FP_TO_UINT); 521 setTargetDAGCombine(ISD::FDIV); 522 } 523 524 computeRegisterProperties(); 525 526 // ARM does not have f32 extending load. 527 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 528 529 // ARM does not have i1 sign extending load. 530 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 531 532 // ARM supports all 4 flavors of integer indexed load / store. 533 if (!Subtarget->isThumb1Only()) { 534 for (unsigned im = (unsigned)ISD::PRE_INC; 535 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 536 setIndexedLoadAction(im, MVT::i1, Legal); 537 setIndexedLoadAction(im, MVT::i8, Legal); 538 setIndexedLoadAction(im, MVT::i16, Legal); 539 setIndexedLoadAction(im, MVT::i32, Legal); 540 setIndexedStoreAction(im, MVT::i1, Legal); 541 setIndexedStoreAction(im, MVT::i8, Legal); 542 setIndexedStoreAction(im, MVT::i16, Legal); 543 setIndexedStoreAction(im, MVT::i32, Legal); 544 } 545 } 546 547 // i64 operation support. 548 setOperationAction(ISD::MUL, MVT::i64, Expand); 549 setOperationAction(ISD::MULHU, MVT::i32, Expand); 550 if (Subtarget->isThumb1Only()) { 551 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 552 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 553 } 554 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 555 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 556 setOperationAction(ISD::MULHS, MVT::i32, Expand); 557 558 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 559 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 560 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 561 setOperationAction(ISD::SRL, MVT::i64, Custom); 562 setOperationAction(ISD::SRA, MVT::i64, Custom); 563 564 if (!Subtarget->isThumb1Only()) { 565 // FIXME: We should do this for Thumb1 as well. 566 setOperationAction(ISD::ADDC, MVT::i32, Custom); 567 setOperationAction(ISD::ADDE, MVT::i32, Custom); 568 setOperationAction(ISD::SUBC, MVT::i32, Custom); 569 setOperationAction(ISD::SUBE, MVT::i32, Custom); 570 } 571 572 // ARM does not have ROTL. 573 setOperationAction(ISD::ROTL, MVT::i32, Expand); 574 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 575 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 576 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 577 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 578 579 // Only ARMv6 has BSWAP. 580 if (!Subtarget->hasV6Ops()) 581 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 582 583 // These are expanded into libcalls. 584 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 585 // v7M has a hardware divider 586 setOperationAction(ISD::SDIV, MVT::i32, Expand); 587 setOperationAction(ISD::UDIV, MVT::i32, Expand); 588 } 589 setOperationAction(ISD::SREM, MVT::i32, Expand); 590 setOperationAction(ISD::UREM, MVT::i32, Expand); 591 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 592 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 593 594 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 595 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 596 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 597 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 598 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 599 600 setOperationAction(ISD::TRAP, MVT::Other, Legal); 601 602 // Use the default implementation. 603 setOperationAction(ISD::VASTART, MVT::Other, Custom); 604 setOperationAction(ISD::VAARG, MVT::Other, Expand); 605 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 606 setOperationAction(ISD::VAEND, MVT::Other, Expand); 607 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 608 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 609 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 610 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 611 setExceptionPointerRegister(ARM::R0); 612 setExceptionSelectorRegister(ARM::R1); 613 614 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 615 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 616 // the default expansion. 617 // FIXME: This should be checking for v6k, not just v6. 618 if (Subtarget->hasDataBarrier() || 619 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 620 // membarrier needs custom lowering; the rest are legal and handled 621 // normally. 622 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 623 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 624 // Custom lowering for 64-bit ops 625 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 626 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 627 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 628 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 629 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 630 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 631 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 632 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 633 setInsertFencesForAtomic(true); 634 } else { 635 // Set them all for expansion, which will force libcalls. 636 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 637 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 638 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 639 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 640 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 644 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 645 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 646 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 647 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 648 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 649 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 650 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 651 // Unordered/Monotonic case. 652 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 653 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 654 // Since the libcalls include locking, fold in the fences 655 setShouldFoldAtomicFences(true); 656 } 657 658 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 659 660 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 661 if (!Subtarget->hasV6Ops()) { 662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 663 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 664 } 665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 666 667 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 668 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 669 // iff target supports vfp2. 670 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 671 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 672 } 673 674 // We want to custom lower some of our intrinsics. 675 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 676 if (Subtarget->isTargetDarwin()) { 677 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 678 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 679 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 680 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 681 } 682 683 setOperationAction(ISD::SETCC, MVT::i32, Expand); 684 setOperationAction(ISD::SETCC, MVT::f32, Expand); 685 setOperationAction(ISD::SETCC, MVT::f64, Expand); 686 setOperationAction(ISD::SELECT, MVT::i32, Custom); 687 setOperationAction(ISD::SELECT, MVT::f32, Custom); 688 setOperationAction(ISD::SELECT, MVT::f64, Custom); 689 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 690 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 691 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 692 693 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 694 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 695 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 696 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 697 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 698 699 // We don't support sin/cos/fmod/copysign/pow 700 setOperationAction(ISD::FSIN, MVT::f64, Expand); 701 setOperationAction(ISD::FSIN, MVT::f32, Expand); 702 setOperationAction(ISD::FCOS, MVT::f32, Expand); 703 setOperationAction(ISD::FCOS, MVT::f64, Expand); 704 setOperationAction(ISD::FREM, MVT::f64, Expand); 705 setOperationAction(ISD::FREM, MVT::f32, Expand); 706 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 707 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 708 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 709 } 710 setOperationAction(ISD::FPOW, MVT::f64, Expand); 711 setOperationAction(ISD::FPOW, MVT::f32, Expand); 712 713 setOperationAction(ISD::FMA, MVT::f64, Expand); 714 setOperationAction(ISD::FMA, MVT::f32, Expand); 715 716 // Various VFP goodness 717 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 718 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 719 if (Subtarget->hasVFP2()) { 720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 721 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 722 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 723 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 724 } 725 // Special handling for half-precision FP. 726 if (!Subtarget->hasFP16()) { 727 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 728 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 729 } 730 } 731 732 // We have target-specific dag combine patterns for the following nodes: 733 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 734 setTargetDAGCombine(ISD::ADD); 735 setTargetDAGCombine(ISD::SUB); 736 setTargetDAGCombine(ISD::MUL); 737 738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 739 setTargetDAGCombine(ISD::OR); 740 if (Subtarget->hasNEON()) 741 setTargetDAGCombine(ISD::AND); 742 743 setStackPointerRegisterToSaveRestore(ARM::SP); 744 745 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 746 setSchedulingPreference(Sched::RegPressure); 747 else 748 setSchedulingPreference(Sched::Hybrid); 749 750 //// temporary - rewrite interface to use type 751 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 752 753 // On ARM arguments smaller than 4 bytes are extended, so all arguments 754 // are at least 4 bytes aligned. 755 setMinStackArgumentAlignment(4); 756 757 benefitFromCodePlacementOpt = true; 758 759 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 760} 761 762// FIXME: It might make sense to define the representative register class as the 763// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 764// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 765// SPR's representative would be DPR_VFP2. This should work well if register 766// pressure tracking were modified such that a register use would increment the 767// pressure of the register class's representative and all of it's super 768// classes' representatives transitively. We have not implemented this because 769// of the difficulty prior to coalescing of modeling operand register classes 770// due to the common occurrence of cross class copies and subregister insertions 771// and extractions. 772std::pair<const TargetRegisterClass*, uint8_t> 773ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 774 const TargetRegisterClass *RRC = 0; 775 uint8_t Cost = 1; 776 switch (VT.getSimpleVT().SimpleTy) { 777 default: 778 return TargetLowering::findRepresentativeClass(VT); 779 // Use DPR as representative register class for all floating point 780 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 781 // the cost is 1 for both f32 and f64. 782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 783 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 784 RRC = ARM::DPRRegisterClass; 785 // When NEON is used for SP, only half of the register file is available 786 // because operations that define both SP and DP results will be constrained 787 // to the VFP2 class (D0-D15). We currently model this constraint prior to 788 // coalescing by double-counting the SP regs. See the FIXME above. 789 if (Subtarget->useNEONForSinglePrecisionFP()) 790 Cost = 2; 791 break; 792 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 793 case MVT::v4f32: case MVT::v2f64: 794 RRC = ARM::DPRRegisterClass; 795 Cost = 2; 796 break; 797 case MVT::v4i64: 798 RRC = ARM::DPRRegisterClass; 799 Cost = 4; 800 break; 801 case MVT::v8i64: 802 RRC = ARM::DPRRegisterClass; 803 Cost = 8; 804 break; 805 } 806 return std::make_pair(RRC, Cost); 807} 808 809const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 810 switch (Opcode) { 811 default: return 0; 812 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 813 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 814 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 815 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 816 case ARMISD::CALL: return "ARMISD::CALL"; 817 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 818 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 819 case ARMISD::tCALL: return "ARMISD::tCALL"; 820 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 821 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 822 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 823 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 824 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 825 case ARMISD::CMP: return "ARMISD::CMP"; 826 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 827 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 828 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 829 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 830 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 831 case ARMISD::CMOV: return "ARMISD::CMOV"; 832 833 case ARMISD::RBIT: return "ARMISD::RBIT"; 834 835 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 836 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 837 case ARMISD::SITOF: return "ARMISD::SITOF"; 838 case ARMISD::UITOF: return "ARMISD::UITOF"; 839 840 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 841 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 842 case ARMISD::RRX: return "ARMISD::RRX"; 843 844 case ARMISD::ADDC: return "ARMISD::ADDC"; 845 case ARMISD::ADDE: return "ARMISD::ADDE"; 846 case ARMISD::SUBC: return "ARMISD::SUBC"; 847 case ARMISD::SUBE: return "ARMISD::SUBE"; 848 849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 850 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 851 852 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 853 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 854 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 855 856 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 857 858 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 859 860 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 861 862 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 863 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 864 865 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 866 867 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 868 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 869 case ARMISD::VCGE: return "ARMISD::VCGE"; 870 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 871 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 872 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 873 case ARMISD::VCGT: return "ARMISD::VCGT"; 874 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 875 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 876 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 877 case ARMISD::VTST: return "ARMISD::VTST"; 878 879 case ARMISD::VSHL: return "ARMISD::VSHL"; 880 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 881 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 882 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 883 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 884 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 885 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 886 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 887 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 888 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 889 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 890 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 891 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 892 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 893 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 894 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 895 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 896 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 897 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 898 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 899 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 900 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 901 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 902 case ARMISD::VDUP: return "ARMISD::VDUP"; 903 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 904 case ARMISD::VEXT: return "ARMISD::VEXT"; 905 case ARMISD::VREV64: return "ARMISD::VREV64"; 906 case ARMISD::VREV32: return "ARMISD::VREV32"; 907 case ARMISD::VREV16: return "ARMISD::VREV16"; 908 case ARMISD::VZIP: return "ARMISD::VZIP"; 909 case ARMISD::VUZP: return "ARMISD::VUZP"; 910 case ARMISD::VTRN: return "ARMISD::VTRN"; 911 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 912 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 913 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 914 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 915 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 916 case ARMISD::FMAX: return "ARMISD::FMAX"; 917 case ARMISD::FMIN: return "ARMISD::FMIN"; 918 case ARMISD::BFI: return "ARMISD::BFI"; 919 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 920 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 921 case ARMISD::VBSL: return "ARMISD::VBSL"; 922 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 925 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 926 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 927 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 928 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 929 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 930 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 931 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 932 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 933 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 934 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 935 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 936 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 937 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 938 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 939 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 940 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 941 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 942 } 943} 944 945EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 946 if (!VT.isVector()) return getPointerTy(); 947 return VT.changeVectorElementTypeToInteger(); 948} 949 950/// getRegClassFor - Return the register class that should be used for the 951/// specified value type. 952TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 953 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 954 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 955 // load / store 4 to 8 consecutive D registers. 956 if (Subtarget->hasNEON()) { 957 if (VT == MVT::v4i64) 958 return ARM::QQPRRegisterClass; 959 else if (VT == MVT::v8i64) 960 return ARM::QQQQPRRegisterClass; 961 } 962 return TargetLowering::getRegClassFor(VT); 963} 964 965// Create a fast isel object. 966FastISel * 967ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 968 return ARM::createFastISel(funcInfo); 969} 970 971/// getMaximalGlobalOffset - Returns the maximal possible offset which can 972/// be used for loads / stores from the global. 973unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 974 return (Subtarget->isThumb1Only() ? 127 : 4095); 975} 976 977Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 978 unsigned NumVals = N->getNumValues(); 979 if (!NumVals) 980 return Sched::RegPressure; 981 982 for (unsigned i = 0; i != NumVals; ++i) { 983 EVT VT = N->getValueType(i); 984 if (VT == MVT::Glue || VT == MVT::Other) 985 continue; 986 if (VT.isFloatingPoint() || VT.isVector()) 987 return Sched::Latency; 988 } 989 990 if (!N->isMachineOpcode()) 991 return Sched::RegPressure; 992 993 // Load are scheduled for latency even if there instruction itinerary 994 // is not available. 995 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 996 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 997 998 if (MCID.getNumDefs() == 0) 999 return Sched::RegPressure; 1000 if (!Itins->isEmpty() && 1001 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1002 return Sched::Latency; 1003 1004 return Sched::RegPressure; 1005} 1006 1007//===----------------------------------------------------------------------===// 1008// Lowering Code 1009//===----------------------------------------------------------------------===// 1010 1011/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1012static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1013 switch (CC) { 1014 default: llvm_unreachable("Unknown condition code!"); 1015 case ISD::SETNE: return ARMCC::NE; 1016 case ISD::SETEQ: return ARMCC::EQ; 1017 case ISD::SETGT: return ARMCC::GT; 1018 case ISD::SETGE: return ARMCC::GE; 1019 case ISD::SETLT: return ARMCC::LT; 1020 case ISD::SETLE: return ARMCC::LE; 1021 case ISD::SETUGT: return ARMCC::HI; 1022 case ISD::SETUGE: return ARMCC::HS; 1023 case ISD::SETULT: return ARMCC::LO; 1024 case ISD::SETULE: return ARMCC::LS; 1025 } 1026} 1027 1028/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1029static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1030 ARMCC::CondCodes &CondCode2) { 1031 CondCode2 = ARMCC::AL; 1032 switch (CC) { 1033 default: llvm_unreachable("Unknown FP condition!"); 1034 case ISD::SETEQ: 1035 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1036 case ISD::SETGT: 1037 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1038 case ISD::SETGE: 1039 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1040 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1041 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1042 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1043 case ISD::SETO: CondCode = ARMCC::VC; break; 1044 case ISD::SETUO: CondCode = ARMCC::VS; break; 1045 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1046 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1047 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1048 case ISD::SETLT: 1049 case ISD::SETULT: CondCode = ARMCC::LT; break; 1050 case ISD::SETLE: 1051 case ISD::SETULE: CondCode = ARMCC::LE; break; 1052 case ISD::SETNE: 1053 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1054 } 1055} 1056 1057//===----------------------------------------------------------------------===// 1058// Calling Convention Implementation 1059//===----------------------------------------------------------------------===// 1060 1061#include "ARMGenCallingConv.inc" 1062 1063/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1064/// given CallingConvention value. 1065CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1066 bool Return, 1067 bool isVarArg) const { 1068 switch (CC) { 1069 default: 1070 llvm_unreachable("Unsupported calling convention"); 1071 case CallingConv::Fast: 1072 if (Subtarget->hasVFP2() && !isVarArg) { 1073 if (!Subtarget->isAAPCS_ABI()) 1074 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1075 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1076 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1077 } 1078 // Fallthrough 1079 case CallingConv::C: { 1080 // Use target triple & subtarget features to do actual dispatch. 1081 if (!Subtarget->isAAPCS_ABI()) 1082 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1083 else if (Subtarget->hasVFP2() && 1084 FloatABIType == FloatABI::Hard && !isVarArg) 1085 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1086 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1087 } 1088 case CallingConv::ARM_AAPCS_VFP: 1089 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1090 case CallingConv::ARM_AAPCS: 1091 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1092 case CallingConv::ARM_APCS: 1093 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1094 } 1095} 1096 1097/// LowerCallResult - Lower the result values of a call into the 1098/// appropriate copies out of appropriate physical registers. 1099SDValue 1100ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1101 CallingConv::ID CallConv, bool isVarArg, 1102 const SmallVectorImpl<ISD::InputArg> &Ins, 1103 DebugLoc dl, SelectionDAG &DAG, 1104 SmallVectorImpl<SDValue> &InVals) const { 1105 1106 // Assign locations to each value returned by this call. 1107 SmallVector<CCValAssign, 16> RVLocs; 1108 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1109 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1110 CCInfo.AnalyzeCallResult(Ins, 1111 CCAssignFnForNode(CallConv, /* Return*/ true, 1112 isVarArg)); 1113 1114 // Copy all of the result registers out of their specified physreg. 1115 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1116 CCValAssign VA = RVLocs[i]; 1117 1118 SDValue Val; 1119 if (VA.needsCustom()) { 1120 // Handle f64 or half of a v2f64. 1121 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1122 InFlag); 1123 Chain = Lo.getValue(1); 1124 InFlag = Lo.getValue(2); 1125 VA = RVLocs[++i]; // skip ahead to next loc 1126 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1127 InFlag); 1128 Chain = Hi.getValue(1); 1129 InFlag = Hi.getValue(2); 1130 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1131 1132 if (VA.getLocVT() == MVT::v2f64) { 1133 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1134 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1135 DAG.getConstant(0, MVT::i32)); 1136 1137 VA = RVLocs[++i]; // skip ahead to next loc 1138 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1139 Chain = Lo.getValue(1); 1140 InFlag = Lo.getValue(2); 1141 VA = RVLocs[++i]; // skip ahead to next loc 1142 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1143 Chain = Hi.getValue(1); 1144 InFlag = Hi.getValue(2); 1145 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1146 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1147 DAG.getConstant(1, MVT::i32)); 1148 } 1149 } else { 1150 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1151 InFlag); 1152 Chain = Val.getValue(1); 1153 InFlag = Val.getValue(2); 1154 } 1155 1156 switch (VA.getLocInfo()) { 1157 default: llvm_unreachable("Unknown loc info!"); 1158 case CCValAssign::Full: break; 1159 case CCValAssign::BCvt: 1160 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1161 break; 1162 } 1163 1164 InVals.push_back(Val); 1165 } 1166 1167 return Chain; 1168} 1169 1170/// LowerMemOpCallTo - Store the argument to the stack. 1171SDValue 1172ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1173 SDValue StackPtr, SDValue Arg, 1174 DebugLoc dl, SelectionDAG &DAG, 1175 const CCValAssign &VA, 1176 ISD::ArgFlagsTy Flags) const { 1177 unsigned LocMemOffset = VA.getLocMemOffset(); 1178 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1179 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1180 return DAG.getStore(Chain, dl, Arg, PtrOff, 1181 MachinePointerInfo::getStack(LocMemOffset), 1182 false, false, 0); 1183} 1184 1185void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1186 SDValue Chain, SDValue &Arg, 1187 RegsToPassVector &RegsToPass, 1188 CCValAssign &VA, CCValAssign &NextVA, 1189 SDValue &StackPtr, 1190 SmallVector<SDValue, 8> &MemOpChains, 1191 ISD::ArgFlagsTy Flags) const { 1192 1193 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1194 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1195 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1196 1197 if (NextVA.isRegLoc()) 1198 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1199 else { 1200 assert(NextVA.isMemLoc()); 1201 if (StackPtr.getNode() == 0) 1202 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1203 1204 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1205 dl, DAG, NextVA, 1206 Flags)); 1207 } 1208} 1209 1210/// LowerCall - Lowering a call into a callseq_start <- 1211/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1212/// nodes. 1213SDValue 1214ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1215 CallingConv::ID CallConv, bool isVarArg, 1216 bool &isTailCall, 1217 const SmallVectorImpl<ISD::OutputArg> &Outs, 1218 const SmallVectorImpl<SDValue> &OutVals, 1219 const SmallVectorImpl<ISD::InputArg> &Ins, 1220 DebugLoc dl, SelectionDAG &DAG, 1221 SmallVectorImpl<SDValue> &InVals) const { 1222 MachineFunction &MF = DAG.getMachineFunction(); 1223 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1224 bool IsSibCall = false; 1225 // Temporarily disable tail calls so things don't break. 1226 if (!EnableARMTailCalls) 1227 isTailCall = false; 1228 if (isTailCall) { 1229 // Check if it's really possible to do a tail call. 1230 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1231 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1232 Outs, OutVals, Ins, DAG); 1233 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1234 // detected sibcalls. 1235 if (isTailCall) { 1236 ++NumTailCalls; 1237 IsSibCall = true; 1238 } 1239 } 1240 1241 // Analyze operands of the call, assigning locations to each operand. 1242 SmallVector<CCValAssign, 16> ArgLocs; 1243 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1244 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1245 CCInfo.AnalyzeCallOperands(Outs, 1246 CCAssignFnForNode(CallConv, /* Return*/ false, 1247 isVarArg)); 1248 1249 // Get a count of how many bytes are to be pushed on the stack. 1250 unsigned NumBytes = CCInfo.getNextStackOffset(); 1251 1252 // For tail calls, memory operands are available in our caller's stack. 1253 if (IsSibCall) 1254 NumBytes = 0; 1255 1256 // Adjust the stack pointer for the new arguments... 1257 // These operations are automatically eliminated by the prolog/epilog pass 1258 if (!IsSibCall) 1259 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1260 1261 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1262 1263 RegsToPassVector RegsToPass; 1264 SmallVector<SDValue, 8> MemOpChains; 1265 1266 // Walk the register/memloc assignments, inserting copies/loads. In the case 1267 // of tail call optimization, arguments are handled later. 1268 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1269 i != e; 1270 ++i, ++realArgIdx) { 1271 CCValAssign &VA = ArgLocs[i]; 1272 SDValue Arg = OutVals[realArgIdx]; 1273 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1274 bool isByVal = Flags.isByVal(); 1275 1276 // Promote the value if needed. 1277 switch (VA.getLocInfo()) { 1278 default: llvm_unreachable("Unknown loc info!"); 1279 case CCValAssign::Full: break; 1280 case CCValAssign::SExt: 1281 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1282 break; 1283 case CCValAssign::ZExt: 1284 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1285 break; 1286 case CCValAssign::AExt: 1287 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1288 break; 1289 case CCValAssign::BCvt: 1290 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1291 break; 1292 } 1293 1294 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1295 if (VA.needsCustom()) { 1296 if (VA.getLocVT() == MVT::v2f64) { 1297 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1298 DAG.getConstant(0, MVT::i32)); 1299 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1300 DAG.getConstant(1, MVT::i32)); 1301 1302 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1303 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1304 1305 VA = ArgLocs[++i]; // skip ahead to next loc 1306 if (VA.isRegLoc()) { 1307 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1308 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1309 } else { 1310 assert(VA.isMemLoc()); 1311 1312 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1313 dl, DAG, VA, Flags)); 1314 } 1315 } else { 1316 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1317 StackPtr, MemOpChains, Flags); 1318 } 1319 } else if (VA.isRegLoc()) { 1320 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1321 } else if (isByVal) { 1322 assert(VA.isMemLoc()); 1323 unsigned offset = 0; 1324 1325 // True if this byval aggregate will be split between registers 1326 // and memory. 1327 if (CCInfo.isFirstByValRegValid()) { 1328 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1329 unsigned int i, j; 1330 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1331 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1332 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1333 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1334 MachinePointerInfo(), 1335 false, false, 0); 1336 MemOpChains.push_back(Load.getValue(1)); 1337 RegsToPass.push_back(std::make_pair(j, Load)); 1338 } 1339 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1340 CCInfo.clearFirstByValReg(); 1341 } 1342 1343 unsigned LocMemOffset = VA.getLocMemOffset(); 1344 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1345 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1346 StkPtrOff); 1347 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1348 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1349 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1350 MVT::i32); 1351 // TODO: Disable AlwaysInline when it becomes possible 1352 // to emit a nested call sequence. 1353 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1354 Flags.getByValAlign(), 1355 /*isVolatile=*/false, 1356 /*AlwaysInline=*/true, 1357 MachinePointerInfo(0), 1358 MachinePointerInfo(0))); 1359 1360 } else if (!IsSibCall) { 1361 assert(VA.isMemLoc()); 1362 1363 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1364 dl, DAG, VA, Flags)); 1365 } 1366 } 1367 1368 if (!MemOpChains.empty()) 1369 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1370 &MemOpChains[0], MemOpChains.size()); 1371 1372 // Build a sequence of copy-to-reg nodes chained together with token chain 1373 // and flag operands which copy the outgoing args into the appropriate regs. 1374 SDValue InFlag; 1375 // Tail call byval lowering might overwrite argument registers so in case of 1376 // tail call optimization the copies to registers are lowered later. 1377 if (!isTailCall) 1378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1380 RegsToPass[i].second, InFlag); 1381 InFlag = Chain.getValue(1); 1382 } 1383 1384 // For tail calls lower the arguments to the 'real' stack slot. 1385 if (isTailCall) { 1386 // Force all the incoming stack arguments to be loaded from the stack 1387 // before any new outgoing arguments are stored to the stack, because the 1388 // outgoing stack slots may alias the incoming argument stack slots, and 1389 // the alias isn't otherwise explicit. This is slightly more conservative 1390 // than necessary, because it means that each store effectively depends 1391 // on every argument instead of just those arguments it would clobber. 1392 1393 // Do not flag preceding copytoreg stuff together with the following stuff. 1394 InFlag = SDValue(); 1395 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1396 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1397 RegsToPass[i].second, InFlag); 1398 InFlag = Chain.getValue(1); 1399 } 1400 InFlag =SDValue(); 1401 } 1402 1403 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1404 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1405 // node so that legalize doesn't hack it. 1406 bool isDirect = false; 1407 bool isARMFunc = false; 1408 bool isLocalARMFunc = false; 1409 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1410 1411 if (EnableARMLongCalls) { 1412 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1413 && "long-calls with non-static relocation model!"); 1414 // Handle a global address or an external symbol. If it's not one of 1415 // those, the target's already in a register, so we don't need to do 1416 // anything extra. 1417 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1418 const GlobalValue *GV = G->getGlobal(); 1419 // Create a constant pool entry for the callee address 1420 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1421 ARMConstantPoolValue *CPV = 1422 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1423 1424 // Get the address of the callee into a register 1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1427 Callee = DAG.getLoad(getPointerTy(), dl, 1428 DAG.getEntryNode(), CPAddr, 1429 MachinePointerInfo::getConstantPool(), 1430 false, false, 0); 1431 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1432 const char *Sym = S->getSymbol(); 1433 1434 // Create a constant pool entry for the callee address 1435 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1436 ARMConstantPoolValue *CPV = 1437 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1438 ARMPCLabelIndex, 0); 1439 // Get the address of the callee into a register 1440 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1441 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1442 Callee = DAG.getLoad(getPointerTy(), dl, 1443 DAG.getEntryNode(), CPAddr, 1444 MachinePointerInfo::getConstantPool(), 1445 false, false, 0); 1446 } 1447 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1448 const GlobalValue *GV = G->getGlobal(); 1449 isDirect = true; 1450 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1451 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1452 getTargetMachine().getRelocationModel() != Reloc::Static; 1453 isARMFunc = !Subtarget->isThumb() || isStub; 1454 // ARM call to a local ARM function is predicable. 1455 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1456 // tBX takes a register source operand. 1457 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1458 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1459 ARMConstantPoolValue *CPV = 1460 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1463 Callee = DAG.getLoad(getPointerTy(), dl, 1464 DAG.getEntryNode(), CPAddr, 1465 MachinePointerInfo::getConstantPool(), 1466 false, false, 0); 1467 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1468 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1469 getPointerTy(), Callee, PICLabel); 1470 } else { 1471 // On ELF targets for PIC code, direct calls should go through the PLT 1472 unsigned OpFlags = 0; 1473 if (Subtarget->isTargetELF() && 1474 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1475 OpFlags = ARMII::MO_PLT; 1476 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1477 } 1478 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1479 isDirect = true; 1480 bool isStub = Subtarget->isTargetDarwin() && 1481 getTargetMachine().getRelocationModel() != Reloc::Static; 1482 isARMFunc = !Subtarget->isThumb() || isStub; 1483 // tBX takes a register source operand. 1484 const char *Sym = S->getSymbol(); 1485 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1487 ARMConstantPoolValue *CPV = 1488 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1489 ARMPCLabelIndex, 4); 1490 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1491 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1492 Callee = DAG.getLoad(getPointerTy(), dl, 1493 DAG.getEntryNode(), CPAddr, 1494 MachinePointerInfo::getConstantPool(), 1495 false, false, 0); 1496 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1497 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1498 getPointerTy(), Callee, PICLabel); 1499 } else { 1500 unsigned OpFlags = 0; 1501 // On ELF targets for PIC code, direct calls should go through the PLT 1502 if (Subtarget->isTargetELF() && 1503 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1504 OpFlags = ARMII::MO_PLT; 1505 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1506 } 1507 } 1508 1509 // FIXME: handle tail calls differently. 1510 unsigned CallOpc; 1511 if (Subtarget->isThumb()) { 1512 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1513 CallOpc = ARMISD::CALL_NOLINK; 1514 else 1515 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1516 } else { 1517 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1518 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1519 : ARMISD::CALL_NOLINK; 1520 } 1521 1522 std::vector<SDValue> Ops; 1523 Ops.push_back(Chain); 1524 Ops.push_back(Callee); 1525 1526 // Add argument registers to the end of the list so that they are known live 1527 // into the call. 1528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1529 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1530 RegsToPass[i].second.getValueType())); 1531 1532 if (InFlag.getNode()) 1533 Ops.push_back(InFlag); 1534 1535 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1536 if (isTailCall) 1537 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1538 1539 // Returns a chain and a flag for retval copy to use. 1540 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1541 InFlag = Chain.getValue(1); 1542 1543 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1544 DAG.getIntPtrConstant(0, true), InFlag); 1545 if (!Ins.empty()) 1546 InFlag = Chain.getValue(1); 1547 1548 // Handle result values, copying them out of physregs into vregs that we 1549 // return. 1550 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1551 dl, DAG, InVals); 1552} 1553 1554/// HandleByVal - Every parameter *after* a byval parameter is passed 1555/// on the stack. Remember the next parameter register to allocate, 1556/// and then confiscate the rest of the parameter registers to insure 1557/// this. 1558void 1559llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1560 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1561 assert((State->getCallOrPrologue() == Prologue || 1562 State->getCallOrPrologue() == Call) && 1563 "unhandled ParmContext"); 1564 if ((!State->isFirstByValRegValid()) && 1565 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1566 State->setFirstByValReg(reg); 1567 // At a call site, a byval parameter that is split between 1568 // registers and memory needs its size truncated here. In a 1569 // function prologue, such byval parameters are reassembled in 1570 // memory, and are not truncated. 1571 if (State->getCallOrPrologue() == Call) { 1572 unsigned excess = 4 * (ARM::R4 - reg); 1573 assert(size >= excess && "expected larger existing stack allocation"); 1574 size -= excess; 1575 } 1576 } 1577 // Confiscate any remaining parameter registers to preclude their 1578 // assignment to subsequent parameters. 1579 while (State->AllocateReg(GPRArgRegs, 4)) 1580 ; 1581} 1582 1583/// MatchingStackOffset - Return true if the given stack call argument is 1584/// already available in the same position (relatively) of the caller's 1585/// incoming argument stack. 1586static 1587bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1588 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1589 const ARMInstrInfo *TII) { 1590 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1591 int FI = INT_MAX; 1592 if (Arg.getOpcode() == ISD::CopyFromReg) { 1593 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1594 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1595 return false; 1596 MachineInstr *Def = MRI->getVRegDef(VR); 1597 if (!Def) 1598 return false; 1599 if (!Flags.isByVal()) { 1600 if (!TII->isLoadFromStackSlot(Def, FI)) 1601 return false; 1602 } else { 1603 return false; 1604 } 1605 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1606 if (Flags.isByVal()) 1607 // ByVal argument is passed in as a pointer but it's now being 1608 // dereferenced. e.g. 1609 // define @foo(%struct.X* %A) { 1610 // tail call @bar(%struct.X* byval %A) 1611 // } 1612 return false; 1613 SDValue Ptr = Ld->getBasePtr(); 1614 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1615 if (!FINode) 1616 return false; 1617 FI = FINode->getIndex(); 1618 } else 1619 return false; 1620 1621 assert(FI != INT_MAX); 1622 if (!MFI->isFixedObjectIndex(FI)) 1623 return false; 1624 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1625} 1626 1627/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1628/// for tail call optimization. Targets which want to do tail call 1629/// optimization should implement this function. 1630bool 1631ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1632 CallingConv::ID CalleeCC, 1633 bool isVarArg, 1634 bool isCalleeStructRet, 1635 bool isCallerStructRet, 1636 const SmallVectorImpl<ISD::OutputArg> &Outs, 1637 const SmallVectorImpl<SDValue> &OutVals, 1638 const SmallVectorImpl<ISD::InputArg> &Ins, 1639 SelectionDAG& DAG) const { 1640 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1641 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1642 bool CCMatch = CallerCC == CalleeCC; 1643 1644 // Look for obvious safe cases to perform tail call optimization that do not 1645 // require ABI changes. This is what gcc calls sibcall. 1646 1647 // Do not sibcall optimize vararg calls unless the call site is not passing 1648 // any arguments. 1649 if (isVarArg && !Outs.empty()) 1650 return false; 1651 1652 // Also avoid sibcall optimization if either caller or callee uses struct 1653 // return semantics. 1654 if (isCalleeStructRet || isCallerStructRet) 1655 return false; 1656 1657 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1658 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1659 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1660 // support in the assembler and linker to be used. This would need to be 1661 // fixed to fully support tail calls in Thumb1. 1662 // 1663 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1664 // LR. This means if we need to reload LR, it takes an extra instructions, 1665 // which outweighs the value of the tail call; but here we don't know yet 1666 // whether LR is going to be used. Probably the right approach is to 1667 // generate the tail call here and turn it back into CALL/RET in 1668 // emitEpilogue if LR is used. 1669 1670 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1671 // but we need to make sure there are enough registers; the only valid 1672 // registers are the 4 used for parameters. We don't currently do this 1673 // case. 1674 if (Subtarget->isThumb1Only()) 1675 return false; 1676 1677 // If the calling conventions do not match, then we'd better make sure the 1678 // results are returned in the same way as what the caller expects. 1679 if (!CCMatch) { 1680 SmallVector<CCValAssign, 16> RVLocs1; 1681 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1682 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1683 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1684 1685 SmallVector<CCValAssign, 16> RVLocs2; 1686 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1687 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1688 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1689 1690 if (RVLocs1.size() != RVLocs2.size()) 1691 return false; 1692 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1693 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1694 return false; 1695 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1696 return false; 1697 if (RVLocs1[i].isRegLoc()) { 1698 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1699 return false; 1700 } else { 1701 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1702 return false; 1703 } 1704 } 1705 } 1706 1707 // If the callee takes no arguments then go on to check the results of the 1708 // call. 1709 if (!Outs.empty()) { 1710 // Check if stack adjustment is needed. For now, do not do this if any 1711 // argument is passed on the stack. 1712 SmallVector<CCValAssign, 16> ArgLocs; 1713 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1714 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1715 CCInfo.AnalyzeCallOperands(Outs, 1716 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1717 if (CCInfo.getNextStackOffset()) { 1718 MachineFunction &MF = DAG.getMachineFunction(); 1719 1720 // Check if the arguments are already laid out in the right way as 1721 // the caller's fixed stack objects. 1722 MachineFrameInfo *MFI = MF.getFrameInfo(); 1723 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1724 const ARMInstrInfo *TII = 1725 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1726 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1727 i != e; 1728 ++i, ++realArgIdx) { 1729 CCValAssign &VA = ArgLocs[i]; 1730 EVT RegVT = VA.getLocVT(); 1731 SDValue Arg = OutVals[realArgIdx]; 1732 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1733 if (VA.getLocInfo() == CCValAssign::Indirect) 1734 return false; 1735 if (VA.needsCustom()) { 1736 // f64 and vector types are split into multiple registers or 1737 // register/stack-slot combinations. The types will not match 1738 // the registers; give up on memory f64 refs until we figure 1739 // out what to do about this. 1740 if (!VA.isRegLoc()) 1741 return false; 1742 if (!ArgLocs[++i].isRegLoc()) 1743 return false; 1744 if (RegVT == MVT::v2f64) { 1745 if (!ArgLocs[++i].isRegLoc()) 1746 return false; 1747 if (!ArgLocs[++i].isRegLoc()) 1748 return false; 1749 } 1750 } else if (!VA.isRegLoc()) { 1751 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1752 MFI, MRI, TII)) 1753 return false; 1754 } 1755 } 1756 } 1757 } 1758 1759 return true; 1760} 1761 1762SDValue 1763ARMTargetLowering::LowerReturn(SDValue Chain, 1764 CallingConv::ID CallConv, bool isVarArg, 1765 const SmallVectorImpl<ISD::OutputArg> &Outs, 1766 const SmallVectorImpl<SDValue> &OutVals, 1767 DebugLoc dl, SelectionDAG &DAG) const { 1768 1769 // CCValAssign - represent the assignment of the return value to a location. 1770 SmallVector<CCValAssign, 16> RVLocs; 1771 1772 // CCState - Info about the registers and stack slots. 1773 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1774 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1775 1776 // Analyze outgoing return values. 1777 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1778 isVarArg)); 1779 1780 // If this is the first return lowered for this function, add 1781 // the regs to the liveout set for the function. 1782 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1783 for (unsigned i = 0; i != RVLocs.size(); ++i) 1784 if (RVLocs[i].isRegLoc()) 1785 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1786 } 1787 1788 SDValue Flag; 1789 1790 // Copy the result values into the output registers. 1791 for (unsigned i = 0, realRVLocIdx = 0; 1792 i != RVLocs.size(); 1793 ++i, ++realRVLocIdx) { 1794 CCValAssign &VA = RVLocs[i]; 1795 assert(VA.isRegLoc() && "Can only return in registers!"); 1796 1797 SDValue Arg = OutVals[realRVLocIdx]; 1798 1799 switch (VA.getLocInfo()) { 1800 default: llvm_unreachable("Unknown loc info!"); 1801 case CCValAssign::Full: break; 1802 case CCValAssign::BCvt: 1803 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1804 break; 1805 } 1806 1807 if (VA.needsCustom()) { 1808 if (VA.getLocVT() == MVT::v2f64) { 1809 // Extract the first half and return it in two registers. 1810 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1811 DAG.getConstant(0, MVT::i32)); 1812 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1813 DAG.getVTList(MVT::i32, MVT::i32), Half); 1814 1815 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1816 Flag = Chain.getValue(1); 1817 VA = RVLocs[++i]; // skip ahead to next loc 1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1819 HalfGPRs.getValue(1), Flag); 1820 Flag = Chain.getValue(1); 1821 VA = RVLocs[++i]; // skip ahead to next loc 1822 1823 // Extract the 2nd half and fall through to handle it as an f64 value. 1824 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1825 DAG.getConstant(1, MVT::i32)); 1826 } 1827 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1828 // available. 1829 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1830 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1832 Flag = Chain.getValue(1); 1833 VA = RVLocs[++i]; // skip ahead to next loc 1834 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1835 Flag); 1836 } else 1837 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1838 1839 // Guarantee that all emitted copies are 1840 // stuck together, avoiding something bad. 1841 Flag = Chain.getValue(1); 1842 } 1843 1844 SDValue result; 1845 if (Flag.getNode()) 1846 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1847 else // Return Void 1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1849 1850 return result; 1851} 1852 1853bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1854 if (N->getNumValues() != 1) 1855 return false; 1856 if (!N->hasNUsesOfValue(1, 0)) 1857 return false; 1858 1859 unsigned NumCopies = 0; 1860 SDNode* Copies[2]; 1861 SDNode *Use = *N->use_begin(); 1862 if (Use->getOpcode() == ISD::CopyToReg) { 1863 Copies[NumCopies++] = Use; 1864 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1865 // f64 returned in a pair of GPRs. 1866 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1867 UI != UE; ++UI) { 1868 if (UI->getOpcode() != ISD::CopyToReg) 1869 return false; 1870 Copies[UI.getUse().getResNo()] = *UI; 1871 ++NumCopies; 1872 } 1873 } else if (Use->getOpcode() == ISD::BITCAST) { 1874 // f32 returned in a single GPR. 1875 if (!Use->hasNUsesOfValue(1, 0)) 1876 return false; 1877 Use = *Use->use_begin(); 1878 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1879 return false; 1880 Copies[NumCopies++] = Use; 1881 } else { 1882 return false; 1883 } 1884 1885 if (NumCopies != 1 && NumCopies != 2) 1886 return false; 1887 1888 bool HasRet = false; 1889 for (unsigned i = 0; i < NumCopies; ++i) { 1890 SDNode *Copy = Copies[i]; 1891 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1892 UI != UE; ++UI) { 1893 if (UI->getOpcode() == ISD::CopyToReg) { 1894 SDNode *Use = *UI; 1895 if (Use == Copies[0] || Use == Copies[1]) 1896 continue; 1897 return false; 1898 } 1899 if (UI->getOpcode() != ARMISD::RET_FLAG) 1900 return false; 1901 HasRet = true; 1902 } 1903 } 1904 1905 return HasRet; 1906} 1907 1908bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1909 if (!EnableARMTailCalls) 1910 return false; 1911 1912 if (!CI->isTailCall()) 1913 return false; 1914 1915 return !Subtarget->isThumb1Only(); 1916} 1917 1918// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1919// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1920// one of the above mentioned nodes. It has to be wrapped because otherwise 1921// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1922// be used to form addressing mode. These wrapped nodes will be selected 1923// into MOVi. 1924static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1925 EVT PtrVT = Op.getValueType(); 1926 // FIXME there is no actual debug info here 1927 DebugLoc dl = Op.getDebugLoc(); 1928 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1929 SDValue Res; 1930 if (CP->isMachineConstantPoolEntry()) 1931 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1932 CP->getAlignment()); 1933 else 1934 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1935 CP->getAlignment()); 1936 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1937} 1938 1939unsigned ARMTargetLowering::getJumpTableEncoding() const { 1940 return MachineJumpTableInfo::EK_Inline; 1941} 1942 1943SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1944 SelectionDAG &DAG) const { 1945 MachineFunction &MF = DAG.getMachineFunction(); 1946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1947 unsigned ARMPCLabelIndex = 0; 1948 DebugLoc DL = Op.getDebugLoc(); 1949 EVT PtrVT = getPointerTy(); 1950 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1951 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1952 SDValue CPAddr; 1953 if (RelocM == Reloc::Static) { 1954 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1955 } else { 1956 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1957 ARMPCLabelIndex = AFI->createPICLabelUId(); 1958 ARMConstantPoolValue *CPV = 1959 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 1960 ARMCP::CPBlockAddress, PCAdj); 1961 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1962 } 1963 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1964 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1965 MachinePointerInfo::getConstantPool(), 1966 false, false, 0); 1967 if (RelocM == Reloc::Static) 1968 return Result; 1969 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1970 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1971} 1972 1973// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1974SDValue 1975ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1976 SelectionDAG &DAG) const { 1977 DebugLoc dl = GA->getDebugLoc(); 1978 EVT PtrVT = getPointerTy(); 1979 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1980 MachineFunction &MF = DAG.getMachineFunction(); 1981 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1982 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1983 ARMConstantPoolValue *CPV = 1984 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 1985 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1986 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1987 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1988 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1989 MachinePointerInfo::getConstantPool(), 1990 false, false, 0); 1991 SDValue Chain = Argument.getValue(1); 1992 1993 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1994 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1995 1996 // call __tls_get_addr. 1997 ArgListTy Args; 1998 ArgListEntry Entry; 1999 Entry.Node = Argument; 2000 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2001 Args.push_back(Entry); 2002 // FIXME: is there useful debug info available here? 2003 std::pair<SDValue, SDValue> CallResult = 2004 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2005 false, false, false, false, 2006 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2007 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2008 return CallResult.first; 2009} 2010 2011// Lower ISD::GlobalTLSAddress using the "initial exec" or 2012// "local exec" model. 2013SDValue 2014ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2015 SelectionDAG &DAG) const { 2016 const GlobalValue *GV = GA->getGlobal(); 2017 DebugLoc dl = GA->getDebugLoc(); 2018 SDValue Offset; 2019 SDValue Chain = DAG.getEntryNode(); 2020 EVT PtrVT = getPointerTy(); 2021 // Get the Thread Pointer 2022 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2023 2024 if (GV->isDeclaration()) { 2025 MachineFunction &MF = DAG.getMachineFunction(); 2026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2027 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2028 // Initial exec model. 2029 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2030 ARMConstantPoolValue *CPV = 2031 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2032 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2033 true); 2034 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2035 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2036 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2037 MachinePointerInfo::getConstantPool(), 2038 false, false, 0); 2039 Chain = Offset.getValue(1); 2040 2041 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2042 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2043 2044 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2045 MachinePointerInfo::getConstantPool(), 2046 false, false, 0); 2047 } else { 2048 // local exec model 2049 ARMConstantPoolValue *CPV = 2050 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2051 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2052 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2053 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2054 MachinePointerInfo::getConstantPool(), 2055 false, false, 0); 2056 } 2057 2058 // The address of the thread local variable is the add of the thread 2059 // pointer with the offset of the variable. 2060 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2061} 2062 2063SDValue 2064ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2065 // TODO: implement the "local dynamic" model 2066 assert(Subtarget->isTargetELF() && 2067 "TLS not implemented for non-ELF targets"); 2068 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2069 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2070 // otherwise use the "Local Exec" TLS Model 2071 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2072 return LowerToTLSGeneralDynamicModel(GA, DAG); 2073 else 2074 return LowerToTLSExecModels(GA, DAG); 2075} 2076 2077SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2078 SelectionDAG &DAG) const { 2079 EVT PtrVT = getPointerTy(); 2080 DebugLoc dl = Op.getDebugLoc(); 2081 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2082 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2083 if (RelocM == Reloc::PIC_) { 2084 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2085 ARMConstantPoolValue *CPV = 2086 ARMConstantPoolConstant::Create(GV, 2087 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2088 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2089 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2090 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2091 CPAddr, 2092 MachinePointerInfo::getConstantPool(), 2093 false, false, 0); 2094 SDValue Chain = Result.getValue(1); 2095 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2096 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2097 if (!UseGOTOFF) 2098 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2099 MachinePointerInfo::getGOT(), false, false, 0); 2100 return Result; 2101 } 2102 2103 // If we have T2 ops, we can materialize the address directly via movt/movw 2104 // pair. This is always cheaper. 2105 if (Subtarget->useMovt()) { 2106 ++NumMovwMovt; 2107 // FIXME: Once remat is capable of dealing with instructions with register 2108 // operands, expand this into two nodes. 2109 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2110 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2111 } else { 2112 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2113 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2115 MachinePointerInfo::getConstantPool(), 2116 false, false, 0); 2117 } 2118} 2119 2120SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2121 SelectionDAG &DAG) const { 2122 EVT PtrVT = getPointerTy(); 2123 DebugLoc dl = Op.getDebugLoc(); 2124 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2125 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2126 MachineFunction &MF = DAG.getMachineFunction(); 2127 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2128 2129 // FIXME: Enable this for static codegen when tool issues are fixed. 2130 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2131 ++NumMovwMovt; 2132 // FIXME: Once remat is capable of dealing with instructions with register 2133 // operands, expand this into two nodes. 2134 if (RelocM == Reloc::Static) 2135 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2136 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2137 2138 unsigned Wrapper = (RelocM == Reloc::PIC_) 2139 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2140 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2141 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2142 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2143 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2144 MachinePointerInfo::getGOT(), false, false, 0); 2145 return Result; 2146 } 2147 2148 unsigned ARMPCLabelIndex = 0; 2149 SDValue CPAddr; 2150 if (RelocM == Reloc::Static) { 2151 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2152 } else { 2153 ARMPCLabelIndex = AFI->createPICLabelUId(); 2154 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2155 ARMConstantPoolValue *CPV = 2156 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2157 PCAdj); 2158 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2159 } 2160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2161 2162 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2163 MachinePointerInfo::getConstantPool(), 2164 false, false, 0); 2165 SDValue Chain = Result.getValue(1); 2166 2167 if (RelocM == Reloc::PIC_) { 2168 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2169 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2170 } 2171 2172 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2173 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2174 false, false, 0); 2175 2176 return Result; 2177} 2178 2179SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2180 SelectionDAG &DAG) const { 2181 assert(Subtarget->isTargetELF() && 2182 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2183 MachineFunction &MF = DAG.getMachineFunction(); 2184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2185 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2186 EVT PtrVT = getPointerTy(); 2187 DebugLoc dl = Op.getDebugLoc(); 2188 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2189 ARMConstantPoolValue *CPV = 2190 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2191 ARMPCLabelIndex, PCAdj); 2192 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2193 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2194 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2195 MachinePointerInfo::getConstantPool(), 2196 false, false, 0); 2197 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2198 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2199} 2200 2201SDValue 2202ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2203 const { 2204 DebugLoc dl = Op.getDebugLoc(); 2205 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2206 Op.getOperand(0), Op.getOperand(1)); 2207} 2208 2209SDValue 2210ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2211 DebugLoc dl = Op.getDebugLoc(); 2212 SDValue Val = DAG.getConstant(0, MVT::i32); 2213 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0), 2214 Op.getOperand(1), Val); 2215} 2216 2217SDValue 2218ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2219 DebugLoc dl = Op.getDebugLoc(); 2220 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2221 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2222} 2223 2224SDValue 2225ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2226 const ARMSubtarget *Subtarget) const { 2227 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2228 DebugLoc dl = Op.getDebugLoc(); 2229 switch (IntNo) { 2230 default: return SDValue(); // Don't custom lower most intrinsics. 2231 case Intrinsic::arm_thread_pointer: { 2232 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2233 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2234 } 2235 case Intrinsic::eh_sjlj_lsda: { 2236 MachineFunction &MF = DAG.getMachineFunction(); 2237 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2238 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2239 EVT PtrVT = getPointerTy(); 2240 DebugLoc dl = Op.getDebugLoc(); 2241 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2242 SDValue CPAddr; 2243 unsigned PCAdj = (RelocM != Reloc::PIC_) 2244 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2245 ARMConstantPoolValue *CPV = 2246 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2247 ARMCP::CPLSDA, PCAdj); 2248 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2249 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2250 SDValue Result = 2251 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2252 MachinePointerInfo::getConstantPool(), 2253 false, false, 0); 2254 2255 if (RelocM == Reloc::PIC_) { 2256 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2257 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2258 } 2259 return Result; 2260 } 2261 case Intrinsic::arm_neon_vmulls: 2262 case Intrinsic::arm_neon_vmullu: { 2263 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2264 ? ARMISD::VMULLs : ARMISD::VMULLu; 2265 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2266 Op.getOperand(1), Op.getOperand(2)); 2267 } 2268 } 2269} 2270 2271static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2272 const ARMSubtarget *Subtarget) { 2273 DebugLoc dl = Op.getDebugLoc(); 2274 if (!Subtarget->hasDataBarrier()) { 2275 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2276 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2277 // here. 2278 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2279 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2280 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2281 DAG.getConstant(0, MVT::i32)); 2282 } 2283 2284 SDValue Op5 = Op.getOperand(5); 2285 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2286 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2287 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2288 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2289 2290 ARM_MB::MemBOpt DMBOpt; 2291 if (isDeviceBarrier) 2292 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2293 else 2294 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2295 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2296 DAG.getConstant(DMBOpt, MVT::i32)); 2297} 2298 2299 2300static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2301 const ARMSubtarget *Subtarget) { 2302 // FIXME: handle "fence singlethread" more efficiently. 2303 DebugLoc dl = Op.getDebugLoc(); 2304 if (!Subtarget->hasDataBarrier()) { 2305 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2306 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2307 // here. 2308 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2309 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2310 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2311 DAG.getConstant(0, MVT::i32)); 2312 } 2313 2314 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2315 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2316} 2317 2318static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2319 const ARMSubtarget *Subtarget) { 2320 // ARM pre v5TE and Thumb1 does not have preload instructions. 2321 if (!(Subtarget->isThumb2() || 2322 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2323 // Just preserve the chain. 2324 return Op.getOperand(0); 2325 2326 DebugLoc dl = Op.getDebugLoc(); 2327 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2328 if (!isRead && 2329 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2330 // ARMv7 with MP extension has PLDW. 2331 return Op.getOperand(0); 2332 2333 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2334 if (Subtarget->isThumb()) { 2335 // Invert the bits. 2336 isRead = ~isRead & 1; 2337 isData = ~isData & 1; 2338 } 2339 2340 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2341 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2342 DAG.getConstant(isData, MVT::i32)); 2343} 2344 2345static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2346 MachineFunction &MF = DAG.getMachineFunction(); 2347 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2348 2349 // vastart just stores the address of the VarArgsFrameIndex slot into the 2350 // memory location argument. 2351 DebugLoc dl = Op.getDebugLoc(); 2352 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2353 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2354 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2355 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2356 MachinePointerInfo(SV), false, false, 0); 2357} 2358 2359SDValue 2360ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2361 SDValue &Root, SelectionDAG &DAG, 2362 DebugLoc dl) const { 2363 MachineFunction &MF = DAG.getMachineFunction(); 2364 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2365 2366 TargetRegisterClass *RC; 2367 if (AFI->isThumb1OnlyFunction()) 2368 RC = ARM::tGPRRegisterClass; 2369 else 2370 RC = ARM::GPRRegisterClass; 2371 2372 // Transform the arguments stored in physical registers into virtual ones. 2373 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2374 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2375 2376 SDValue ArgValue2; 2377 if (NextVA.isMemLoc()) { 2378 MachineFrameInfo *MFI = MF.getFrameInfo(); 2379 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2380 2381 // Create load node to retrieve arguments from the stack. 2382 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2383 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2384 MachinePointerInfo::getFixedStack(FI), 2385 false, false, 0); 2386 } else { 2387 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2388 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2389 } 2390 2391 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2392} 2393 2394void 2395ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2396 unsigned &VARegSize, unsigned &VARegSaveSize) 2397 const { 2398 unsigned NumGPRs; 2399 if (CCInfo.isFirstByValRegValid()) 2400 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2401 else { 2402 unsigned int firstUnalloced; 2403 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2404 sizeof(GPRArgRegs) / 2405 sizeof(GPRArgRegs[0])); 2406 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2407 } 2408 2409 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2410 VARegSize = NumGPRs * 4; 2411 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2412} 2413 2414// The remaining GPRs hold either the beginning of variable-argument 2415// data, or the beginning of an aggregate passed by value (usuall 2416// byval). Either way, we allocate stack slots adjacent to the data 2417// provided by our caller, and store the unallocated registers there. 2418// If this is a variadic function, the va_list pointer will begin with 2419// these values; otherwise, this reassembles a (byval) structure that 2420// was split between registers and memory. 2421void 2422ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2423 DebugLoc dl, SDValue &Chain, 2424 unsigned ArgOffset) const { 2425 MachineFunction &MF = DAG.getMachineFunction(); 2426 MachineFrameInfo *MFI = MF.getFrameInfo(); 2427 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2428 unsigned firstRegToSaveIndex; 2429 if (CCInfo.isFirstByValRegValid()) 2430 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2431 else { 2432 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2433 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2434 } 2435 2436 unsigned VARegSize, VARegSaveSize; 2437 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2438 if (VARegSaveSize) { 2439 // If this function is vararg, store any remaining integer argument regs 2440 // to their spots on the stack so that they may be loaded by deferencing 2441 // the result of va_next. 2442 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2443 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2444 ArgOffset + VARegSaveSize 2445 - VARegSize, 2446 false)); 2447 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2448 getPointerTy()); 2449 2450 SmallVector<SDValue, 4> MemOps; 2451 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2452 TargetRegisterClass *RC; 2453 if (AFI->isThumb1OnlyFunction()) 2454 RC = ARM::tGPRRegisterClass; 2455 else 2456 RC = ARM::GPRRegisterClass; 2457 2458 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2459 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2460 SDValue Store = 2461 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2462 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2463 false, false, 0); 2464 MemOps.push_back(Store); 2465 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2466 DAG.getConstant(4, getPointerTy())); 2467 } 2468 if (!MemOps.empty()) 2469 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2470 &MemOps[0], MemOps.size()); 2471 } else 2472 // This will point to the next argument passed via stack. 2473 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2474} 2475 2476SDValue 2477ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2478 CallingConv::ID CallConv, bool isVarArg, 2479 const SmallVectorImpl<ISD::InputArg> 2480 &Ins, 2481 DebugLoc dl, SelectionDAG &DAG, 2482 SmallVectorImpl<SDValue> &InVals) 2483 const { 2484 MachineFunction &MF = DAG.getMachineFunction(); 2485 MachineFrameInfo *MFI = MF.getFrameInfo(); 2486 2487 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2488 2489 // Assign locations to all of the incoming arguments. 2490 SmallVector<CCValAssign, 16> ArgLocs; 2491 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2492 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2493 CCInfo.AnalyzeFormalArguments(Ins, 2494 CCAssignFnForNode(CallConv, /* Return*/ false, 2495 isVarArg)); 2496 2497 SmallVector<SDValue, 16> ArgValues; 2498 int lastInsIndex = -1; 2499 2500 SDValue ArgValue; 2501 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2502 CCValAssign &VA = ArgLocs[i]; 2503 2504 // Arguments stored in registers. 2505 if (VA.isRegLoc()) { 2506 EVT RegVT = VA.getLocVT(); 2507 2508 if (VA.needsCustom()) { 2509 // f64 and vector types are split up into multiple registers or 2510 // combinations of registers and stack slots. 2511 if (VA.getLocVT() == MVT::v2f64) { 2512 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2513 Chain, DAG, dl); 2514 VA = ArgLocs[++i]; // skip ahead to next loc 2515 SDValue ArgValue2; 2516 if (VA.isMemLoc()) { 2517 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2518 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2519 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2520 MachinePointerInfo::getFixedStack(FI), 2521 false, false, 0); 2522 } else { 2523 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2524 Chain, DAG, dl); 2525 } 2526 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2527 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2528 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2529 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2530 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2531 } else 2532 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2533 2534 } else { 2535 TargetRegisterClass *RC; 2536 2537 if (RegVT == MVT::f32) 2538 RC = ARM::SPRRegisterClass; 2539 else if (RegVT == MVT::f64) 2540 RC = ARM::DPRRegisterClass; 2541 else if (RegVT == MVT::v2f64) 2542 RC = ARM::QPRRegisterClass; 2543 else if (RegVT == MVT::i32) 2544 RC = (AFI->isThumb1OnlyFunction() ? 2545 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2546 else 2547 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2548 2549 // Transform the arguments in physical registers into virtual ones. 2550 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2551 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2552 } 2553 2554 // If this is an 8 or 16-bit value, it is really passed promoted 2555 // to 32 bits. Insert an assert[sz]ext to capture this, then 2556 // truncate to the right size. 2557 switch (VA.getLocInfo()) { 2558 default: llvm_unreachable("Unknown loc info!"); 2559 case CCValAssign::Full: break; 2560 case CCValAssign::BCvt: 2561 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2562 break; 2563 case CCValAssign::SExt: 2564 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2565 DAG.getValueType(VA.getValVT())); 2566 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2567 break; 2568 case CCValAssign::ZExt: 2569 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2570 DAG.getValueType(VA.getValVT())); 2571 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2572 break; 2573 } 2574 2575 InVals.push_back(ArgValue); 2576 2577 } else { // VA.isRegLoc() 2578 2579 // sanity check 2580 assert(VA.isMemLoc()); 2581 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2582 2583 int index = ArgLocs[i].getValNo(); 2584 2585 // Some Ins[] entries become multiple ArgLoc[] entries. 2586 // Process them only once. 2587 if (index != lastInsIndex) 2588 { 2589 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2590 // FIXME: For now, all byval parameter objects are marked mutable. 2591 // This can be changed with more analysis. 2592 // In case of tail call optimization mark all arguments mutable. 2593 // Since they could be overwritten by lowering of arguments in case of 2594 // a tail call. 2595 if (Flags.isByVal()) { 2596 unsigned VARegSize, VARegSaveSize; 2597 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2598 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2599 unsigned Bytes = Flags.getByValSize() - VARegSize; 2600 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2601 int FI = MFI->CreateFixedObject(Bytes, 2602 VA.getLocMemOffset(), false); 2603 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2604 } else { 2605 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2606 VA.getLocMemOffset(), true); 2607 2608 // Create load nodes to retrieve arguments from the stack. 2609 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2610 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2611 MachinePointerInfo::getFixedStack(FI), 2612 false, false, 0)); 2613 } 2614 lastInsIndex = index; 2615 } 2616 } 2617 } 2618 2619 // varargs 2620 if (isVarArg) 2621 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2622 2623 return Chain; 2624} 2625 2626/// isFloatingPointZero - Return true if this is +0.0. 2627static bool isFloatingPointZero(SDValue Op) { 2628 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2629 return CFP->getValueAPF().isPosZero(); 2630 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2631 // Maybe this has already been legalized into the constant pool? 2632 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2633 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2634 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2635 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2636 return CFP->getValueAPF().isPosZero(); 2637 } 2638 } 2639 return false; 2640} 2641 2642/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2643/// the given operands. 2644SDValue 2645ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2646 SDValue &ARMcc, SelectionDAG &DAG, 2647 DebugLoc dl) const { 2648 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2649 unsigned C = RHSC->getZExtValue(); 2650 if (!isLegalICmpImmediate(C)) { 2651 // Constant does not fit, try adjusting it by one? 2652 switch (CC) { 2653 default: break; 2654 case ISD::SETLT: 2655 case ISD::SETGE: 2656 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2657 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2658 RHS = DAG.getConstant(C-1, MVT::i32); 2659 } 2660 break; 2661 case ISD::SETULT: 2662 case ISD::SETUGE: 2663 if (C != 0 && isLegalICmpImmediate(C-1)) { 2664 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2665 RHS = DAG.getConstant(C-1, MVT::i32); 2666 } 2667 break; 2668 case ISD::SETLE: 2669 case ISD::SETGT: 2670 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2671 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2672 RHS = DAG.getConstant(C+1, MVT::i32); 2673 } 2674 break; 2675 case ISD::SETULE: 2676 case ISD::SETUGT: 2677 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2678 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2679 RHS = DAG.getConstant(C+1, MVT::i32); 2680 } 2681 break; 2682 } 2683 } 2684 } 2685 2686 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2687 ARMISD::NodeType CompareType; 2688 switch (CondCode) { 2689 default: 2690 CompareType = ARMISD::CMP; 2691 break; 2692 case ARMCC::EQ: 2693 case ARMCC::NE: 2694 // Uses only Z Flag 2695 CompareType = ARMISD::CMPZ; 2696 break; 2697 } 2698 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2699 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2700} 2701 2702/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2703SDValue 2704ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2705 DebugLoc dl) const { 2706 SDValue Cmp; 2707 if (!isFloatingPointZero(RHS)) 2708 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2709 else 2710 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2711 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2712} 2713 2714/// duplicateCmp - Glue values can have only one use, so this function 2715/// duplicates a comparison node. 2716SDValue 2717ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2718 unsigned Opc = Cmp.getOpcode(); 2719 DebugLoc DL = Cmp.getDebugLoc(); 2720 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2721 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2722 2723 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2724 Cmp = Cmp.getOperand(0); 2725 Opc = Cmp.getOpcode(); 2726 if (Opc == ARMISD::CMPFP) 2727 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2728 else { 2729 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2730 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2731 } 2732 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2733} 2734 2735SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2736 SDValue Cond = Op.getOperand(0); 2737 SDValue SelectTrue = Op.getOperand(1); 2738 SDValue SelectFalse = Op.getOperand(2); 2739 DebugLoc dl = Op.getDebugLoc(); 2740 2741 // Convert: 2742 // 2743 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2744 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2745 // 2746 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2747 const ConstantSDNode *CMOVTrue = 2748 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2749 const ConstantSDNode *CMOVFalse = 2750 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2751 2752 if (CMOVTrue && CMOVFalse) { 2753 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2754 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2755 2756 SDValue True; 2757 SDValue False; 2758 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2759 True = SelectTrue; 2760 False = SelectFalse; 2761 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2762 True = SelectFalse; 2763 False = SelectTrue; 2764 } 2765 2766 if (True.getNode() && False.getNode()) { 2767 EVT VT = Op.getValueType(); 2768 SDValue ARMcc = Cond.getOperand(2); 2769 SDValue CCR = Cond.getOperand(3); 2770 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2771 assert(True.getValueType() == VT); 2772 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2773 } 2774 } 2775 } 2776 2777 return DAG.getSelectCC(dl, Cond, 2778 DAG.getConstant(0, Cond.getValueType()), 2779 SelectTrue, SelectFalse, ISD::SETNE); 2780} 2781 2782SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2783 EVT VT = Op.getValueType(); 2784 SDValue LHS = Op.getOperand(0); 2785 SDValue RHS = Op.getOperand(1); 2786 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2787 SDValue TrueVal = Op.getOperand(2); 2788 SDValue FalseVal = Op.getOperand(3); 2789 DebugLoc dl = Op.getDebugLoc(); 2790 2791 if (LHS.getValueType() == MVT::i32) { 2792 SDValue ARMcc; 2793 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2794 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2795 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2796 } 2797 2798 ARMCC::CondCodes CondCode, CondCode2; 2799 FPCCToARMCC(CC, CondCode, CondCode2); 2800 2801 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2802 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2803 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2804 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2805 ARMcc, CCR, Cmp); 2806 if (CondCode2 != ARMCC::AL) { 2807 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2808 // FIXME: Needs another CMP because flag can have but one use. 2809 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2810 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2811 Result, TrueVal, ARMcc2, CCR, Cmp2); 2812 } 2813 return Result; 2814} 2815 2816/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2817/// to morph to an integer compare sequence. 2818static bool canChangeToInt(SDValue Op, bool &SeenZero, 2819 const ARMSubtarget *Subtarget) { 2820 SDNode *N = Op.getNode(); 2821 if (!N->hasOneUse()) 2822 // Otherwise it requires moving the value from fp to integer registers. 2823 return false; 2824 if (!N->getNumValues()) 2825 return false; 2826 EVT VT = Op.getValueType(); 2827 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2828 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2829 // vmrs are very slow, e.g. cortex-a8. 2830 return false; 2831 2832 if (isFloatingPointZero(Op)) { 2833 SeenZero = true; 2834 return true; 2835 } 2836 return ISD::isNormalLoad(N); 2837} 2838 2839static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2840 if (isFloatingPointZero(Op)) 2841 return DAG.getConstant(0, MVT::i32); 2842 2843 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2844 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2845 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2846 Ld->isVolatile(), Ld->isNonTemporal(), 2847 Ld->getAlignment()); 2848 2849 llvm_unreachable("Unknown VFP cmp argument!"); 2850} 2851 2852static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2853 SDValue &RetVal1, SDValue &RetVal2) { 2854 if (isFloatingPointZero(Op)) { 2855 RetVal1 = DAG.getConstant(0, MVT::i32); 2856 RetVal2 = DAG.getConstant(0, MVT::i32); 2857 return; 2858 } 2859 2860 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2861 SDValue Ptr = Ld->getBasePtr(); 2862 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2863 Ld->getChain(), Ptr, 2864 Ld->getPointerInfo(), 2865 Ld->isVolatile(), Ld->isNonTemporal(), 2866 Ld->getAlignment()); 2867 2868 EVT PtrType = Ptr.getValueType(); 2869 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2870 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2871 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2872 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2873 Ld->getChain(), NewPtr, 2874 Ld->getPointerInfo().getWithOffset(4), 2875 Ld->isVolatile(), Ld->isNonTemporal(), 2876 NewAlign); 2877 return; 2878 } 2879 2880 llvm_unreachable("Unknown VFP cmp argument!"); 2881} 2882 2883/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2884/// f32 and even f64 comparisons to integer ones. 2885SDValue 2886ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2887 SDValue Chain = Op.getOperand(0); 2888 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2889 SDValue LHS = Op.getOperand(2); 2890 SDValue RHS = Op.getOperand(3); 2891 SDValue Dest = Op.getOperand(4); 2892 DebugLoc dl = Op.getDebugLoc(); 2893 2894 bool SeenZero = false; 2895 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2896 canChangeToInt(RHS, SeenZero, Subtarget) && 2897 // If one of the operand is zero, it's safe to ignore the NaN case since 2898 // we only care about equality comparisons. 2899 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2900 // If unsafe fp math optimization is enabled and there are no other uses of 2901 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2902 // to an integer comparison. 2903 if (CC == ISD::SETOEQ) 2904 CC = ISD::SETEQ; 2905 else if (CC == ISD::SETUNE) 2906 CC = ISD::SETNE; 2907 2908 SDValue ARMcc; 2909 if (LHS.getValueType() == MVT::f32) { 2910 LHS = bitcastf32Toi32(LHS, DAG); 2911 RHS = bitcastf32Toi32(RHS, DAG); 2912 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2913 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2914 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2915 Chain, Dest, ARMcc, CCR, Cmp); 2916 } 2917 2918 SDValue LHS1, LHS2; 2919 SDValue RHS1, RHS2; 2920 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2921 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2922 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2923 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2924 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2925 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2926 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2927 } 2928 2929 return SDValue(); 2930} 2931 2932SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2933 SDValue Chain = Op.getOperand(0); 2934 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2935 SDValue LHS = Op.getOperand(2); 2936 SDValue RHS = Op.getOperand(3); 2937 SDValue Dest = Op.getOperand(4); 2938 DebugLoc dl = Op.getDebugLoc(); 2939 2940 if (LHS.getValueType() == MVT::i32) { 2941 SDValue ARMcc; 2942 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2943 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2944 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2945 Chain, Dest, ARMcc, CCR, Cmp); 2946 } 2947 2948 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2949 2950 if (UnsafeFPMath && 2951 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2952 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2953 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2954 if (Result.getNode()) 2955 return Result; 2956 } 2957 2958 ARMCC::CondCodes CondCode, CondCode2; 2959 FPCCToARMCC(CC, CondCode, CondCode2); 2960 2961 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2962 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2963 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2964 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2965 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2966 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2967 if (CondCode2 != ARMCC::AL) { 2968 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2969 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2970 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2971 } 2972 return Res; 2973} 2974 2975SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2976 SDValue Chain = Op.getOperand(0); 2977 SDValue Table = Op.getOperand(1); 2978 SDValue Index = Op.getOperand(2); 2979 DebugLoc dl = Op.getDebugLoc(); 2980 2981 EVT PTy = getPointerTy(); 2982 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2983 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2984 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2985 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2986 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2987 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2988 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2989 if (Subtarget->isThumb2()) { 2990 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2991 // which does another jump to the destination. This also makes it easier 2992 // to translate it to TBB / TBH later. 2993 // FIXME: This might not work if the function is extremely large. 2994 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2995 Addr, Op.getOperand(2), JTI, UId); 2996 } 2997 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2998 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 2999 MachinePointerInfo::getJumpTable(), 3000 false, false, 0); 3001 Chain = Addr.getValue(1); 3002 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3003 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3004 } else { 3005 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3006 MachinePointerInfo::getJumpTable(), false, false, 0); 3007 Chain = Addr.getValue(1); 3008 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3009 } 3010} 3011 3012static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3013 DebugLoc dl = Op.getDebugLoc(); 3014 unsigned Opc; 3015 3016 switch (Op.getOpcode()) { 3017 default: 3018 assert(0 && "Invalid opcode!"); 3019 case ISD::FP_TO_SINT: 3020 Opc = ARMISD::FTOSI; 3021 break; 3022 case ISD::FP_TO_UINT: 3023 Opc = ARMISD::FTOUI; 3024 break; 3025 } 3026 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3027 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3028} 3029 3030static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3031 EVT VT = Op.getValueType(); 3032 DebugLoc dl = Op.getDebugLoc(); 3033 3034 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3035 "Invalid type for custom lowering!"); 3036 if (VT != MVT::v4f32) 3037 return DAG.UnrollVectorOp(Op.getNode()); 3038 3039 unsigned CastOpc; 3040 unsigned Opc; 3041 switch (Op.getOpcode()) { 3042 default: 3043 assert(0 && "Invalid opcode!"); 3044 case ISD::SINT_TO_FP: 3045 CastOpc = ISD::SIGN_EXTEND; 3046 Opc = ISD::SINT_TO_FP; 3047 break; 3048 case ISD::UINT_TO_FP: 3049 CastOpc = ISD::ZERO_EXTEND; 3050 Opc = ISD::UINT_TO_FP; 3051 break; 3052 } 3053 3054 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3055 return DAG.getNode(Opc, dl, VT, Op); 3056} 3057 3058static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3059 EVT VT = Op.getValueType(); 3060 if (VT.isVector()) 3061 return LowerVectorINT_TO_FP(Op, DAG); 3062 3063 DebugLoc dl = Op.getDebugLoc(); 3064 unsigned Opc; 3065 3066 switch (Op.getOpcode()) { 3067 default: 3068 assert(0 && "Invalid opcode!"); 3069 case ISD::SINT_TO_FP: 3070 Opc = ARMISD::SITOF; 3071 break; 3072 case ISD::UINT_TO_FP: 3073 Opc = ARMISD::UITOF; 3074 break; 3075 } 3076 3077 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3078 return DAG.getNode(Opc, dl, VT, Op); 3079} 3080 3081SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3082 // Implement fcopysign with a fabs and a conditional fneg. 3083 SDValue Tmp0 = Op.getOperand(0); 3084 SDValue Tmp1 = Op.getOperand(1); 3085 DebugLoc dl = Op.getDebugLoc(); 3086 EVT VT = Op.getValueType(); 3087 EVT SrcVT = Tmp1.getValueType(); 3088 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3089 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3090 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3091 3092 if (UseNEON) { 3093 // Use VBSL to copy the sign bit. 3094 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3095 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3096 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3097 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3098 if (VT == MVT::f64) 3099 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3100 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3101 DAG.getConstant(32, MVT::i32)); 3102 else /*if (VT == MVT::f32)*/ 3103 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3104 if (SrcVT == MVT::f32) { 3105 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3106 if (VT == MVT::f64) 3107 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3108 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3109 DAG.getConstant(32, MVT::i32)); 3110 } else if (VT == MVT::f32) 3111 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3112 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3113 DAG.getConstant(32, MVT::i32)); 3114 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3115 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3116 3117 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3118 MVT::i32); 3119 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3120 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3121 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3122 3123 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3124 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3125 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3126 if (VT == MVT::f32) { 3127 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3128 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3129 DAG.getConstant(0, MVT::i32)); 3130 } else { 3131 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3132 } 3133 3134 return Res; 3135 } 3136 3137 // Bitcast operand 1 to i32. 3138 if (SrcVT == MVT::f64) 3139 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3140 &Tmp1, 1).getValue(1); 3141 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3142 3143 // Or in the signbit with integer operations. 3144 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3145 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3146 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3147 if (VT == MVT::f32) { 3148 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3149 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3150 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3151 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3152 } 3153 3154 // f64: Or the high part with signbit and then combine two parts. 3155 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3156 &Tmp0, 1); 3157 SDValue Lo = Tmp0.getValue(0); 3158 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3159 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3160 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3161} 3162 3163SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3164 MachineFunction &MF = DAG.getMachineFunction(); 3165 MachineFrameInfo *MFI = MF.getFrameInfo(); 3166 MFI->setReturnAddressIsTaken(true); 3167 3168 EVT VT = Op.getValueType(); 3169 DebugLoc dl = Op.getDebugLoc(); 3170 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3171 if (Depth) { 3172 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3173 SDValue Offset = DAG.getConstant(4, MVT::i32); 3174 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3175 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3176 MachinePointerInfo(), false, false, 0); 3177 } 3178 3179 // Return LR, which contains the return address. Mark it an implicit live-in. 3180 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3181 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3182} 3183 3184SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3185 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3186 MFI->setFrameAddressIsTaken(true); 3187 3188 EVT VT = Op.getValueType(); 3189 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3190 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3191 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3192 ? ARM::R7 : ARM::R11; 3193 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3194 while (Depth--) 3195 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3196 MachinePointerInfo(), 3197 false, false, 0); 3198 return FrameAddr; 3199} 3200 3201/// ExpandBITCAST - If the target supports VFP, this function is called to 3202/// expand a bit convert where either the source or destination type is i64 to 3203/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3204/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3205/// vectors), since the legalizer won't know what to do with that. 3206static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3207 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3208 DebugLoc dl = N->getDebugLoc(); 3209 SDValue Op = N->getOperand(0); 3210 3211 // This function is only supposed to be called for i64 types, either as the 3212 // source or destination of the bit convert. 3213 EVT SrcVT = Op.getValueType(); 3214 EVT DstVT = N->getValueType(0); 3215 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3216 "ExpandBITCAST called for non-i64 type"); 3217 3218 // Turn i64->f64 into VMOVDRR. 3219 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3220 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3221 DAG.getConstant(0, MVT::i32)); 3222 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3223 DAG.getConstant(1, MVT::i32)); 3224 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3225 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3226 } 3227 3228 // Turn f64->i64 into VMOVRRD. 3229 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3230 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3231 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3232 // Merge the pieces into a single i64 value. 3233 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3234 } 3235 3236 return SDValue(); 3237} 3238 3239/// getZeroVector - Returns a vector of specified type with all zero elements. 3240/// Zero vectors are used to represent vector negation and in those cases 3241/// will be implemented with the NEON VNEG instruction. However, VNEG does 3242/// not support i64 elements, so sometimes the zero vectors will need to be 3243/// explicitly constructed. Regardless, use a canonical VMOV to create the 3244/// zero vector. 3245static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3246 assert(VT.isVector() && "Expected a vector type"); 3247 // The canonical modified immediate encoding of a zero vector is....0! 3248 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3249 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3250 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3251 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3252} 3253 3254/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3255/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3256SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3257 SelectionDAG &DAG) const { 3258 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3259 EVT VT = Op.getValueType(); 3260 unsigned VTBits = VT.getSizeInBits(); 3261 DebugLoc dl = Op.getDebugLoc(); 3262 SDValue ShOpLo = Op.getOperand(0); 3263 SDValue ShOpHi = Op.getOperand(1); 3264 SDValue ShAmt = Op.getOperand(2); 3265 SDValue ARMcc; 3266 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3267 3268 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3269 3270 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3271 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3272 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3273 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3274 DAG.getConstant(VTBits, MVT::i32)); 3275 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3276 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3277 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3278 3279 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3280 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3281 ARMcc, DAG, dl); 3282 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3283 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3284 CCR, Cmp); 3285 3286 SDValue Ops[2] = { Lo, Hi }; 3287 return DAG.getMergeValues(Ops, 2, dl); 3288} 3289 3290/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3291/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3292SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3293 SelectionDAG &DAG) const { 3294 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3295 EVT VT = Op.getValueType(); 3296 unsigned VTBits = VT.getSizeInBits(); 3297 DebugLoc dl = Op.getDebugLoc(); 3298 SDValue ShOpLo = Op.getOperand(0); 3299 SDValue ShOpHi = Op.getOperand(1); 3300 SDValue ShAmt = Op.getOperand(2); 3301 SDValue ARMcc; 3302 3303 assert(Op.getOpcode() == ISD::SHL_PARTS); 3304 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3305 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3306 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3307 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3308 DAG.getConstant(VTBits, MVT::i32)); 3309 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3310 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3311 3312 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3313 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3314 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3315 ARMcc, DAG, dl); 3316 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3317 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3318 CCR, Cmp); 3319 3320 SDValue Ops[2] = { Lo, Hi }; 3321 return DAG.getMergeValues(Ops, 2, dl); 3322} 3323 3324SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3325 SelectionDAG &DAG) const { 3326 // The rounding mode is in bits 23:22 of the FPSCR. 3327 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3328 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3329 // so that the shift + and get folded into a bitfield extract. 3330 DebugLoc dl = Op.getDebugLoc(); 3331 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3332 DAG.getConstant(Intrinsic::arm_get_fpscr, 3333 MVT::i32)); 3334 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3335 DAG.getConstant(1U << 22, MVT::i32)); 3336 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3337 DAG.getConstant(22, MVT::i32)); 3338 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3339 DAG.getConstant(3, MVT::i32)); 3340} 3341 3342static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3343 const ARMSubtarget *ST) { 3344 EVT VT = N->getValueType(0); 3345 DebugLoc dl = N->getDebugLoc(); 3346 3347 if (!ST->hasV6T2Ops()) 3348 return SDValue(); 3349 3350 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3351 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3352} 3353 3354static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3355 const ARMSubtarget *ST) { 3356 EVT VT = N->getValueType(0); 3357 DebugLoc dl = N->getDebugLoc(); 3358 3359 if (!VT.isVector()) 3360 return SDValue(); 3361 3362 // Lower vector shifts on NEON to use VSHL. 3363 assert(ST->hasNEON() && "unexpected vector shift"); 3364 3365 // Left shifts translate directly to the vshiftu intrinsic. 3366 if (N->getOpcode() == ISD::SHL) 3367 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3368 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3369 N->getOperand(0), N->getOperand(1)); 3370 3371 assert((N->getOpcode() == ISD::SRA || 3372 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3373 3374 // NEON uses the same intrinsics for both left and right shifts. For 3375 // right shifts, the shift amounts are negative, so negate the vector of 3376 // shift amounts. 3377 EVT ShiftVT = N->getOperand(1).getValueType(); 3378 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3379 getZeroVector(ShiftVT, DAG, dl), 3380 N->getOperand(1)); 3381 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3382 Intrinsic::arm_neon_vshifts : 3383 Intrinsic::arm_neon_vshiftu); 3384 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3385 DAG.getConstant(vshiftInt, MVT::i32), 3386 N->getOperand(0), NegatedCount); 3387} 3388 3389static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3390 const ARMSubtarget *ST) { 3391 EVT VT = N->getValueType(0); 3392 DebugLoc dl = N->getDebugLoc(); 3393 3394 // We can get here for a node like i32 = ISD::SHL i32, i64 3395 if (VT != MVT::i64) 3396 return SDValue(); 3397 3398 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3399 "Unknown shift to lower!"); 3400 3401 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3402 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3403 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3404 return SDValue(); 3405 3406 // If we are in thumb mode, we don't have RRX. 3407 if (ST->isThumb1Only()) return SDValue(); 3408 3409 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3410 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3411 DAG.getConstant(0, MVT::i32)); 3412 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3413 DAG.getConstant(1, MVT::i32)); 3414 3415 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3416 // captures the result into a carry flag. 3417 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3418 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3419 3420 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3421 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3422 3423 // Merge the pieces into a single i64 value. 3424 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3425} 3426 3427static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3428 SDValue TmpOp0, TmpOp1; 3429 bool Invert = false; 3430 bool Swap = false; 3431 unsigned Opc = 0; 3432 3433 SDValue Op0 = Op.getOperand(0); 3434 SDValue Op1 = Op.getOperand(1); 3435 SDValue CC = Op.getOperand(2); 3436 EVT VT = Op.getValueType(); 3437 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3438 DebugLoc dl = Op.getDebugLoc(); 3439 3440 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3441 switch (SetCCOpcode) { 3442 default: llvm_unreachable("Illegal FP comparison"); break; 3443 case ISD::SETUNE: 3444 case ISD::SETNE: Invert = true; // Fallthrough 3445 case ISD::SETOEQ: 3446 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3447 case ISD::SETOLT: 3448 case ISD::SETLT: Swap = true; // Fallthrough 3449 case ISD::SETOGT: 3450 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3451 case ISD::SETOLE: 3452 case ISD::SETLE: Swap = true; // Fallthrough 3453 case ISD::SETOGE: 3454 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3455 case ISD::SETUGE: Swap = true; // Fallthrough 3456 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3457 case ISD::SETUGT: Swap = true; // Fallthrough 3458 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3459 case ISD::SETUEQ: Invert = true; // Fallthrough 3460 case ISD::SETONE: 3461 // Expand this to (OLT | OGT). 3462 TmpOp0 = Op0; 3463 TmpOp1 = Op1; 3464 Opc = ISD::OR; 3465 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3466 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3467 break; 3468 case ISD::SETUO: Invert = true; // Fallthrough 3469 case ISD::SETO: 3470 // Expand this to (OLT | OGE). 3471 TmpOp0 = Op0; 3472 TmpOp1 = Op1; 3473 Opc = ISD::OR; 3474 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3475 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3476 break; 3477 } 3478 } else { 3479 // Integer comparisons. 3480 switch (SetCCOpcode) { 3481 default: llvm_unreachable("Illegal integer comparison"); break; 3482 case ISD::SETNE: Invert = true; 3483 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3484 case ISD::SETLT: Swap = true; 3485 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3486 case ISD::SETLE: Swap = true; 3487 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3488 case ISD::SETULT: Swap = true; 3489 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3490 case ISD::SETULE: Swap = true; 3491 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3492 } 3493 3494 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3495 if (Opc == ARMISD::VCEQ) { 3496 3497 SDValue AndOp; 3498 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3499 AndOp = Op0; 3500 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3501 AndOp = Op1; 3502 3503 // Ignore bitconvert. 3504 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3505 AndOp = AndOp.getOperand(0); 3506 3507 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3508 Opc = ARMISD::VTST; 3509 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3510 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3511 Invert = !Invert; 3512 } 3513 } 3514 } 3515 3516 if (Swap) 3517 std::swap(Op0, Op1); 3518 3519 // If one of the operands is a constant vector zero, attempt to fold the 3520 // comparison to a specialized compare-against-zero form. 3521 SDValue SingleOp; 3522 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3523 SingleOp = Op0; 3524 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3525 if (Opc == ARMISD::VCGE) 3526 Opc = ARMISD::VCLEZ; 3527 else if (Opc == ARMISD::VCGT) 3528 Opc = ARMISD::VCLTZ; 3529 SingleOp = Op1; 3530 } 3531 3532 SDValue Result; 3533 if (SingleOp.getNode()) { 3534 switch (Opc) { 3535 case ARMISD::VCEQ: 3536 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3537 case ARMISD::VCGE: 3538 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3539 case ARMISD::VCLEZ: 3540 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3541 case ARMISD::VCGT: 3542 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3543 case ARMISD::VCLTZ: 3544 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3545 default: 3546 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3547 } 3548 } else { 3549 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3550 } 3551 3552 if (Invert) 3553 Result = DAG.getNOT(dl, Result, VT); 3554 3555 return Result; 3556} 3557 3558/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3559/// valid vector constant for a NEON instruction with a "modified immediate" 3560/// operand (e.g., VMOV). If so, return the encoded value. 3561static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3562 unsigned SplatBitSize, SelectionDAG &DAG, 3563 EVT &VT, bool is128Bits, NEONModImmType type) { 3564 unsigned OpCmode, Imm; 3565 3566 // SplatBitSize is set to the smallest size that splats the vector, so a 3567 // zero vector will always have SplatBitSize == 8. However, NEON modified 3568 // immediate instructions others than VMOV do not support the 8-bit encoding 3569 // of a zero vector, and the default encoding of zero is supposed to be the 3570 // 32-bit version. 3571 if (SplatBits == 0) 3572 SplatBitSize = 32; 3573 3574 switch (SplatBitSize) { 3575 case 8: 3576 if (type != VMOVModImm) 3577 return SDValue(); 3578 // Any 1-byte value is OK. Op=0, Cmode=1110. 3579 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3580 OpCmode = 0xe; 3581 Imm = SplatBits; 3582 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3583 break; 3584 3585 case 16: 3586 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3587 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3588 if ((SplatBits & ~0xff) == 0) { 3589 // Value = 0x00nn: Op=x, Cmode=100x. 3590 OpCmode = 0x8; 3591 Imm = SplatBits; 3592 break; 3593 } 3594 if ((SplatBits & ~0xff00) == 0) { 3595 // Value = 0xnn00: Op=x, Cmode=101x. 3596 OpCmode = 0xa; 3597 Imm = SplatBits >> 8; 3598 break; 3599 } 3600 return SDValue(); 3601 3602 case 32: 3603 // NEON's 32-bit VMOV supports splat values where: 3604 // * only one byte is nonzero, or 3605 // * the least significant byte is 0xff and the second byte is nonzero, or 3606 // * the least significant 2 bytes are 0xff and the third is nonzero. 3607 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3608 if ((SplatBits & ~0xff) == 0) { 3609 // Value = 0x000000nn: Op=x, Cmode=000x. 3610 OpCmode = 0; 3611 Imm = SplatBits; 3612 break; 3613 } 3614 if ((SplatBits & ~0xff00) == 0) { 3615 // Value = 0x0000nn00: Op=x, Cmode=001x. 3616 OpCmode = 0x2; 3617 Imm = SplatBits >> 8; 3618 break; 3619 } 3620 if ((SplatBits & ~0xff0000) == 0) { 3621 // Value = 0x00nn0000: Op=x, Cmode=010x. 3622 OpCmode = 0x4; 3623 Imm = SplatBits >> 16; 3624 break; 3625 } 3626 if ((SplatBits & ~0xff000000) == 0) { 3627 // Value = 0xnn000000: Op=x, Cmode=011x. 3628 OpCmode = 0x6; 3629 Imm = SplatBits >> 24; 3630 break; 3631 } 3632 3633 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3634 if (type == OtherModImm) return SDValue(); 3635 3636 if ((SplatBits & ~0xffff) == 0 && 3637 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3638 // Value = 0x0000nnff: Op=x, Cmode=1100. 3639 OpCmode = 0xc; 3640 Imm = SplatBits >> 8; 3641 SplatBits |= 0xff; 3642 break; 3643 } 3644 3645 if ((SplatBits & ~0xffffff) == 0 && 3646 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3647 // Value = 0x00nnffff: Op=x, Cmode=1101. 3648 OpCmode = 0xd; 3649 Imm = SplatBits >> 16; 3650 SplatBits |= 0xffff; 3651 break; 3652 } 3653 3654 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3655 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3656 // VMOV.I32. A (very) minor optimization would be to replicate the value 3657 // and fall through here to test for a valid 64-bit splat. But, then the 3658 // caller would also need to check and handle the change in size. 3659 return SDValue(); 3660 3661 case 64: { 3662 if (type != VMOVModImm) 3663 return SDValue(); 3664 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3665 uint64_t BitMask = 0xff; 3666 uint64_t Val = 0; 3667 unsigned ImmMask = 1; 3668 Imm = 0; 3669 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3670 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3671 Val |= BitMask; 3672 Imm |= ImmMask; 3673 } else if ((SplatBits & BitMask) != 0) { 3674 return SDValue(); 3675 } 3676 BitMask <<= 8; 3677 ImmMask <<= 1; 3678 } 3679 // Op=1, Cmode=1110. 3680 OpCmode = 0x1e; 3681 SplatBits = Val; 3682 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3683 break; 3684 } 3685 3686 default: 3687 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3688 return SDValue(); 3689 } 3690 3691 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3692 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3693} 3694 3695static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3696 bool &ReverseVEXT, unsigned &Imm) { 3697 unsigned NumElts = VT.getVectorNumElements(); 3698 ReverseVEXT = false; 3699 3700 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3701 if (M[0] < 0) 3702 return false; 3703 3704 Imm = M[0]; 3705 3706 // If this is a VEXT shuffle, the immediate value is the index of the first 3707 // element. The other shuffle indices must be the successive elements after 3708 // the first one. 3709 unsigned ExpectedElt = Imm; 3710 for (unsigned i = 1; i < NumElts; ++i) { 3711 // Increment the expected index. If it wraps around, it may still be 3712 // a VEXT but the source vectors must be swapped. 3713 ExpectedElt += 1; 3714 if (ExpectedElt == NumElts * 2) { 3715 ExpectedElt = 0; 3716 ReverseVEXT = true; 3717 } 3718 3719 if (M[i] < 0) continue; // ignore UNDEF indices 3720 if (ExpectedElt != static_cast<unsigned>(M[i])) 3721 return false; 3722 } 3723 3724 // Adjust the index value if the source operands will be swapped. 3725 if (ReverseVEXT) 3726 Imm -= NumElts; 3727 3728 return true; 3729} 3730 3731/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3732/// instruction with the specified blocksize. (The order of the elements 3733/// within each block of the vector is reversed.) 3734static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3735 unsigned BlockSize) { 3736 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3737 "Only possible block sizes for VREV are: 16, 32, 64"); 3738 3739 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3740 if (EltSz == 64) 3741 return false; 3742 3743 unsigned NumElts = VT.getVectorNumElements(); 3744 unsigned BlockElts = M[0] + 1; 3745 // If the first shuffle index is UNDEF, be optimistic. 3746 if (M[0] < 0) 3747 BlockElts = BlockSize / EltSz; 3748 3749 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3750 return false; 3751 3752 for (unsigned i = 0; i < NumElts; ++i) { 3753 if (M[i] < 0) continue; // ignore UNDEF indices 3754 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3755 return false; 3756 } 3757 3758 return true; 3759} 3760 3761static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) { 3762 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3763 // range, then 0 is placed into the resulting vector. So pretty much any mask 3764 // of 8 elements can work here. 3765 return VT == MVT::v8i8 && M.size() == 8; 3766} 3767 3768static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3769 unsigned &WhichResult) { 3770 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3771 if (EltSz == 64) 3772 return false; 3773 3774 unsigned NumElts = VT.getVectorNumElements(); 3775 WhichResult = (M[0] == 0 ? 0 : 1); 3776 for (unsigned i = 0; i < NumElts; i += 2) { 3777 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3778 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3779 return false; 3780 } 3781 return true; 3782} 3783 3784/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3785/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3786/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3787static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3788 unsigned &WhichResult) { 3789 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3790 if (EltSz == 64) 3791 return false; 3792 3793 unsigned NumElts = VT.getVectorNumElements(); 3794 WhichResult = (M[0] == 0 ? 0 : 1); 3795 for (unsigned i = 0; i < NumElts; i += 2) { 3796 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3797 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3798 return false; 3799 } 3800 return true; 3801} 3802 3803static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3804 unsigned &WhichResult) { 3805 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3806 if (EltSz == 64) 3807 return false; 3808 3809 unsigned NumElts = VT.getVectorNumElements(); 3810 WhichResult = (M[0] == 0 ? 0 : 1); 3811 for (unsigned i = 0; i != NumElts; ++i) { 3812 if (M[i] < 0) continue; // ignore UNDEF indices 3813 if ((unsigned) M[i] != 2 * i + WhichResult) 3814 return false; 3815 } 3816 3817 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3818 if (VT.is64BitVector() && EltSz == 32) 3819 return false; 3820 3821 return true; 3822} 3823 3824/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3825/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3826/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3827static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3828 unsigned &WhichResult) { 3829 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3830 if (EltSz == 64) 3831 return false; 3832 3833 unsigned Half = VT.getVectorNumElements() / 2; 3834 WhichResult = (M[0] == 0 ? 0 : 1); 3835 for (unsigned j = 0; j != 2; ++j) { 3836 unsigned Idx = WhichResult; 3837 for (unsigned i = 0; i != Half; ++i) { 3838 int MIdx = M[i + j * Half]; 3839 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3840 return false; 3841 Idx += 2; 3842 } 3843 } 3844 3845 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3846 if (VT.is64BitVector() && EltSz == 32) 3847 return false; 3848 3849 return true; 3850} 3851 3852static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3853 unsigned &WhichResult) { 3854 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3855 if (EltSz == 64) 3856 return false; 3857 3858 unsigned NumElts = VT.getVectorNumElements(); 3859 WhichResult = (M[0] == 0 ? 0 : 1); 3860 unsigned Idx = WhichResult * NumElts / 2; 3861 for (unsigned i = 0; i != NumElts; i += 2) { 3862 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3863 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3864 return false; 3865 Idx += 1; 3866 } 3867 3868 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3869 if (VT.is64BitVector() && EltSz == 32) 3870 return false; 3871 3872 return true; 3873} 3874 3875/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3876/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3877/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3878static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3879 unsigned &WhichResult) { 3880 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3881 if (EltSz == 64) 3882 return false; 3883 3884 unsigned NumElts = VT.getVectorNumElements(); 3885 WhichResult = (M[0] == 0 ? 0 : 1); 3886 unsigned Idx = WhichResult * NumElts / 2; 3887 for (unsigned i = 0; i != NumElts; i += 2) { 3888 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3889 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3890 return false; 3891 Idx += 1; 3892 } 3893 3894 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3895 if (VT.is64BitVector() && EltSz == 32) 3896 return false; 3897 3898 return true; 3899} 3900 3901// If N is an integer constant that can be moved into a register in one 3902// instruction, return an SDValue of such a constant (will become a MOV 3903// instruction). Otherwise return null. 3904static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3905 const ARMSubtarget *ST, DebugLoc dl) { 3906 uint64_t Val; 3907 if (!isa<ConstantSDNode>(N)) 3908 return SDValue(); 3909 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3910 3911 if (ST->isThumb1Only()) { 3912 if (Val <= 255 || ~Val <= 255) 3913 return DAG.getConstant(Val, MVT::i32); 3914 } else { 3915 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3916 return DAG.getConstant(Val, MVT::i32); 3917 } 3918 return SDValue(); 3919} 3920 3921// If this is a case we can't handle, return null and let the default 3922// expansion code take care of it. 3923SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3924 const ARMSubtarget *ST) const { 3925 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3926 DebugLoc dl = Op.getDebugLoc(); 3927 EVT VT = Op.getValueType(); 3928 3929 APInt SplatBits, SplatUndef; 3930 unsigned SplatBitSize; 3931 bool HasAnyUndefs; 3932 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3933 if (SplatBitSize <= 64) { 3934 // Check if an immediate VMOV works. 3935 EVT VmovVT; 3936 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3937 SplatUndef.getZExtValue(), SplatBitSize, 3938 DAG, VmovVT, VT.is128BitVector(), 3939 VMOVModImm); 3940 if (Val.getNode()) { 3941 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3942 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3943 } 3944 3945 // Try an immediate VMVN. 3946 uint64_t NegatedImm = (SplatBits.getZExtValue() ^ 3947 ((1LL << SplatBitSize) - 1)); 3948 Val = isNEONModifiedImm(NegatedImm, 3949 SplatUndef.getZExtValue(), SplatBitSize, 3950 DAG, VmovVT, VT.is128BitVector(), 3951 VMVNModImm); 3952 if (Val.getNode()) { 3953 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3954 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3955 } 3956 } 3957 } 3958 3959 // Scan through the operands to see if only one value is used. 3960 unsigned NumElts = VT.getVectorNumElements(); 3961 bool isOnlyLowElement = true; 3962 bool usesOnlyOneValue = true; 3963 bool isConstant = true; 3964 SDValue Value; 3965 for (unsigned i = 0; i < NumElts; ++i) { 3966 SDValue V = Op.getOperand(i); 3967 if (V.getOpcode() == ISD::UNDEF) 3968 continue; 3969 if (i > 0) 3970 isOnlyLowElement = false; 3971 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3972 isConstant = false; 3973 3974 if (!Value.getNode()) 3975 Value = V; 3976 else if (V != Value) 3977 usesOnlyOneValue = false; 3978 } 3979 3980 if (!Value.getNode()) 3981 return DAG.getUNDEF(VT); 3982 3983 if (isOnlyLowElement) 3984 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3985 3986 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3987 3988 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3989 // i32 and try again. 3990 if (usesOnlyOneValue && EltSize <= 32) { 3991 if (!isConstant) 3992 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3993 if (VT.getVectorElementType().isFloatingPoint()) { 3994 SmallVector<SDValue, 8> Ops; 3995 for (unsigned i = 0; i < NumElts; ++i) 3996 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 3997 Op.getOperand(i))); 3998 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 3999 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4000 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4001 if (Val.getNode()) 4002 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4003 } 4004 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4005 if (Val.getNode()) 4006 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4007 } 4008 4009 // If all elements are constants and the case above didn't get hit, fall back 4010 // to the default expansion, which will generate a load from the constant 4011 // pool. 4012 if (isConstant) 4013 return SDValue(); 4014 4015 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4016 if (NumElts >= 4) { 4017 SDValue shuffle = ReconstructShuffle(Op, DAG); 4018 if (shuffle != SDValue()) 4019 return shuffle; 4020 } 4021 4022 // Vectors with 32- or 64-bit elements can be built by directly assigning 4023 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4024 // will be legalized. 4025 if (EltSize >= 32) { 4026 // Do the expansion with floating-point types, since that is what the VFP 4027 // registers are defined to use, and since i64 is not legal. 4028 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4029 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4030 SmallVector<SDValue, 8> Ops; 4031 for (unsigned i = 0; i < NumElts; ++i) 4032 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4033 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4034 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4035 } 4036 4037 return SDValue(); 4038} 4039 4040// Gather data to see if the operation can be modelled as a 4041// shuffle in combination with VEXTs. 4042SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4043 SelectionDAG &DAG) const { 4044 DebugLoc dl = Op.getDebugLoc(); 4045 EVT VT = Op.getValueType(); 4046 unsigned NumElts = VT.getVectorNumElements(); 4047 4048 SmallVector<SDValue, 2> SourceVecs; 4049 SmallVector<unsigned, 2> MinElts; 4050 SmallVector<unsigned, 2> MaxElts; 4051 4052 for (unsigned i = 0; i < NumElts; ++i) { 4053 SDValue V = Op.getOperand(i); 4054 if (V.getOpcode() == ISD::UNDEF) 4055 continue; 4056 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4057 // A shuffle can only come from building a vector from various 4058 // elements of other vectors. 4059 return SDValue(); 4060 } 4061 4062 // Record this extraction against the appropriate vector if possible... 4063 SDValue SourceVec = V.getOperand(0); 4064 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4065 bool FoundSource = false; 4066 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4067 if (SourceVecs[j] == SourceVec) { 4068 if (MinElts[j] > EltNo) 4069 MinElts[j] = EltNo; 4070 if (MaxElts[j] < EltNo) 4071 MaxElts[j] = EltNo; 4072 FoundSource = true; 4073 break; 4074 } 4075 } 4076 4077 // Or record a new source if not... 4078 if (!FoundSource) { 4079 SourceVecs.push_back(SourceVec); 4080 MinElts.push_back(EltNo); 4081 MaxElts.push_back(EltNo); 4082 } 4083 } 4084 4085 // Currently only do something sane when at most two source vectors 4086 // involved. 4087 if (SourceVecs.size() > 2) 4088 return SDValue(); 4089 4090 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4091 int VEXTOffsets[2] = {0, 0}; 4092 4093 // This loop extracts the usage patterns of the source vectors 4094 // and prepares appropriate SDValues for a shuffle if possible. 4095 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4096 if (SourceVecs[i].getValueType() == VT) { 4097 // No VEXT necessary 4098 ShuffleSrcs[i] = SourceVecs[i]; 4099 VEXTOffsets[i] = 0; 4100 continue; 4101 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4102 // It probably isn't worth padding out a smaller vector just to 4103 // break it down again in a shuffle. 4104 return SDValue(); 4105 } 4106 4107 // Since only 64-bit and 128-bit vectors are legal on ARM and 4108 // we've eliminated the other cases... 4109 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4110 "unexpected vector sizes in ReconstructShuffle"); 4111 4112 if (MaxElts[i] - MinElts[i] >= NumElts) { 4113 // Span too large for a VEXT to cope 4114 return SDValue(); 4115 } 4116 4117 if (MinElts[i] >= NumElts) { 4118 // The extraction can just take the second half 4119 VEXTOffsets[i] = NumElts; 4120 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4121 SourceVecs[i], 4122 DAG.getIntPtrConstant(NumElts)); 4123 } else if (MaxElts[i] < NumElts) { 4124 // The extraction can just take the first half 4125 VEXTOffsets[i] = 0; 4126 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4127 SourceVecs[i], 4128 DAG.getIntPtrConstant(0)); 4129 } else { 4130 // An actual VEXT is needed 4131 VEXTOffsets[i] = MinElts[i]; 4132 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4133 SourceVecs[i], 4134 DAG.getIntPtrConstant(0)); 4135 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4136 SourceVecs[i], 4137 DAG.getIntPtrConstant(NumElts)); 4138 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4139 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4140 } 4141 } 4142 4143 SmallVector<int, 8> Mask; 4144 4145 for (unsigned i = 0; i < NumElts; ++i) { 4146 SDValue Entry = Op.getOperand(i); 4147 if (Entry.getOpcode() == ISD::UNDEF) { 4148 Mask.push_back(-1); 4149 continue; 4150 } 4151 4152 SDValue ExtractVec = Entry.getOperand(0); 4153 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4154 .getOperand(1))->getSExtValue(); 4155 if (ExtractVec == SourceVecs[0]) { 4156 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4157 } else { 4158 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4159 } 4160 } 4161 4162 // Final check before we try to produce nonsense... 4163 if (isShuffleMaskLegal(Mask, VT)) 4164 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4165 &Mask[0]); 4166 4167 return SDValue(); 4168} 4169 4170/// isShuffleMaskLegal - Targets can use this to indicate that they only 4171/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4172/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4173/// are assumed to be legal. 4174bool 4175ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4176 EVT VT) const { 4177 if (VT.getVectorNumElements() == 4 && 4178 (VT.is128BitVector() || VT.is64BitVector())) { 4179 unsigned PFIndexes[4]; 4180 for (unsigned i = 0; i != 4; ++i) { 4181 if (M[i] < 0) 4182 PFIndexes[i] = 8; 4183 else 4184 PFIndexes[i] = M[i]; 4185 } 4186 4187 // Compute the index in the perfect shuffle table. 4188 unsigned PFTableIndex = 4189 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4190 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4191 unsigned Cost = (PFEntry >> 30); 4192 4193 if (Cost <= 4) 4194 return true; 4195 } 4196 4197 bool ReverseVEXT; 4198 unsigned Imm, WhichResult; 4199 4200 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4201 return (EltSize >= 32 || 4202 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4203 isVREVMask(M, VT, 64) || 4204 isVREVMask(M, VT, 32) || 4205 isVREVMask(M, VT, 16) || 4206 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4207 isVTBLMask(M, VT) || 4208 isVTRNMask(M, VT, WhichResult) || 4209 isVUZPMask(M, VT, WhichResult) || 4210 isVZIPMask(M, VT, WhichResult) || 4211 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4212 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4213 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4214} 4215 4216/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4217/// the specified operations to build the shuffle. 4218static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4219 SDValue RHS, SelectionDAG &DAG, 4220 DebugLoc dl) { 4221 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4222 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4223 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4224 4225 enum { 4226 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4227 OP_VREV, 4228 OP_VDUP0, 4229 OP_VDUP1, 4230 OP_VDUP2, 4231 OP_VDUP3, 4232 OP_VEXT1, 4233 OP_VEXT2, 4234 OP_VEXT3, 4235 OP_VUZPL, // VUZP, left result 4236 OP_VUZPR, // VUZP, right result 4237 OP_VZIPL, // VZIP, left result 4238 OP_VZIPR, // VZIP, right result 4239 OP_VTRNL, // VTRN, left result 4240 OP_VTRNR // VTRN, right result 4241 }; 4242 4243 if (OpNum == OP_COPY) { 4244 if (LHSID == (1*9+2)*9+3) return LHS; 4245 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4246 return RHS; 4247 } 4248 4249 SDValue OpLHS, OpRHS; 4250 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4251 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4252 EVT VT = OpLHS.getValueType(); 4253 4254 switch (OpNum) { 4255 default: llvm_unreachable("Unknown shuffle opcode!"); 4256 case OP_VREV: 4257 // VREV divides the vector in half and swaps within the half. 4258 if (VT.getVectorElementType() == MVT::i32 || 4259 VT.getVectorElementType() == MVT::f32) 4260 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4261 // vrev <4 x i16> -> VREV32 4262 if (VT.getVectorElementType() == MVT::i16) 4263 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4264 // vrev <4 x i8> -> VREV16 4265 assert(VT.getVectorElementType() == MVT::i8); 4266 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4267 case OP_VDUP0: 4268 case OP_VDUP1: 4269 case OP_VDUP2: 4270 case OP_VDUP3: 4271 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4272 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4273 case OP_VEXT1: 4274 case OP_VEXT2: 4275 case OP_VEXT3: 4276 return DAG.getNode(ARMISD::VEXT, dl, VT, 4277 OpLHS, OpRHS, 4278 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4279 case OP_VUZPL: 4280 case OP_VUZPR: 4281 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4282 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4283 case OP_VZIPL: 4284 case OP_VZIPR: 4285 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4286 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4287 case OP_VTRNL: 4288 case OP_VTRNR: 4289 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4290 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4291 } 4292} 4293 4294static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4295 SmallVectorImpl<int> &ShuffleMask, 4296 SelectionDAG &DAG) { 4297 // Check to see if we can use the VTBL instruction. 4298 SDValue V1 = Op.getOperand(0); 4299 SDValue V2 = Op.getOperand(1); 4300 DebugLoc DL = Op.getDebugLoc(); 4301 4302 SmallVector<SDValue, 8> VTBLMask; 4303 for (SmallVectorImpl<int>::iterator 4304 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4305 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4306 4307 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4308 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4309 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4310 &VTBLMask[0], 8)); 4311 4312 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4313 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4314 &VTBLMask[0], 8)); 4315} 4316 4317static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4318 SDValue V1 = Op.getOperand(0); 4319 SDValue V2 = Op.getOperand(1); 4320 DebugLoc dl = Op.getDebugLoc(); 4321 EVT VT = Op.getValueType(); 4322 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4323 SmallVector<int, 8> ShuffleMask; 4324 4325 // Convert shuffles that are directly supported on NEON to target-specific 4326 // DAG nodes, instead of keeping them as shuffles and matching them again 4327 // during code selection. This is more efficient and avoids the possibility 4328 // of inconsistencies between legalization and selection. 4329 // FIXME: floating-point vectors should be canonicalized to integer vectors 4330 // of the same time so that they get CSEd properly. 4331 SVN->getMask(ShuffleMask); 4332 4333 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4334 if (EltSize <= 32) { 4335 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4336 int Lane = SVN->getSplatIndex(); 4337 // If this is undef splat, generate it via "just" vdup, if possible. 4338 if (Lane == -1) Lane = 0; 4339 4340 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4341 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4342 } 4343 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4344 DAG.getConstant(Lane, MVT::i32)); 4345 } 4346 4347 bool ReverseVEXT; 4348 unsigned Imm; 4349 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4350 if (ReverseVEXT) 4351 std::swap(V1, V2); 4352 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4353 DAG.getConstant(Imm, MVT::i32)); 4354 } 4355 4356 if (isVREVMask(ShuffleMask, VT, 64)) 4357 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4358 if (isVREVMask(ShuffleMask, VT, 32)) 4359 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4360 if (isVREVMask(ShuffleMask, VT, 16)) 4361 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4362 4363 // Check for Neon shuffles that modify both input vectors in place. 4364 // If both results are used, i.e., if there are two shuffles with the same 4365 // source operands and with masks corresponding to both results of one of 4366 // these operations, DAG memoization will ensure that a single node is 4367 // used for both shuffles. 4368 unsigned WhichResult; 4369 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4370 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4371 V1, V2).getValue(WhichResult); 4372 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4373 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4374 V1, V2).getValue(WhichResult); 4375 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4376 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4377 V1, V2).getValue(WhichResult); 4378 4379 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4381 V1, V1).getValue(WhichResult); 4382 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4383 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4384 V1, V1).getValue(WhichResult); 4385 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4386 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4387 V1, V1).getValue(WhichResult); 4388 } 4389 4390 // If the shuffle is not directly supported and it has 4 elements, use 4391 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4392 unsigned NumElts = VT.getVectorNumElements(); 4393 if (NumElts == 4) { 4394 unsigned PFIndexes[4]; 4395 for (unsigned i = 0; i != 4; ++i) { 4396 if (ShuffleMask[i] < 0) 4397 PFIndexes[i] = 8; 4398 else 4399 PFIndexes[i] = ShuffleMask[i]; 4400 } 4401 4402 // Compute the index in the perfect shuffle table. 4403 unsigned PFTableIndex = 4404 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4405 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4406 unsigned Cost = (PFEntry >> 30); 4407 4408 if (Cost <= 4) 4409 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4410 } 4411 4412 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4413 if (EltSize >= 32) { 4414 // Do the expansion with floating-point types, since that is what the VFP 4415 // registers are defined to use, and since i64 is not legal. 4416 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4417 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4418 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4419 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4420 SmallVector<SDValue, 8> Ops; 4421 for (unsigned i = 0; i < NumElts; ++i) { 4422 if (ShuffleMask[i] < 0) 4423 Ops.push_back(DAG.getUNDEF(EltVT)); 4424 else 4425 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4426 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4427 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4428 MVT::i32))); 4429 } 4430 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4431 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4432 } 4433 4434 if (VT == MVT::v8i8) { 4435 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4436 if (NewOp.getNode()) 4437 return NewOp; 4438 } 4439 4440 return SDValue(); 4441} 4442 4443static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4444 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4445 SDValue Lane = Op.getOperand(1); 4446 if (!isa<ConstantSDNode>(Lane)) 4447 return SDValue(); 4448 4449 SDValue Vec = Op.getOperand(0); 4450 if (Op.getValueType() == MVT::i32 && 4451 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4452 DebugLoc dl = Op.getDebugLoc(); 4453 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4454 } 4455 4456 return Op; 4457} 4458 4459static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4460 // The only time a CONCAT_VECTORS operation can have legal types is when 4461 // two 64-bit vectors are concatenated to a 128-bit vector. 4462 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4463 "unexpected CONCAT_VECTORS"); 4464 DebugLoc dl = Op.getDebugLoc(); 4465 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4466 SDValue Op0 = Op.getOperand(0); 4467 SDValue Op1 = Op.getOperand(1); 4468 if (Op0.getOpcode() != ISD::UNDEF) 4469 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4470 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4471 DAG.getIntPtrConstant(0)); 4472 if (Op1.getOpcode() != ISD::UNDEF) 4473 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4474 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4475 DAG.getIntPtrConstant(1)); 4476 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4477} 4478 4479/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4480/// element has been zero/sign-extended, depending on the isSigned parameter, 4481/// from an integer type half its size. 4482static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4483 bool isSigned) { 4484 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4485 EVT VT = N->getValueType(0); 4486 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4487 SDNode *BVN = N->getOperand(0).getNode(); 4488 if (BVN->getValueType(0) != MVT::v4i32 || 4489 BVN->getOpcode() != ISD::BUILD_VECTOR) 4490 return false; 4491 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4492 unsigned HiElt = 1 - LoElt; 4493 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4494 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4495 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4496 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4497 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4498 return false; 4499 if (isSigned) { 4500 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4501 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4502 return true; 4503 } else { 4504 if (Hi0->isNullValue() && Hi1->isNullValue()) 4505 return true; 4506 } 4507 return false; 4508 } 4509 4510 if (N->getOpcode() != ISD::BUILD_VECTOR) 4511 return false; 4512 4513 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4514 SDNode *Elt = N->getOperand(i).getNode(); 4515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4517 unsigned HalfSize = EltSize / 2; 4518 if (isSigned) { 4519 int64_t SExtVal = C->getSExtValue(); 4520 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) 4521 return false; 4522 } else { 4523 if ((C->getZExtValue() >> HalfSize) != 0) 4524 return false; 4525 } 4526 continue; 4527 } 4528 return false; 4529 } 4530 4531 return true; 4532} 4533 4534/// isSignExtended - Check if a node is a vector value that is sign-extended 4535/// or a constant BUILD_VECTOR with sign-extended elements. 4536static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4537 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4538 return true; 4539 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4540 return true; 4541 return false; 4542} 4543 4544/// isZeroExtended - Check if a node is a vector value that is zero-extended 4545/// or a constant BUILD_VECTOR with zero-extended elements. 4546static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4547 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4548 return true; 4549 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4550 return true; 4551 return false; 4552} 4553 4554/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4555/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4556static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4557 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4558 return N->getOperand(0); 4559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4560 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4561 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4562 LD->isNonTemporal(), LD->getAlignment()); 4563 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4564 // have been legalized as a BITCAST from v4i32. 4565 if (N->getOpcode() == ISD::BITCAST) { 4566 SDNode *BVN = N->getOperand(0).getNode(); 4567 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4568 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4569 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4570 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4571 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4572 } 4573 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4574 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4575 EVT VT = N->getValueType(0); 4576 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4577 unsigned NumElts = VT.getVectorNumElements(); 4578 MVT TruncVT = MVT::getIntegerVT(EltSize); 4579 SmallVector<SDValue, 8> Ops; 4580 for (unsigned i = 0; i != NumElts; ++i) { 4581 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4582 const APInt &CInt = C->getAPIntValue(); 4583 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4584 } 4585 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4586 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4587} 4588 4589static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4590 unsigned Opcode = N->getOpcode(); 4591 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4592 SDNode *N0 = N->getOperand(0).getNode(); 4593 SDNode *N1 = N->getOperand(1).getNode(); 4594 return N0->hasOneUse() && N1->hasOneUse() && 4595 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4596 } 4597 return false; 4598} 4599 4600static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4601 unsigned Opcode = N->getOpcode(); 4602 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4603 SDNode *N0 = N->getOperand(0).getNode(); 4604 SDNode *N1 = N->getOperand(1).getNode(); 4605 return N0->hasOneUse() && N1->hasOneUse() && 4606 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4607 } 4608 return false; 4609} 4610 4611static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4612 // Multiplications are only custom-lowered for 128-bit vectors so that 4613 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4614 EVT VT = Op.getValueType(); 4615 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4616 SDNode *N0 = Op.getOperand(0).getNode(); 4617 SDNode *N1 = Op.getOperand(1).getNode(); 4618 unsigned NewOpc = 0; 4619 bool isMLA = false; 4620 bool isN0SExt = isSignExtended(N0, DAG); 4621 bool isN1SExt = isSignExtended(N1, DAG); 4622 if (isN0SExt && isN1SExt) 4623 NewOpc = ARMISD::VMULLs; 4624 else { 4625 bool isN0ZExt = isZeroExtended(N0, DAG); 4626 bool isN1ZExt = isZeroExtended(N1, DAG); 4627 if (isN0ZExt && isN1ZExt) 4628 NewOpc = ARMISD::VMULLu; 4629 else if (isN1SExt || isN1ZExt) { 4630 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4631 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4632 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4633 NewOpc = ARMISD::VMULLs; 4634 isMLA = true; 4635 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4636 NewOpc = ARMISD::VMULLu; 4637 isMLA = true; 4638 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4639 std::swap(N0, N1); 4640 NewOpc = ARMISD::VMULLu; 4641 isMLA = true; 4642 } 4643 } 4644 4645 if (!NewOpc) { 4646 if (VT == MVT::v2i64) 4647 // Fall through to expand this. It is not legal. 4648 return SDValue(); 4649 else 4650 // Other vector multiplications are legal. 4651 return Op; 4652 } 4653 } 4654 4655 // Legalize to a VMULL instruction. 4656 DebugLoc DL = Op.getDebugLoc(); 4657 SDValue Op0; 4658 SDValue Op1 = SkipExtension(N1, DAG); 4659 if (!isMLA) { 4660 Op0 = SkipExtension(N0, DAG); 4661 assert(Op0.getValueType().is64BitVector() && 4662 Op1.getValueType().is64BitVector() && 4663 "unexpected types for extended operands to VMULL"); 4664 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4665 } 4666 4667 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4668 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4669 // vmull q0, d4, d6 4670 // vmlal q0, d5, d6 4671 // is faster than 4672 // vaddl q0, d4, d5 4673 // vmovl q1, d6 4674 // vmul q0, q0, q1 4675 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4676 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4677 EVT Op1VT = Op1.getValueType(); 4678 return DAG.getNode(N0->getOpcode(), DL, VT, 4679 DAG.getNode(NewOpc, DL, VT, 4680 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4681 DAG.getNode(NewOpc, DL, VT, 4682 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4683} 4684 4685static SDValue 4686LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4687 // Convert to float 4688 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4689 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4690 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4691 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4692 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4693 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4694 // Get reciprocal estimate. 4695 // float4 recip = vrecpeq_f32(yf); 4696 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4697 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4698 // Because char has a smaller range than uchar, we can actually get away 4699 // without any newton steps. This requires that we use a weird bias 4700 // of 0xb000, however (again, this has been exhaustively tested). 4701 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4702 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4703 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4704 Y = DAG.getConstant(0xb000, MVT::i32); 4705 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4706 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4707 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4708 // Convert back to short. 4709 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4710 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4711 return X; 4712} 4713 4714static SDValue 4715LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4716 SDValue N2; 4717 // Convert to float. 4718 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4719 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4720 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4721 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4722 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4723 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4724 4725 // Use reciprocal estimate and one refinement step. 4726 // float4 recip = vrecpeq_f32(yf); 4727 // recip *= vrecpsq_f32(yf, recip); 4728 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4729 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4730 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4731 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4732 N1, N2); 4733 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4734 // Because short has a smaller range than ushort, we can actually get away 4735 // with only a single newton step. This requires that we use a weird bias 4736 // of 89, however (again, this has been exhaustively tested). 4737 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4738 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4739 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4740 N1 = DAG.getConstant(0x89, MVT::i32); 4741 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4742 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4743 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4744 // Convert back to integer and return. 4745 // return vmovn_s32(vcvt_s32_f32(result)); 4746 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4747 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4748 return N0; 4749} 4750 4751static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4752 EVT VT = Op.getValueType(); 4753 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4754 "unexpected type for custom-lowering ISD::SDIV"); 4755 4756 DebugLoc dl = Op.getDebugLoc(); 4757 SDValue N0 = Op.getOperand(0); 4758 SDValue N1 = Op.getOperand(1); 4759 SDValue N2, N3; 4760 4761 if (VT == MVT::v8i8) { 4762 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4763 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4764 4765 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4766 DAG.getIntPtrConstant(4)); 4767 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4768 DAG.getIntPtrConstant(4)); 4769 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4770 DAG.getIntPtrConstant(0)); 4771 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4772 DAG.getIntPtrConstant(0)); 4773 4774 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4775 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4776 4777 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4778 N0 = LowerCONCAT_VECTORS(N0, DAG); 4779 4780 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4781 return N0; 4782 } 4783 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4784} 4785 4786static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4787 EVT VT = Op.getValueType(); 4788 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4789 "unexpected type for custom-lowering ISD::UDIV"); 4790 4791 DebugLoc dl = Op.getDebugLoc(); 4792 SDValue N0 = Op.getOperand(0); 4793 SDValue N1 = Op.getOperand(1); 4794 SDValue N2, N3; 4795 4796 if (VT == MVT::v8i8) { 4797 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4798 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4799 4800 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4801 DAG.getIntPtrConstant(4)); 4802 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4803 DAG.getIntPtrConstant(4)); 4804 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4805 DAG.getIntPtrConstant(0)); 4806 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4807 DAG.getIntPtrConstant(0)); 4808 4809 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4810 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4811 4812 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4813 N0 = LowerCONCAT_VECTORS(N0, DAG); 4814 4815 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4816 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4817 N0); 4818 return N0; 4819 } 4820 4821 // v4i16 sdiv ... Convert to float. 4822 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4823 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4824 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4825 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4826 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4827 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4828 4829 // Use reciprocal estimate and two refinement steps. 4830 // float4 recip = vrecpeq_f32(yf); 4831 // recip *= vrecpsq_f32(yf, recip); 4832 // recip *= vrecpsq_f32(yf, recip); 4833 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4834 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4835 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4836 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4837 BN1, N2); 4838 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4839 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4840 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4841 BN1, N2); 4842 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4843 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4844 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4845 // and that it will never cause us to return an answer too large). 4846 // float4 result = as_float4(as_int4(xf*recip) + 2); 4847 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4848 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4849 N1 = DAG.getConstant(2, MVT::i32); 4850 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4851 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4852 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4853 // Convert back to integer and return. 4854 // return vmovn_u32(vcvt_s32_f32(result)); 4855 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4856 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4857 return N0; 4858} 4859 4860static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4861 EVT VT = Op.getNode()->getValueType(0); 4862 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4863 4864 unsigned Opc; 4865 bool ExtraOp = false; 4866 switch (Op.getOpcode()) { 4867 default: assert(0 && "Invalid code"); 4868 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4869 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4870 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4871 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4872 } 4873 4874 if (!ExtraOp) 4875 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4876 Op.getOperand(1)); 4877 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4878 Op.getOperand(1), Op.getOperand(2)); 4879} 4880 4881static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 4882 // Monotonic load/store is legal for all targets 4883 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 4884 return Op; 4885 4886 // Aquire/Release load/store is not legal for targets without a 4887 // dmb or equivalent available. 4888 return SDValue(); 4889} 4890 4891 4892static void 4893ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 4894 SelectionDAG &DAG, unsigned NewOp) { 4895 EVT T = Node->getValueType(0); 4896 DebugLoc dl = Node->getDebugLoc(); 4897 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 4898 4899 SmallVector<SDValue, 6> Ops; 4900 Ops.push_back(Node->getOperand(0)); // Chain 4901 Ops.push_back(Node->getOperand(1)); // Ptr 4902 // Low part of Val1 4903 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4904 Node->getOperand(2), DAG.getIntPtrConstant(0))); 4905 // High part of Val1 4906 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4907 Node->getOperand(2), DAG.getIntPtrConstant(1))); 4908 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 4909 // High part of Val1 4910 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4911 Node->getOperand(3), DAG.getIntPtrConstant(0))); 4912 // High part of Val2 4913 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4914 Node->getOperand(3), DAG.getIntPtrConstant(1))); 4915 } 4916 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4917 SDValue Result = 4918 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 4919 cast<MemSDNode>(Node)->getMemOperand()); 4920 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 4921 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 4922 Results.push_back(Result.getValue(2)); 4923} 4924 4925SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4926 switch (Op.getOpcode()) { 4927 default: llvm_unreachable("Don't know how to custom lower this!"); 4928 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4929 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4930 case ISD::GlobalAddress: 4931 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 4932 LowerGlobalAddressELF(Op, DAG); 4933 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4934 case ISD::SELECT: return LowerSELECT(Op, DAG); 4935 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4936 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 4937 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 4938 case ISD::VASTART: return LowerVASTART(Op, DAG); 4939 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 4940 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 4941 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 4942 case ISD::SINT_TO_FP: 4943 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 4944 case ISD::FP_TO_SINT: 4945 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 4946 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4947 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4948 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4949 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 4950 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 4951 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 4952 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); 4953 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 4954 Subtarget); 4955 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 4956 case ISD::SHL: 4957 case ISD::SRL: 4958 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 4959 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 4960 case ISD::SRL_PARTS: 4961 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 4962 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 4963 case ISD::SETCC: return LowerVSETCC(Op, DAG); 4964 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 4965 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4966 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4967 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 4968 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4969 case ISD::MUL: return LowerMUL(Op, DAG); 4970 case ISD::SDIV: return LowerSDIV(Op, DAG); 4971 case ISD::UDIV: return LowerUDIV(Op, DAG); 4972 case ISD::ADDC: 4973 case ISD::ADDE: 4974 case ISD::SUBC: 4975 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 4976 case ISD::ATOMIC_LOAD: 4977 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 4978 } 4979 return SDValue(); 4980} 4981 4982/// ReplaceNodeResults - Replace the results of node with an illegal result 4983/// type with new values built out of custom code. 4984void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 4985 SmallVectorImpl<SDValue>&Results, 4986 SelectionDAG &DAG) const { 4987 SDValue Res; 4988 switch (N->getOpcode()) { 4989 default: 4990 llvm_unreachable("Don't know how to custom expand this!"); 4991 break; 4992 case ISD::BITCAST: 4993 Res = ExpandBITCAST(N, DAG); 4994 break; 4995 case ISD::SRL: 4996 case ISD::SRA: 4997 Res = Expand64BitShift(N, DAG, Subtarget); 4998 break; 4999 case ISD::ATOMIC_LOAD_ADD: 5000 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5001 return; 5002 case ISD::ATOMIC_LOAD_AND: 5003 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5004 return; 5005 case ISD::ATOMIC_LOAD_NAND: 5006 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5007 return; 5008 case ISD::ATOMIC_LOAD_OR: 5009 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5010 return; 5011 case ISD::ATOMIC_LOAD_SUB: 5012 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5013 return; 5014 case ISD::ATOMIC_LOAD_XOR: 5015 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5016 return; 5017 case ISD::ATOMIC_SWAP: 5018 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5019 return; 5020 case ISD::ATOMIC_CMP_SWAP: 5021 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5022 return; 5023 } 5024 if (Res.getNode()) 5025 Results.push_back(Res); 5026} 5027 5028//===----------------------------------------------------------------------===// 5029// ARM Scheduler Hooks 5030//===----------------------------------------------------------------------===// 5031 5032MachineBasicBlock * 5033ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5034 MachineBasicBlock *BB, 5035 unsigned Size) const { 5036 unsigned dest = MI->getOperand(0).getReg(); 5037 unsigned ptr = MI->getOperand(1).getReg(); 5038 unsigned oldval = MI->getOperand(2).getReg(); 5039 unsigned newval = MI->getOperand(3).getReg(); 5040 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5041 DebugLoc dl = MI->getDebugLoc(); 5042 bool isThumb2 = Subtarget->isThumb2(); 5043 5044 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5045 unsigned scratch = 5046 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5047 : ARM::GPRRegisterClass); 5048 5049 if (isThumb2) { 5050 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5051 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5052 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5053 } 5054 5055 unsigned ldrOpc, strOpc; 5056 switch (Size) { 5057 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5058 case 1: 5059 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5060 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5061 break; 5062 case 2: 5063 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5064 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5065 break; 5066 case 4: 5067 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5068 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5069 break; 5070 } 5071 5072 MachineFunction *MF = BB->getParent(); 5073 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5074 MachineFunction::iterator It = BB; 5075 ++It; // insert the new blocks after the current block 5076 5077 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5078 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5079 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5080 MF->insert(It, loop1MBB); 5081 MF->insert(It, loop2MBB); 5082 MF->insert(It, exitMBB); 5083 5084 // Transfer the remainder of BB and its successor edges to exitMBB. 5085 exitMBB->splice(exitMBB->begin(), BB, 5086 llvm::next(MachineBasicBlock::iterator(MI)), 5087 BB->end()); 5088 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5089 5090 // thisMBB: 5091 // ... 5092 // fallthrough --> loop1MBB 5093 BB->addSuccessor(loop1MBB); 5094 5095 // loop1MBB: 5096 // ldrex dest, [ptr] 5097 // cmp dest, oldval 5098 // bne exitMBB 5099 BB = loop1MBB; 5100 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5101 if (ldrOpc == ARM::t2LDREX) 5102 MIB.addImm(0); 5103 AddDefaultPred(MIB); 5104 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5105 .addReg(dest).addReg(oldval)); 5106 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5107 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5108 BB->addSuccessor(loop2MBB); 5109 BB->addSuccessor(exitMBB); 5110 5111 // loop2MBB: 5112 // strex scratch, newval, [ptr] 5113 // cmp scratch, #0 5114 // bne loop1MBB 5115 BB = loop2MBB; 5116 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5117 if (strOpc == ARM::t2STREX) 5118 MIB.addImm(0); 5119 AddDefaultPred(MIB); 5120 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5121 .addReg(scratch).addImm(0)); 5122 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5123 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5124 BB->addSuccessor(loop1MBB); 5125 BB->addSuccessor(exitMBB); 5126 5127 // exitMBB: 5128 // ... 5129 BB = exitMBB; 5130 5131 MI->eraseFromParent(); // The instruction is gone now. 5132 5133 return BB; 5134} 5135 5136MachineBasicBlock * 5137ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5138 unsigned Size, unsigned BinOpcode) const { 5139 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5140 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5141 5142 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5143 MachineFunction *MF = BB->getParent(); 5144 MachineFunction::iterator It = BB; 5145 ++It; 5146 5147 unsigned dest = MI->getOperand(0).getReg(); 5148 unsigned ptr = MI->getOperand(1).getReg(); 5149 unsigned incr = MI->getOperand(2).getReg(); 5150 DebugLoc dl = MI->getDebugLoc(); 5151 bool isThumb2 = Subtarget->isThumb2(); 5152 5153 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5154 if (isThumb2) { 5155 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5156 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5157 } 5158 5159 unsigned ldrOpc, strOpc; 5160 switch (Size) { 5161 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5162 case 1: 5163 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5164 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5165 break; 5166 case 2: 5167 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5168 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5169 break; 5170 case 4: 5171 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5172 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5173 break; 5174 } 5175 5176 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5177 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5178 MF->insert(It, loopMBB); 5179 MF->insert(It, exitMBB); 5180 5181 // Transfer the remainder of BB and its successor edges to exitMBB. 5182 exitMBB->splice(exitMBB->begin(), BB, 5183 llvm::next(MachineBasicBlock::iterator(MI)), 5184 BB->end()); 5185 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5186 5187 TargetRegisterClass *TRC = 5188 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5189 unsigned scratch = MRI.createVirtualRegister(TRC); 5190 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5191 5192 // thisMBB: 5193 // ... 5194 // fallthrough --> loopMBB 5195 BB->addSuccessor(loopMBB); 5196 5197 // loopMBB: 5198 // ldrex dest, ptr 5199 // <binop> scratch2, dest, incr 5200 // strex scratch, scratch2, ptr 5201 // cmp scratch, #0 5202 // bne- loopMBB 5203 // fallthrough --> exitMBB 5204 BB = loopMBB; 5205 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5206 if (ldrOpc == ARM::t2LDREX) 5207 MIB.addImm(0); 5208 AddDefaultPred(MIB); 5209 if (BinOpcode) { 5210 // operand order needs to go the other way for NAND 5211 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5212 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5213 addReg(incr).addReg(dest)).addReg(0); 5214 else 5215 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5216 addReg(dest).addReg(incr)).addReg(0); 5217 } 5218 5219 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5220 if (strOpc == ARM::t2STREX) 5221 MIB.addImm(0); 5222 AddDefaultPred(MIB); 5223 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5224 .addReg(scratch).addImm(0)); 5225 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5226 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5227 5228 BB->addSuccessor(loopMBB); 5229 BB->addSuccessor(exitMBB); 5230 5231 // exitMBB: 5232 // ... 5233 BB = exitMBB; 5234 5235 MI->eraseFromParent(); // The instruction is gone now. 5236 5237 return BB; 5238} 5239 5240MachineBasicBlock * 5241ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5242 MachineBasicBlock *BB, 5243 unsigned Size, 5244 bool signExtend, 5245 ARMCC::CondCodes Cond) const { 5246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5247 5248 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5249 MachineFunction *MF = BB->getParent(); 5250 MachineFunction::iterator It = BB; 5251 ++It; 5252 5253 unsigned dest = MI->getOperand(0).getReg(); 5254 unsigned ptr = MI->getOperand(1).getReg(); 5255 unsigned incr = MI->getOperand(2).getReg(); 5256 unsigned oldval = dest; 5257 DebugLoc dl = MI->getDebugLoc(); 5258 bool isThumb2 = Subtarget->isThumb2(); 5259 5260 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5261 if (isThumb2) { 5262 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5263 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5264 } 5265 5266 unsigned ldrOpc, strOpc, extendOpc; 5267 switch (Size) { 5268 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5269 case 1: 5270 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5271 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5272 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5273 break; 5274 case 2: 5275 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5276 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5277 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5278 break; 5279 case 4: 5280 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5281 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5282 extendOpc = 0; 5283 break; 5284 } 5285 5286 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5287 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5288 MF->insert(It, loopMBB); 5289 MF->insert(It, exitMBB); 5290 5291 // Transfer the remainder of BB and its successor edges to exitMBB. 5292 exitMBB->splice(exitMBB->begin(), BB, 5293 llvm::next(MachineBasicBlock::iterator(MI)), 5294 BB->end()); 5295 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5296 5297 TargetRegisterClass *TRC = 5298 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5299 unsigned scratch = MRI.createVirtualRegister(TRC); 5300 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5301 5302 // thisMBB: 5303 // ... 5304 // fallthrough --> loopMBB 5305 BB->addSuccessor(loopMBB); 5306 5307 // loopMBB: 5308 // ldrex dest, ptr 5309 // (sign extend dest, if required) 5310 // cmp dest, incr 5311 // cmov.cond scratch2, dest, incr 5312 // strex scratch, scratch2, ptr 5313 // cmp scratch, #0 5314 // bne- loopMBB 5315 // fallthrough --> exitMBB 5316 BB = loopMBB; 5317 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5318 if (ldrOpc == ARM::t2LDREX) 5319 MIB.addImm(0); 5320 AddDefaultPred(MIB); 5321 5322 // Sign extend the value, if necessary. 5323 if (signExtend && extendOpc) { 5324 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5325 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5326 .addReg(dest) 5327 .addImm(0)); 5328 } 5329 5330 // Build compare and cmov instructions. 5331 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5332 .addReg(oldval).addReg(incr)); 5333 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5334 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5335 5336 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5337 if (strOpc == ARM::t2STREX) 5338 MIB.addImm(0); 5339 AddDefaultPred(MIB); 5340 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5341 .addReg(scratch).addImm(0)); 5342 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5343 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5344 5345 BB->addSuccessor(loopMBB); 5346 BB->addSuccessor(exitMBB); 5347 5348 // exitMBB: 5349 // ... 5350 BB = exitMBB; 5351 5352 MI->eraseFromParent(); // The instruction is gone now. 5353 5354 return BB; 5355} 5356 5357MachineBasicBlock * 5358ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5359 unsigned Op1, unsigned Op2, 5360 bool NeedsCarry, bool IsCmpxchg) const { 5361 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5362 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5363 5364 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5365 MachineFunction *MF = BB->getParent(); 5366 MachineFunction::iterator It = BB; 5367 ++It; 5368 5369 unsigned destlo = MI->getOperand(0).getReg(); 5370 unsigned desthi = MI->getOperand(1).getReg(); 5371 unsigned ptr = MI->getOperand(2).getReg(); 5372 unsigned vallo = MI->getOperand(3).getReg(); 5373 unsigned valhi = MI->getOperand(4).getReg(); 5374 DebugLoc dl = MI->getDebugLoc(); 5375 bool isThumb2 = Subtarget->isThumb2(); 5376 5377 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5378 if (isThumb2) { 5379 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5380 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5381 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5382 } 5383 5384 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5385 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5386 5387 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5388 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5389 if (IsCmpxchg) { 5390 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5391 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5392 } 5393 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5394 MF->insert(It, loopMBB); 5395 if (IsCmpxchg) { 5396 MF->insert(It, contBB); 5397 MF->insert(It, cont2BB); 5398 } 5399 MF->insert(It, exitMBB); 5400 5401 // Transfer the remainder of BB and its successor edges to exitMBB. 5402 exitMBB->splice(exitMBB->begin(), BB, 5403 llvm::next(MachineBasicBlock::iterator(MI)), 5404 BB->end()); 5405 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5406 5407 TargetRegisterClass *TRC = 5408 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5409 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5410 5411 // thisMBB: 5412 // ... 5413 // fallthrough --> loopMBB 5414 BB->addSuccessor(loopMBB); 5415 5416 // loopMBB: 5417 // ldrexd r2, r3, ptr 5418 // <binopa> r0, r2, incr 5419 // <binopb> r1, r3, incr 5420 // strexd storesuccess, r0, r1, ptr 5421 // cmp storesuccess, #0 5422 // bne- loopMBB 5423 // fallthrough --> exitMBB 5424 // 5425 // Note that the registers are explicitly specified because there is not any 5426 // way to force the register allocator to allocate a register pair. 5427 // 5428 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5429 // need to properly enforce the restriction that the two output registers 5430 // for ldrexd must be different. 5431 BB = loopMBB; 5432 // Load 5433 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5434 .addReg(ARM::R2, RegState::Define) 5435 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5436 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5437 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5438 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5439 5440 if (IsCmpxchg) { 5441 // Add early exit 5442 for (unsigned i = 0; i < 2; i++) { 5443 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5444 ARM::CMPrr)) 5445 .addReg(i == 0 ? destlo : desthi) 5446 .addReg(i == 0 ? vallo : valhi)); 5447 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5448 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5449 BB->addSuccessor(exitMBB); 5450 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5451 BB = (i == 0 ? contBB : cont2BB); 5452 } 5453 5454 // Copy to physregs for strexd 5455 unsigned setlo = MI->getOperand(5).getReg(); 5456 unsigned sethi = MI->getOperand(6).getReg(); 5457 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5458 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5459 } else if (Op1) { 5460 // Perform binary operation 5461 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5462 .addReg(destlo).addReg(vallo)) 5463 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5464 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5465 .addReg(desthi).addReg(valhi)).addReg(0); 5466 } else { 5467 // Copy to physregs for strexd 5468 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5469 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5470 } 5471 5472 // Store 5473 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5474 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5475 // Cmp+jump 5476 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5477 .addReg(storesuccess).addImm(0)); 5478 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5479 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5480 5481 BB->addSuccessor(loopMBB); 5482 BB->addSuccessor(exitMBB); 5483 5484 // exitMBB: 5485 // ... 5486 BB = exitMBB; 5487 5488 MI->eraseFromParent(); // The instruction is gone now. 5489 5490 return BB; 5491} 5492 5493/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5494/// registers the function context. 5495void ARMTargetLowering:: 5496SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5497 MachineBasicBlock *DispatchBB, int FI) const { 5498 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5499 DebugLoc dl = MI->getDebugLoc(); 5500 MachineFunction *MF = MBB->getParent(); 5501 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5502 MachineConstantPool *MCP = MF->getConstantPool(); 5503 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5504 const Function *F = MF->getFunction(); 5505 5506 bool isThumb = Subtarget->isThumb(); 5507 bool isThumb2 = Subtarget->isThumb2(); 5508 5509 unsigned PCLabelId = AFI->createPICLabelUId(); 5510 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5511 ARMConstantPoolValue *CPV = 5512 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5513 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5514 5515 const TargetRegisterClass *TRC = 5516 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5517 5518 // Grab constant pool and fixed stack memory operands. 5519 MachineMemOperand *CPMMO = 5520 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5521 MachineMemOperand::MOLoad, 4, 4); 5522 5523 MachineMemOperand *FIMMOSt = 5524 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5525 MachineMemOperand::MOStore, 4, 4); 5526 5527 // Load the address of the dispatch MBB into the jump buffer. 5528 if (isThumb2) { 5529 // Incoming value: jbuf 5530 // ldr.n r5, LCPI1_1 5531 // orr r5, r5, #1 5532 // add r5, pc 5533 // str r5, [$jbuf, #+4] ; &jbuf[1] 5534 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5535 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5536 .addConstantPoolIndex(CPI) 5537 .addMemOperand(CPMMO)); 5538 // Set the low bit because of thumb mode. 5539 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5540 AddDefaultCC( 5541 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5542 .addReg(NewVReg1, RegState::Kill) 5543 .addImm(0x01))); 5544 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5545 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5546 .addReg(NewVReg2, RegState::Kill) 5547 .addImm(PCLabelId); 5548 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5549 .addReg(NewVReg3, RegState::Kill) 5550 .addFrameIndex(FI) 5551 .addImm(36) // &jbuf[1] :: pc 5552 .addMemOperand(FIMMOSt)); 5553 } else if (isThumb) { 5554 // Incoming value: jbuf 5555 // ldr.n r1, LCPI1_4 5556 // add r1, pc 5557 // mov r2, #1 5558 // orrs r1, r2 5559 // add r2, $jbuf, #+4 ; &jbuf[1] 5560 // str r1, [r2] 5561 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5562 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5563 .addConstantPoolIndex(CPI) 5564 .addMemOperand(CPMMO)); 5565 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5566 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5567 .addReg(NewVReg1, RegState::Kill) 5568 .addImm(PCLabelId); 5569 // Set the low bit because of thumb mode. 5570 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5571 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5572 .addReg(ARM::CPSR, RegState::Define) 5573 .addImm(1)); 5574 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5575 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5576 .addReg(ARM::CPSR, RegState::Define) 5577 .addReg(NewVReg2, RegState::Kill) 5578 .addReg(NewVReg3, RegState::Kill)); 5579 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5580 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5581 .addFrameIndex(FI) 5582 .addImm(36)); // &jbuf[1] :: pc 5583 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5584 .addReg(NewVReg4, RegState::Kill) 5585 .addReg(NewVReg5, RegState::Kill) 5586 .addImm(0) 5587 .addMemOperand(FIMMOSt)); 5588 } else { 5589 // Incoming value: jbuf 5590 // ldr r1, LCPI1_1 5591 // add r1, pc, r1 5592 // str r1, [$jbuf, #+4] ; &jbuf[1] 5593 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5594 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5595 .addConstantPoolIndex(CPI) 5596 .addImm(0) 5597 .addMemOperand(CPMMO)); 5598 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5599 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5600 .addReg(NewVReg1, RegState::Kill) 5601 .addImm(PCLabelId)); 5602 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5603 .addReg(NewVReg2, RegState::Kill) 5604 .addFrameIndex(FI) 5605 .addImm(36) // &jbuf[1] :: pc 5606 .addMemOperand(FIMMOSt)); 5607 } 5608} 5609 5610MachineBasicBlock *ARMTargetLowering:: 5611EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5613 DebugLoc dl = MI->getDebugLoc(); 5614 MachineFunction *MF = MBB->getParent(); 5615 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5616 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5617 MachineFrameInfo *MFI = MF->getFrameInfo(); 5618 int FI = MFI->getFunctionContextIndex(); 5619 5620 const TargetRegisterClass *TRC = 5621 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5622 5623 // Get a mapping of the call site numbers to all of the landing pads they're 5624 // associated with. 5625 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5626 unsigned MaxCSNum = 0; 5627 MachineModuleInfo &MMI = MF->getMMI(); 5628 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) { 5629 if (!BB->isLandingPad()) continue; 5630 5631 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5632 // pad. 5633 for (MachineBasicBlock::iterator 5634 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5635 if (!II->isEHLabel()) continue; 5636 5637 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5638 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5639 5640 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5641 for (SmallVectorImpl<unsigned>::iterator 5642 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5643 CSI != CSE; ++CSI) { 5644 CallSiteNumToLPad[*CSI].push_back(BB); 5645 MaxCSNum = std::max(MaxCSNum, *CSI); 5646 } 5647 break; 5648 } 5649 } 5650 5651 // Get an ordered list of the machine basic blocks for the jump table. 5652 std::vector<MachineBasicBlock*> LPadList; 5653 LPadList.reserve(CallSiteNumToLPad.size()); 5654 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5655 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5656 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5657 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) 5658 LPadList.push_back(*II); 5659 } 5660 5661 assert(!LPadList.empty() && 5662 "No landing pad destinations for the dispatch jump table!"); 5663 5664 // Create the jump table and associated information. 5665 MachineJumpTableInfo *JTI = 5666 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5667 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5668 unsigned UId = AFI->createJumpTableUId(); 5669 5670 // Create the MBBs for the dispatch code. 5671 5672 // Shove the dispatch's address into the return slot in the function context. 5673 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 5674 DispatchBB->setIsLandingPad(); 5675 MBB->addSuccessor(DispatchBB); 5676 5677 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 5678 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 5679 DispatchBB->addSuccessor(TrapBB); 5680 5681 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 5682 DispatchBB->addSuccessor(DispContBB); 5683 5684 // Insert and renumber MBBs. 5685 MachineBasicBlock *Last = &MF->back(); 5686 MF->insert(MF->end(), DispatchBB); 5687 MF->insert(MF->end(), DispContBB); 5688 MF->insert(MF->end(), TrapBB); 5689 MF->RenumberBlocks(Last); 5690 5691 // Insert code into the entry block that creates and registers the function 5692 // context. 5693 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 5694 5695 MachineMemOperand *FIMMOLd = 5696 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5697 MachineMemOperand::MOLoad | 5698 MachineMemOperand::MOVolatile, 4, 4); 5699 5700 if (Subtarget->isThumb2()) { 5701 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5702 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 5703 .addFrameIndex(FI) 5704 .addImm(4) 5705 .addMemOperand(FIMMOLd)); 5706 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 5707 .addReg(NewVReg1) 5708 .addImm(LPadList.size())); 5709 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 5710 .addMBB(TrapBB) 5711 .addImm(ARMCC::HI) 5712 .addReg(ARM::CPSR); 5713 5714 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5715 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2) 5716 .addJumpTableIndex(MJTI) 5717 .addImm(UId)); 5718 5719 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5720 AddDefaultCC( 5721 AddDefaultPred( 5722 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3) 5723 .addReg(NewVReg2, RegState::Kill) 5724 .addReg(NewVReg1) 5725 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5726 5727 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 5728 .addReg(NewVReg3, RegState::Kill) 5729 .addReg(NewVReg1) 5730 .addJumpTableIndex(MJTI) 5731 .addImm(UId); 5732 } else if (Subtarget->isThumb()) { 5733 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5734 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 5735 .addFrameIndex(FI) 5736 .addImm(1) 5737 .addMemOperand(FIMMOLd)); 5738 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 5739 .addReg(NewVReg1) 5740 .addImm(LPadList.size())); 5741 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 5742 .addMBB(TrapBB) 5743 .addImm(ARMCC::HI) 5744 .addReg(ARM::CPSR); 5745 5746 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5747 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 5748 .addReg(ARM::CPSR, RegState::Define) 5749 .addReg(NewVReg1) 5750 .addImm(2)); 5751 5752 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5753 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 5754 .addJumpTableIndex(MJTI) 5755 .addImm(UId)); 5756 5757 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5758 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 5759 .addReg(ARM::CPSR, RegState::Define) 5760 .addReg(NewVReg2, RegState::Kill) 5761 .addReg(NewVReg3)); 5762 5763 MachineMemOperand *JTMMOLd = 5764 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5765 MachineMemOperand::MOLoad, 4, 4); 5766 5767 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5768 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 5769 .addReg(NewVReg4, RegState::Kill) 5770 .addImm(0) 5771 .addMemOperand(JTMMOLd)); 5772 5773 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 5774 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 5775 .addReg(ARM::CPSR, RegState::Define) 5776 .addReg(NewVReg5, RegState::Kill) 5777 .addReg(NewVReg3)); 5778 5779 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 5780 .addReg(NewVReg6, RegState::Kill) 5781 .addJumpTableIndex(MJTI) 5782 .addImm(UId); 5783 } else { 5784 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5785 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 5786 .addFrameIndex(FI) 5787 .addImm(4) 5788 .addMemOperand(FIMMOLd)); 5789 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 5790 .addReg(NewVReg1) 5791 .addImm(LPadList.size())); 5792 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 5793 .addMBB(TrapBB) 5794 .addImm(ARMCC::HI) 5795 .addReg(ARM::CPSR); 5796 5797 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5798 AddDefaultCC( 5799 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2) 5800 .addReg(NewVReg1) 5801 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5802 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5803 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3) 5804 .addJumpTableIndex(MJTI) 5805 .addImm(UId)); 5806 5807 MachineMemOperand *JTMMOLd = 5808 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5809 MachineMemOperand::MOLoad, 4, 4); 5810 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5811 AddDefaultPred( 5812 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4) 5813 .addReg(NewVReg2, RegState::Kill) 5814 .addReg(NewVReg3) 5815 .addImm(0) 5816 .addMemOperand(JTMMOLd)); 5817 5818 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 5819 .addReg(NewVReg4, RegState::Kill) 5820 .addReg(NewVReg3) 5821 .addJumpTableIndex(MJTI) 5822 .addImm(UId); 5823 } 5824 5825 // Add the jump table entries as successors to the MBB. 5826 for (std::vector<MachineBasicBlock*>::iterator 5827 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) 5828 DispContBB->addSuccessor(*I); 5829 5830 // The instruction is gone now. 5831 MI->eraseFromParent(); 5832 5833 return MBB; 5834} 5835 5836static 5837MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 5838 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 5839 E = MBB->succ_end(); I != E; ++I) 5840 if (*I != Succ) 5841 return *I; 5842 llvm_unreachable("Expecting a BB with two successors!"); 5843} 5844 5845MachineBasicBlock * 5846ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5847 MachineBasicBlock *BB) const { 5848 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5849 DebugLoc dl = MI->getDebugLoc(); 5850 bool isThumb2 = Subtarget->isThumb2(); 5851 switch (MI->getOpcode()) { 5852 default: { 5853 MI->dump(); 5854 llvm_unreachable("Unexpected instr type to insert"); 5855 } 5856 // The Thumb2 pre-indexed stores have the same MI operands, they just 5857 // define them differently in the .td files from the isel patterns, so 5858 // they need pseudos. 5859 case ARM::t2STR_preidx: 5860 MI->setDesc(TII->get(ARM::t2STR_PRE)); 5861 return BB; 5862 case ARM::t2STRB_preidx: 5863 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 5864 return BB; 5865 case ARM::t2STRH_preidx: 5866 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 5867 return BB; 5868 5869 case ARM::STRi_preidx: 5870 case ARM::STRBi_preidx: { 5871 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 5872 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 5873 // Decode the offset. 5874 unsigned Offset = MI->getOperand(4).getImm(); 5875 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 5876 Offset = ARM_AM::getAM2Offset(Offset); 5877 if (isSub) 5878 Offset = -Offset; 5879 5880 MachineMemOperand *MMO = *MI->memoperands_begin(); 5881 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 5882 .addOperand(MI->getOperand(0)) // Rn_wb 5883 .addOperand(MI->getOperand(1)) // Rt 5884 .addOperand(MI->getOperand(2)) // Rn 5885 .addImm(Offset) // offset (skip GPR==zero_reg) 5886 .addOperand(MI->getOperand(5)) // pred 5887 .addOperand(MI->getOperand(6)) 5888 .addMemOperand(MMO); 5889 MI->eraseFromParent(); 5890 return BB; 5891 } 5892 case ARM::STRr_preidx: 5893 case ARM::STRBr_preidx: 5894 case ARM::STRH_preidx: { 5895 unsigned NewOpc; 5896 switch (MI->getOpcode()) { 5897 default: llvm_unreachable("unexpected opcode!"); 5898 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 5899 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 5900 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 5901 } 5902 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 5903 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 5904 MIB.addOperand(MI->getOperand(i)); 5905 MI->eraseFromParent(); 5906 return BB; 5907 } 5908 case ARM::ATOMIC_LOAD_ADD_I8: 5909 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5910 case ARM::ATOMIC_LOAD_ADD_I16: 5911 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5912 case ARM::ATOMIC_LOAD_ADD_I32: 5913 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5914 5915 case ARM::ATOMIC_LOAD_AND_I8: 5916 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5917 case ARM::ATOMIC_LOAD_AND_I16: 5918 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5919 case ARM::ATOMIC_LOAD_AND_I32: 5920 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5921 5922 case ARM::ATOMIC_LOAD_OR_I8: 5923 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5924 case ARM::ATOMIC_LOAD_OR_I16: 5925 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5926 case ARM::ATOMIC_LOAD_OR_I32: 5927 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5928 5929 case ARM::ATOMIC_LOAD_XOR_I8: 5930 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5931 case ARM::ATOMIC_LOAD_XOR_I16: 5932 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5933 case ARM::ATOMIC_LOAD_XOR_I32: 5934 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5935 5936 case ARM::ATOMIC_LOAD_NAND_I8: 5937 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5938 case ARM::ATOMIC_LOAD_NAND_I16: 5939 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5940 case ARM::ATOMIC_LOAD_NAND_I32: 5941 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5942 5943 case ARM::ATOMIC_LOAD_SUB_I8: 5944 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5945 case ARM::ATOMIC_LOAD_SUB_I16: 5946 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5947 case ARM::ATOMIC_LOAD_SUB_I32: 5948 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5949 5950 case ARM::ATOMIC_LOAD_MIN_I8: 5951 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 5952 case ARM::ATOMIC_LOAD_MIN_I16: 5953 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 5954 case ARM::ATOMIC_LOAD_MIN_I32: 5955 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 5956 5957 case ARM::ATOMIC_LOAD_MAX_I8: 5958 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 5959 case ARM::ATOMIC_LOAD_MAX_I16: 5960 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 5961 case ARM::ATOMIC_LOAD_MAX_I32: 5962 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 5963 5964 case ARM::ATOMIC_LOAD_UMIN_I8: 5965 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 5966 case ARM::ATOMIC_LOAD_UMIN_I16: 5967 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 5968 case ARM::ATOMIC_LOAD_UMIN_I32: 5969 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 5970 5971 case ARM::ATOMIC_LOAD_UMAX_I8: 5972 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 5973 case ARM::ATOMIC_LOAD_UMAX_I16: 5974 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 5975 case ARM::ATOMIC_LOAD_UMAX_I32: 5976 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 5977 5978 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 5979 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 5980 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 5981 5982 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 5983 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 5984 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 5985 5986 5987 case ARM::ATOMADD6432: 5988 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 5989 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 5990 /*NeedsCarry*/ true); 5991 case ARM::ATOMSUB6432: 5992 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 5993 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 5994 /*NeedsCarry*/ true); 5995 case ARM::ATOMOR6432: 5996 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 5997 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5998 case ARM::ATOMXOR6432: 5999 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6000 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6001 case ARM::ATOMAND6432: 6002 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6003 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6004 case ARM::ATOMSWAP6432: 6005 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6006 case ARM::ATOMCMPXCHG6432: 6007 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6008 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6009 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6010 6011 case ARM::tMOVCCr_pseudo: { 6012 // To "insert" a SELECT_CC instruction, we actually have to insert the 6013 // diamond control-flow pattern. The incoming instruction knows the 6014 // destination vreg to set, the condition code register to branch on, the 6015 // true/false values to select between, and a branch opcode to use. 6016 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6017 MachineFunction::iterator It = BB; 6018 ++It; 6019 6020 // thisMBB: 6021 // ... 6022 // TrueVal = ... 6023 // cmpTY ccX, r1, r2 6024 // bCC copy1MBB 6025 // fallthrough --> copy0MBB 6026 MachineBasicBlock *thisMBB = BB; 6027 MachineFunction *F = BB->getParent(); 6028 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6029 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6030 F->insert(It, copy0MBB); 6031 F->insert(It, sinkMBB); 6032 6033 // Transfer the remainder of BB and its successor edges to sinkMBB. 6034 sinkMBB->splice(sinkMBB->begin(), BB, 6035 llvm::next(MachineBasicBlock::iterator(MI)), 6036 BB->end()); 6037 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6038 6039 BB->addSuccessor(copy0MBB); 6040 BB->addSuccessor(sinkMBB); 6041 6042 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6043 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6044 6045 // copy0MBB: 6046 // %FalseValue = ... 6047 // # fallthrough to sinkMBB 6048 BB = copy0MBB; 6049 6050 // Update machine-CFG edges 6051 BB->addSuccessor(sinkMBB); 6052 6053 // sinkMBB: 6054 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6055 // ... 6056 BB = sinkMBB; 6057 BuildMI(*BB, BB->begin(), dl, 6058 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6059 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6060 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6061 6062 MI->eraseFromParent(); // The pseudo instruction is gone now. 6063 return BB; 6064 } 6065 6066 case ARM::BCCi64: 6067 case ARM::BCCZi64: { 6068 // If there is an unconditional branch to the other successor, remove it. 6069 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6070 6071 // Compare both parts that make up the double comparison separately for 6072 // equality. 6073 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6074 6075 unsigned LHS1 = MI->getOperand(1).getReg(); 6076 unsigned LHS2 = MI->getOperand(2).getReg(); 6077 if (RHSisZero) { 6078 AddDefaultPred(BuildMI(BB, dl, 6079 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6080 .addReg(LHS1).addImm(0)); 6081 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6082 .addReg(LHS2).addImm(0) 6083 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6084 } else { 6085 unsigned RHS1 = MI->getOperand(3).getReg(); 6086 unsigned RHS2 = MI->getOperand(4).getReg(); 6087 AddDefaultPred(BuildMI(BB, dl, 6088 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6089 .addReg(LHS1).addReg(RHS1)); 6090 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6091 .addReg(LHS2).addReg(RHS2) 6092 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6093 } 6094 6095 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6096 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6097 if (MI->getOperand(0).getImm() == ARMCC::NE) 6098 std::swap(destMBB, exitMBB); 6099 6100 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6101 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6102 if (isThumb2) 6103 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6104 else 6105 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6106 6107 MI->eraseFromParent(); // The pseudo instruction is gone now. 6108 return BB; 6109 } 6110 6111 case ARM::ABS: 6112 case ARM::t2ABS: { 6113 // To insert an ABS instruction, we have to insert the 6114 // diamond control-flow pattern. The incoming instruction knows the 6115 // source vreg to test against 0, the destination vreg to set, 6116 // the condition code register to branch on, the 6117 // true/false values to select between, and a branch opcode to use. 6118 // It transforms 6119 // V1 = ABS V0 6120 // into 6121 // V2 = MOVS V0 6122 // BCC (branch to SinkBB if V0 >= 0) 6123 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6124 // SinkBB: V1 = PHI(V2, V3) 6125 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6126 MachineFunction::iterator BBI = BB; 6127 ++BBI; 6128 MachineFunction *Fn = BB->getParent(); 6129 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6130 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6131 Fn->insert(BBI, RSBBB); 6132 Fn->insert(BBI, SinkBB); 6133 6134 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6135 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6136 bool isThumb2 = Subtarget->isThumb2(); 6137 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6138 // In Thumb mode S must not be specified if source register is the SP or 6139 // PC and if destination register is the SP, so restrict register class 6140 unsigned NewMovDstReg = MRI.createVirtualRegister( 6141 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6142 unsigned NewRsbDstReg = MRI.createVirtualRegister( 6143 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6144 6145 // Transfer the remainder of BB and its successor edges to sinkMBB. 6146 SinkBB->splice(SinkBB->begin(), BB, 6147 llvm::next(MachineBasicBlock::iterator(MI)), 6148 BB->end()); 6149 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6150 6151 BB->addSuccessor(RSBBB); 6152 BB->addSuccessor(SinkBB); 6153 6154 // fall through to SinkMBB 6155 RSBBB->addSuccessor(SinkBB); 6156 6157 // insert a movs at the end of BB 6158 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr), 6159 NewMovDstReg) 6160 .addReg(ABSSrcReg, RegState::Kill) 6161 .addImm((unsigned)ARMCC::AL).addReg(0) 6162 .addReg(ARM::CPSR, RegState::Define); 6163 6164 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6165 BuildMI(BB, dl, 6166 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6167 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6168 6169 // insert rsbri in RSBBB 6170 // Note: BCC and rsbri will be converted into predicated rsbmi 6171 // by if-conversion pass 6172 BuildMI(*RSBBB, RSBBB->begin(), dl, 6173 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6174 .addReg(NewMovDstReg, RegState::Kill) 6175 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6176 6177 // insert PHI in SinkBB, 6178 // reuse ABSDstReg to not change uses of ABS instruction 6179 BuildMI(*SinkBB, SinkBB->begin(), dl, 6180 TII->get(ARM::PHI), ABSDstReg) 6181 .addReg(NewRsbDstReg).addMBB(RSBBB) 6182 .addReg(NewMovDstReg).addMBB(BB); 6183 6184 // remove ABS instruction 6185 MI->eraseFromParent(); 6186 6187 // return last added BB 6188 return SinkBB; 6189 } 6190 } 6191} 6192 6193void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6194 SDNode *Node) const { 6195 const MCInstrDesc &MCID = MI->getDesc(); 6196 if (!MCID.hasPostISelHook()) { 6197 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6198 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6199 return; 6200 } 6201 6202 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6203 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6204 // operand is still set to noreg. If needed, set the optional operand's 6205 // register to CPSR, and remove the redundant implicit def. 6206 // 6207 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6208 6209 // Rename pseudo opcodes. 6210 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 6211 if (NewOpc) { 6212 const ARMBaseInstrInfo *TII = 6213 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 6214 MI->setDesc(TII->get(NewOpc)); 6215 } 6216 unsigned ccOutIdx = MCID.getNumOperands() - 1; 6217 6218 // Any ARM instruction that sets the 's' bit should specify an optional 6219 // "cc_out" operand in the last operand position. 6220 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) { 6221 assert(!NewOpc && "Optional cc_out operand required"); 6222 return; 6223 } 6224 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 6225 // since we already have an optional CPSR def. 6226 bool definesCPSR = false; 6227 bool deadCPSR = false; 6228 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands(); 6229 i != e; ++i) { 6230 const MachineOperand &MO = MI->getOperand(i); 6231 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 6232 definesCPSR = true; 6233 if (MO.isDead()) 6234 deadCPSR = true; 6235 MI->RemoveOperand(i); 6236 break; 6237 } 6238 } 6239 if (!definesCPSR) { 6240 assert(!NewOpc && "Optional cc_out operand required"); 6241 return; 6242 } 6243 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 6244 if (deadCPSR) { 6245 assert(!MI->getOperand(ccOutIdx).getReg() && 6246 "expect uninitialized optional cc_out operand"); 6247 return; 6248 } 6249 6250 // If this instruction was defined with an optional CPSR def and its dag node 6251 // had a live implicit CPSR def, then activate the optional CPSR def. 6252 MachineOperand &MO = MI->getOperand(ccOutIdx); 6253 MO.setReg(ARM::CPSR); 6254 MO.setIsDef(true); 6255} 6256 6257//===----------------------------------------------------------------------===// 6258// ARM Optimization Hooks 6259//===----------------------------------------------------------------------===// 6260 6261static 6262SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 6263 TargetLowering::DAGCombinerInfo &DCI) { 6264 SelectionDAG &DAG = DCI.DAG; 6265 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6266 EVT VT = N->getValueType(0); 6267 unsigned Opc = N->getOpcode(); 6268 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 6269 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 6270 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 6271 ISD::CondCode CC = ISD::SETCC_INVALID; 6272 6273 if (isSlctCC) { 6274 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 6275 } else { 6276 SDValue CCOp = Slct.getOperand(0); 6277 if (CCOp.getOpcode() == ISD::SETCC) 6278 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 6279 } 6280 6281 bool DoXform = false; 6282 bool InvCC = false; 6283 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 6284 "Bad input!"); 6285 6286 if (LHS.getOpcode() == ISD::Constant && 6287 cast<ConstantSDNode>(LHS)->isNullValue()) { 6288 DoXform = true; 6289 } else if (CC != ISD::SETCC_INVALID && 6290 RHS.getOpcode() == ISD::Constant && 6291 cast<ConstantSDNode>(RHS)->isNullValue()) { 6292 std::swap(LHS, RHS); 6293 SDValue Op0 = Slct.getOperand(0); 6294 EVT OpVT = isSlctCC ? Op0.getValueType() : 6295 Op0.getOperand(0).getValueType(); 6296 bool isInt = OpVT.isInteger(); 6297 CC = ISD::getSetCCInverse(CC, isInt); 6298 6299 if (!TLI.isCondCodeLegal(CC, OpVT)) 6300 return SDValue(); // Inverse operator isn't legal. 6301 6302 DoXform = true; 6303 InvCC = true; 6304 } 6305 6306 if (DoXform) { 6307 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 6308 if (isSlctCC) 6309 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 6310 Slct.getOperand(0), Slct.getOperand(1), CC); 6311 SDValue CCOp = Slct.getOperand(0); 6312 if (InvCC) 6313 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 6314 CCOp.getOperand(0), CCOp.getOperand(1), CC); 6315 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 6316 CCOp, OtherOp, Result); 6317 } 6318 return SDValue(); 6319} 6320 6321// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 6322// (only after legalization). 6323static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 6324 TargetLowering::DAGCombinerInfo &DCI, 6325 const ARMSubtarget *Subtarget) { 6326 6327 // Only perform optimization if after legalize, and if NEON is available. We 6328 // also expected both operands to be BUILD_VECTORs. 6329 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 6330 || N0.getOpcode() != ISD::BUILD_VECTOR 6331 || N1.getOpcode() != ISD::BUILD_VECTOR) 6332 return SDValue(); 6333 6334 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 6335 EVT VT = N->getValueType(0); 6336 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 6337 return SDValue(); 6338 6339 // Check that the vector operands are of the right form. 6340 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 6341 // operands, where N is the size of the formed vector. 6342 // Each EXTRACT_VECTOR should have the same input vector and odd or even 6343 // index such that we have a pair wise add pattern. 6344 6345 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 6346 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6347 return SDValue(); 6348 SDValue Vec = N0->getOperand(0)->getOperand(0); 6349 SDNode *V = Vec.getNode(); 6350 unsigned nextIndex = 0; 6351 6352 // For each operands to the ADD which are BUILD_VECTORs, 6353 // check to see if each of their operands are an EXTRACT_VECTOR with 6354 // the same vector and appropriate index. 6355 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 6356 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 6357 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6358 6359 SDValue ExtVec0 = N0->getOperand(i); 6360 SDValue ExtVec1 = N1->getOperand(i); 6361 6362 // First operand is the vector, verify its the same. 6363 if (V != ExtVec0->getOperand(0).getNode() || 6364 V != ExtVec1->getOperand(0).getNode()) 6365 return SDValue(); 6366 6367 // Second is the constant, verify its correct. 6368 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 6369 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 6370 6371 // For the constant, we want to see all the even or all the odd. 6372 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 6373 || C1->getZExtValue() != nextIndex+1) 6374 return SDValue(); 6375 6376 // Increment index. 6377 nextIndex+=2; 6378 } else 6379 return SDValue(); 6380 } 6381 6382 // Create VPADDL node. 6383 SelectionDAG &DAG = DCI.DAG; 6384 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6385 6386 // Build operand list. 6387 SmallVector<SDValue, 8> Ops; 6388 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 6389 TLI.getPointerTy())); 6390 6391 // Input is the vector. 6392 Ops.push_back(Vec); 6393 6394 // Get widened type and narrowed type. 6395 MVT widenType; 6396 unsigned numElem = VT.getVectorNumElements(); 6397 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 6398 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 6399 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 6400 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 6401 default: 6402 assert(0 && "Invalid vector element type for padd optimization."); 6403 } 6404 6405 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6406 widenType, &Ops[0], Ops.size()); 6407 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 6408} 6409 6410/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 6411/// operands N0 and N1. This is a helper for PerformADDCombine that is 6412/// called with the default operands, and if that fails, with commuted 6413/// operands. 6414static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 6415 TargetLowering::DAGCombinerInfo &DCI, 6416 const ARMSubtarget *Subtarget){ 6417 6418 // Attempt to create vpaddl for this add. 6419 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 6420 if (Result.getNode()) 6421 return Result; 6422 6423 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 6424 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 6425 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 6426 if (Result.getNode()) return Result; 6427 } 6428 return SDValue(); 6429} 6430 6431/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 6432/// 6433static SDValue PerformADDCombine(SDNode *N, 6434 TargetLowering::DAGCombinerInfo &DCI, 6435 const ARMSubtarget *Subtarget) { 6436 SDValue N0 = N->getOperand(0); 6437 SDValue N1 = N->getOperand(1); 6438 6439 // First try with the default operand order. 6440 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 6441 if (Result.getNode()) 6442 return Result; 6443 6444 // If that didn't work, try again with the operands commuted. 6445 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 6446} 6447 6448/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 6449/// 6450static SDValue PerformSUBCombine(SDNode *N, 6451 TargetLowering::DAGCombinerInfo &DCI) { 6452 SDValue N0 = N->getOperand(0); 6453 SDValue N1 = N->getOperand(1); 6454 6455 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 6456 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 6457 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 6458 if (Result.getNode()) return Result; 6459 } 6460 6461 return SDValue(); 6462} 6463 6464/// PerformVMULCombine 6465/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 6466/// special multiplier accumulator forwarding. 6467/// vmul d3, d0, d2 6468/// vmla d3, d1, d2 6469/// is faster than 6470/// vadd d3, d0, d1 6471/// vmul d3, d3, d2 6472static SDValue PerformVMULCombine(SDNode *N, 6473 TargetLowering::DAGCombinerInfo &DCI, 6474 const ARMSubtarget *Subtarget) { 6475 if (!Subtarget->hasVMLxForwarding()) 6476 return SDValue(); 6477 6478 SelectionDAG &DAG = DCI.DAG; 6479 SDValue N0 = N->getOperand(0); 6480 SDValue N1 = N->getOperand(1); 6481 unsigned Opcode = N0.getOpcode(); 6482 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6483 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 6484 Opcode = N1.getOpcode(); 6485 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6486 Opcode != ISD::FADD && Opcode != ISD::FSUB) 6487 return SDValue(); 6488 std::swap(N0, N1); 6489 } 6490 6491 EVT VT = N->getValueType(0); 6492 DebugLoc DL = N->getDebugLoc(); 6493 SDValue N00 = N0->getOperand(0); 6494 SDValue N01 = N0->getOperand(1); 6495 return DAG.getNode(Opcode, DL, VT, 6496 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 6497 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 6498} 6499 6500static SDValue PerformMULCombine(SDNode *N, 6501 TargetLowering::DAGCombinerInfo &DCI, 6502 const ARMSubtarget *Subtarget) { 6503 SelectionDAG &DAG = DCI.DAG; 6504 6505 if (Subtarget->isThumb1Only()) 6506 return SDValue(); 6507 6508 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6509 return SDValue(); 6510 6511 EVT VT = N->getValueType(0); 6512 if (VT.is64BitVector() || VT.is128BitVector()) 6513 return PerformVMULCombine(N, DCI, Subtarget); 6514 if (VT != MVT::i32) 6515 return SDValue(); 6516 6517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6518 if (!C) 6519 return SDValue(); 6520 6521 uint64_t MulAmt = C->getZExtValue(); 6522 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6523 ShiftAmt = ShiftAmt & (32 - 1); 6524 SDValue V = N->getOperand(0); 6525 DebugLoc DL = N->getDebugLoc(); 6526 6527 SDValue Res; 6528 MulAmt >>= ShiftAmt; 6529 if (isPowerOf2_32(MulAmt - 1)) { 6530 // (mul x, 2^N + 1) => (add (shl x, N), x) 6531 Res = DAG.getNode(ISD::ADD, DL, VT, 6532 V, DAG.getNode(ISD::SHL, DL, VT, 6533 V, DAG.getConstant(Log2_32(MulAmt-1), 6534 MVT::i32))); 6535 } else if (isPowerOf2_32(MulAmt + 1)) { 6536 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6537 Res = DAG.getNode(ISD::SUB, DL, VT, 6538 DAG.getNode(ISD::SHL, DL, VT, 6539 V, DAG.getConstant(Log2_32(MulAmt+1), 6540 MVT::i32)), 6541 V); 6542 } else 6543 return SDValue(); 6544 6545 if (ShiftAmt != 0) 6546 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6547 DAG.getConstant(ShiftAmt, MVT::i32)); 6548 6549 // Do not add new nodes to DAG combiner worklist. 6550 DCI.CombineTo(N, Res, false); 6551 return SDValue(); 6552} 6553 6554static SDValue PerformANDCombine(SDNode *N, 6555 TargetLowering::DAGCombinerInfo &DCI) { 6556 6557 // Attempt to use immediate-form VBIC 6558 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6559 DebugLoc dl = N->getDebugLoc(); 6560 EVT VT = N->getValueType(0); 6561 SelectionDAG &DAG = DCI.DAG; 6562 6563 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6564 return SDValue(); 6565 6566 APInt SplatBits, SplatUndef; 6567 unsigned SplatBitSize; 6568 bool HasAnyUndefs; 6569 if (BVN && 6570 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6571 if (SplatBitSize <= 64) { 6572 EVT VbicVT; 6573 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6574 SplatUndef.getZExtValue(), SplatBitSize, 6575 DAG, VbicVT, VT.is128BitVector(), 6576 OtherModImm); 6577 if (Val.getNode()) { 6578 SDValue Input = 6579 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6580 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6581 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6582 } 6583 } 6584 } 6585 6586 return SDValue(); 6587} 6588 6589/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6590static SDValue PerformORCombine(SDNode *N, 6591 TargetLowering::DAGCombinerInfo &DCI, 6592 const ARMSubtarget *Subtarget) { 6593 // Attempt to use immediate-form VORR 6594 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6595 DebugLoc dl = N->getDebugLoc(); 6596 EVT VT = N->getValueType(0); 6597 SelectionDAG &DAG = DCI.DAG; 6598 6599 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6600 return SDValue(); 6601 6602 APInt SplatBits, SplatUndef; 6603 unsigned SplatBitSize; 6604 bool HasAnyUndefs; 6605 if (BVN && Subtarget->hasNEON() && 6606 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6607 if (SplatBitSize <= 64) { 6608 EVT VorrVT; 6609 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6610 SplatUndef.getZExtValue(), SplatBitSize, 6611 DAG, VorrVT, VT.is128BitVector(), 6612 OtherModImm); 6613 if (Val.getNode()) { 6614 SDValue Input = 6615 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6616 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6617 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6618 } 6619 } 6620 } 6621 6622 SDValue N0 = N->getOperand(0); 6623 if (N0.getOpcode() != ISD::AND) 6624 return SDValue(); 6625 SDValue N1 = N->getOperand(1); 6626 6627 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6628 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6629 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6630 APInt SplatUndef; 6631 unsigned SplatBitSize; 6632 bool HasAnyUndefs; 6633 6634 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6635 APInt SplatBits0; 6636 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6637 HasAnyUndefs) && !HasAnyUndefs) { 6638 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6639 APInt SplatBits1; 6640 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6641 HasAnyUndefs) && !HasAnyUndefs && 6642 SplatBits0 == ~SplatBits1) { 6643 // Canonicalize the vector type to make instruction selection simpler. 6644 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 6645 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 6646 N0->getOperand(1), N0->getOperand(0), 6647 N1->getOperand(0)); 6648 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 6649 } 6650 } 6651 } 6652 6653 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 6654 // reasonable. 6655 6656 // BFI is only available on V6T2+ 6657 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 6658 return SDValue(); 6659 6660 DebugLoc DL = N->getDebugLoc(); 6661 // 1) or (and A, mask), val => ARMbfi A, val, mask 6662 // iff (val & mask) == val 6663 // 6664 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6665 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 6666 // && mask == ~mask2 6667 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 6668 // && ~mask == mask2 6669 // (i.e., copy a bitfield value into another bitfield of the same width) 6670 6671 if (VT != MVT::i32) 6672 return SDValue(); 6673 6674 SDValue N00 = N0.getOperand(0); 6675 6676 // The value and the mask need to be constants so we can verify this is 6677 // actually a bitfield set. If the mask is 0xffff, we can do better 6678 // via a movt instruction, so don't use BFI in that case. 6679 SDValue MaskOp = N0.getOperand(1); 6680 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 6681 if (!MaskC) 6682 return SDValue(); 6683 unsigned Mask = MaskC->getZExtValue(); 6684 if (Mask == 0xffff) 6685 return SDValue(); 6686 SDValue Res; 6687 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 6688 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 6689 if (N1C) { 6690 unsigned Val = N1C->getZExtValue(); 6691 if ((Val & ~Mask) != Val) 6692 return SDValue(); 6693 6694 if (ARM::isBitFieldInvertedMask(Mask)) { 6695 Val >>= CountTrailingZeros_32(~Mask); 6696 6697 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 6698 DAG.getConstant(Val, MVT::i32), 6699 DAG.getConstant(Mask, MVT::i32)); 6700 6701 // Do not add new nodes to DAG combiner worklist. 6702 DCI.CombineTo(N, Res, false); 6703 return SDValue(); 6704 } 6705 } else if (N1.getOpcode() == ISD::AND) { 6706 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6707 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6708 if (!N11C) 6709 return SDValue(); 6710 unsigned Mask2 = N11C->getZExtValue(); 6711 6712 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 6713 // as is to match. 6714 if (ARM::isBitFieldInvertedMask(Mask) && 6715 (Mask == ~Mask2)) { 6716 // The pack halfword instruction works better for masks that fit it, 6717 // so use that when it's available. 6718 if (Subtarget->hasT2ExtractPack() && 6719 (Mask == 0xffff || Mask == 0xffff0000)) 6720 return SDValue(); 6721 // 2a 6722 unsigned amt = CountTrailingZeros_32(Mask2); 6723 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 6724 DAG.getConstant(amt, MVT::i32)); 6725 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 6726 DAG.getConstant(Mask, MVT::i32)); 6727 // Do not add new nodes to DAG combiner worklist. 6728 DCI.CombineTo(N, Res, false); 6729 return SDValue(); 6730 } else if (ARM::isBitFieldInvertedMask(~Mask) && 6731 (~Mask == Mask2)) { 6732 // The pack halfword instruction works better for masks that fit it, 6733 // so use that when it's available. 6734 if (Subtarget->hasT2ExtractPack() && 6735 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 6736 return SDValue(); 6737 // 2b 6738 unsigned lsb = CountTrailingZeros_32(Mask); 6739 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 6740 DAG.getConstant(lsb, MVT::i32)); 6741 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 6742 DAG.getConstant(Mask2, MVT::i32)); 6743 // Do not add new nodes to DAG combiner worklist. 6744 DCI.CombineTo(N, Res, false); 6745 return SDValue(); 6746 } 6747 } 6748 6749 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 6750 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 6751 ARM::isBitFieldInvertedMask(~Mask)) { 6752 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 6753 // where lsb(mask) == #shamt and masked bits of B are known zero. 6754 SDValue ShAmt = N00.getOperand(1); 6755 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 6756 unsigned LSB = CountTrailingZeros_32(Mask); 6757 if (ShAmtC != LSB) 6758 return SDValue(); 6759 6760 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 6761 DAG.getConstant(~Mask, MVT::i32)); 6762 6763 // Do not add new nodes to DAG combiner worklist. 6764 DCI.CombineTo(N, Res, false); 6765 } 6766 6767 return SDValue(); 6768} 6769 6770/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 6771/// the bits being cleared by the AND are not demanded by the BFI. 6772static SDValue PerformBFICombine(SDNode *N, 6773 TargetLowering::DAGCombinerInfo &DCI) { 6774 SDValue N1 = N->getOperand(1); 6775 if (N1.getOpcode() == ISD::AND) { 6776 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6777 if (!N11C) 6778 return SDValue(); 6779 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 6780 unsigned LSB = CountTrailingZeros_32(~InvMask); 6781 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 6782 unsigned Mask = (1 << Width)-1; 6783 unsigned Mask2 = N11C->getZExtValue(); 6784 if ((Mask & (~Mask2)) == 0) 6785 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 6786 N->getOperand(0), N1.getOperand(0), 6787 N->getOperand(2)); 6788 } 6789 return SDValue(); 6790} 6791 6792/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 6793/// ARMISD::VMOVRRD. 6794static SDValue PerformVMOVRRDCombine(SDNode *N, 6795 TargetLowering::DAGCombinerInfo &DCI) { 6796 // vmovrrd(vmovdrr x, y) -> x,y 6797 SDValue InDouble = N->getOperand(0); 6798 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 6799 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 6800 6801 // vmovrrd(load f64) -> (load i32), (load i32) 6802 SDNode *InNode = InDouble.getNode(); 6803 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 6804 InNode->getValueType(0) == MVT::f64 && 6805 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 6806 !cast<LoadSDNode>(InNode)->isVolatile()) { 6807 // TODO: Should this be done for non-FrameIndex operands? 6808 LoadSDNode *LD = cast<LoadSDNode>(InNode); 6809 6810 SelectionDAG &DAG = DCI.DAG; 6811 DebugLoc DL = LD->getDebugLoc(); 6812 SDValue BasePtr = LD->getBasePtr(); 6813 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 6814 LD->getPointerInfo(), LD->isVolatile(), 6815 LD->isNonTemporal(), LD->getAlignment()); 6816 6817 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6818 DAG.getConstant(4, MVT::i32)); 6819 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 6820 LD->getPointerInfo(), LD->isVolatile(), 6821 LD->isNonTemporal(), 6822 std::min(4U, LD->getAlignment() / 2)); 6823 6824 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 6825 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 6826 DCI.RemoveFromWorklist(LD); 6827 DAG.DeleteNode(LD); 6828 return Result; 6829 } 6830 6831 return SDValue(); 6832} 6833 6834/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 6835/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 6836static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 6837 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 6838 SDValue Op0 = N->getOperand(0); 6839 SDValue Op1 = N->getOperand(1); 6840 if (Op0.getOpcode() == ISD::BITCAST) 6841 Op0 = Op0.getOperand(0); 6842 if (Op1.getOpcode() == ISD::BITCAST) 6843 Op1 = Op1.getOperand(0); 6844 if (Op0.getOpcode() == ARMISD::VMOVRRD && 6845 Op0.getNode() == Op1.getNode() && 6846 Op0.getResNo() == 0 && Op1.getResNo() == 1) 6847 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6848 N->getValueType(0), Op0.getOperand(0)); 6849 return SDValue(); 6850} 6851 6852/// PerformSTORECombine - Target-specific dag combine xforms for 6853/// ISD::STORE. 6854static SDValue PerformSTORECombine(SDNode *N, 6855 TargetLowering::DAGCombinerInfo &DCI) { 6856 // Bitcast an i64 store extracted from a vector to f64. 6857 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6858 StoreSDNode *St = cast<StoreSDNode>(N); 6859 SDValue StVal = St->getValue(); 6860 if (!ISD::isNormalStore(St) || St->isVolatile()) 6861 return SDValue(); 6862 6863 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 6864 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 6865 SelectionDAG &DAG = DCI.DAG; 6866 DebugLoc DL = St->getDebugLoc(); 6867 SDValue BasePtr = St->getBasePtr(); 6868 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 6869 StVal.getNode()->getOperand(0), BasePtr, 6870 St->getPointerInfo(), St->isVolatile(), 6871 St->isNonTemporal(), St->getAlignment()); 6872 6873 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6874 DAG.getConstant(4, MVT::i32)); 6875 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 6876 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 6877 St->isNonTemporal(), 6878 std::min(4U, St->getAlignment() / 2)); 6879 } 6880 6881 if (StVal.getValueType() != MVT::i64 || 6882 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6883 return SDValue(); 6884 6885 SelectionDAG &DAG = DCI.DAG; 6886 DebugLoc dl = StVal.getDebugLoc(); 6887 SDValue IntVec = StVal.getOperand(0); 6888 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6889 IntVec.getValueType().getVectorNumElements()); 6890 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 6891 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6892 Vec, StVal.getOperand(1)); 6893 dl = N->getDebugLoc(); 6894 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 6895 // Make the DAGCombiner fold the bitcasts. 6896 DCI.AddToWorklist(Vec.getNode()); 6897 DCI.AddToWorklist(ExtElt.getNode()); 6898 DCI.AddToWorklist(V.getNode()); 6899 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 6900 St->getPointerInfo(), St->isVolatile(), 6901 St->isNonTemporal(), St->getAlignment(), 6902 St->getTBAAInfo()); 6903} 6904 6905/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 6906/// are normal, non-volatile loads. If so, it is profitable to bitcast an 6907/// i64 vector to have f64 elements, since the value can then be loaded 6908/// directly into a VFP register. 6909static bool hasNormalLoadOperand(SDNode *N) { 6910 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 6911 for (unsigned i = 0; i < NumElts; ++i) { 6912 SDNode *Elt = N->getOperand(i).getNode(); 6913 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 6914 return true; 6915 } 6916 return false; 6917} 6918 6919/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 6920/// ISD::BUILD_VECTOR. 6921static SDValue PerformBUILD_VECTORCombine(SDNode *N, 6922 TargetLowering::DAGCombinerInfo &DCI){ 6923 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 6924 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 6925 // into a pair of GPRs, which is fine when the value is used as a scalar, 6926 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 6927 SelectionDAG &DAG = DCI.DAG; 6928 if (N->getNumOperands() == 2) { 6929 SDValue RV = PerformVMOVDRRCombine(N, DAG); 6930 if (RV.getNode()) 6931 return RV; 6932 } 6933 6934 // Load i64 elements as f64 values so that type legalization does not split 6935 // them up into i32 values. 6936 EVT VT = N->getValueType(0); 6937 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 6938 return SDValue(); 6939 DebugLoc dl = N->getDebugLoc(); 6940 SmallVector<SDValue, 8> Ops; 6941 unsigned NumElts = VT.getVectorNumElements(); 6942 for (unsigned i = 0; i < NumElts; ++i) { 6943 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 6944 Ops.push_back(V); 6945 // Make the DAGCombiner fold the bitcast. 6946 DCI.AddToWorklist(V.getNode()); 6947 } 6948 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 6949 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 6950 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 6951} 6952 6953/// PerformInsertEltCombine - Target-specific dag combine xforms for 6954/// ISD::INSERT_VECTOR_ELT. 6955static SDValue PerformInsertEltCombine(SDNode *N, 6956 TargetLowering::DAGCombinerInfo &DCI) { 6957 // Bitcast an i64 load inserted into a vector to f64. 6958 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6959 EVT VT = N->getValueType(0); 6960 SDNode *Elt = N->getOperand(1).getNode(); 6961 if (VT.getVectorElementType() != MVT::i64 || 6962 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 6963 return SDValue(); 6964 6965 SelectionDAG &DAG = DCI.DAG; 6966 DebugLoc dl = N->getDebugLoc(); 6967 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6968 VT.getVectorNumElements()); 6969 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 6970 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 6971 // Make the DAGCombiner fold the bitcasts. 6972 DCI.AddToWorklist(Vec.getNode()); 6973 DCI.AddToWorklist(V.getNode()); 6974 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 6975 Vec, V, N->getOperand(2)); 6976 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 6977} 6978 6979/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 6980/// ISD::VECTOR_SHUFFLE. 6981static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 6982 // The LLVM shufflevector instruction does not require the shuffle mask 6983 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 6984 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 6985 // operands do not match the mask length, they are extended by concatenating 6986 // them with undef vectors. That is probably the right thing for other 6987 // targets, but for NEON it is better to concatenate two double-register 6988 // size vector operands into a single quad-register size vector. Do that 6989 // transformation here: 6990 // shuffle(concat(v1, undef), concat(v2, undef)) -> 6991 // shuffle(concat(v1, v2), undef) 6992 SDValue Op0 = N->getOperand(0); 6993 SDValue Op1 = N->getOperand(1); 6994 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 6995 Op1.getOpcode() != ISD::CONCAT_VECTORS || 6996 Op0.getNumOperands() != 2 || 6997 Op1.getNumOperands() != 2) 6998 return SDValue(); 6999 SDValue Concat0Op1 = Op0.getOperand(1); 7000 SDValue Concat1Op1 = Op1.getOperand(1); 7001 if (Concat0Op1.getOpcode() != ISD::UNDEF || 7002 Concat1Op1.getOpcode() != ISD::UNDEF) 7003 return SDValue(); 7004 // Skip the transformation if any of the types are illegal. 7005 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7006 EVT VT = N->getValueType(0); 7007 if (!TLI.isTypeLegal(VT) || 7008 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 7009 !TLI.isTypeLegal(Concat1Op1.getValueType())) 7010 return SDValue(); 7011 7012 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7013 Op0.getOperand(0), Op1.getOperand(0)); 7014 // Translate the shuffle mask. 7015 SmallVector<int, 16> NewMask; 7016 unsigned NumElts = VT.getVectorNumElements(); 7017 unsigned HalfElts = NumElts/2; 7018 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7019 for (unsigned n = 0; n < NumElts; ++n) { 7020 int MaskElt = SVN->getMaskElt(n); 7021 int NewElt = -1; 7022 if (MaskElt < (int)HalfElts) 7023 NewElt = MaskElt; 7024 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 7025 NewElt = HalfElts + MaskElt - NumElts; 7026 NewMask.push_back(NewElt); 7027 } 7028 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 7029 DAG.getUNDEF(VT), NewMask.data()); 7030} 7031 7032/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 7033/// NEON load/store intrinsics to merge base address updates. 7034static SDValue CombineBaseUpdate(SDNode *N, 7035 TargetLowering::DAGCombinerInfo &DCI) { 7036 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7037 return SDValue(); 7038 7039 SelectionDAG &DAG = DCI.DAG; 7040 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 7041 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 7042 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 7043 SDValue Addr = N->getOperand(AddrOpIdx); 7044 7045 // Search for a use of the address operand that is an increment. 7046 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7047 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7048 SDNode *User = *UI; 7049 if (User->getOpcode() != ISD::ADD || 7050 UI.getUse().getResNo() != Addr.getResNo()) 7051 continue; 7052 7053 // Check that the add is independent of the load/store. Otherwise, folding 7054 // it would create a cycle. 7055 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7056 continue; 7057 7058 // Find the new opcode for the updating load/store. 7059 bool isLoad = true; 7060 bool isLaneOp = false; 7061 unsigned NewOpc = 0; 7062 unsigned NumVecs = 0; 7063 if (isIntrinsic) { 7064 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7065 switch (IntNo) { 7066 default: assert(0 && "unexpected intrinsic for Neon base update"); 7067 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 7068 NumVecs = 1; break; 7069 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 7070 NumVecs = 2; break; 7071 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 7072 NumVecs = 3; break; 7073 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 7074 NumVecs = 4; break; 7075 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 7076 NumVecs = 2; isLaneOp = true; break; 7077 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 7078 NumVecs = 3; isLaneOp = true; break; 7079 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 7080 NumVecs = 4; isLaneOp = true; break; 7081 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 7082 NumVecs = 1; isLoad = false; break; 7083 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 7084 NumVecs = 2; isLoad = false; break; 7085 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 7086 NumVecs = 3; isLoad = false; break; 7087 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 7088 NumVecs = 4; isLoad = false; break; 7089 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 7090 NumVecs = 2; isLoad = false; isLaneOp = true; break; 7091 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 7092 NumVecs = 3; isLoad = false; isLaneOp = true; break; 7093 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 7094 NumVecs = 4; isLoad = false; isLaneOp = true; break; 7095 } 7096 } else { 7097 isLaneOp = true; 7098 switch (N->getOpcode()) { 7099 default: assert(0 && "unexpected opcode for Neon base update"); 7100 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 7101 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 7102 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 7103 } 7104 } 7105 7106 // Find the size of memory referenced by the load/store. 7107 EVT VecTy; 7108 if (isLoad) 7109 VecTy = N->getValueType(0); 7110 else 7111 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 7112 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7113 if (isLaneOp) 7114 NumBytes /= VecTy.getVectorNumElements(); 7115 7116 // If the increment is a constant, it must match the memory ref size. 7117 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7118 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7119 uint64_t IncVal = CInc->getZExtValue(); 7120 if (IncVal != NumBytes) 7121 continue; 7122 } else if (NumBytes >= 3 * 16) { 7123 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 7124 // separate instructions that make it harder to use a non-constant update. 7125 continue; 7126 } 7127 7128 // Create the new updating load/store node. 7129 EVT Tys[6]; 7130 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 7131 unsigned n; 7132 for (n = 0; n < NumResultVecs; ++n) 7133 Tys[n] = VecTy; 7134 Tys[n++] = MVT::i32; 7135 Tys[n] = MVT::Other; 7136 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 7137 SmallVector<SDValue, 8> Ops; 7138 Ops.push_back(N->getOperand(0)); // incoming chain 7139 Ops.push_back(N->getOperand(AddrOpIdx)); 7140 Ops.push_back(Inc); 7141 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 7142 Ops.push_back(N->getOperand(i)); 7143 } 7144 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7145 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 7146 Ops.data(), Ops.size(), 7147 MemInt->getMemoryVT(), 7148 MemInt->getMemOperand()); 7149 7150 // Update the uses. 7151 std::vector<SDValue> NewResults; 7152 for (unsigned i = 0; i < NumResultVecs; ++i) { 7153 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7154 } 7155 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 7156 DCI.CombineTo(N, NewResults); 7157 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7158 7159 break; 7160 } 7161 return SDValue(); 7162} 7163 7164/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 7165/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 7166/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 7167/// return true. 7168static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 7169 SelectionDAG &DAG = DCI.DAG; 7170 EVT VT = N->getValueType(0); 7171 // vldN-dup instructions only support 64-bit vectors for N > 1. 7172 if (!VT.is64BitVector()) 7173 return false; 7174 7175 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 7176 SDNode *VLD = N->getOperand(0).getNode(); 7177 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 7178 return false; 7179 unsigned NumVecs = 0; 7180 unsigned NewOpc = 0; 7181 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 7182 if (IntNo == Intrinsic::arm_neon_vld2lane) { 7183 NumVecs = 2; 7184 NewOpc = ARMISD::VLD2DUP; 7185 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 7186 NumVecs = 3; 7187 NewOpc = ARMISD::VLD3DUP; 7188 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 7189 NumVecs = 4; 7190 NewOpc = ARMISD::VLD4DUP; 7191 } else { 7192 return false; 7193 } 7194 7195 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 7196 // numbers match the load. 7197 unsigned VLDLaneNo = 7198 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 7199 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7200 UI != UE; ++UI) { 7201 // Ignore uses of the chain result. 7202 if (UI.getUse().getResNo() == NumVecs) 7203 continue; 7204 SDNode *User = *UI; 7205 if (User->getOpcode() != ARMISD::VDUPLANE || 7206 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 7207 return false; 7208 } 7209 7210 // Create the vldN-dup node. 7211 EVT Tys[5]; 7212 unsigned n; 7213 for (n = 0; n < NumVecs; ++n) 7214 Tys[n] = VT; 7215 Tys[n] = MVT::Other; 7216 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 7217 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 7218 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 7219 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 7220 Ops, 2, VLDMemInt->getMemoryVT(), 7221 VLDMemInt->getMemOperand()); 7222 7223 // Update the uses. 7224 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7225 UI != UE; ++UI) { 7226 unsigned ResNo = UI.getUse().getResNo(); 7227 // Ignore uses of the chain result. 7228 if (ResNo == NumVecs) 7229 continue; 7230 SDNode *User = *UI; 7231 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 7232 } 7233 7234 // Now the vldN-lane intrinsic is dead except for its chain result. 7235 // Update uses of the chain. 7236 std::vector<SDValue> VLDDupResults; 7237 for (unsigned n = 0; n < NumVecs; ++n) 7238 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 7239 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 7240 DCI.CombineTo(VLD, VLDDupResults); 7241 7242 return true; 7243} 7244 7245/// PerformVDUPLANECombine - Target-specific dag combine xforms for 7246/// ARMISD::VDUPLANE. 7247static SDValue PerformVDUPLANECombine(SDNode *N, 7248 TargetLowering::DAGCombinerInfo &DCI) { 7249 SDValue Op = N->getOperand(0); 7250 7251 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 7252 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 7253 if (CombineVLDDUP(N, DCI)) 7254 return SDValue(N, 0); 7255 7256 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 7257 // redundant. Ignore bit_converts for now; element sizes are checked below. 7258 while (Op.getOpcode() == ISD::BITCAST) 7259 Op = Op.getOperand(0); 7260 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 7261 return SDValue(); 7262 7263 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 7264 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 7265 // The canonical VMOV for a zero vector uses a 32-bit element size. 7266 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7267 unsigned EltBits; 7268 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 7269 EltSize = 8; 7270 EVT VT = N->getValueType(0); 7271 if (EltSize > VT.getVectorElementType().getSizeInBits()) 7272 return SDValue(); 7273 7274 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 7275} 7276 7277// isConstVecPow2 - Return true if each vector element is a power of 2, all 7278// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 7279static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 7280{ 7281 integerPart cN; 7282 integerPart c0 = 0; 7283 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 7284 I != E; I++) { 7285 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 7286 if (!C) 7287 return false; 7288 7289 bool isExact; 7290 APFloat APF = C->getValueAPF(); 7291 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 7292 != APFloat::opOK || !isExact) 7293 return false; 7294 7295 c0 = (I == 0) ? cN : c0; 7296 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 7297 return false; 7298 } 7299 C = c0; 7300 return true; 7301} 7302 7303/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 7304/// can replace combinations of VMUL and VCVT (floating-point to integer) 7305/// when the VMUL has a constant operand that is a power of 2. 7306/// 7307/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7308/// vmul.f32 d16, d17, d16 7309/// vcvt.s32.f32 d16, d16 7310/// becomes: 7311/// vcvt.s32.f32 d16, d16, #3 7312static SDValue PerformVCVTCombine(SDNode *N, 7313 TargetLowering::DAGCombinerInfo &DCI, 7314 const ARMSubtarget *Subtarget) { 7315 SelectionDAG &DAG = DCI.DAG; 7316 SDValue Op = N->getOperand(0); 7317 7318 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 7319 Op.getOpcode() != ISD::FMUL) 7320 return SDValue(); 7321 7322 uint64_t C; 7323 SDValue N0 = Op->getOperand(0); 7324 SDValue ConstVec = Op->getOperand(1); 7325 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 7326 7327 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7328 !isConstVecPow2(ConstVec, isSigned, C)) 7329 return SDValue(); 7330 7331 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 7332 Intrinsic::arm_neon_vcvtfp2fxu; 7333 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7334 N->getValueType(0), 7335 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 7336 DAG.getConstant(Log2_64(C), MVT::i32)); 7337} 7338 7339/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 7340/// can replace combinations of VCVT (integer to floating-point) and VDIV 7341/// when the VDIV has a constant operand that is a power of 2. 7342/// 7343/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7344/// vcvt.f32.s32 d16, d16 7345/// vdiv.f32 d16, d17, d16 7346/// becomes: 7347/// vcvt.f32.s32 d16, d16, #3 7348static SDValue PerformVDIVCombine(SDNode *N, 7349 TargetLowering::DAGCombinerInfo &DCI, 7350 const ARMSubtarget *Subtarget) { 7351 SelectionDAG &DAG = DCI.DAG; 7352 SDValue Op = N->getOperand(0); 7353 unsigned OpOpcode = Op.getNode()->getOpcode(); 7354 7355 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 7356 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 7357 return SDValue(); 7358 7359 uint64_t C; 7360 SDValue ConstVec = N->getOperand(1); 7361 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 7362 7363 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7364 !isConstVecPow2(ConstVec, isSigned, C)) 7365 return SDValue(); 7366 7367 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 7368 Intrinsic::arm_neon_vcvtfxu2fp; 7369 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7370 Op.getValueType(), 7371 DAG.getConstant(IntrinsicOpcode, MVT::i32), 7372 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 7373} 7374 7375/// Getvshiftimm - Check if this is a valid build_vector for the immediate 7376/// operand of a vector shift operation, where all the elements of the 7377/// build_vector must have the same constant integer value. 7378static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 7379 // Ignore bit_converts. 7380 while (Op.getOpcode() == ISD::BITCAST) 7381 Op = Op.getOperand(0); 7382 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 7383 APInt SplatBits, SplatUndef; 7384 unsigned SplatBitSize; 7385 bool HasAnyUndefs; 7386 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 7387 HasAnyUndefs, ElementBits) || 7388 SplatBitSize > ElementBits) 7389 return false; 7390 Cnt = SplatBits.getSExtValue(); 7391 return true; 7392} 7393 7394/// isVShiftLImm - Check if this is a valid build_vector for the immediate 7395/// operand of a vector shift left operation. That value must be in the range: 7396/// 0 <= Value < ElementBits for a left shift; or 7397/// 0 <= Value <= ElementBits for a long left shift. 7398static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 7399 assert(VT.isVector() && "vector shift count is not a vector type"); 7400 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7401 if (! getVShiftImm(Op, ElementBits, Cnt)) 7402 return false; 7403 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 7404} 7405 7406/// isVShiftRImm - Check if this is a valid build_vector for the immediate 7407/// operand of a vector shift right operation. For a shift opcode, the value 7408/// is positive, but for an intrinsic the value count must be negative. The 7409/// absolute value must be in the range: 7410/// 1 <= |Value| <= ElementBits for a right shift; or 7411/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 7412static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 7413 int64_t &Cnt) { 7414 assert(VT.isVector() && "vector shift count is not a vector type"); 7415 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7416 if (! getVShiftImm(Op, ElementBits, Cnt)) 7417 return false; 7418 if (isIntrinsic) 7419 Cnt = -Cnt; 7420 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 7421} 7422 7423/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 7424static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 7425 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 7426 switch (IntNo) { 7427 default: 7428 // Don't do anything for most intrinsics. 7429 break; 7430 7431 // Vector shifts: check for immediate versions and lower them. 7432 // Note: This is done during DAG combining instead of DAG legalizing because 7433 // the build_vectors for 64-bit vector element shift counts are generally 7434 // not legal, and it is hard to see their values after they get legalized to 7435 // loads from a constant pool. 7436 case Intrinsic::arm_neon_vshifts: 7437 case Intrinsic::arm_neon_vshiftu: 7438 case Intrinsic::arm_neon_vshiftls: 7439 case Intrinsic::arm_neon_vshiftlu: 7440 case Intrinsic::arm_neon_vshiftn: 7441 case Intrinsic::arm_neon_vrshifts: 7442 case Intrinsic::arm_neon_vrshiftu: 7443 case Intrinsic::arm_neon_vrshiftn: 7444 case Intrinsic::arm_neon_vqshifts: 7445 case Intrinsic::arm_neon_vqshiftu: 7446 case Intrinsic::arm_neon_vqshiftsu: 7447 case Intrinsic::arm_neon_vqshiftns: 7448 case Intrinsic::arm_neon_vqshiftnu: 7449 case Intrinsic::arm_neon_vqshiftnsu: 7450 case Intrinsic::arm_neon_vqrshiftns: 7451 case Intrinsic::arm_neon_vqrshiftnu: 7452 case Intrinsic::arm_neon_vqrshiftnsu: { 7453 EVT VT = N->getOperand(1).getValueType(); 7454 int64_t Cnt; 7455 unsigned VShiftOpc = 0; 7456 7457 switch (IntNo) { 7458 case Intrinsic::arm_neon_vshifts: 7459 case Intrinsic::arm_neon_vshiftu: 7460 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 7461 VShiftOpc = ARMISD::VSHL; 7462 break; 7463 } 7464 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 7465 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 7466 ARMISD::VSHRs : ARMISD::VSHRu); 7467 break; 7468 } 7469 return SDValue(); 7470 7471 case Intrinsic::arm_neon_vshiftls: 7472 case Intrinsic::arm_neon_vshiftlu: 7473 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 7474 break; 7475 llvm_unreachable("invalid shift count for vshll intrinsic"); 7476 7477 case Intrinsic::arm_neon_vrshifts: 7478 case Intrinsic::arm_neon_vrshiftu: 7479 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 7480 break; 7481 return SDValue(); 7482 7483 case Intrinsic::arm_neon_vqshifts: 7484 case Intrinsic::arm_neon_vqshiftu: 7485 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7486 break; 7487 return SDValue(); 7488 7489 case Intrinsic::arm_neon_vqshiftsu: 7490 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7491 break; 7492 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 7493 7494 case Intrinsic::arm_neon_vshiftn: 7495 case Intrinsic::arm_neon_vrshiftn: 7496 case Intrinsic::arm_neon_vqshiftns: 7497 case Intrinsic::arm_neon_vqshiftnu: 7498 case Intrinsic::arm_neon_vqshiftnsu: 7499 case Intrinsic::arm_neon_vqrshiftns: 7500 case Intrinsic::arm_neon_vqrshiftnu: 7501 case Intrinsic::arm_neon_vqrshiftnsu: 7502 // Narrowing shifts require an immediate right shift. 7503 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 7504 break; 7505 llvm_unreachable("invalid shift count for narrowing vector shift " 7506 "intrinsic"); 7507 7508 default: 7509 llvm_unreachable("unhandled vector shift"); 7510 } 7511 7512 switch (IntNo) { 7513 case Intrinsic::arm_neon_vshifts: 7514 case Intrinsic::arm_neon_vshiftu: 7515 // Opcode already set above. 7516 break; 7517 case Intrinsic::arm_neon_vshiftls: 7518 case Intrinsic::arm_neon_vshiftlu: 7519 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7520 VShiftOpc = ARMISD::VSHLLi; 7521 else 7522 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7523 ARMISD::VSHLLs : ARMISD::VSHLLu); 7524 break; 7525 case Intrinsic::arm_neon_vshiftn: 7526 VShiftOpc = ARMISD::VSHRN; break; 7527 case Intrinsic::arm_neon_vrshifts: 7528 VShiftOpc = ARMISD::VRSHRs; break; 7529 case Intrinsic::arm_neon_vrshiftu: 7530 VShiftOpc = ARMISD::VRSHRu; break; 7531 case Intrinsic::arm_neon_vrshiftn: 7532 VShiftOpc = ARMISD::VRSHRN; break; 7533 case Intrinsic::arm_neon_vqshifts: 7534 VShiftOpc = ARMISD::VQSHLs; break; 7535 case Intrinsic::arm_neon_vqshiftu: 7536 VShiftOpc = ARMISD::VQSHLu; break; 7537 case Intrinsic::arm_neon_vqshiftsu: 7538 VShiftOpc = ARMISD::VQSHLsu; break; 7539 case Intrinsic::arm_neon_vqshiftns: 7540 VShiftOpc = ARMISD::VQSHRNs; break; 7541 case Intrinsic::arm_neon_vqshiftnu: 7542 VShiftOpc = ARMISD::VQSHRNu; break; 7543 case Intrinsic::arm_neon_vqshiftnsu: 7544 VShiftOpc = ARMISD::VQSHRNsu; break; 7545 case Intrinsic::arm_neon_vqrshiftns: 7546 VShiftOpc = ARMISD::VQRSHRNs; break; 7547 case Intrinsic::arm_neon_vqrshiftnu: 7548 VShiftOpc = ARMISD::VQRSHRNu; break; 7549 case Intrinsic::arm_neon_vqrshiftnsu: 7550 VShiftOpc = ARMISD::VQRSHRNsu; break; 7551 } 7552 7553 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7554 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7555 } 7556 7557 case Intrinsic::arm_neon_vshiftins: { 7558 EVT VT = N->getOperand(1).getValueType(); 7559 int64_t Cnt; 7560 unsigned VShiftOpc = 0; 7561 7562 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7563 VShiftOpc = ARMISD::VSLI; 7564 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7565 VShiftOpc = ARMISD::VSRI; 7566 else { 7567 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7568 } 7569 7570 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7571 N->getOperand(1), N->getOperand(2), 7572 DAG.getConstant(Cnt, MVT::i32)); 7573 } 7574 7575 case Intrinsic::arm_neon_vqrshifts: 7576 case Intrinsic::arm_neon_vqrshiftu: 7577 // No immediate versions of these to check for. 7578 break; 7579 } 7580 7581 return SDValue(); 7582} 7583 7584/// PerformShiftCombine - Checks for immediate versions of vector shifts and 7585/// lowers them. As with the vector shift intrinsics, this is done during DAG 7586/// combining instead of DAG legalizing because the build_vectors for 64-bit 7587/// vector element shift counts are generally not legal, and it is hard to see 7588/// their values after they get legalized to loads from a constant pool. 7589static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7590 const ARMSubtarget *ST) { 7591 EVT VT = N->getValueType(0); 7592 7593 // Nothing to be done for scalar shifts. 7594 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7595 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7596 return SDValue(); 7597 7598 assert(ST->hasNEON() && "unexpected vector shift"); 7599 int64_t Cnt; 7600 7601 switch (N->getOpcode()) { 7602 default: llvm_unreachable("unexpected shift opcode"); 7603 7604 case ISD::SHL: 7605 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7606 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7607 DAG.getConstant(Cnt, MVT::i32)); 7608 break; 7609 7610 case ISD::SRA: 7611 case ISD::SRL: 7612 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7613 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7614 ARMISD::VSHRs : ARMISD::VSHRu); 7615 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7616 DAG.getConstant(Cnt, MVT::i32)); 7617 } 7618 } 7619 return SDValue(); 7620} 7621 7622/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7623/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7624static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 7625 const ARMSubtarget *ST) { 7626 SDValue N0 = N->getOperand(0); 7627 7628 // Check for sign- and zero-extensions of vector extract operations of 8- 7629 // and 16-bit vector elements. NEON supports these directly. They are 7630 // handled during DAG combining because type legalization will promote them 7631 // to 32-bit types and it is messy to recognize the operations after that. 7632 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7633 SDValue Vec = N0.getOperand(0); 7634 SDValue Lane = N0.getOperand(1); 7635 EVT VT = N->getValueType(0); 7636 EVT EltVT = N0.getValueType(); 7637 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7638 7639 if (VT == MVT::i32 && 7640 (EltVT == MVT::i8 || EltVT == MVT::i16) && 7641 TLI.isTypeLegal(Vec.getValueType()) && 7642 isa<ConstantSDNode>(Lane)) { 7643 7644 unsigned Opc = 0; 7645 switch (N->getOpcode()) { 7646 default: llvm_unreachable("unexpected opcode"); 7647 case ISD::SIGN_EXTEND: 7648 Opc = ARMISD::VGETLANEs; 7649 break; 7650 case ISD::ZERO_EXTEND: 7651 case ISD::ANY_EXTEND: 7652 Opc = ARMISD::VGETLANEu; 7653 break; 7654 } 7655 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 7656 } 7657 } 7658 7659 return SDValue(); 7660} 7661 7662/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 7663/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 7664static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 7665 const ARMSubtarget *ST) { 7666 // If the target supports NEON, try to use vmax/vmin instructions for f32 7667 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 7668 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 7669 // a NaN; only do the transformation when it matches that behavior. 7670 7671 // For now only do this when using NEON for FP operations; if using VFP, it 7672 // is not obvious that the benefit outweighs the cost of switching to the 7673 // NEON pipeline. 7674 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 7675 N->getValueType(0) != MVT::f32) 7676 return SDValue(); 7677 7678 SDValue CondLHS = N->getOperand(0); 7679 SDValue CondRHS = N->getOperand(1); 7680 SDValue LHS = N->getOperand(2); 7681 SDValue RHS = N->getOperand(3); 7682 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 7683 7684 unsigned Opcode = 0; 7685 bool IsReversed; 7686 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 7687 IsReversed = false; // x CC y ? x : y 7688 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 7689 IsReversed = true ; // x CC y ? y : x 7690 } else { 7691 return SDValue(); 7692 } 7693 7694 bool IsUnordered; 7695 switch (CC) { 7696 default: break; 7697 case ISD::SETOLT: 7698 case ISD::SETOLE: 7699 case ISD::SETLT: 7700 case ISD::SETLE: 7701 case ISD::SETULT: 7702 case ISD::SETULE: 7703 // If LHS is NaN, an ordered comparison will be false and the result will 7704 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 7705 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7706 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 7707 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7708 break; 7709 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 7710 // will return -0, so vmin can only be used for unsafe math or if one of 7711 // the operands is known to be nonzero. 7712 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 7713 !UnsafeFPMath && 7714 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7715 break; 7716 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 7717 break; 7718 7719 case ISD::SETOGT: 7720 case ISD::SETOGE: 7721 case ISD::SETGT: 7722 case ISD::SETGE: 7723 case ISD::SETUGT: 7724 case ISD::SETUGE: 7725 // If LHS is NaN, an ordered comparison will be false and the result will 7726 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 7727 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7728 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 7729 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7730 break; 7731 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 7732 // will return +0, so vmax can only be used for unsafe math or if one of 7733 // the operands is known to be nonzero. 7734 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 7735 !UnsafeFPMath && 7736 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7737 break; 7738 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 7739 break; 7740 } 7741 7742 if (!Opcode) 7743 return SDValue(); 7744 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 7745} 7746 7747/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 7748SDValue 7749ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 7750 SDValue Cmp = N->getOperand(4); 7751 if (Cmp.getOpcode() != ARMISD::CMPZ) 7752 // Only looking at EQ and NE cases. 7753 return SDValue(); 7754 7755 EVT VT = N->getValueType(0); 7756 DebugLoc dl = N->getDebugLoc(); 7757 SDValue LHS = Cmp.getOperand(0); 7758 SDValue RHS = Cmp.getOperand(1); 7759 SDValue FalseVal = N->getOperand(0); 7760 SDValue TrueVal = N->getOperand(1); 7761 SDValue ARMcc = N->getOperand(2); 7762 ARMCC::CondCodes CC = 7763 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 7764 7765 // Simplify 7766 // mov r1, r0 7767 // cmp r1, x 7768 // mov r0, y 7769 // moveq r0, x 7770 // to 7771 // cmp r0, x 7772 // movne r0, y 7773 // 7774 // mov r1, r0 7775 // cmp r1, x 7776 // mov r0, x 7777 // movne r0, y 7778 // to 7779 // cmp r0, x 7780 // movne r0, y 7781 /// FIXME: Turn this into a target neutral optimization? 7782 SDValue Res; 7783 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 7784 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 7785 N->getOperand(3), Cmp); 7786 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 7787 SDValue ARMcc; 7788 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 7789 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 7790 N->getOperand(3), NewCmp); 7791 } 7792 7793 if (Res.getNode()) { 7794 APInt KnownZero, KnownOne; 7795 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 7796 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 7797 // Capture demanded bits information that would be otherwise lost. 7798 if (KnownZero == 0xfffffffe) 7799 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7800 DAG.getValueType(MVT::i1)); 7801 else if (KnownZero == 0xffffff00) 7802 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7803 DAG.getValueType(MVT::i8)); 7804 else if (KnownZero == 0xffff0000) 7805 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7806 DAG.getValueType(MVT::i16)); 7807 } 7808 7809 return Res; 7810} 7811 7812SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 7813 DAGCombinerInfo &DCI) const { 7814 switch (N->getOpcode()) { 7815 default: break; 7816 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 7817 case ISD::SUB: return PerformSUBCombine(N, DCI); 7818 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 7819 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 7820 case ISD::AND: return PerformANDCombine(N, DCI); 7821 case ARMISD::BFI: return PerformBFICombine(N, DCI); 7822 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 7823 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 7824 case ISD::STORE: return PerformSTORECombine(N, DCI); 7825 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 7826 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 7827 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 7828 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 7829 case ISD::FP_TO_SINT: 7830 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 7831 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 7832 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 7833 case ISD::SHL: 7834 case ISD::SRA: 7835 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 7836 case ISD::SIGN_EXTEND: 7837 case ISD::ZERO_EXTEND: 7838 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 7839 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 7840 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 7841 case ARMISD::VLD2DUP: 7842 case ARMISD::VLD3DUP: 7843 case ARMISD::VLD4DUP: 7844 return CombineBaseUpdate(N, DCI); 7845 case ISD::INTRINSIC_VOID: 7846 case ISD::INTRINSIC_W_CHAIN: 7847 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 7848 case Intrinsic::arm_neon_vld1: 7849 case Intrinsic::arm_neon_vld2: 7850 case Intrinsic::arm_neon_vld3: 7851 case Intrinsic::arm_neon_vld4: 7852 case Intrinsic::arm_neon_vld2lane: 7853 case Intrinsic::arm_neon_vld3lane: 7854 case Intrinsic::arm_neon_vld4lane: 7855 case Intrinsic::arm_neon_vst1: 7856 case Intrinsic::arm_neon_vst2: 7857 case Intrinsic::arm_neon_vst3: 7858 case Intrinsic::arm_neon_vst4: 7859 case Intrinsic::arm_neon_vst2lane: 7860 case Intrinsic::arm_neon_vst3lane: 7861 case Intrinsic::arm_neon_vst4lane: 7862 return CombineBaseUpdate(N, DCI); 7863 default: break; 7864 } 7865 break; 7866 } 7867 return SDValue(); 7868} 7869 7870bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 7871 EVT VT) const { 7872 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 7873} 7874 7875bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 7876 if (!Subtarget->allowsUnalignedMem()) 7877 return false; 7878 7879 switch (VT.getSimpleVT().SimpleTy) { 7880 default: 7881 return false; 7882 case MVT::i8: 7883 case MVT::i16: 7884 case MVT::i32: 7885 return true; 7886 // FIXME: VLD1 etc with standard alignment is legal. 7887 } 7888} 7889 7890static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 7891 if (V < 0) 7892 return false; 7893 7894 unsigned Scale = 1; 7895 switch (VT.getSimpleVT().SimpleTy) { 7896 default: return false; 7897 case MVT::i1: 7898 case MVT::i8: 7899 // Scale == 1; 7900 break; 7901 case MVT::i16: 7902 // Scale == 2; 7903 Scale = 2; 7904 break; 7905 case MVT::i32: 7906 // Scale == 4; 7907 Scale = 4; 7908 break; 7909 } 7910 7911 if ((V & (Scale - 1)) != 0) 7912 return false; 7913 V /= Scale; 7914 return V == (V & ((1LL << 5) - 1)); 7915} 7916 7917static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 7918 const ARMSubtarget *Subtarget) { 7919 bool isNeg = false; 7920 if (V < 0) { 7921 isNeg = true; 7922 V = - V; 7923 } 7924 7925 switch (VT.getSimpleVT().SimpleTy) { 7926 default: return false; 7927 case MVT::i1: 7928 case MVT::i8: 7929 case MVT::i16: 7930 case MVT::i32: 7931 // + imm12 or - imm8 7932 if (isNeg) 7933 return V == (V & ((1LL << 8) - 1)); 7934 return V == (V & ((1LL << 12) - 1)); 7935 case MVT::f32: 7936 case MVT::f64: 7937 // Same as ARM mode. FIXME: NEON? 7938 if (!Subtarget->hasVFP2()) 7939 return false; 7940 if ((V & 3) != 0) 7941 return false; 7942 V >>= 2; 7943 return V == (V & ((1LL << 8) - 1)); 7944 } 7945} 7946 7947/// isLegalAddressImmediate - Return true if the integer value can be used 7948/// as the offset of the target addressing mode for load / store of the 7949/// given type. 7950static bool isLegalAddressImmediate(int64_t V, EVT VT, 7951 const ARMSubtarget *Subtarget) { 7952 if (V == 0) 7953 return true; 7954 7955 if (!VT.isSimple()) 7956 return false; 7957 7958 if (Subtarget->isThumb1Only()) 7959 return isLegalT1AddressImmediate(V, VT); 7960 else if (Subtarget->isThumb2()) 7961 return isLegalT2AddressImmediate(V, VT, Subtarget); 7962 7963 // ARM mode. 7964 if (V < 0) 7965 V = - V; 7966 switch (VT.getSimpleVT().SimpleTy) { 7967 default: return false; 7968 case MVT::i1: 7969 case MVT::i8: 7970 case MVT::i32: 7971 // +- imm12 7972 return V == (V & ((1LL << 12) - 1)); 7973 case MVT::i16: 7974 // +- imm8 7975 return V == (V & ((1LL << 8) - 1)); 7976 case MVT::f32: 7977 case MVT::f64: 7978 if (!Subtarget->hasVFP2()) // FIXME: NEON? 7979 return false; 7980 if ((V & 3) != 0) 7981 return false; 7982 V >>= 2; 7983 return V == (V & ((1LL << 8) - 1)); 7984 } 7985} 7986 7987bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 7988 EVT VT) const { 7989 int Scale = AM.Scale; 7990 if (Scale < 0) 7991 return false; 7992 7993 switch (VT.getSimpleVT().SimpleTy) { 7994 default: return false; 7995 case MVT::i1: 7996 case MVT::i8: 7997 case MVT::i16: 7998 case MVT::i32: 7999 if (Scale == 1) 8000 return true; 8001 // r + r << imm 8002 Scale = Scale & ~1; 8003 return Scale == 2 || Scale == 4 || Scale == 8; 8004 case MVT::i64: 8005 // r + r 8006 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8007 return true; 8008 return false; 8009 case MVT::isVoid: 8010 // Note, we allow "void" uses (basically, uses that aren't loads or 8011 // stores), because arm allows folding a scale into many arithmetic 8012 // operations. This should be made more precise and revisited later. 8013 8014 // Allow r << imm, but the imm has to be a multiple of two. 8015 if (Scale & 1) return false; 8016 return isPowerOf2_32(Scale); 8017 } 8018} 8019 8020/// isLegalAddressingMode - Return true if the addressing mode represented 8021/// by AM is legal for this target, for a load/store of the specified type. 8022bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 8023 Type *Ty) const { 8024 EVT VT = getValueType(Ty, true); 8025 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 8026 return false; 8027 8028 // Can never fold addr of global into load/store. 8029 if (AM.BaseGV) 8030 return false; 8031 8032 switch (AM.Scale) { 8033 case 0: // no scale reg, must be "r+i" or "r", or "i". 8034 break; 8035 case 1: 8036 if (Subtarget->isThumb1Only()) 8037 return false; 8038 // FALL THROUGH. 8039 default: 8040 // ARM doesn't support any R+R*scale+imm addr modes. 8041 if (AM.BaseOffs) 8042 return false; 8043 8044 if (!VT.isSimple()) 8045 return false; 8046 8047 if (Subtarget->isThumb2()) 8048 return isLegalT2ScaledAddressingMode(AM, VT); 8049 8050 int Scale = AM.Scale; 8051 switch (VT.getSimpleVT().SimpleTy) { 8052 default: return false; 8053 case MVT::i1: 8054 case MVT::i8: 8055 case MVT::i32: 8056 if (Scale < 0) Scale = -Scale; 8057 if (Scale == 1) 8058 return true; 8059 // r + r << imm 8060 return isPowerOf2_32(Scale & ~1); 8061 case MVT::i16: 8062 case MVT::i64: 8063 // r + r 8064 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8065 return true; 8066 return false; 8067 8068 case MVT::isVoid: 8069 // Note, we allow "void" uses (basically, uses that aren't loads or 8070 // stores), because arm allows folding a scale into many arithmetic 8071 // operations. This should be made more precise and revisited later. 8072 8073 // Allow r << imm, but the imm has to be a multiple of two. 8074 if (Scale & 1) return false; 8075 return isPowerOf2_32(Scale); 8076 } 8077 break; 8078 } 8079 return true; 8080} 8081 8082/// isLegalICmpImmediate - Return true if the specified immediate is legal 8083/// icmp immediate, that is the target has icmp instructions which can compare 8084/// a register against the immediate without having to materialize the 8085/// immediate into a register. 8086bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 8087 if (!Subtarget->isThumb()) 8088 return ARM_AM::getSOImmVal(Imm) != -1; 8089 if (Subtarget->isThumb2()) 8090 return ARM_AM::getT2SOImmVal(Imm) != -1; 8091 return Imm >= 0 && Imm <= 255; 8092} 8093 8094/// isLegalAddImmediate - Return true if the specified immediate is legal 8095/// add immediate, that is the target has add instructions which can add 8096/// a register with the immediate without having to materialize the 8097/// immediate into a register. 8098bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 8099 return ARM_AM::getSOImmVal(Imm) != -1; 8100} 8101 8102static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 8103 bool isSEXTLoad, SDValue &Base, 8104 SDValue &Offset, bool &isInc, 8105 SelectionDAG &DAG) { 8106 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8107 return false; 8108 8109 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8110 // AddressingMode 3 8111 Base = Ptr->getOperand(0); 8112 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8113 int RHSC = (int)RHS->getZExtValue(); 8114 if (RHSC < 0 && RHSC > -256) { 8115 assert(Ptr->getOpcode() == ISD::ADD); 8116 isInc = false; 8117 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8118 return true; 8119 } 8120 } 8121 isInc = (Ptr->getOpcode() == ISD::ADD); 8122 Offset = Ptr->getOperand(1); 8123 return true; 8124 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 8125 // AddressingMode 2 8126 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8127 int RHSC = (int)RHS->getZExtValue(); 8128 if (RHSC < 0 && RHSC > -0x1000) { 8129 assert(Ptr->getOpcode() == ISD::ADD); 8130 isInc = false; 8131 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8132 Base = Ptr->getOperand(0); 8133 return true; 8134 } 8135 } 8136 8137 if (Ptr->getOpcode() == ISD::ADD) { 8138 isInc = true; 8139 ARM_AM::ShiftOpc ShOpcVal= 8140 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 8141 if (ShOpcVal != ARM_AM::no_shift) { 8142 Base = Ptr->getOperand(1); 8143 Offset = Ptr->getOperand(0); 8144 } else { 8145 Base = Ptr->getOperand(0); 8146 Offset = Ptr->getOperand(1); 8147 } 8148 return true; 8149 } 8150 8151 isInc = (Ptr->getOpcode() == ISD::ADD); 8152 Base = Ptr->getOperand(0); 8153 Offset = Ptr->getOperand(1); 8154 return true; 8155 } 8156 8157 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 8158 return false; 8159} 8160 8161static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 8162 bool isSEXTLoad, SDValue &Base, 8163 SDValue &Offset, bool &isInc, 8164 SelectionDAG &DAG) { 8165 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8166 return false; 8167 8168 Base = Ptr->getOperand(0); 8169 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8170 int RHSC = (int)RHS->getZExtValue(); 8171 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 8172 assert(Ptr->getOpcode() == ISD::ADD); 8173 isInc = false; 8174 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8175 return true; 8176 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 8177 isInc = Ptr->getOpcode() == ISD::ADD; 8178 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 8179 return true; 8180 } 8181 } 8182 8183 return false; 8184} 8185 8186/// getPreIndexedAddressParts - returns true by value, base pointer and 8187/// offset pointer and addressing mode by reference if the node's address 8188/// can be legally represented as pre-indexed load / store address. 8189bool 8190ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8191 SDValue &Offset, 8192 ISD::MemIndexedMode &AM, 8193 SelectionDAG &DAG) const { 8194 if (Subtarget->isThumb1Only()) 8195 return false; 8196 8197 EVT VT; 8198 SDValue Ptr; 8199 bool isSEXTLoad = false; 8200 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8201 Ptr = LD->getBasePtr(); 8202 VT = LD->getMemoryVT(); 8203 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8204 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8205 Ptr = ST->getBasePtr(); 8206 VT = ST->getMemoryVT(); 8207 } else 8208 return false; 8209 8210 bool isInc; 8211 bool isLegal = false; 8212 if (Subtarget->isThumb2()) 8213 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8214 Offset, isInc, DAG); 8215 else 8216 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8217 Offset, isInc, DAG); 8218 if (!isLegal) 8219 return false; 8220 8221 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 8222 return true; 8223} 8224 8225/// getPostIndexedAddressParts - returns true by value, base pointer and 8226/// offset pointer and addressing mode by reference if this node can be 8227/// combined with a load / store to form a post-indexed load / store. 8228bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 8229 SDValue &Base, 8230 SDValue &Offset, 8231 ISD::MemIndexedMode &AM, 8232 SelectionDAG &DAG) const { 8233 if (Subtarget->isThumb1Only()) 8234 return false; 8235 8236 EVT VT; 8237 SDValue Ptr; 8238 bool isSEXTLoad = false; 8239 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8240 VT = LD->getMemoryVT(); 8241 Ptr = LD->getBasePtr(); 8242 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8243 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8244 VT = ST->getMemoryVT(); 8245 Ptr = ST->getBasePtr(); 8246 } else 8247 return false; 8248 8249 bool isInc; 8250 bool isLegal = false; 8251 if (Subtarget->isThumb2()) 8252 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8253 isInc, DAG); 8254 else 8255 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8256 isInc, DAG); 8257 if (!isLegal) 8258 return false; 8259 8260 if (Ptr != Base) { 8261 // Swap base ptr and offset to catch more post-index load / store when 8262 // it's legal. In Thumb2 mode, offset must be an immediate. 8263 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 8264 !Subtarget->isThumb2()) 8265 std::swap(Base, Offset); 8266 8267 // Post-indexed load / store update the base pointer. 8268 if (Ptr != Base) 8269 return false; 8270 } 8271 8272 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 8273 return true; 8274} 8275 8276void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8277 const APInt &Mask, 8278 APInt &KnownZero, 8279 APInt &KnownOne, 8280 const SelectionDAG &DAG, 8281 unsigned Depth) const { 8282 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 8283 switch (Op.getOpcode()) { 8284 default: break; 8285 case ARMISD::CMOV: { 8286 // Bits are known zero/one if known on the LHS and RHS. 8287 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 8288 if (KnownZero == 0 && KnownOne == 0) return; 8289 8290 APInt KnownZeroRHS, KnownOneRHS; 8291 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 8292 KnownZeroRHS, KnownOneRHS, Depth+1); 8293 KnownZero &= KnownZeroRHS; 8294 KnownOne &= KnownOneRHS; 8295 return; 8296 } 8297 } 8298} 8299 8300//===----------------------------------------------------------------------===// 8301// ARM Inline Assembly Support 8302//===----------------------------------------------------------------------===// 8303 8304bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 8305 // Looking for "rev" which is V6+. 8306 if (!Subtarget->hasV6Ops()) 8307 return false; 8308 8309 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8310 std::string AsmStr = IA->getAsmString(); 8311 SmallVector<StringRef, 4> AsmPieces; 8312 SplitString(AsmStr, AsmPieces, ";\n"); 8313 8314 switch (AsmPieces.size()) { 8315 default: return false; 8316 case 1: 8317 AsmStr = AsmPieces[0]; 8318 AsmPieces.clear(); 8319 SplitString(AsmStr, AsmPieces, " \t,"); 8320 8321 // rev $0, $1 8322 if (AsmPieces.size() == 3 && 8323 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 8324 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 8325 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8326 if (Ty && Ty->getBitWidth() == 32) 8327 return IntrinsicLowering::LowerToByteSwap(CI); 8328 } 8329 break; 8330 } 8331 8332 return false; 8333} 8334 8335/// getConstraintType - Given a constraint letter, return the type of 8336/// constraint it is for this target. 8337ARMTargetLowering::ConstraintType 8338ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 8339 if (Constraint.size() == 1) { 8340 switch (Constraint[0]) { 8341 default: break; 8342 case 'l': return C_RegisterClass; 8343 case 'w': return C_RegisterClass; 8344 case 'h': return C_RegisterClass; 8345 case 'x': return C_RegisterClass; 8346 case 't': return C_RegisterClass; 8347 case 'j': return C_Other; // Constant for movw. 8348 // An address with a single base register. Due to the way we 8349 // currently handle addresses it is the same as an 'r' memory constraint. 8350 case 'Q': return C_Memory; 8351 } 8352 } else if (Constraint.size() == 2) { 8353 switch (Constraint[0]) { 8354 default: break; 8355 // All 'U+' constraints are addresses. 8356 case 'U': return C_Memory; 8357 } 8358 } 8359 return TargetLowering::getConstraintType(Constraint); 8360} 8361 8362/// Examine constraint type and operand type and determine a weight value. 8363/// This object must already have been set up with the operand type 8364/// and the current alternative constraint selected. 8365TargetLowering::ConstraintWeight 8366ARMTargetLowering::getSingleConstraintMatchWeight( 8367 AsmOperandInfo &info, const char *constraint) const { 8368 ConstraintWeight weight = CW_Invalid; 8369 Value *CallOperandVal = info.CallOperandVal; 8370 // If we don't have a value, we can't do a match, 8371 // but allow it at the lowest weight. 8372 if (CallOperandVal == NULL) 8373 return CW_Default; 8374 Type *type = CallOperandVal->getType(); 8375 // Look at the constraint type. 8376 switch (*constraint) { 8377 default: 8378 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 8379 break; 8380 case 'l': 8381 if (type->isIntegerTy()) { 8382 if (Subtarget->isThumb()) 8383 weight = CW_SpecificReg; 8384 else 8385 weight = CW_Register; 8386 } 8387 break; 8388 case 'w': 8389 if (type->isFloatingPointTy()) 8390 weight = CW_Register; 8391 break; 8392 } 8393 return weight; 8394} 8395 8396typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 8397RCPair 8398ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8399 EVT VT) const { 8400 if (Constraint.size() == 1) { 8401 // GCC ARM Constraint Letters 8402 switch (Constraint[0]) { 8403 case 'l': // Low regs or general regs. 8404 if (Subtarget->isThumb()) 8405 return RCPair(0U, ARM::tGPRRegisterClass); 8406 else 8407 return RCPair(0U, ARM::GPRRegisterClass); 8408 case 'h': // High regs or no regs. 8409 if (Subtarget->isThumb()) 8410 return RCPair(0U, ARM::hGPRRegisterClass); 8411 break; 8412 case 'r': 8413 return RCPair(0U, ARM::GPRRegisterClass); 8414 case 'w': 8415 if (VT == MVT::f32) 8416 return RCPair(0U, ARM::SPRRegisterClass); 8417 if (VT.getSizeInBits() == 64) 8418 return RCPair(0U, ARM::DPRRegisterClass); 8419 if (VT.getSizeInBits() == 128) 8420 return RCPair(0U, ARM::QPRRegisterClass); 8421 break; 8422 case 'x': 8423 if (VT == MVT::f32) 8424 return RCPair(0U, ARM::SPR_8RegisterClass); 8425 if (VT.getSizeInBits() == 64) 8426 return RCPair(0U, ARM::DPR_8RegisterClass); 8427 if (VT.getSizeInBits() == 128) 8428 return RCPair(0U, ARM::QPR_8RegisterClass); 8429 break; 8430 case 't': 8431 if (VT == MVT::f32) 8432 return RCPair(0U, ARM::SPRRegisterClass); 8433 break; 8434 } 8435 } 8436 if (StringRef("{cc}").equals_lower(Constraint)) 8437 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 8438 8439 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8440} 8441 8442/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8443/// vector. If it is invalid, don't add anything to Ops. 8444void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8445 std::string &Constraint, 8446 std::vector<SDValue>&Ops, 8447 SelectionDAG &DAG) const { 8448 SDValue Result(0, 0); 8449 8450 // Currently only support length 1 constraints. 8451 if (Constraint.length() != 1) return; 8452 8453 char ConstraintLetter = Constraint[0]; 8454 switch (ConstraintLetter) { 8455 default: break; 8456 case 'j': 8457 case 'I': case 'J': case 'K': case 'L': 8458 case 'M': case 'N': case 'O': 8459 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 8460 if (!C) 8461 return; 8462 8463 int64_t CVal64 = C->getSExtValue(); 8464 int CVal = (int) CVal64; 8465 // None of these constraints allow values larger than 32 bits. Check 8466 // that the value fits in an int. 8467 if (CVal != CVal64) 8468 return; 8469 8470 switch (ConstraintLetter) { 8471 case 'j': 8472 // Constant suitable for movw, must be between 0 and 8473 // 65535. 8474 if (Subtarget->hasV6T2Ops()) 8475 if (CVal >= 0 && CVal <= 65535) 8476 break; 8477 return; 8478 case 'I': 8479 if (Subtarget->isThumb1Only()) { 8480 // This must be a constant between 0 and 255, for ADD 8481 // immediates. 8482 if (CVal >= 0 && CVal <= 255) 8483 break; 8484 } else if (Subtarget->isThumb2()) { 8485 // A constant that can be used as an immediate value in a 8486 // data-processing instruction. 8487 if (ARM_AM::getT2SOImmVal(CVal) != -1) 8488 break; 8489 } else { 8490 // A constant that can be used as an immediate value in a 8491 // data-processing instruction. 8492 if (ARM_AM::getSOImmVal(CVal) != -1) 8493 break; 8494 } 8495 return; 8496 8497 case 'J': 8498 if (Subtarget->isThumb()) { // FIXME thumb2 8499 // This must be a constant between -255 and -1, for negated ADD 8500 // immediates. This can be used in GCC with an "n" modifier that 8501 // prints the negated value, for use with SUB instructions. It is 8502 // not useful otherwise but is implemented for compatibility. 8503 if (CVal >= -255 && CVal <= -1) 8504 break; 8505 } else { 8506 // This must be a constant between -4095 and 4095. It is not clear 8507 // what this constraint is intended for. Implemented for 8508 // compatibility with GCC. 8509 if (CVal >= -4095 && CVal <= 4095) 8510 break; 8511 } 8512 return; 8513 8514 case 'K': 8515 if (Subtarget->isThumb1Only()) { 8516 // A 32-bit value where only one byte has a nonzero value. Exclude 8517 // zero to match GCC. This constraint is used by GCC internally for 8518 // constants that can be loaded with a move/shift combination. 8519 // It is not useful otherwise but is implemented for compatibility. 8520 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8521 break; 8522 } else if (Subtarget->isThumb2()) { 8523 // A constant whose bitwise inverse can be used as an immediate 8524 // value in a data-processing instruction. This can be used in GCC 8525 // with a "B" modifier that prints the inverted value, for use with 8526 // BIC and MVN instructions. It is not useful otherwise but is 8527 // implemented for compatibility. 8528 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8529 break; 8530 } else { 8531 // A constant whose bitwise inverse can be used as an immediate 8532 // value in a data-processing instruction. This can be used in GCC 8533 // with a "B" modifier that prints the inverted value, for use with 8534 // BIC and MVN instructions. It is not useful otherwise but is 8535 // implemented for compatibility. 8536 if (ARM_AM::getSOImmVal(~CVal) != -1) 8537 break; 8538 } 8539 return; 8540 8541 case 'L': 8542 if (Subtarget->isThumb1Only()) { 8543 // This must be a constant between -7 and 7, 8544 // for 3-operand ADD/SUB immediate instructions. 8545 if (CVal >= -7 && CVal < 7) 8546 break; 8547 } else if (Subtarget->isThumb2()) { 8548 // A constant whose negation can be used as an immediate value in a 8549 // data-processing instruction. This can be used in GCC with an "n" 8550 // modifier that prints the negated value, for use with SUB 8551 // instructions. It is not useful otherwise but is implemented for 8552 // compatibility. 8553 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8554 break; 8555 } else { 8556 // A constant whose negation can be used as an immediate value in a 8557 // data-processing instruction. This can be used in GCC with an "n" 8558 // modifier that prints the negated value, for use with SUB 8559 // instructions. It is not useful otherwise but is implemented for 8560 // compatibility. 8561 if (ARM_AM::getSOImmVal(-CVal) != -1) 8562 break; 8563 } 8564 return; 8565 8566 case 'M': 8567 if (Subtarget->isThumb()) { // FIXME thumb2 8568 // This must be a multiple of 4 between 0 and 1020, for 8569 // ADD sp + immediate. 8570 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8571 break; 8572 } else { 8573 // A power of two or a constant between 0 and 32. This is used in 8574 // GCC for the shift amount on shifted register operands, but it is 8575 // useful in general for any shift amounts. 8576 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8577 break; 8578 } 8579 return; 8580 8581 case 'N': 8582 if (Subtarget->isThumb()) { // FIXME thumb2 8583 // This must be a constant between 0 and 31, for shift amounts. 8584 if (CVal >= 0 && CVal <= 31) 8585 break; 8586 } 8587 return; 8588 8589 case 'O': 8590 if (Subtarget->isThumb()) { // FIXME thumb2 8591 // This must be a multiple of 4 between -508 and 508, for 8592 // ADD/SUB sp = sp + immediate. 8593 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 8594 break; 8595 } 8596 return; 8597 } 8598 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 8599 break; 8600 } 8601 8602 if (Result.getNode()) { 8603 Ops.push_back(Result); 8604 return; 8605 } 8606 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 8607} 8608 8609bool 8610ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 8611 // The ARM target isn't yet aware of offsets. 8612 return false; 8613} 8614 8615bool ARM::isBitFieldInvertedMask(unsigned v) { 8616 if (v == 0xffffffff) 8617 return 0; 8618 // there can be 1's on either or both "outsides", all the "inside" 8619 // bits must be 0's 8620 unsigned int lsb = 0, msb = 31; 8621 while (v & (1 << msb)) --msb; 8622 while (v & (1 << lsb)) ++lsb; 8623 for (unsigned int i = lsb; i <= msb; ++i) { 8624 if (v & (1 << i)) 8625 return 0; 8626 } 8627 return 1; 8628} 8629 8630/// isFPImmLegal - Returns true if the target can instruction select the 8631/// specified FP immediate natively. If false, the legalizer will 8632/// materialize the FP immediate as a load from a constant pool. 8633bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 8634 if (!Subtarget->hasVFP3()) 8635 return false; 8636 if (VT == MVT::f32) 8637 return ARM_AM::getFP32Imm(Imm) != -1; 8638 if (VT == MVT::f64) 8639 return ARM_AM::getFP64Imm(Imm) != -1; 8640 return false; 8641} 8642 8643/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 8644/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 8645/// specified in the intrinsic calls. 8646bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 8647 const CallInst &I, 8648 unsigned Intrinsic) const { 8649 switch (Intrinsic) { 8650 case Intrinsic::arm_neon_vld1: 8651 case Intrinsic::arm_neon_vld2: 8652 case Intrinsic::arm_neon_vld3: 8653 case Intrinsic::arm_neon_vld4: 8654 case Intrinsic::arm_neon_vld2lane: 8655 case Intrinsic::arm_neon_vld3lane: 8656 case Intrinsic::arm_neon_vld4lane: { 8657 Info.opc = ISD::INTRINSIC_W_CHAIN; 8658 // Conservatively set memVT to the entire set of vectors loaded. 8659 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 8660 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8661 Info.ptrVal = I.getArgOperand(0); 8662 Info.offset = 0; 8663 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8664 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8665 Info.vol = false; // volatile loads with NEON intrinsics not supported 8666 Info.readMem = true; 8667 Info.writeMem = false; 8668 return true; 8669 } 8670 case Intrinsic::arm_neon_vst1: 8671 case Intrinsic::arm_neon_vst2: 8672 case Intrinsic::arm_neon_vst3: 8673 case Intrinsic::arm_neon_vst4: 8674 case Intrinsic::arm_neon_vst2lane: 8675 case Intrinsic::arm_neon_vst3lane: 8676 case Intrinsic::arm_neon_vst4lane: { 8677 Info.opc = ISD::INTRINSIC_VOID; 8678 // Conservatively set memVT to the entire set of vectors stored. 8679 unsigned NumElts = 0; 8680 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 8681 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 8682 if (!ArgTy->isVectorTy()) 8683 break; 8684 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 8685 } 8686 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8687 Info.ptrVal = I.getArgOperand(0); 8688 Info.offset = 0; 8689 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8690 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8691 Info.vol = false; // volatile stores with NEON intrinsics not supported 8692 Info.readMem = false; 8693 Info.writeMem = true; 8694 return true; 8695 } 8696 case Intrinsic::arm_strexd: { 8697 Info.opc = ISD::INTRINSIC_W_CHAIN; 8698 Info.memVT = MVT::i64; 8699 Info.ptrVal = I.getArgOperand(2); 8700 Info.offset = 0; 8701 Info.align = 8; 8702 Info.vol = true; 8703 Info.readMem = false; 8704 Info.writeMem = true; 8705 return true; 8706 } 8707 case Intrinsic::arm_ldrexd: { 8708 Info.opc = ISD::INTRINSIC_W_CHAIN; 8709 Info.memVT = MVT::i64; 8710 Info.ptrVal = I.getArgOperand(0); 8711 Info.offset = 0; 8712 Info.align = 8; 8713 Info.vol = true; 8714 Info.readMem = true; 8715 Info.writeMem = false; 8716 return true; 8717 } 8718 default: 8719 break; 8720 } 8721 8722 return false; 8723} 8724