Searched defs:imm (Results 1 - 15 of 15) sorted by relevance

/art/compiler/linker/arm/
H A Drelative_patcher_thumb2.cc72 uint32_t imm = (diff16 >> 11) & 0x1u; local
75 insn = (insn & 0xfbf08f00u) | (imm << 26) | (imm4 << 16) | (imm3 << 12) | imm8;
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc158 void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, argument
162 LoadImmediate(scratch.AsXRegister(), imm);
167 void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, argument
171 LoadImmediate(scratch.AsXRegister(), imm);
/art/compiler/utils/
H A Dassembler_test.h154 for (int64_t imm : imms) {
155 ImmType new_imm = CreateImmediate(imm);
174 sreg << imm; local
206 for (int64_t imm : imms) {
207 ImmType new_imm = CreateImmediate(imm);
226 sreg << imm; local
253 for (int64_t imm : imms) {
254 ImmType new_imm = CreateImmediate(imm);
267 sreg << imm; local
400 for (int64_t imm
408 sreg << imm; local
805 sreg << imm; local
893 sreg << imm; local
[all...]
/art/disassembler/
H A Ddisassembler_arm.cc169 uint32_t imm = (instruction & 0xff); local
170 value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate)));
898 // |1110|1110|1|D|11| iH | Vd |101|S|0|0|0|0| iL | VMOV (imm)
1906 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
1907 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
1916 // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii
1917 // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
/art/compiler/optimizing/
H A Dcode_generator_mips64.cc1029 int64_t imm = CodeGenerator::GetInt64ValueOf(right->AsConstant()); local
1031 can_use_imm = IsUint<16>(imm);
1033 can_use_imm = IsInt<16>(imm);
1036 can_use_imm = IsInt<16>(-imm);
1856 int64_t imm = Int64FromConstant(second.GetConstant()); local
1857 DCHECK(imm == 1 || imm == -1);
1862 if (imm == -1) {
1885 int64_t imm = Int64FromConstant(second.GetConstant()); local
1886 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm));
1988 int64_t imm = Int64FromConstant(second.GetConstant()); local
2063 int64_t imm = Int64FromConstant(second.GetConstant()); local
[all...]
H A Dcode_generator_arm64.cc2526 int64_t imm = Int64FromConstant(second.GetConstant()); local
2527 DCHECK(imm == 1 || imm == -1);
2532 if (imm == 1) {
2549 int64_t imm = Int64FromConstant(second.GetConstant()); local
2550 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm));
2560 if (imm > 0) {
2584 int64_t imm = Int64FromConstant(second.GetConstant()); local
2591 CalculateMagicAndShiftForDivRem(imm, type == Primitive::kPrimLong /* is_long */, &magic, &shift);
2605 if (imm >
2636 int64_t imm = Int64FromConstant(second.GetConstant()); local
[all...]
H A Dcode_generator_mips.cc1146 int32_t imm = CodeGenerator::GetInt32ValueOf(right->AsConstant()); local
1148 can_use_imm = IsUint<16>(imm);
1150 can_use_imm = IsInt<16>(imm);
1153 can_use_imm = IsInt<16>(-imm);
2272 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2273 DCHECK(imm == 1 || imm == -1);
2278 if (imm == -1) {
2296 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2297 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
2345 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2395 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2838 int64_t imm = 0; local
[all...]
H A Dcode_generator_arm.cc2707 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2708 DCHECK(imm == 1 || imm == -1);
2713 if (imm == 1) {
2732 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2733 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
2746 if (imm < 0) {
2767 int64_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
2771 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift);
2776 if (imm >
2804 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
[all...]
H A Dcode_generator_x86.cc2999 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue());
3000 __ imull(out.AsRegister<Register>(), first.AsRegister<Register>(), imm);
3239 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3241 DCHECK(imm == 1 || imm == -1);
3247 if (imm == -1) {
3259 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3260 DCHECK(IsPowerOfTwo(AbsOrMin(imm)));
3261 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
3268 int shift = CTZ(imm);
3282 int imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local
3372 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local
5728 __ movl(Address(ESP, destination.GetStackIndex()), imm); local
[all...]
H A Dcode_generator_x86_64.cc3026 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue());
3027 __ subl(first.AsRegister<CpuRegister>(), imm);
3129 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue());
3130 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm);
3287 int64_t imm = Int64FromConstant(second.GetConstant()); local
3289 DCHECK(imm == 1 || imm == -1);
3297 if (imm == -1) {
3309 if (imm == -1) {
3328 int64_t imm local
3391 int imm = second.GetConstant()->AsIntConstant()->GetValue(); local
3434 int64_t imm = second.GetConstant()->AsLongConstant()->GetValue(); local
3502 int64_t imm = Int64FromConstant(second.GetConstant()); local
[all...]
/art/compiler/utils/x86/
H A Dassembler_x86.cc81 void X86Assembler::pushl(const Immediate& imm) { argument
83 if (imm.is_int8()) {
85 EmitUint8(imm.value() & 0xFF);
88 EmitImmediate(imm);
106 void X86Assembler::movl(Register dst, const Immediate& imm) { argument
109 EmitImmediate(imm);
134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument
138 EmitImmediate(imm);
249 void X86Assembler::movb(const Address& dst, const Immediate& imm) { argument
253 CHECK(imm
303 movw(const Address& dst, const Immediate& imm) argument
773 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
784 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1033 cmpw(const Address& address, const Immediate& imm) argument
1040 cmpl(Register reg, const Immediate& imm) argument
1081 cmpl(const Address& address, const Immediate& imm) argument
1140 andl(Register dst, const Immediate& imm) argument
1160 orl(Register dst, const Immediate& imm) argument
1180 xorl(Register dst, const Immediate& imm) argument
1186 addl(Register reg, const Immediate& imm) argument
1199 addl(const Address& address, const Immediate& imm) argument
1205 adcl(Register reg, const Immediate& imm) argument
1232 subl(Register reg, const Immediate& imm) argument
1273 imull(Register dst, Register src, const Immediate& imm) argument
1291 imull(Register reg, const Immediate& imm) argument
1339 sbbl(Register reg, const Immediate& imm) argument
1385 shll(Register reg, const Immediate& imm) argument
1395 shll(const Address& address, const Immediate& imm) argument
1405 shrl(Register reg, const Immediate& imm) argument
1415 shrl(const Address& address, const Immediate& imm) argument
1425 sarl(Register reg, const Immediate& imm) argument
1435 sarl(const Address& address, const Immediate& imm) argument
1454 shld(Register dst, Register src, const Immediate& imm) argument
1472 shrd(Register dst, Register src, const Immediate& imm) argument
1481 roll(Register reg, const Immediate& imm) argument
1491 rorl(Register reg, const Immediate& imm) argument
1515 enter(const Immediate& imm) argument
1537 ret(const Immediate& imm) argument
1744 AddImmediate(Register reg, const Immediate& imm) argument
1835 EmitImmediate(const Immediate& imm) argument
1896 EmitGenericShift(int reg_or_opcode, const Operand& operand, const Immediate& imm) argument
2040 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument
2045 StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister) argument
[all...]
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.cc78 void X86_64Assembler::pushq(const Immediate& imm) { argument
80 CHECK(imm.is_int32()); // pushq only supports 32b immediate.
81 if (imm.is_int8()) {
83 EmitUint8(imm.value() & 0xFF);
86 EmitImmediate(imm);
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument
108 if (imm.is_int32()) {
113 EmitInt32(static_cast<int32_t>(imm.value()));
117 EmitInt64(imm.value());
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument
131 movq(const Address& dst, const Immediate& imm) argument
189 movl(const Address& dst, const Immediate& imm) argument
292 movb(const Address& dst, const Immediate& imm) argument
352 movw(const Address& dst, const Immediate& imm) argument
929 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
941 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument
1227 cmpw(const Address& address, const Immediate& imm) argument
1236 cmpl(CpuRegister reg, const Immediate& imm) argument
1268 cmpl(const Address& address, const Immediate& imm) argument
1284 cmpq(CpuRegister reg, const Immediate& imm) argument
1300 cmpq(const Address& address, const Immediate& imm) argument
1398 andl(CpuRegister dst, const Immediate& imm) argument
1405 andq(CpuRegister reg, const Immediate& imm) argument
1445 orl(CpuRegister dst, const Immediate& imm) argument
1452 orq(CpuRegister dst, const Immediate& imm) argument
1492 xorl(CpuRegister dst, const Immediate& imm) argument
1507 xorq(CpuRegister dst, const Immediate& imm) argument
1575 addl(CpuRegister reg, const Immediate& imm) argument
1582 addq(CpuRegister reg, const Immediate& imm) argument
1615 addl(const Address& address, const Immediate& imm) argument
1630 subl(CpuRegister reg, const Immediate& imm) argument
1637 subq(CpuRegister reg, const Immediate& imm) argument
1706 imull(CpuRegister dst, CpuRegister src, const Immediate& imm) argument
1728 imull(CpuRegister reg, const Immediate& imm) argument
1751 imulq(CpuRegister reg, const Immediate& imm) argument
1755 imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) argument
1825 shll(CpuRegister reg, const Immediate& imm) argument
1830 shlq(CpuRegister reg, const Immediate& imm) argument
1845 shrl(CpuRegister reg, const Immediate& imm) argument
1850 shrq(CpuRegister reg, const Immediate& imm) argument
1865 sarl(CpuRegister reg, const Immediate& imm) argument
1875 sarq(CpuRegister reg, const Immediate& imm) argument
1885 roll(CpuRegister reg, const Immediate& imm) argument
1895 rorl(CpuRegister reg, const Immediate& imm) argument
1905 rolq(CpuRegister reg, const Immediate& imm) argument
1915 rorq(CpuRegister reg, const Immediate& imm) argument
1957 enter(const Immediate& imm) argument
1979 ret(const Immediate& imm) argument
2162 AddImmediate(CpuRegister reg, const Immediate& imm) argument
2396 EmitImmediate(const Immediate& imm) argument
2461 EmitGenericShift(bool wide, int reg_or_opcode, CpuRegister reg, const Immediate& imm) argument
2791 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument
2796 StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister) argument
[all...]
/art/compiler/utils/arm/
H A Dassembler_thumb2.cc1384 uint32_t imm = so.GetImmediate(); local
1386 uint32_t i = (imm >> 11) & 1;
1387 uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */;
1388 uint32_t imm8 = imm & 0xff;
1400 uint32_t imm = ModifiedImmediate(so.encodingThumb()); local
1401 if (imm == kInvalidModifiedImmediate) {
1410 imm;
1672 // ADD sp, sp, #imm
1686 // ADD rd, SP, #imm
1732 // SUB sp, sp, #imm
2725 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument
2745 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
[all...]
/art/compiler/utils/mips/
H A Dassembler_mips.cc138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
144 imm;
177 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister ft, uint16_t imm) { argument
182 imm;
2565 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, argument
2569 LoadConst32(scratch.AsCoreRegister(), imm);
2573 void MipsAssembler::StoreImmediateToThread32(ThreadOffset<kMipsWordSize> dest, uint32_t imm, argument
2578 LoadConst32(scratch.AsCoreRegister(), imm);
/art/compiler/utils/mips64/
H A Dassembler_mips64.cc131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument
137 imm;
170 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) { argument
175 imm;
2104 void Mips64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, argument
2108 LoadConst32(scratch.AsGpuRegister(), imm);

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