| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 86 registers_.push_back(new mips64::GpuRegister(mips64::A1));
119 secondary_register_names_.emplace(mips64::GpuRegister(mips64::A1), "a1");
227 (Base::GetAssembler()->*f)(mips64::A1, &label);
246 (Base::GetAssembler()->*f)(mips64::A0, mips64::A1, &label);
788 __ Beqc(mips64::A0, mips64::A1, &label);
1009 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0);
1010 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1);
1011 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 256);
1012 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1000);
1013 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1,
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 62 registers_.push_back(new mips::Register(mips::A1));
95 secondary_register_names_.emplace(mips::Register(mips::A1), "a1");
203 (Base::GetAssembler()->*f)(mips::A1, &label);
222 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label);
728 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0);
729 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 256);
730 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 1000);
731 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0x8000);
732 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1, 0x10000);
733 __ LoadFromOffset(mips::kLoadSignedByte, mips::A0, mips::A1,
[all...] |
| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 35 A1 = 5, enumerator in enum:art::mips::Register
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| H A D | context_mips.cc | 75 gprs_[A1] = nullptr;
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| H A D | quick_method_frame_info_mips.h | 34 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3);
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| H A D | quick_entrypoints_mips.S | 665 li $t3, 2 # t3 = gpr_index = 2 (skip A0 and A1)
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 35 A1 = 5, enumerator in enum:art::mips64::GpuRegister
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| H A D | quick_method_frame_info_mips64.h | 33 (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) |
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| H A D | context_mips64.cc | 75 gprs_[A1] = nullptr;
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips.h | 33 { A1, A2, A3 };
44 { A0, A1, A2, A3 };
110 return Location::RegisterLocation(A1);
123 : (is_instance ? Location::RegisterLocation(A2) : Location::RegisterLocation(A1));
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| H A D | code_generator_mips64.h | 33 { A1, A2, A3, A4, A5, A6, A7 };
44 { A0, A1, A2, A3, A4, A5, A6, A7 };
110 return Location::RegisterLocation(A1);
123 : Location::RegisterLocation(A1));
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| H A D | optimizing_cfi_test.cc | 233 __ Beqc(mips64::A1, mips64::A2, &target);
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| H A D | code_generator_mips.cc | 97 if (calling_convention.GetRegisterAt(gp_index) == A1) {
98 gp_index_++; // Skip A1, and use A2_A3 instead.
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 26 static const Register kCoreArgumentRegisters[] = { A0, A1, A2, A3 };
223 A0, A1, A2, A3
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 27 A0, A1, A2, A3, A4, A5, A6, A7
97 int reg_index = 1; // we start from A1, A0 holds ArtMethod*.
114 // e.g. A1, A2, F3, A4, F5, F6, A7
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