1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_
18#define ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_
19
20#include <iosfwd>
21
22#include "base/logging.h"
23#include "base/macros.h"
24#include "globals.h"
25
26namespace art {
27namespace mips64 {
28
29enum GpuRegister {
30  ZERO =  0,
31  AT   =  1,  // Assembler temporary.
32  V0   =  2,  // Values.
33  V1   =  3,
34  A0   =  4,  // Arguments.
35  A1   =  5,
36  A2   =  6,
37  A3   =  7,
38  A4   =  8,
39  A5   =  9,
40  A6   = 10,
41  A7   = 11,
42  T0   = 12,  // Temporaries.
43  T1   = 13,
44  T2   = 14,
45  T3   = 15,
46  S0   = 16,  // Saved values.
47  S1   = 17,
48  S2   = 18,
49  S3   = 19,
50  S4   = 20,
51  S5   = 21,
52  S6   = 22,
53  S7   = 23,
54  T8   = 24,  // More temporaries.
55  T9   = 25,
56  K0   = 26,  // Reserved for trap handler.
57  K1   = 27,
58  GP   = 28,  // Global pointer.
59  SP   = 29,  // Stack pointer.
60  S8   = 30,  // Saved value/frame pointer.
61  RA   = 31,  // Return address.
62  TR   = S1,  // ART Thread Register
63  TMP  = T8,  // scratch register (in addition to AT)
64  TMP2 = T3,  // scratch register (in addition to AT, reserved for assembler)
65  kNumberOfGpuRegisters = 32,
66  kNoGpuRegister = -1  // Signals an illegal register.
67};
68std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs);
69
70// Values for floating point registers.
71enum FpuRegister {
72  F0  =  0,
73  F1  =  1,
74  F2  =  2,
75  F3  =  3,
76  F4  =  4,
77  F5  =  5,
78  F6  =  6,
79  F7  =  7,
80  F8  =  8,
81  F9  =  9,
82  F10 = 10,
83  F11 = 11,
84  F12 = 12,
85  F13 = 13,
86  F14 = 14,
87  F15 = 15,
88  F16 = 16,
89  F17 = 17,
90  F18 = 18,
91  F19 = 19,
92  F20 = 20,
93  F21 = 21,
94  F22 = 22,
95  F23 = 23,
96  F24 = 24,
97  F25 = 25,
98  F26 = 26,
99  F27 = 27,
100  F28 = 28,
101  F29 = 29,
102  F30 = 30,
103  F31 = 31,
104  FTMP = F8,  // scratch register
105  kNumberOfFpuRegisters = 32,
106  kNoFpuRegister = -1,
107};
108std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs);
109
110}  // namespace mips64
111}  // namespace art
112
113#endif  // ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_
114