| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 36 A2 = 6, enumerator in enum:art::mips::Register
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| H A D | context_mips.cc | 76 gprs_[A2] = nullptr;
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| H A D | quick_method_frame_info_mips.h | 34 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3);
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 36 A2 = 6, enumerator in enum:art::mips64::GpuRegister
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| H A D | quick_method_frame_info_mips64.h | 33 (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) |
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| H A D | context_mips64.cc | 77 gprs_[A2] = nullptr;
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 63 registers_.push_back(new mips::Register(mips::A2));
96 secondary_register_names_.emplace(mips::Register(mips::A2), "a2");
232 (Base::GetAssembler()->*f)(mips::A2, mips::A3, &label);
785 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 0);
786 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 256);
787 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 1000);
788 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 0x8000);
789 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 0x10000);
790 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, 0x12345678);
791 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2,
[all...] |
| /art/compiler/optimizing/ |
| H A D | code_generator_mips.h | 33 { A1, A2, A3 };
44 { A0, A1, A2, A3 };
122 ? Location::RegisterPairLocation(A2, A3)
123 : (is_instance ? Location::RegisterLocation(A2) : Location::RegisterLocation(A1));
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| H A D | code_generator_mips64.h | 33 { A1, A2, A3, A4, A5, A6, A7 };
44 { A0, A1, A2, A3, A4, A5, A6, A7 };
120 ? Location::RegisterLocation(A2)
122 ? Location::RegisterLocation(A2)
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| H A D | optimizing_cfi_test.cc | 233 __ Beqc(mips64::A1, mips64::A2, &target);
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| H A D | intrinsics_mips64.cc | 1503 DCHECK_EQ(tmp_reg, A2);
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| H A D | intrinsics_mips.cc | 2101 DCHECK_EQ(tmp_reg, A2);
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 26 static const Register kCoreArgumentRegisters[] = { A0, A1, A2, A3 };
151 // or jclass for static methods and the JNIEnv. We start at the aligned register A2.
223 A0, A1, A2, A3
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 27 A0, A1, A2, A3, A4, A5, A6, A7
114 // e.g. A1, A2, F3, A4, F5, F6, A7
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 87 registers_.push_back(new mips64::GpuRegister(mips64::A2));
120 secondary_register_names_.emplace(mips64::GpuRegister(mips64::A2), "a2");
256 (Base::GetAssembler()->*f)(mips64::A2, mips64::A3, &label);
798 __ Beqc(mips64::A2, mips64::A3, &label);
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