Searched refs:ESP (Results 1 - 10 of 10) sorted by relevance

/art/runtime/arch/x86/
H A Dregisters_x86.h34 ESP = 4, enumerator in enum:art::x86::Register
H A Dcontext_x86.cc30 gprs_[ESP] = &esp_;
33 esp_ = X86Context::kBadGprBase + ESP;
102 uintptr_t esp = gprs[kNumberOfCpuRegisters - ESP - 1] - sizeof(intptr_t);
115 "movl %0, %%esp\n\t" // ESP points to gprs.
116 "popal\n\t" // Load all registers except ESP and EIP with values in gprs.
H A Dcontext_x86.h40 SetGPR(ESP, new_sp);
/art/compiler/utils/x86/
H A Dassembler_x86_test.cc64 new x86::Register(x86::ESP),
193 GetAssembler()->filds(x86::Address(x86::Register(x86::ESP), 4));
194 GetAssembler()->fildl(x86::Address(x86::Register(x86::ESP), 12));
196 "fildl 0x4(%ESP)\n"
197 "fildll 0xc(%ESP)\n";
202 GetAssembler()->fistps(x86::Address(x86::Register(x86::ESP), 16));
203 GetAssembler()->fistpl(x86::Address(x86::Register(x86::ESP), 24));
205 "fistpl 0x10(%ESP)\n"
206 "fistpll 0x18(%ESP)\n";
360 GetAssembler()->addl(x86::EDI, x86::Address(x86::ESP,
[all...]
H A Dassembler_x86.h164 CHECK_EQ(base_in, ESP);
165 Init(ESP, disp.Int32Value());
173 CHECK_NE(index_in, ESP); // Illegal addressing mode.
174 SetModRM(0, ESP);
208 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
211 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
215 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_i
[all...]
H A Dassembler_x86.cc1767 movsd(dst, Address(ESP, 0));
1768 addl(ESP, Immediate(2 * sizeof(int32_t)));
1946 addl(ESP, Immediate(-adjust));
1956 movl(Address(ESP, offset), spill.AsX86().AsCpuRegister());
1960 movsd(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister());
1963 movss(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister());
1974 addl(ESP, Immediate(adjust));
1990 addl(ESP, Immediate(-adjust));
1996 addl(ESP, Immediate(adjust));
2006 movl(Address(ESP, off
2060 fs()->movl(Address::Absolute(thr_offs), ESP); local
[all...]
H A Dmanaged_register_x86.h94 CHECK_LT(AsCpuRegister(), ESP); // ESP, EBP, ESI and EDI cannot be encoded as byte registers. local
/art/compiler/optimizing/
H A Dcode_generator_x86.cc742 __ movl(Address(ESP, stack_index), static_cast<Register>(reg_id));
747 __ movl(static_cast<Register>(reg_id), Address(ESP, stack_index));
752 __ movsd(Address(ESP, stack_index), XmmRegister(reg_id));
757 __ movsd(XmmRegister(reg_id), Address(ESP, stack_index));
817 blocked_core_registers_[ESP] = true;
850 __ testl(EAX, Address(ESP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kX86))));
868 __ subl(ESP, Immediate(adjust));
870 __ movl(Address(ESP, kCurrentMethodStackOffset), kMethodRegisterArgument);
877 __ addl(ESP, Immediate(adjust));
994 __ movl(destination.AsRegister<Register>(), Address(ESP, sourc
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H A Dintrinsics_x86.cc295 __ subl(ESP, Immediate(8));
298 __ andpd(output.AsFpuRegister<XmmRegister>(), Address(ESP, 0));
300 __ subl(ESP, Immediate(12));
302 __ andps(output.AsFpuRegister<XmmRegister>(), Address(ESP, 0));
304 __ addl(ESP, Immediate(16));
481 __ movsd(out, Address(ESP, 0));
482 __ addl(ESP, Immediate(8));
485 __ movss(out, Address(ESP, 0));
486 __ addl(ESP, Immediate(4));
861 __ subl(ESP, Immediat
[all...]
H A Dcode_generator_x86.h542 assembler_.lock()->addl(Address(ESP, 0), Immediate(0));

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