Searched refs:FpuRegister (Results 1 - 10 of 10) sorted by relevance

/art/compiler/utils/mips64/
H A Dassembler_mips64.h233 void Bc1eqz(FpuRegister ft, uint16_t imm16);
234 void Bc1nez(FpuRegister ft, uint16_t imm16);
236 void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
237 void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
238 void MulS(FpuRegister fd, FpuRegister f
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H A Dassembler_mips64.cc156 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
170 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) {
626 void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) {
630 void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) {
689 Bc1eqz(static_cast<FpuRegister>(rs), imm16_21);
693 Bc1nez(static_cast<FpuRegister>(rs), imm16_21);
701 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister f
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H A Dmanaged_register_mips64.h37 // Register) or a double precision FP register (enum FpuRegister)
47 FpuRegister AsFpuRegister() const {
49 return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds);
75 static Mips64ManagedRegister FromFpuRegister(FpuRegister r) {
H A Dassembler_mips64_test.cc39 mips64::FpuRegister,
44 mips64::FpuRegister,
147 fp_registers_.push_back(new mips64::FpuRegister(mips64::F0));
148 fp_registers_.push_back(new mips64::FpuRegister(mips64::F1));
149 fp_registers_.push_back(new mips64::FpuRegister(mips64::F2));
150 fp_registers_.push_back(new mips64::FpuRegister(mips64::F3));
151 fp_registers_.push_back(new mips64::FpuRegister(mips64::F4));
152 fp_registers_.push_back(new mips64::FpuRegister(mips64::F5));
153 fp_registers_.push_back(new mips64::FpuRegister(mips64::F6));
154 fp_registers_.push_back(new mips64::FpuRegister(mips6
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/art/runtime/arch/mips64/
H A Dregisters_mips64.cc40 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs) {
44 os << "FpuRegister[" << static_cast<int>(rhs) << "]";
H A Dregisters_mips64.h71 enum FpuRegister { enum in namespace:art::mips64
108 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs);
/art/compiler/optimizing/
H A Dintrinsics_mips64.cc64 FpuRegister trg_reg = trg.AsFpuRegister<FpuRegister>();
150 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
188 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
389 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
390 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
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H A Dcode_generator_mips64.cc514 static dwarf::Reg DWARFReg(FpuRegister reg) {
562 FpuRegister reg = kFpuCalleeSaves[i];
599 FpuRegister reg = kFpuCalleeSaves[i];
668 destination.AsFpuRegister<FpuRegister>(),
700 __ Mtc1(gpr, destination.AsFpuRegister<FpuRegister>());
702 __ Dmtc1(gpr, destination.AsFpuRegister<FpuRegister>());
711 __ Dmtc1(source.AsRegister<GpuRegister>(), destination.AsFpuRegister<FpuRegister>());
713 __ Mtc1(source.AsRegister<GpuRegister>(), destination.AsFpuRegister<FpuRegister>());
720 __ MovS(destination.AsFpuRegister<FpuRegister>(), source.AsFpuRegister<FpuRegister>());
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H A Dcode_generator_mips64.h36 static constexpr FpuRegister kParameterFpuRegisters[] =
48 static constexpr FpuRegister kRuntimeParameterFpuRegisters[] =
56 static constexpr FpuRegister kFpuCalleeSaves[] =
62 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
90 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
/art/compiler/jni/quick/mips64/
H A Dcalling_convention_mips64.cc30 static const FpuRegister kFpuArgumentRegisters[] = {
105 FpuRegister arg = kFpuArgumentRegisters[reg_index];

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