| /art/runtime/arch/mips/ |
| H A D | registers_mips.cc | 31 if (rhs >= ZERO && rhs <= RA) {
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| H A D | registers_mips.h | 61 RA = 31, // Return address. enumerator in enum:art::mips::Register
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| H A D | quick_method_frame_info_mips.h | 29 (1 << art::mips::RA);
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| H A D | quick_entrypoints_mips.S | 332 // Save callee general purpose registers, RA and GP.
423 sw $ra, 0($t0) # Store RA per the compiler ABI
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 61 RA = 31, // Return address. enumerator in enum:art::mips64::GpuRegister
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| H A D | quick_method_frame_info_mips64.h | 53 (type == Runtime::kSaveAll ? kMips64CalleeSaveAllSpills : 0) | (1 << art::mips64::RA);
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| H A D | quick_entrypoints_mips64.S | 376 // Save callee general purpose registers, SP, T8(GP), RA, A3, and A4 (8x14 bytes)
465 sw $ra, 0($t0) # Store low half of RA per compiler ABI
467 sw $t1, 4($t0) # Store high half of RA per compiler ABI
473 // a1 = args length in bytes (does not include 8 bytes for RA)
1834 jal artInstrumentationMethodEntryFromCode # (Method*, Object*, Thread*, RA)
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA;
152 // ArtMethod*, RA and callee save area size, local reference segment state
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA;
186 // ArtMethod*, RA and callee save area size, local reference segment state
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 595 Jalr(RA, rs);
2052 Addiu(lhs, RA, offset);
2060 // NAL clobbers the RA register. However, RA must be preserved if the
2062 // of preserving RA (typically, leaf methods don't preserve RA explicitly).
2063 // So, we need to preserve RA in some temporary storage ourselves. The AT
2065 // which will be added to the value that NAL stores in RA. And we can't
2068 // If we were to add a 32-bit constant to RA using two ADDIU instructions,
2074 // For now simply use the stack for RA
[all...] |
| H A D | assembler_mips_test.cc | 88 registers_.push_back(new mips::Register(mips::RA));
121 secondary_register_names_.emplace(mips::Register(mips::RA), "ra");
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| H A D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| H A D | code_generator_mips64.cc | 422 // Save RA (containing the return address) to mimic Quick.
423 AddAllocatedRegister(Location::RegisterLocation(RA));
620 __ Jr(RA);
895 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
901 blocked_core_registers_[RA] = true;
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| H A D | code_generator_mips.cc | 476 // Save RA (containing the return address) to mimic Quick.
477 AddAllocatedRegister(Location::RegisterLocation(RA));
796 __ Jr(RA);
996 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
1002 blocked_core_registers_[RA] = true;
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 526 Jalr(RA, rs);
1991 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset);
1992 cfi_.RelOffset(DWARFReg(RA), stack_offset);
2038 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset);
2039 cfi_.Restore(DWARFReg(RA));
2045 Jr(RA);
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| H A D | assembler_mips64_test.cc | 112 registers_.push_back(new mips64::GpuRegister(mips64::RA));
145 secondary_register_names_.emplace(mips64::GpuRegister(mips64::RA), "ra");
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