/art/runtime/arch/arm/ |
H A D | registers_arm.cc | 38 if (rhs >= S0 && rhs < kNumberOfSRegisters) {
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H A D | registers_arm.h | 57 S0 = 0, enumerator in enum:art::arm::SRegister
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H A D | context_arm.cc | 81 fprs_[S0] = nullptr;
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H A D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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/art/runtime/arch/arm64/ |
H A D | registers_arm64.cc | 66 if (rhs >= S0 && rhs < kNumberOfSRegisters) {
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H A D | registers_arm64.h | 153 S0 = 0, enumerator in enum:art::arm64::SRegister
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/art/compiler/utils/arm/ |
H A D | managed_register_arm_test.cc | 69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); 76 EXPECT_EQ(S0, reg.AsSRegister()); 134 EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow()); 136 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S0))); 294 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromSRegister(S0))); 302 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromSRegister(S0))); 310 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S0))); 320 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S0))); 326 ArmManagedRegister reg_S0 = ArmManagedRegister::FromSRegister(S0); 330 EXPECT_TRUE(reg_S0.Equals(ArmManagedRegister::FromSRegister(S0))); [all...] |
H A D | assembler_arm32.cc | 339 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 356 sd, S0, S0); 451 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); 461 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); 471 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 490 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 500 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); 510 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); 520 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, s [all...] |
H A D | assembler_thumb2.cc | 934 sd, S0, S0); 957 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 1039 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); 1049 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); 1059 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 1078 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 1088 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); 1098 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); 1108 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, s [all...] |
H A D | assembler_arm.cc | 51 if (rhs >= S0 && rhs < kNumberOfSRegisters) {
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/art/compiler/utils/arm64/ |
H A D | managed_register_arm64_test.cc | 169 Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0); 177 EXPECT_EQ(S0, reg.AsOverlappingSRegister()); 219 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); 227 EXPECT_EQ(S0, reg.AsSRegister()); 229 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); 276 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); 283 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromSRegister(S0))); 292 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S0))); 299 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0))); 308 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S0))); [all...] |
/art/runtime/arch/mips/ |
H A D | registers_mips.h | 46 S0 = 16, // Saved values. enumerator in enum:art::mips::Register
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H A D | quick_method_frame_info_mips.h | 36 (1 << art::mips::S0) | (1 << art::mips::S1);
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/art/runtime/arch/mips64/ |
H A D | registers_mips64.h | 46 S0 = 16, // Saved values. enumerator in enum:art::mips64::GpuRegister
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H A D | quick_method_frame_info_mips64.h | 37 (1 << art::mips64::S0) | (1 << art::mips64::S1);
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/art/compiler/jni/quick/arm/ |
H A D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 73 return ArmManagedRegister::FromSRegister(S0); 145 uint32_t fpr_index = 0; // S0 ~ S15.
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/art/compiler/jni/quick/arm64/ |
H A D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7 56 return Arm64ManagedRegister::FromSRegister(S0); 113 int fp_reg_index = 0; // D0/S0.
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/art/compiler/optimizing/ |
H A D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 }; 48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 }; 124 ? Location::FpuRegisterPairLocation(S0, S1) 125 : Location::FpuRegisterLocation(S0);
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H A D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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H A D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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H A D | code_generator_arm.cc | 921 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); 1045 return Location::FpuRegisterLocation(S0); 1053 return Location::FpuRegisterPairLocation(S0, S1); 3002 locations->SetOut(Location::FpuRegisterLocation(S0)); 3012 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1));
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H A D | code_generator_mips64.cc | 911 blocked_core_registers_[S0] = true;
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/art/compiler/utils/ |
H A D | assembler_thumb_test.cc | 985 __ vadds(S0, S1, S2); 986 __ vsubs(S0, S1, S2); 987 __ vmuls(S0, S1, S2); 988 __ vmlas(S0, S1, S2); 989 __ vmlss(S0, S1, S2); 990 __ vdivs(S0, S1, S2); 991 __ vabss(S0, S1); 992 __ vnegs(S0, S1); 993 __ vsqrts(S0, S1); 1028 __ vcmps(S0, S [all...] |
/art/compiler/utils/mips/ |
H A D | assembler_mips_test.cc | 73 registers_.push_back(new mips::Register(mips::S0)); 106 secondary_register_names_.emplace(mips::Register(mips::S0), "s0");
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/art/compiler/utils/mips64/ |
H A D | assembler_mips64_test.cc | 97 registers_.push_back(new mips64::GpuRegister(mips64::S0)); 130 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S0), "s0");
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