| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 47 S1 = 17, enumerator in enum:art::mips::Register
62 TR = S1, // ART Thread Register
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| H A D | quick_method_frame_info_mips.h | 36 (1 << art::mips::S0) | (1 << art::mips::S1);
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 47 S1 = 17, enumerator in enum:art::mips64::GpuRegister
62 TR = S1, // ART Thread Register
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| H A D | quick_method_frame_info_mips64.h | 37 (1 << art::mips64::S0) | (1 << art::mips64::S1);
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| /art/runtime/arch/arm/ |
| H A D | registers_arm.h | 58 S1 = 1, enumerator in enum:art::arm::SRegister
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| H A D | context_arm.cc | 82 fprs_[S1] = nullptr;
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| H A D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/compiler/utils/arm/ |
| H A D | managed_register_arm_test.cc | 78 reg = ArmManagedRegister::FromSRegister(S1);
85 EXPECT_EQ(S1, reg.AsSRegister());
135 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh());
312 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1)));
322 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1)));
331 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1)));
336 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1);
341 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1)));
465 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
487 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
[all...] |
| /art/compiler/utils/arm64/ |
| H A D | managed_register_arm64_test.cc | 181 sreg = Arm64ManagedRegister::FromSRegister(S1);
189 EXPECT_EQ(S1, reg.AsOverlappingSRegister());
294 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1)));
310 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1)));
320 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1)));
328 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1)));
332 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1);
338 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1)));
387 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
409 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
[all...] |
| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.h | 154 S1 = 1, enumerator in enum:art::arm64::SRegister
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| /art/compiler/trampolines/ |
| H A D | trampoline_compiler.cc | 133 case kQuickAbi: // S1 holds Thread*.
134 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value());
166 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value());
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| /art/compiler/optimizing/ |
| H A D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
124 ? Location::FpuRegisterPairLocation(S0, S1)
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| H A D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| H A D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| H A D | code_generator_arm.cc | 1053 return Location::FpuRegisterPairLocation(S0, S1);
3012 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1));
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| /art/compiler/utils/ |
| H A D | assembler_thumb_test.cc | 974 __ vmovs(S1, 1.0);
977 __ vmovs(S1, S2);
985 __ vadds(S0, S1, S2);
986 __ vsubs(S0, S1, S2);
987 __ vmuls(S0, S1, S2);
988 __ vmlas(S0, S1, S2);
989 __ vmlss(S0, S1, S2);
990 __ vdivs(S0, S1, S2);
991 __ vabss(S0, S1);
992 __ vnegs(S0, S1);
[all...] |
| /art/compiler/jni/quick/arm/ |
| H A D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/jni/quick/arm64/ |
| H A D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 2579 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value());
2589 S1, thr_offs.Int32Value());
2593 StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value());
2611 return EmitLoad(mdest, S1, src.Int32Value(), size);
2642 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value());
2699 S1, thr_offs.Int32Value());
2712 S1, thr_offs.Int32Value());
2884 Move(tr.AsMips().AsCoreRegister(), S1);
2889 StoreToOffset(kStoreWord, S1, SP, offset.Int32Value());
2896 S1, Threa
[all...] |
| H A D | assembler_mips_test.cc | 74 registers_.push_back(new mips::Register(mips::S1));
107 secondary_register_names_.emplace(mips::Register(mips::S1), "s1");
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 2118 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());
2122 StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value());
2141 return EmitLoad(mdest, S1, src.Int32Value(), size);
2177 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value());
2223 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());
2235 S1, thr_offs.Int32Value());
2437 Move(tr.AsMips64().AsGpuRegister(), S1);
2442 StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value());
2450 S1,
2467 S1,
[all...] |
| H A D | assembler_mips64_test.cc | 98 registers_.push_back(new mips64::GpuRegister(mips64::S1));
131 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1");
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