| /art/runtime/arch/arm/ |
| H A D | registers_arm.h | 60 S3 = 3, enumerator in enum:art::arm::SRegister
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| H A D | context_arm.cc | 84 fprs_[S3] = nullptr;
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| H A D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 49 S3 = 19, enumerator in enum:art::mips::Register
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| H A D | quick_method_frame_info_mips.h | 31 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 49 S3 = 19, enumerator in enum:art::mips64::GpuRegister
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| H A D | quick_method_frame_info_mips64.h | 29 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 130 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S3));
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA;
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| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.h | 156 S3 = 3, enumerator in enum:art::arm64::SRegister
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 166 callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(S3));
177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA;
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| /art/compiler/jni/quick/arm/ |
| H A D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/jni/quick/arm64/ |
| H A D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/optimizing/ |
| H A D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
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| H A D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| H A D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| /art/compiler/utils/arm/ |
| H A D | managed_register_arm_test.cc | 87 reg = ArmManagedRegister::FromSRegister(S3);
94 EXPECT_EQ(S3, reg.AsSRegister());
147 EXPECT_EQ(S3, reg.AsOverlappingDRegisterHigh());
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| H A D | assembler_thumb2_test.cc | 890 __ LoadLiteral(arm::S3, literal);
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 76 registers_.push_back(new mips::Register(mips::S3));
109 secondary_register_names_.emplace(mips::Register(mips::S3), "s3");
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 100 registers_.push_back(new mips64::GpuRegister(mips64::S3));
133 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S3), "s3");
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| /art/compiler/utils/arm64/ |
| H A D | managed_register_arm64_test.cc | 708 EXPECT_TRUE(vixl::s3.Is(Arm64Assembler::reg_s(S3)));
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