| /art/runtime/arch/arm/ |
| H A D | registers_arm.h | 62 S5 = 5, enumerator in enum:art::arm::SRegister
|
| H A D | context_arm.cc | 86 fprs_[S5] = nullptr;
|
| H A D | quick_method_frame_info_arm.h | 42 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
|
| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 51 S5 = 21, enumerator in enum:art::mips::Register
|
| H A D | quick_method_frame_info_mips.h | 31 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
|
| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 51 S5 = 21, enumerator in enum:art::mips64::GpuRegister
|
| H A D | quick_method_frame_info_mips64.h | 30 (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) |
|
| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 132 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S5));
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA;
|
| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.h | 158 S5 = 5, enumerator in enum:art::arm64::SRegister
|
| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 168 callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(S5));
177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA;
|
| /art/compiler/jni/quick/arm/ |
| H A D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
|
| /art/compiler/jni/quick/arm64/ |
| H A D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
|
| /art/compiler/optimizing/ |
| H A D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
|
| H A D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
|
| H A D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
|
| /art/compiler/utils/arm64/ |
| H A D | managed_register_arm64_test.cc | 231 reg = Arm64ManagedRegister::FromSRegister(S5);
239 EXPECT_EQ(S5, reg.AsSRegister());
241 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5)));
710 EXPECT_TRUE(vixl::s5.Is(Arm64Assembler::reg_s(S5)));
|
| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 78 registers_.push_back(new mips::Register(mips::S5));
111 secondary_register_names_.emplace(mips::Register(mips::S5), "s5");
|
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 102 registers_.push_back(new mips64::GpuRegister(mips64::S5));
135 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S5), "s5");
|