| /art/compiler/trampolines/ |
| H A D | trampoline_compiler.cc | 127 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value());
130 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value());
131 __ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value());
134 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value());
136 __ Jr(T9);
159 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value());
162 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value());
163 __ LoadFromOffset(kLoadDoubleword, T9, T9, offse
[all...] |
| /art/runtime/arch/mips/ |
| H A D | context_mips.cc | 31 gprs_[T9] = &t9_;
35 t9_ = MipsContext::kBadGprBase + T9;
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| H A D | registers_mips.h | 55 T9 = 25, enumerator in enum:art::mips::Register
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| H A D | context_mips.h | 44 SetGPR(T9, new_pc);
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 55 T9 = 25, enumerator in enum:art::mips64::GpuRegister
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| H A D | context_mips64.cc | 31 gprs_[T9] = &t9_;
35 t9_ = Mips64Context::kBadGprBase + T9;
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| H A D | context_mips64.h | 44 SetGPR(T9, new_pc);
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 36 return Mips64ManagedRegister::FromGpuRegister(T9);
40 return Mips64ManagedRegister::FromGpuRegister(T9);
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 32 return MipsManagedRegister::FromCoreRegister(T9);
36 return MipsManagedRegister::FromCoreRegister(T9);
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| /art/compiler/optimizing/ |
| H A D | intrinsics_mips64.cc | 1359 T9,
1362 __ Jalr(T9);
1509 T9,
1513 __ Jalr(T9);
1586 T9,
1591 __ Jalr(T9);
1620 T9,
1625 __ Jalr(T9);
1651 T9,
1656 __ Jalr(T9);
[all...] |
| H A D | code_generator_mips64.cc | 531 // TODO: anything related to T9/GP/GOT/PIC/.so's?
583 // TODO: anything related to T9/GP/GOT/PIC/.so's?
914 // Reserve T9 for function calls
915 blocked_core_registers_[T9] = true;
972 // TODO: anything related to T9/GP/GOT/PIC/.so's?
973 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset);
974 __ Jalr(T9);
2958 // T9 = temp->GetEntryPoint();
2959 __ LoadFromOffset(kLoadDoubleword, T9, temp, entry_point.Int32Value());
2960 // T9();
[all...] |
| H A D | intrinsics_mips.cc | 1948 T9,
1952 __ Jalr(T9);
2107 T9,
2110 __ Jalr(T9);
2193 T9,
2196 __ Jalr(T9);
2226 T9,
2229 __ Jalr(T9);
2255 T9,
2258 __ Jalr(T9);
[all...] |
| H A D | code_generator_mips.cc | 1014 // Reserve T9 for function calls
1015 blocked_core_registers_[T9] = true;
1082 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset);
1083 __ Jalr(T9);
3756 // T9 = temp->GetEntryPoint();
3757 __ LoadFromOffset(kLoadWord, T9, temp, entry_point.Int32Value());
3758 // T9();
3759 __ Jalr(T9);
3889 __ Jalr(&frame_entry_label_, T9);
3893 __ LoadConst32(T9, invok
[all...] |
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 106 registers_.push_back(new mips64::GpuRegister(mips64::T9));
139 secondary_register_names_.emplace(mips64::GpuRegister(mips64::T9), "t9");
581 __ Jialc(&label1, mips64::T9);
587 __ Jialc(&label2, mips64::T9);
593 __ Jialc(&label1, mips64::T9);
612 __ Jialc(&label1, mips64::T9);
618 __ Jialc(&label2, mips64::T9);
624 __ Jialc(&label1, mips64::T9);
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| H A D | assembler_mips64.cc | 2466 T9,
2469 Jr(T9);
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 82 registers_.push_back(new mips::Register(mips::T9));
115 secondary_register_names_.emplace(mips::Register(mips::T9), "t9");
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| H A D | assembler_mips.cc | 2066 // use T9 for this in the context of the JNI compiler, which uses it
2913 LoadFromOffset(kLoadWord, T9, S1,
2915 Jr(T9);
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