Searched refs:TMP2 (Results 1 - 3 of 3) sorted by relevance
| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 64 TMP2 = T3, // scratch register (in addition to AT, reserved for assembler) enumerator in enum:art::mips64::GpuRegister
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 1839 Lwu(TMP2, base, offset + kMips64WordSize);
1840 Dinsu(reg, TMP2, 32, 32);
1868 Lw(TMP2, base, offset + kMips64WordSize);
1869 Mthc1(TMP2, reg);
1932 Dsrl32(TMP2, reg, 0);
1933 Sw(TMP2, base, offset + kMips64WordSize);
1962 Mfhc1(TMP2, reg);
1964 Sw(TMP2, base, offset + kMips64WordSize);
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 903 // AT, TMP(T8) and TMP2(T3) are used as temporary/scratch
907 blocked_core_registers_[TMP2] = true;
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