| /art/disassembler/ |
| H A D | disassembler_arm64.cc | 34 TR = 19, enumerator in enum:art::arm64::__anon25
46 if (reg.code() == TR) {
101 if (instr->Rn() == TR) {
|
| H A D | disassembler_arm.cc | 1418 if (Rn.r == TR && is_load) {
|
| /art/runtime/arch/arm/ |
| H A D | registers_arm.h | 43 TR = 9, // thread register enumerator in enum:art::arm::Register
|
| H A D | context_arm.cc | 110 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
|
| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 62 TR = S1, // ART Thread Register enumerator in enum:art::mips::Register
|
| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 62 TR = S1, // ART Thread Register enumerator in enum:art::mips64::GpuRegister
|
| /art/cmdline/detail/ |
| H A D | cmdline_parser_detail.h | 54 template <typename TL, typename TR>
55 static std::true_type EqualityOperatorTest(const TL& left, const TR& right,
|
| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 56 ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(TR));
60 StoreToOffset(TR, SP, offset.Int32Value());
172 StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value());
181 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
188 ___ Str(temp, MEM_OP(reg_x(TR), tr_offs.Int32Value()));
289 return Load(m_dst.AsArm64(), TR, src.Int32Value(), size);
324 LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value());
362 LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
372 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
615 LoadFromOffset(scratch.AsXRegister(), TR, Threa
[all...] |
| H A D | managed_register_arm64_test.cc | 626 EXPECT_TRUE(vixl::x19.Is(Arm64Assembler::reg_x(TR)));
|
| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.h | 63 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) enumerator in enum:art::arm64::XRegister
|
| H A D | context_arm64.cc | 139 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]);
|
| /art/compiler/utils/arm/ |
| H A D | assembler_arm.cc | 575 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value());
603 return EmitLoad(this, m_dst, TR, src.Int32Value(), size);
609 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
618 TR, thr_offs.Int32Value());
631 TR, thr_offs.Int32Value());
641 TR, thr_offs.Int32Value());
645 StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
838 mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR));
843 StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL);
851 TR, Threa
[all...] |
| /art/compiler/optimizing/ |
| H A D | intrinsics_mips64.cc | 919 TR,
1360 TR,
1510 TR,
1587 TR,
1621 TR,
1652 TR,
|
| H A D | intrinsics_arm.cc | 496 TR,
1012 kLoadWord, LR, TR, QUICK_ENTRYPOINT_OFFSET(kArmWordSize, pStringCompareTo).Int32Value());
1152 __ LoadFromOffset(kLoadWord, LR, TR,
1226 kLoadWord, LR, TR, QUICK_ENTRYPOINT_OFFSET(kArmWordSize, pAllocStringFromBytes).Int32Value());
1254 kLoadWord, LR, TR, QUICK_ENTRYPOINT_OFFSET(kArmWordSize, pAllocStringFromChars).Int32Value());
1280 LR, TR, QUICK_ENTRYPOINT_OFFSET(kArmWordSize, pAllocStringFromString).Int32Value());
1671 __ LoadFromOffset(kLoadWord, LR, TR, GetThreadOffset<kArmWordSize>(entry).Int32Value());
1697 __ LoadFromOffset(kLoadWord, LR, TR, GetThreadOffset<kArmWordSize>(entry).Int32Value());
|
| H A D | code_generator_mips64.cc | 884 TR,
912 blocked_core_registers_[TR] = true;
973 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset);
1000 TR,
3057 TR,
3252 __ LoadFromOffset(kLoadUnsignedWord, out, TR, GetExceptionTlsOffset());
3260 __ StoreToOffset(kStoreWord, ZERO, TR, GetExceptionTlsOffset());
3467 __ LoadFromOffset(kLoadDoubleword, temp, TR, QUICK_ENTRY_POINT(pNewEmptyString));
|
| H A D | intrinsics_mips.cc | 1473 TR,
1949 TR,
2108 TR,
2194 TR,
2227 TR,
2256 TR,
|
| H A D | code_generator_mips.cc | 984 TR,
1012 blocked_core_registers_[TR] = true;
1082 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset);
1118 TR,
3842 TR,
4033 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset());
4041 __ StoreToOffset(kStoreWord, ZERO, TR, GetExceptionTlsOffset());
4301 __ LoadFromOffset(kLoadWord, temp, TR, QUICK_ENTRY_POINT(pNewEmptyString));
|
| H A D | code_generator_arm.cc | 837 blocked_core_registers_[TR] = true;
1204 __ LoadFromOffset(kLoadWord, LR, TR, entry_point_offset);
3501 __ LoadFromOffset(kLoadWord, temp, TR, QUICK_ENTRY_POINT(pNewEmptyString));
4788 __ LoadFromOffset(kLoadWord, card, TR, Thread::CardTableOffset<kArmWordSize>().Int32Value());
4839 kLoadUnsignedHalfword, IP, TR, Thread::ThreadFlagsOffset<kArmWordSize>().Int32Value());
5311 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset());
5320 __ StoreToOffset(kStoreWord, IP, TR, GetExceptionTlsOffset());
6055 kLoadWord, IP, TR, Thread::IsGcMarkingOffset<kArmWordSize>().Int32Value());
6340 __ LoadFromOffset(kLoadWord, temp.AsRegister<Register>(), TR, invoke->GetStringInitOffset());
|
| /art/compiler/trampolines/ |
| H A D | trampoline_compiler.cc | 102 __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()),
|