Searched refs:V0 (Results 1 - 14 of 14) sorted by relevance
| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 32 V0 = 2, // Values. enumerator in enum:art::mips::Register
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| H A D | context_mips.cc | 73 gprs_[V0] = const_cast<uint32_t*>(&gZero);
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| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 32 V0 = 2, // Values. enumerator in enum:art::mips64::GpuRegister
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| H A D | context_mips64.cc | 73 gprs_[V0] = const_cast<uintptr_t*>(&gZero);
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| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 49 return Mips64ManagedRegister::FromGpuRegister(V0);
62 return Mips64ManagedRegister::FromGpuRegister(V0);
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 49 return MipsManagedRegister::FromCoreRegister(V0);
62 return MipsManagedRegister::FromCoreRegister(V0);
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips.h | 117 ? Location::RegisterPairLocation(V0, V1)
118 : Location::RegisterLocation(V0);
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| H A D | code_generator_mips64.h | 116 return Location::RegisterLocation(V0);
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| H A D | intrinsics_mips64.cc | 60 if (trg_reg != V0) {
61 __ Move(V0, trg_reg);
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| H A D | code_generator_mips.cc | 50 return Location::RegisterLocation(V0);
53 return Location::RegisterPairLocation(V0, V1);
644 // Else, spill V0 (arbitrary choice) and use it as a scratch register (it will be
646 ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters());
647 // If V0 spills onto the stack, SP-relative offsets need to be adjusted.
3973 Location::RegisterLocation(V0));
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| H A D | intrinsics_mips.cc | 72 if (trg_reg != V0) {
73 __ Move(V0, trg_reg);
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| H A D | code_generator_mips64.cc | 49 return Location::RegisterLocation(V0);
490 // Else, spill V0 (arbitrary choice) and use it as a scratch register (it will be
492 ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters());
493 // If V0 spills onto the stack, SP-relative offsets need to be adjusted.
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 59 registers_.push_back(new mips::Register(mips::V0));
92 secondary_register_names_.emplace(mips::Register(mips::V0), "v0");
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 83 registers_.push_back(new mips64::GpuRegister(mips64::V0));
116 secondary_register_names_.emplace(mips64::GpuRegister(mips64::V0), "v0");
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