Searched refs:ATOMIC_LOAD_SUB (Results 1 - 13 of 13) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h720 ATOMIC_LOAD_SUB, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAGNodes.h1200 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1319 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp68 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
H A DLegalizeIntegerTypes.cpp138 case ISD::ATOMIC_LOAD_SUB:
1333 case ISD::ATOMIC_LOAD_SUB:
H A DSelectionDAG.cpp492 case ISD::ATOMIC_LOAD_SUB:
4891 Opcode == ISD::ATOMIC_LOAD_SUB ||
H A DLegalizeDAG.cpp3987 case ISD::ATOMIC_LOAD_SUB:
H A DSelectionDAGBuilder.cpp3514 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
/external/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp678 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp278 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
2121 case ISD::ATOMIC_LOAD_SUB:
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp175 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
177 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
208 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
3128 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
4365 case ISD::ATOMIC_LOAD_SUB:
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp480 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
20060 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
20361 case ISD::ATOMIC_LOAD_SUB:
[all...]
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp862 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);

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