| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 301 auto &HRI = *HST.getRegisterInfo(); local
332 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
397 auto &HRI = *HST.getRegisterInfo(); local
407 insertCSRSpillsInBlock(*PrologB, CSI, HRI);
411 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
416 insertCSRRestoresInBlock(B, CSI, HRI);
430 auto &HRI = *HST.getRegisterInfo(); local
449 unsigned SP = HRI.getStackRegister();
483 unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
509 auto &HRI local
618 auto &HRI = *HST.getRegisterInfo(); local
713 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); local
831 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); local
1047 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI) argument
1155 auto &HRI = *HST.getRegisterInfo(); local
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| H A D | HexagonFrameLowering.h | 89 const HexagonRegisterInfo &HRI) const;
91 const HexagonRegisterInfo &HRI) const;
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| H A D | HexagonGenMux.cpp | 42 HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) {
55 const HexagonRegisterInfo *HRI; member in class:__anon12606::HexagonGenMux
105 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
144 unsigned NR = HRI->getNumRegs();
309 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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| H A D | HexagonVLIWPacketizer.cpp | 87 const HexagonRegisterInfo *HRI; member in class:__anon12620::HexagonPacketizer
108 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
175 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
268 if (DepReg == HRI->getRARegister())
272 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
276 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg);
538 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
588 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
600 predRegClass = HRI
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| H A D | HexagonInstrInfo.cpp | 113 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { argument
114 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
115 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
599 auto &HRI = getRegisterInfo(); local
660 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
662 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
684 HRI.getSubReg(DestReg, Hexagon::subreg_hireg)).
685 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
688 HRI.getSubReg(DestReg, Hexagon::subreg_loreg)).
689 addReg(HRI
768 const HexagonRegisterInfo &HRI = getRegisterInfo(); local
1105 auto &HRI = getRegisterInfo(); local
3173 auto &HRI = getRegisterInfo(); local
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| H A D | HexagonVLIWPacketizer.h | 41 const HexagonRegisterInfo *HRI; member in class:llvm::HexagonPacketizerList
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| H A D | HexagonGenInsert.cpp | 469 HexagonGenInsert() : MachineFunctionPass(ID), HII(0), HRI(0) {
525 const HexagonRegisterInfo *HRI;
544 dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
547 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
548 << PrintRegSet(LL[i].second, HRI) << '\n';
762 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI)
763 << " AVs: " << PrintORL(AVs, HRI) << "\n";
826 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
831 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
879 dbgs() << PrintReg(VR, HRI) << "
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| H A D | HexagonBitSimplify.cpp | 2179 auto &HRI = *HST.getRegisterInfo();
2188 const HexagonEvaluator HE(HRI, MRI, HII, MF);
2208 CopyPropagation CopyP(HRI, MRI);
2302 HII(0), HRI(0), MRI(0), BTP(0) {
2310 const HexagonRegisterInfo *HRI;
2548 dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi("
2549 << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
2550 << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
2670 << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
2671 << " out: " << PrintReg(G.Out.Reg, HRI,
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| H A D | HexagonISelLowering.cpp | 712 auto &HRI = *Subtarget.getRegisterInfo(); local
714 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
1402 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); local
1422 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1428 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); local
1436 HRI.getFrameRegister(), VT);
1519 auto &HRI = *Subtarget.getRegisterInfo(); local
1528 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1891 computeRegisterProperties(&HRI);
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| H A D | HexagonISelDAGToDAG.cpp | 54 const HexagonRegisterInfo *HRI; member in class:__anon12610::HexagonDAGToDAGISel
59 HRI(nullptr) {
67 HRI = HST->getRegisterInfo();
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