Searched refs:INSERT_SUBVECTOR (Results 1 - 12 of 12) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h285 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
291 INSERT_SUBVECTOR, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h747 ISD::INSERT_SUBVECTOR, 0),
749 ISD::INSERT_SUBVECTOR, 0),
751 ISD::INSERT_SUBVECTOR, 0),
753 ISD::INSERT_SUBVECTOR, 0),
755 ISD::INSERT_SUBVECTOR, 0),
757 ISD::INSERT_SUBVECTOR, 0),
759 ISD::INSERT_SUBVECTOR, 0),
761 ISD::INSERT_SUBVECTOR, 0),
763 ISD::INSERT_SUBVECTOR, 0),
765 ISD::INSERT_SUBVECTOR,
[all...]
H A DX86ISelLowering.cpp702 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
1286 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1605 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1640 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1710 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1711 setOperationAction(ISD::INSERT_SUBVECTOR, MV
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp220 case ISD::INSERT_SUBVECTOR: return "insert_subvector";
H A DLegalizeVectorTypes.cpp601 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
3036 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
H A DDAGCombiner.cpp1442 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
13019 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
13088 case ISD::INSERT_SUBVECTOR: {
13113 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
H A DLegalizeDAG.cpp3197 case ISD::INSERT_SUBVECTOR:
H A DSelectionDAG.cpp3948 case ISD::INSERT_SUBVECTOR: {
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1768 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1795 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2584 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp214 case ISD::INSERT_SUBVECTOR:
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp423 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
H A DAArch64ISelLowering.cpp4807 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),

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