Searched refs:NewOpc (Results 1 - 25 of 33) sorted by relevance

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/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp345 unsigned NewOpc; local
348 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
349 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
350 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
351 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
352 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
353 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
354 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
355 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
356 case X86::VPCOMBri: NewOpc
379 unsigned NewOpc; local
410 unsigned NewOpc; local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1201 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local
1202 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1301 unsigned NewOpc; local
1303 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1305 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1309 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1311 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1326 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1335 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc
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H A DThumb2InstrInfo.cpp497 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
498 MI.setDesc(TII.get(NewOpc));
531 unsigned NewOpc = Opcode;
541 NewOpc = immediateOffsetOpcode(Opcode);
553 NewOpc = negativeOffsetOpcode(Opcode);
558 NewOpc = positiveOffsetOpcode(Opcode);
585 if (NewOpc != Opcode)
586 MI.setDesc(TII.get(NewOpc));
619 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
H A DARMConstantIslandPass.cpp1842 unsigned NewOpc = 0; local
1849 NewOpc = ARM::tLEApcrel;
1856 NewOpc = ARM::tLDRpci;
1863 if (!NewOpc)
1876 U.MI->setDesc(TII->get(NewOpc));
1901 unsigned NewOpc = 0; local
1907 NewOpc = ARM::tB;
1912 NewOpc = ARM::tBcc;
1918 if (NewOpc) {
1923 Br.MI->setDesc(TII->get(NewOpc));
[all...]
H A DARMExpandPseudoInsts.cpp848 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; local
849 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
887 unsigned NewOpc; local
889 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
890 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
891 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
892 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
895 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1131 unsigned NewOpc = ARM::VLDMDIA; local
1133 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1162 unsigned NewOpc = ARM::VSTMDIA; local
[all...]
H A DThumbRegisterInfo.cpp398 unsigned NewOpc = convertToNonSPOpcode(Opcode);
399 if (NewOpc != Opcode && FrameReg != ARM::SP)
400 MI.setDesc(TII.get(NewOpc));
H A DARMISelLowering.cpp2825 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local
2827 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2832 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm) local
2834 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2841 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu) local
2843 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2850 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) local
2852 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2855 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) local
2857 return DAG.getNode(NewOpc, SDLo
6360 unsigned NewOpc = 0; local
7909 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? local
7933 unsigned NewOpc; local
8184 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); local
9513 unsigned NewOpc = 0; local
9715 unsigned NewOpc = 0; local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h91 unsigned NewOpc) const;
H A DMipsSEISelLowering.h68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
H A DMipsInstrInfo.cpp278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
H A DMipsInstrInfo.h125 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
H A DMipsLongBranch.cpp219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); local
220 const MCInstrDesc &NewDesc = TII->get(NewOpc);
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp478 unsigned NewOpc; local
481 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
482 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
483 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
484 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
485 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
486 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
487 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
488 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
489 case X86::VMOVDQUYrr: NewOpc
503 unsigned NewOpc; local
[all...]
H A DX86InstrInfo.cpp5066 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5132 unsigned NewOpc; local
5134 NewOpc = GetCondBranchFromCond(NewCC);
5136 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5139 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5146 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5933 unsigned NewOpc = 0; local
5937 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5938 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5939 case X86::TEST32rr: NewOpc
6067 unsigned NewOpc = 0; local
6250 unsigned NewOpc; local
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/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp301 unsigned NewOpc = getTransformOpcode(OldOpc); local
302 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
356 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
H A DAArch64InstrInfo.cpp840 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); local
841 if (NewOpc == Opc)
843 const MCInstrDesc &MCID = get(NewOpc);
873 unsigned NewOpc = MI->getOpcode(); local
886 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break;
887 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break;
888 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break;
889 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break;
890 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break;
891 case AArch64::ADCXr: NewOpc
[all...]
H A DAArch64LoadStoreOptimizer.cpp591 unsigned NewOpc = getMatchingPairOpcode(Opc); local
632 TII->get(NewOpc))
726 TII->get(NewOpc))
737 TII->get(NewOpc))
1062 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode()) local
1067 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1075 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
/external/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp370 unsigned NewOpc = getPredForm(Opc); local
372 if (NewOpc == 0) {
375 NewOpc = Hexagon::C2_not;
378 NewOpc = TargetOpcode::COPY;
405 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
H A DHexagonBitSimplify.cpp2025 unsigned NewOpc = (W == 8) ? Hexagon::A2_zxtb
2046 auto MIB = BuildMI(B, MI, DL, HII.get(NewOpc), NewR)
2048 if (NewOpc == Hexagon::A2_andir)
2050 else if (NewOpc == Hexagon::S2_extractu)
2110 unsigned NewOpc = V.is(0) ? Hexagon::TFR_PdFalse : Hexagon::TFR_PdTrue;
2111 BuildMI(B, MI, DL, HII.get(NewOpc), NewR);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp2410 unsigned NewOpc; local
2413 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
2414 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2415 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2416 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2417 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2418 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2419 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2420 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2421 case X86::VMOVDQUYrr: NewOpc
2435 unsigned NewOpc; local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp474 unsigned NewOpc; local
479 NewOpc = ISD::FP_TO_SINT;
483 NewOpc = ISD::FP_TO_UINT;
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7844 unsigned NewOpc; local
7847 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7848 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7849 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7853 TmpInst.setOpcode(NewOpc);
8326 unsigned NewOpc; local
8329 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8330 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8331 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8332 case ARM::t2UXTB: NewOpc
8441 unsigned NewOpc; local
8481 unsigned NewOpc; local
[all...]
/external/llvm/lib/CodeGen/
H A DMachineLICM.cpp1175 unsigned NewOpc = local
1180 if (NewOpc == 0) return nullptr;
1181 const MCInstrDesc &MID = TII->get(NewOpc);
/external/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp476 int NewOpc; local
479 NewOpc = AMDGPU::getCommuteRev(Opcode);
480 if (NewOpc != -1)
482 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
485 NewOpc = AMDGPU::getCommuteOrig(Opcode);
486 if (NewOpc != -1)
488 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;

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