| /external/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 390 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); local
393 if (!isRegUsed(SReg)) {
394 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
395 return SReg;
411 Scavenged[SI].Reg = SReg;
415 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
419 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
427 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
438 // Scavenged[SI].Reg = SReg;
440 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 106 unsigned getDPRLaneFromSPR(unsigned SReg);
121 unsigned getPrefSPRLane(unsigned SReg);
150 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { argument
151 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
159 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { argument
160 if (!TRI->isVirtualRegister(SReg))
161 return getDPRLaneFromSPR(SReg);
163 MachineInstr *MI = MRI->getVRegDef(SReg);
165 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
172 SReg
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 4183 unsigned SReg, unsigned &Lane) {
4184 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4191 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4182 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 137 /// @brief records virtReg is a split live interval from SReg.
138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { argument
139 Virt2SplitMap[virtReg] = SReg;
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 275 unsigned SReg = Src2->getReg(); local
276 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
277 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
280 if (SReg != AMDGPU::VCC)
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3242 unsigned SReg = Inst.getOperand(1).getReg(); local
3251 if (DReg == SReg) {
3259 emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Instructions);
3264 emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3291 emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Instructions);
3292 emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3306 unsigned SReg = Inst.getOperand(1).getReg(); local
3319 emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Instructions);
3324 emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Instructions);
3334 emitRRI(Mips::SRL, DReg, SReg,
3370 unsigned SReg = Inst.getOperand(1).getReg(); local
3434 unsigned SReg = Inst.getOperand(1).getReg(); local
[all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | MemRegion.h | 1084 const MemRegion *SReg)
1085 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) {}
1088 bool IsVirtual, const MemRegion *SReg);
1083 CXXBaseObjectRegion(const CXXRecordDecl *RD, bool IsVirtual, const MemRegion *SReg) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 861 SReg = MF.getRegInfo().createVirtualRegister(RC); local
866 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
890 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| H A D | MemRegion.cpp | 413 const MemRegion *SReg) {
416 ID.AddPointer(SReg);
410 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, bool IsVirtual, const MemRegion *SReg) argument
|