1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMFeatures.h"
19#include "ARMHazardRecognizer.h"
20#include "ARMMachineFunctionInfo.h"
21#include "MCTargetDesc/ARMAddressingModes.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineJumpTableInfo.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetSchedule.h"
32#include "llvm/IR/Constants.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/GlobalValue.h"
35#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/MC/MCExpr.h"
37#include "llvm/Support/BranchProbability.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/raw_ostream.h"
42
43using namespace llvm;
44
45#define DEBUG_TYPE "arm-instrinfo"
46
47#define GET_INSTRINFO_CTOR_DTOR
48#include "ARMGenInstrInfo.inc"
49
50static cl::opt<bool>
51EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52               cl::desc("Enable ARM 2-addr to 3-addr conv"));
53
54static cl::opt<bool>
55WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
56           cl::desc("Widen ARM vmovs to vmovd when possible"));
57
58static cl::opt<unsigned>
59SwiftPartialUpdateClearance("swift-partial-update-clearance",
60     cl::Hidden, cl::init(12),
61     cl::desc("Clearance before partial register updates"));
62
63/// ARM_MLxEntry - Record information about MLA / MLS instructions.
64struct ARM_MLxEntry {
65  uint16_t MLxOpc;     // MLA / MLS opcode
66  uint16_t MulOpc;     // Expanded multiplication opcode
67  uint16_t AddSubOpc;  // Expanded add / sub opcode
68  bool NegAcc;         // True if the acc is negated before the add / sub.
69  bool HasLane;        // True if instruction has an extra "lane" operand.
70};
71
72static const ARM_MLxEntry ARM_MLxTable[] = {
73  // MLxOpc,          MulOpc,           AddSubOpc,       NegAcc, HasLane
74  // fp scalar ops
75  { ARM::VMLAS,       ARM::VMULS,       ARM::VADDS,      false,  false },
76  { ARM::VMLSS,       ARM::VMULS,       ARM::VSUBS,      false,  false },
77  { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
78  { ARM::VMLSD,       ARM::VMULD,       ARM::VSUBD,      false,  false },
79  { ARM::VNMLAS,      ARM::VNMULS,      ARM::VSUBS,      true,   false },
80  { ARM::VNMLSS,      ARM::VMULS,       ARM::VSUBS,      true,   false },
81  { ARM::VNMLAD,      ARM::VNMULD,      ARM::VSUBD,      true,   false },
82  { ARM::VNMLSD,      ARM::VMULD,       ARM::VSUBD,      true,   false },
83
84  // fp SIMD ops
85  { ARM::VMLAfd,      ARM::VMULfd,      ARM::VADDfd,     false,  false },
86  { ARM::VMLSfd,      ARM::VMULfd,      ARM::VSUBfd,     false,  false },
87  { ARM::VMLAfq,      ARM::VMULfq,      ARM::VADDfq,     false,  false },
88  { ARM::VMLSfq,      ARM::VMULfq,      ARM::VSUBfq,     false,  false },
89  { ARM::VMLAslfd,    ARM::VMULslfd,    ARM::VADDfd,     false,  true  },
90  { ARM::VMLSslfd,    ARM::VMULslfd,    ARM::VSUBfd,     false,  true  },
91  { ARM::VMLAslfq,    ARM::VMULslfq,    ARM::VADDfq,     false,  true  },
92  { ARM::VMLSslfq,    ARM::VMULslfq,    ARM::VSUBfq,     false,  true  },
93};
94
95ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
96  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
97    Subtarget(STI) {
98  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
99    if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
100      llvm_unreachable("Duplicated entries?");
101    MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
102    MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
103  }
104}
105
106// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
107// currently defaults to no prepass hazard recognizer.
108ScheduleHazardRecognizer *
109ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110                                               const ScheduleDAG *DAG) const {
111  if (usePreRAHazardRecognizer()) {
112    const InstrItineraryData *II =
113        static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114    return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
115  }
116  return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
117}
118
119ScheduleHazardRecognizer *ARMBaseInstrInfo::
120CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
121                                   const ScheduleDAG *DAG) const {
122  if (Subtarget.isThumb2() || Subtarget.hasVFP2())
123    return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
124  return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
125}
126
127MachineInstr *
128ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
129                                        MachineBasicBlock::iterator &MBBI,
130                                        LiveVariables *LV) const {
131  // FIXME: Thumb2 support.
132
133  if (!EnableARM3Addr)
134    return nullptr;
135
136  MachineInstr *MI = MBBI;
137  MachineFunction &MF = *MI->getParent()->getParent();
138  uint64_t TSFlags = MI->getDesc().TSFlags;
139  bool isPre = false;
140  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
141  default: return nullptr;
142  case ARMII::IndexModePre:
143    isPre = true;
144    break;
145  case ARMII::IndexModePost:
146    break;
147  }
148
149  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
150  // operation.
151  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
152  if (MemOpc == 0)
153    return nullptr;
154
155  MachineInstr *UpdateMI = nullptr;
156  MachineInstr *MemMI = nullptr;
157  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158  const MCInstrDesc &MCID = MI->getDesc();
159  unsigned NumOps = MCID.getNumOperands();
160  bool isLoad = !MI->mayStore();
161  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162  const MachineOperand &Base = MI->getOperand(2);
163  const MachineOperand &Offset = MI->getOperand(NumOps-3);
164  unsigned WBReg = WB.getReg();
165  unsigned BaseReg = Base.getReg();
166  unsigned OffReg = Offset.getReg();
167  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
169  switch (AddrMode) {
170  default: llvm_unreachable("Unknown indexed op!");
171  case ARMII::AddrMode2: {
172    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
173    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
174    if (OffReg == 0) {
175      if (ARM_AM::getSOImmVal(Amt) == -1)
176        // Can't encode it in a so_imm operand. This transformation will
177        // add more than 1 instruction. Abandon!
178        return nullptr;
179      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181        .addReg(BaseReg).addImm(Amt)
182        .addImm(Pred).addReg(0).addReg(0);
183    } else if (Amt != 0) {
184      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
185      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
186      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
187                         get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
188        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189        .addImm(Pred).addReg(0).addReg(0);
190    } else
191      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
193        .addReg(BaseReg).addReg(OffReg)
194        .addImm(Pred).addReg(0).addReg(0);
195    break;
196  }
197  case ARMII::AddrMode3 : {
198    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
199    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
200    if (OffReg == 0)
201      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
202      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
203                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
204        .addReg(BaseReg).addImm(Amt)
205        .addImm(Pred).addReg(0).addReg(0);
206    else
207      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
208                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
209        .addReg(BaseReg).addReg(OffReg)
210        .addImm(Pred).addReg(0).addReg(0);
211    break;
212  }
213  }
214
215  std::vector<MachineInstr*> NewMIs;
216  if (isPre) {
217    if (isLoad)
218      MemMI = BuildMI(MF, MI->getDebugLoc(),
219                      get(MemOpc), MI->getOperand(0).getReg())
220        .addReg(WBReg).addImm(0).addImm(Pred);
221    else
222      MemMI = BuildMI(MF, MI->getDebugLoc(),
223                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
224        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
225    NewMIs.push_back(MemMI);
226    NewMIs.push_back(UpdateMI);
227  } else {
228    if (isLoad)
229      MemMI = BuildMI(MF, MI->getDebugLoc(),
230                      get(MemOpc), MI->getOperand(0).getReg())
231        .addReg(BaseReg).addImm(0).addImm(Pred);
232    else
233      MemMI = BuildMI(MF, MI->getDebugLoc(),
234                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
235        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
236    if (WB.isDead())
237      UpdateMI->getOperand(0).setIsDead();
238    NewMIs.push_back(UpdateMI);
239    NewMIs.push_back(MemMI);
240  }
241
242  // Transfer LiveVariables states, kill / dead info.
243  if (LV) {
244    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245      MachineOperand &MO = MI->getOperand(i);
246      if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
247        unsigned Reg = MO.getReg();
248
249        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
250        if (MO.isDef()) {
251          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
252          if (MO.isDead())
253            LV->addVirtualRegisterDead(Reg, NewMI);
254        }
255        if (MO.isUse() && MO.isKill()) {
256          for (unsigned j = 0; j < 2; ++j) {
257            // Look at the two new MI's in reverse order.
258            MachineInstr *NewMI = NewMIs[j];
259            if (!NewMI->readsRegister(Reg))
260              continue;
261            LV->addVirtualRegisterKilled(Reg, NewMI);
262            if (VI.removeKill(MI))
263              VI.Kills.push_back(NewMI);
264            break;
265          }
266        }
267      }
268    }
269  }
270
271  MFI->insert(MBBI, NewMIs[1]);
272  MFI->insert(MBBI, NewMIs[0]);
273  return NewMIs[0];
274}
275
276// Branch analysis.
277bool
278ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
279                                MachineBasicBlock *&FBB,
280                                SmallVectorImpl<MachineOperand> &Cond,
281                                bool AllowModify) const {
282  TBB = nullptr;
283  FBB = nullptr;
284
285  MachineBasicBlock::iterator I = MBB.end();
286  if (I == MBB.begin())
287    return false; // Empty blocks are easy.
288  --I;
289
290  // Walk backwards from the end of the basic block until the branch is
291  // analyzed or we give up.
292  while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
293
294    // Flag to be raised on unanalyzeable instructions. This is useful in cases
295    // where we want to clean up on the end of the basic block before we bail
296    // out.
297    bool CantAnalyze = false;
298
299    // Skip over DEBUG values and predicated nonterminators.
300    while (I->isDebugValue() || !I->isTerminator()) {
301      if (I == MBB.begin())
302        return false;
303      --I;
304    }
305
306    if (isIndirectBranchOpcode(I->getOpcode()) ||
307        isJumpTableBranchOpcode(I->getOpcode())) {
308      // Indirect branches and jump tables can't be analyzed, but we still want
309      // to clean up any instructions at the tail of the basic block.
310      CantAnalyze = true;
311    } else if (isUncondBranchOpcode(I->getOpcode())) {
312      TBB = I->getOperand(0).getMBB();
313    } else if (isCondBranchOpcode(I->getOpcode())) {
314      // Bail out if we encounter multiple conditional branches.
315      if (!Cond.empty())
316        return true;
317
318      assert(!FBB && "FBB should have been null.");
319      FBB = TBB;
320      TBB = I->getOperand(0).getMBB();
321      Cond.push_back(I->getOperand(1));
322      Cond.push_back(I->getOperand(2));
323    } else if (I->isReturn()) {
324      // Returns can't be analyzed, but we should run cleanup.
325      CantAnalyze = !isPredicated(I);
326    } else {
327      // We encountered other unrecognized terminator. Bail out immediately.
328      return true;
329    }
330
331    // Cleanup code - to be run for unpredicated unconditional branches and
332    //                returns.
333    if (!isPredicated(I) &&
334          (isUncondBranchOpcode(I->getOpcode()) ||
335           isIndirectBranchOpcode(I->getOpcode()) ||
336           isJumpTableBranchOpcode(I->getOpcode()) ||
337           I->isReturn())) {
338      // Forget any previous condition branch information - it no longer applies.
339      Cond.clear();
340      FBB = nullptr;
341
342      // If we can modify the function, delete everything below this
343      // unconditional branch.
344      if (AllowModify) {
345        MachineBasicBlock::iterator DI = std::next(I);
346        while (DI != MBB.end()) {
347          MachineInstr *InstToDelete = DI;
348          ++DI;
349          InstToDelete->eraseFromParent();
350        }
351      }
352    }
353
354    if (CantAnalyze)
355      return true;
356
357    if (I == MBB.begin())
358      return false;
359
360    --I;
361  }
362
363  // We made it past the terminators without bailing out - we must have
364  // analyzed this branch successfully.
365  return false;
366}
367
368
369unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
371  if (I == MBB.end())
372    return 0;
373
374  if (!isUncondBranchOpcode(I->getOpcode()) &&
375      !isCondBranchOpcode(I->getOpcode()))
376    return 0;
377
378  // Remove the branch.
379  I->eraseFromParent();
380
381  I = MBB.end();
382
383  if (I == MBB.begin()) return 1;
384  --I;
385  if (!isCondBranchOpcode(I->getOpcode()))
386    return 1;
387
388  // Remove the branch.
389  I->eraseFromParent();
390  return 2;
391}
392
393unsigned
394ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395                               MachineBasicBlock *FBB,
396                               ArrayRef<MachineOperand> Cond,
397                               DebugLoc DL) const {
398  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399  int BOpc   = !AFI->isThumbFunction()
400    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401  int BccOpc = !AFI->isThumbFunction()
402    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
404
405  // Shouldn't be a fall through.
406  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
407  assert((Cond.size() == 2 || Cond.size() == 0) &&
408         "ARM branch conditions have two components!");
409
410  // For conditional branches, we use addOperand to preserve CPSR flags.
411
412  if (!FBB) {
413    if (Cond.empty()) { // Unconditional branch?
414      if (isThumb)
415        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416      else
417        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418    } else
419      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420        .addImm(Cond[0].getImm()).addOperand(Cond[1]);
421    return 1;
422  }
423
424  // Two-way conditional branch.
425  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426    .addImm(Cond[0].getImm()).addOperand(Cond[1]);
427  if (isThumb)
428    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429  else
430    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
431  return 2;
432}
433
434bool ARMBaseInstrInfo::
435ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
438  return false;
439}
440
441bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442  if (MI->isBundle()) {
443    MachineBasicBlock::const_instr_iterator I = MI->getIterator();
444    MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445    while (++I != E && I->isInsideBundle()) {
446      int PIdx = I->findFirstPredOperandIdx();
447      if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
448        return true;
449    }
450    return false;
451  }
452
453  int PIdx = MI->findFirstPredOperandIdx();
454  return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
455}
456
457bool ARMBaseInstrInfo::
458PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
459  unsigned Opc = MI->getOpcode();
460  if (isUncondBranchOpcode(Opc)) {
461    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462    MachineInstrBuilder(*MI->getParent()->getParent(), MI)
463      .addImm(Pred[0].getImm())
464      .addReg(Pred[1].getReg());
465    return true;
466  }
467
468  int PIdx = MI->findFirstPredOperandIdx();
469  if (PIdx != -1) {
470    MachineOperand &PMO = MI->getOperand(PIdx);
471    PMO.setImm(Pred[0].getImm());
472    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
473    return true;
474  }
475  return false;
476}
477
478bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
479                                         ArrayRef<MachineOperand> Pred2) const {
480  if (Pred1.size() > 2 || Pred2.size() > 2)
481    return false;
482
483  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
485  if (CC1 == CC2)
486    return true;
487
488  switch (CC1) {
489  default:
490    return false;
491  case ARMCC::AL:
492    return true;
493  case ARMCC::HS:
494    return CC2 == ARMCC::HI;
495  case ARMCC::LS:
496    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
497  case ARMCC::GE:
498    return CC2 == ARMCC::GT;
499  case ARMCC::LE:
500    return CC2 == ARMCC::LT;
501  }
502}
503
504bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505                                    std::vector<MachineOperand> &Pred) const {
506  bool Found = false;
507  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508    const MachineOperand &MO = MI->getOperand(i);
509    if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510        (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
511      Pred.push_back(MO);
512      Found = true;
513    }
514  }
515
516  return Found;
517}
518
519static bool isCPSRDefined(const MachineInstr *MI) {
520  for (const auto &MO : MI->operands())
521    if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
522      return true;
523  return false;
524}
525
526static bool isEligibleForITBlock(const MachineInstr *MI) {
527  switch (MI->getOpcode()) {
528  default: return true;
529  case ARM::tADC:   // ADC (register) T1
530  case ARM::tADDi3: // ADD (immediate) T1
531  case ARM::tADDi8: // ADD (immediate) T2
532  case ARM::tADDrr: // ADD (register) T1
533  case ARM::tAND:   // AND (register) T1
534  case ARM::tASRri: // ASR (immediate) T1
535  case ARM::tASRrr: // ASR (register) T1
536  case ARM::tBIC:   // BIC (register) T1
537  case ARM::tEOR:   // EOR (register) T1
538  case ARM::tLSLri: // LSL (immediate) T1
539  case ARM::tLSLrr: // LSL (register) T1
540  case ARM::tLSRri: // LSR (immediate) T1
541  case ARM::tLSRrr: // LSR (register) T1
542  case ARM::tMUL:   // MUL T1
543  case ARM::tMVN:   // MVN (register) T1
544  case ARM::tORR:   // ORR (register) T1
545  case ARM::tROR:   // ROR (register) T1
546  case ARM::tRSB:   // RSB (immediate) T1
547  case ARM::tSBC:   // SBC (register) T1
548  case ARM::tSUBi3: // SUB (immediate) T1
549  case ARM::tSUBi8: // SUB (immediate) T2
550  case ARM::tSUBrr: // SUB (register) T1
551    return !isCPSRDefined(MI);
552  }
553}
554
555/// isPredicable - Return true if the specified instruction can be predicated.
556/// By default, this returns true for every instruction with a
557/// PredicateOperand.
558bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
559  if (!MI->isPredicable())
560    return false;
561
562  if (!isEligibleForITBlock(MI))
563    return false;
564
565  ARMFunctionInfo *AFI =
566    MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
567
568  if (AFI->isThumb2Function()) {
569    if (getSubtarget().restrictIT())
570      return isV8EligibleForIT(MI);
571  } else { // non-Thumb
572    if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
573      return false;
574  }
575
576  return true;
577}
578
579namespace llvm {
580template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
581  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582    const MachineOperand &MO = MI->getOperand(i);
583    if (!MO.isReg() || MO.isUndef() || MO.isUse())
584      continue;
585    if (MO.getReg() != ARM::CPSR)
586      continue;
587    if (!MO.isDead())
588      return false;
589  }
590  // all definitions of CPSR are dead
591  return true;
592}
593}
594
595/// GetInstSize - Return the size of the specified MachineInstr.
596///
597unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
598  const MachineBasicBlock &MBB = *MI->getParent();
599  const MachineFunction *MF = MBB.getParent();
600  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
601
602  const MCInstrDesc &MCID = MI->getDesc();
603  if (MCID.getSize())
604    return MCID.getSize();
605
606  // If this machine instr is an inline asm, measure it.
607  if (MI->getOpcode() == ARM::INLINEASM)
608    return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
609  unsigned Opc = MI->getOpcode();
610  switch (Opc) {
611  default:
612    // pseudo-instruction sizes are zero.
613    return 0;
614  case TargetOpcode::BUNDLE:
615    return getInstBundleLength(MI);
616  case ARM::MOVi16_ga_pcrel:
617  case ARM::MOVTi16_ga_pcrel:
618  case ARM::t2MOVi16_ga_pcrel:
619  case ARM::t2MOVTi16_ga_pcrel:
620    return 4;
621  case ARM::MOVi32imm:
622  case ARM::t2MOVi32imm:
623    return 8;
624  case ARM::CONSTPOOL_ENTRY:
625  case ARM::JUMPTABLE_INSTS:
626  case ARM::JUMPTABLE_ADDRS:
627  case ARM::JUMPTABLE_TBB:
628  case ARM::JUMPTABLE_TBH:
629    // If this machine instr is a constant pool entry, its size is recorded as
630    // operand #2.
631    return MI->getOperand(2).getImm();
632  case ARM::Int_eh_sjlj_longjmp:
633    return 16;
634  case ARM::tInt_eh_sjlj_longjmp:
635    return 10;
636  case ARM::Int_eh_sjlj_setjmp:
637  case ARM::Int_eh_sjlj_setjmp_nofp:
638    return 20;
639  case ARM::tInt_eh_sjlj_setjmp:
640  case ARM::t2Int_eh_sjlj_setjmp:
641  case ARM::t2Int_eh_sjlj_setjmp_nofp:
642    return 12;
643  case ARM::SPACE:
644    return MI->getOperand(1).getImm();
645  }
646}
647
648unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
649  unsigned Size = 0;
650  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
651  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
652  while (++I != E && I->isInsideBundle()) {
653    assert(!I->isBundle() && "No nested bundle!");
654    Size += GetInstSizeInBytes(&*I);
655  }
656  return Size;
657}
658
659void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
660                                    MachineBasicBlock::iterator I,
661                                    unsigned DestReg, bool KillSrc,
662                                    const ARMSubtarget &Subtarget) const {
663  unsigned Opc = Subtarget.isThumb()
664                     ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
665                     : ARM::MRS;
666
667  MachineInstrBuilder MIB =
668      BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
669
670  // There is only 1 A/R class MRS instruction, and it always refers to
671  // APSR. However, there are lots of other possibilities on M-class cores.
672  if (Subtarget.isMClass())
673    MIB.addImm(0x800);
674
675  AddDefaultPred(MIB);
676
677  MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
678}
679
680void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
681                                  MachineBasicBlock::iterator I,
682                                  unsigned SrcReg, bool KillSrc,
683                                  const ARMSubtarget &Subtarget) const {
684  unsigned Opc = Subtarget.isThumb()
685                     ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
686                     : ARM::MSR;
687
688  MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
689
690  if (Subtarget.isMClass())
691    MIB.addImm(0x800);
692  else
693    MIB.addImm(8);
694
695  MIB.addReg(SrcReg, getKillRegState(KillSrc));
696
697  AddDefaultPred(MIB);
698
699  MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
700}
701
702void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
703                                   MachineBasicBlock::iterator I, DebugLoc DL,
704                                   unsigned DestReg, unsigned SrcReg,
705                                   bool KillSrc) const {
706  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
707  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
708
709  if (GPRDest && GPRSrc) {
710    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
711                                    .addReg(SrcReg, getKillRegState(KillSrc))));
712    return;
713  }
714
715  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
716  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
717
718  unsigned Opc = 0;
719  if (SPRDest && SPRSrc)
720    Opc = ARM::VMOVS;
721  else if (GPRDest && SPRSrc)
722    Opc = ARM::VMOVRS;
723  else if (SPRDest && GPRSrc)
724    Opc = ARM::VMOVSR;
725  else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
726    Opc = ARM::VMOVD;
727  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
728    Opc = ARM::VORRq;
729
730  if (Opc) {
731    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
732    MIB.addReg(SrcReg, getKillRegState(KillSrc));
733    if (Opc == ARM::VORRq)
734      MIB.addReg(SrcReg, getKillRegState(KillSrc));
735    AddDefaultPred(MIB);
736    return;
737  }
738
739  // Handle register classes that require multiple instructions.
740  unsigned BeginIdx = 0;
741  unsigned SubRegs = 0;
742  int Spacing = 1;
743
744  // Use VORRq when possible.
745  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
746    Opc = ARM::VORRq;
747    BeginIdx = ARM::qsub_0;
748    SubRegs = 2;
749  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
750    Opc = ARM::VORRq;
751    BeginIdx = ARM::qsub_0;
752    SubRegs = 4;
753  // Fall back to VMOVD.
754  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
755    Opc = ARM::VMOVD;
756    BeginIdx = ARM::dsub_0;
757    SubRegs = 2;
758  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
759    Opc = ARM::VMOVD;
760    BeginIdx = ARM::dsub_0;
761    SubRegs = 3;
762  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
763    Opc = ARM::VMOVD;
764    BeginIdx = ARM::dsub_0;
765    SubRegs = 4;
766  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
767    Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
768    BeginIdx = ARM::gsub_0;
769    SubRegs = 2;
770  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
771    Opc = ARM::VMOVD;
772    BeginIdx = ARM::dsub_0;
773    SubRegs = 2;
774    Spacing = 2;
775  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
776    Opc = ARM::VMOVD;
777    BeginIdx = ARM::dsub_0;
778    SubRegs = 3;
779    Spacing = 2;
780  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
781    Opc = ARM::VMOVD;
782    BeginIdx = ARM::dsub_0;
783    SubRegs = 4;
784    Spacing = 2;
785  } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
786    Opc = ARM::VMOVS;
787    BeginIdx = ARM::ssub_0;
788    SubRegs = 2;
789  } else if (SrcReg == ARM::CPSR) {
790    copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
791    return;
792  } else if (DestReg == ARM::CPSR) {
793    copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
794    return;
795  }
796
797  assert(Opc && "Impossible reg-to-reg copy");
798
799  const TargetRegisterInfo *TRI = &getRegisterInfo();
800  MachineInstrBuilder Mov;
801
802  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
803  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
804    BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
805    Spacing = -Spacing;
806  }
807#ifndef NDEBUG
808  SmallSet<unsigned, 4> DstRegs;
809#endif
810  for (unsigned i = 0; i != SubRegs; ++i) {
811    unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812    unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
813    assert(Dst && Src && "Bad sub-register");
814#ifndef NDEBUG
815    assert(!DstRegs.count(Src) && "destructive vector copy");
816    DstRegs.insert(Dst);
817#endif
818    Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
819    // VORR takes two source operands.
820    if (Opc == ARM::VORRq)
821      Mov.addReg(Src);
822    Mov = AddDefaultPred(Mov);
823    // MOVr can set CC.
824    if (Opc == ARM::MOVr)
825      Mov = AddDefaultCC(Mov);
826  }
827  // Add implicit super-register defs and kills to the last instruction.
828  Mov->addRegisterDefined(DestReg, TRI);
829  if (KillSrc)
830    Mov->addRegisterKilled(SrcReg, TRI);
831}
832
833const MachineInstrBuilder &
834ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
835                          unsigned SubIdx, unsigned State,
836                          const TargetRegisterInfo *TRI) const {
837  if (!SubIdx)
838    return MIB.addReg(Reg, State);
839
840  if (TargetRegisterInfo::isPhysicalRegister(Reg))
841    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842  return MIB.addReg(Reg, State, SubIdx);
843}
844
845void ARMBaseInstrInfo::
846storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
847                    unsigned SrcReg, bool isKill, int FI,
848                    const TargetRegisterClass *RC,
849                    const TargetRegisterInfo *TRI) const {
850  DebugLoc DL;
851  if (I != MBB.end()) DL = I->getDebugLoc();
852  MachineFunction &MF = *MBB.getParent();
853  MachineFrameInfo &MFI = *MF.getFrameInfo();
854  unsigned Align = MFI.getObjectAlignment(FI);
855
856  MachineMemOperand *MMO = MF.getMachineMemOperand(
857      MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
858      MFI.getObjectSize(FI), Align);
859
860  switch (RC->getSize()) {
861    case 4:
862      if (ARM::GPRRegClass.hasSubClassEq(RC)) {
863        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
864                   .addReg(SrcReg, getKillRegState(isKill))
865                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
866      } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
867        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
868                   .addReg(SrcReg, getKillRegState(isKill))
869                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
870      } else
871        llvm_unreachable("Unknown reg class!");
872      break;
873    case 8:
874      if (ARM::DPRRegClass.hasSubClassEq(RC)) {
875        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
876                   .addReg(SrcReg, getKillRegState(isKill))
877                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
878      } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
879        if (Subtarget.hasV5TEOps()) {
880          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
881          AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
882          AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
883          MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
884
885          AddDefaultPred(MIB);
886        } else {
887          // Fallback to STM instruction, which has existed since the dawn of
888          // time.
889          MachineInstrBuilder MIB =
890            AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
891                             .addFrameIndex(FI).addMemOperand(MMO));
892          AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
893          AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
894        }
895      } else
896        llvm_unreachable("Unknown reg class!");
897      break;
898    case 16:
899      if (ARM::DPairRegClass.hasSubClassEq(RC)) {
900        // Use aligned spills if the stack can be realigned.
901        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
902          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
903                     .addFrameIndex(FI).addImm(16)
904                     .addReg(SrcReg, getKillRegState(isKill))
905                     .addMemOperand(MMO));
906        } else {
907          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
908                     .addReg(SrcReg, getKillRegState(isKill))
909                     .addFrameIndex(FI)
910                     .addMemOperand(MMO));
911        }
912      } else
913        llvm_unreachable("Unknown reg class!");
914      break;
915    case 24:
916      if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
917        // Use aligned spills if the stack can be realigned.
918        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
919          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
920                     .addFrameIndex(FI).addImm(16)
921                     .addReg(SrcReg, getKillRegState(isKill))
922                     .addMemOperand(MMO));
923        } else {
924          MachineInstrBuilder MIB =
925          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
926                       .addFrameIndex(FI))
927                       .addMemOperand(MMO);
928          MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
929          MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
930          AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
931        }
932      } else
933        llvm_unreachable("Unknown reg class!");
934      break;
935    case 32:
936      if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
937        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
938          // FIXME: It's possible to only store part of the QQ register if the
939          // spilled def has a sub-register index.
940          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
941                     .addFrameIndex(FI).addImm(16)
942                     .addReg(SrcReg, getKillRegState(isKill))
943                     .addMemOperand(MMO));
944        } else {
945          MachineInstrBuilder MIB =
946          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
947                       .addFrameIndex(FI))
948                       .addMemOperand(MMO);
949          MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
950          MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
951          MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
952                AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
953        }
954      } else
955        llvm_unreachable("Unknown reg class!");
956      break;
957    case 64:
958      if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
959        MachineInstrBuilder MIB =
960          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
961                         .addFrameIndex(FI))
962                         .addMemOperand(MMO);
963        MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
964        MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
965        MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
966        MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
967        MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
968        MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
969        MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
970              AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
971      } else
972        llvm_unreachable("Unknown reg class!");
973      break;
974    default:
975      llvm_unreachable("Unknown reg class!");
976  }
977}
978
979unsigned
980ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
981                                     int &FrameIndex) const {
982  switch (MI->getOpcode()) {
983  default: break;
984  case ARM::STRrs:
985  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
986    if (MI->getOperand(1).isFI() &&
987        MI->getOperand(2).isReg() &&
988        MI->getOperand(3).isImm() &&
989        MI->getOperand(2).getReg() == 0 &&
990        MI->getOperand(3).getImm() == 0) {
991      FrameIndex = MI->getOperand(1).getIndex();
992      return MI->getOperand(0).getReg();
993    }
994    break;
995  case ARM::STRi12:
996  case ARM::t2STRi12:
997  case ARM::tSTRspi:
998  case ARM::VSTRD:
999  case ARM::VSTRS:
1000    if (MI->getOperand(1).isFI() &&
1001        MI->getOperand(2).isImm() &&
1002        MI->getOperand(2).getImm() == 0) {
1003      FrameIndex = MI->getOperand(1).getIndex();
1004      return MI->getOperand(0).getReg();
1005    }
1006    break;
1007  case ARM::VST1q64:
1008  case ARM::VST1d64TPseudo:
1009  case ARM::VST1d64QPseudo:
1010    if (MI->getOperand(0).isFI() &&
1011        MI->getOperand(2).getSubReg() == 0) {
1012      FrameIndex = MI->getOperand(0).getIndex();
1013      return MI->getOperand(2).getReg();
1014    }
1015    break;
1016  case ARM::VSTMQIA:
1017    if (MI->getOperand(1).isFI() &&
1018        MI->getOperand(0).getSubReg() == 0) {
1019      FrameIndex = MI->getOperand(1).getIndex();
1020      return MI->getOperand(0).getReg();
1021    }
1022    break;
1023  }
1024
1025  return 0;
1026}
1027
1028unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1029                                                    int &FrameIndex) const {
1030  const MachineMemOperand *Dummy;
1031  return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1032}
1033
1034void ARMBaseInstrInfo::
1035loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1036                     unsigned DestReg, int FI,
1037                     const TargetRegisterClass *RC,
1038                     const TargetRegisterInfo *TRI) const {
1039  DebugLoc DL;
1040  if (I != MBB.end()) DL = I->getDebugLoc();
1041  MachineFunction &MF = *MBB.getParent();
1042  MachineFrameInfo &MFI = *MF.getFrameInfo();
1043  unsigned Align = MFI.getObjectAlignment(FI);
1044  MachineMemOperand *MMO = MF.getMachineMemOperand(
1045      MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1046      MFI.getObjectSize(FI), Align);
1047
1048  switch (RC->getSize()) {
1049  case 4:
1050    if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1051      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1052                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1053
1054    } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1055      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1056                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1057    } else
1058      llvm_unreachable("Unknown reg class!");
1059    break;
1060  case 8:
1061    if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1062      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1063                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1064    } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1065      MachineInstrBuilder MIB;
1066
1067      if (Subtarget.hasV5TEOps()) {
1068        MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1069        AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1070        AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1071        MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1072
1073        AddDefaultPred(MIB);
1074      } else {
1075        // Fallback to LDM instruction, which has existed since the dawn of
1076        // time.
1077        MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1078                                 .addFrameIndex(FI).addMemOperand(MMO));
1079        MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1080        MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1081      }
1082
1083      if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1084        MIB.addReg(DestReg, RegState::ImplicitDefine);
1085    } else
1086      llvm_unreachable("Unknown reg class!");
1087    break;
1088  case 16:
1089    if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1090      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1091        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1092                     .addFrameIndex(FI).addImm(16)
1093                     .addMemOperand(MMO));
1094      } else {
1095        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1096                       .addFrameIndex(FI)
1097                       .addMemOperand(MMO));
1098      }
1099    } else
1100      llvm_unreachable("Unknown reg class!");
1101    break;
1102  case 24:
1103    if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1104      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1105        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1106                     .addFrameIndex(FI).addImm(16)
1107                     .addMemOperand(MMO));
1108      } else {
1109        MachineInstrBuilder MIB =
1110          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1111                         .addFrameIndex(FI)
1112                         .addMemOperand(MMO));
1113        MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1114        MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1115        MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1116        if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1117          MIB.addReg(DestReg, RegState::ImplicitDefine);
1118      }
1119    } else
1120      llvm_unreachable("Unknown reg class!");
1121    break;
1122   case 32:
1123    if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1124      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1125        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1126                     .addFrameIndex(FI).addImm(16)
1127                     .addMemOperand(MMO));
1128      } else {
1129        MachineInstrBuilder MIB =
1130        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1131                       .addFrameIndex(FI))
1132                       .addMemOperand(MMO);
1133        MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1134        MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1135        MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1136        MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1137        if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1138          MIB.addReg(DestReg, RegState::ImplicitDefine);
1139      }
1140    } else
1141      llvm_unreachable("Unknown reg class!");
1142    break;
1143  case 64:
1144    if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1145      MachineInstrBuilder MIB =
1146      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1147                     .addFrameIndex(FI))
1148                     .addMemOperand(MMO);
1149      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1150      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1151      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1152      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1153      MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1154      MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1155      MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1156      MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1157      if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1158        MIB.addReg(DestReg, RegState::ImplicitDefine);
1159    } else
1160      llvm_unreachable("Unknown reg class!");
1161    break;
1162  default:
1163    llvm_unreachable("Unknown regclass!");
1164  }
1165}
1166
1167unsigned
1168ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1169                                      int &FrameIndex) const {
1170  switch (MI->getOpcode()) {
1171  default: break;
1172  case ARM::LDRrs:
1173  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
1174    if (MI->getOperand(1).isFI() &&
1175        MI->getOperand(2).isReg() &&
1176        MI->getOperand(3).isImm() &&
1177        MI->getOperand(2).getReg() == 0 &&
1178        MI->getOperand(3).getImm() == 0) {
1179      FrameIndex = MI->getOperand(1).getIndex();
1180      return MI->getOperand(0).getReg();
1181    }
1182    break;
1183  case ARM::LDRi12:
1184  case ARM::t2LDRi12:
1185  case ARM::tLDRspi:
1186  case ARM::VLDRD:
1187  case ARM::VLDRS:
1188    if (MI->getOperand(1).isFI() &&
1189        MI->getOperand(2).isImm() &&
1190        MI->getOperand(2).getImm() == 0) {
1191      FrameIndex = MI->getOperand(1).getIndex();
1192      return MI->getOperand(0).getReg();
1193    }
1194    break;
1195  case ARM::VLD1q64:
1196  case ARM::VLD1d64TPseudo:
1197  case ARM::VLD1d64QPseudo:
1198    if (MI->getOperand(1).isFI() &&
1199        MI->getOperand(0).getSubReg() == 0) {
1200      FrameIndex = MI->getOperand(1).getIndex();
1201      return MI->getOperand(0).getReg();
1202    }
1203    break;
1204  case ARM::VLDMQIA:
1205    if (MI->getOperand(1).isFI() &&
1206        MI->getOperand(0).getSubReg() == 0) {
1207      FrameIndex = MI->getOperand(1).getIndex();
1208      return MI->getOperand(0).getReg();
1209    }
1210    break;
1211  }
1212
1213  return 0;
1214}
1215
1216unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1217                                             int &FrameIndex) const {
1218  const MachineMemOperand *Dummy;
1219  return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1220}
1221
1222/// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1223/// depending on whether the result is used.
1224void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MBBI) const {
1225  bool isThumb1 = Subtarget.isThumb1Only();
1226  bool isThumb2 = Subtarget.isThumb2();
1227  const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1228
1229  MachineInstr *MI = MBBI;
1230  DebugLoc dl = MI->getDebugLoc();
1231  MachineBasicBlock *BB = MI->getParent();
1232
1233  MachineInstrBuilder LDM, STM;
1234  if (isThumb1 || !MI->getOperand(1).isDead()) {
1235    LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1236                                                 : isThumb1 ? ARM::tLDMIA_UPD
1237                                                            : ARM::LDMIA_UPD))
1238             .addOperand(MI->getOperand(1));
1239  } else {
1240    LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1241  }
1242
1243  if (isThumb1 || !MI->getOperand(0).isDead()) {
1244    STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1245                                                 : isThumb1 ? ARM::tSTMIA_UPD
1246                                                            : ARM::STMIA_UPD))
1247             .addOperand(MI->getOperand(0));
1248  } else {
1249    STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1250  }
1251
1252  AddDefaultPred(LDM.addOperand(MI->getOperand(3)));
1253  AddDefaultPred(STM.addOperand(MI->getOperand(2)));
1254
1255  // Sort the scratch registers into ascending order.
1256  const TargetRegisterInfo &TRI = getRegisterInfo();
1257  llvm::SmallVector<unsigned, 6> ScratchRegs;
1258  for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1259    ScratchRegs.push_back(MI->getOperand(I).getReg());
1260  std::sort(ScratchRegs.begin(), ScratchRegs.end(),
1261            [&TRI](const unsigned &Reg1,
1262                   const unsigned &Reg2) -> bool {
1263              return TRI.getEncodingValue(Reg1) <
1264                     TRI.getEncodingValue(Reg2);
1265            });
1266
1267  for (const auto &Reg : ScratchRegs) {
1268    LDM.addReg(Reg, RegState::Define);
1269    STM.addReg(Reg, RegState::Kill);
1270  }
1271
1272  BB->erase(MBBI);
1273}
1274
1275
1276bool
1277ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1278  MachineFunction &MF = *MI->getParent()->getParent();
1279  Reloc::Model RM = MF.getTarget().getRelocationModel();
1280
1281  if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1282    assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1283           "LOAD_STACK_GUARD currently supported only for MachO.");
1284    expandLoadStackGuard(MI, RM);
1285    MI->getParent()->erase(MI);
1286    return true;
1287  }
1288
1289  if (MI->getOpcode() == ARM::MEMCPY) {
1290    expandMEMCPY(MI);
1291    return true;
1292  }
1293
1294  // This hook gets to expand COPY instructions before they become
1295  // copyPhysReg() calls.  Look for VMOVS instructions that can legally be
1296  // widened to VMOVD.  We prefer the VMOVD when possible because it may be
1297  // changed into a VORR that can go down the NEON pipeline.
1298  if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1299      Subtarget.isFPOnlySP())
1300    return false;
1301
1302  // Look for a copy between even S-registers.  That is where we keep floats
1303  // when using NEON v2f32 instructions for f32 arithmetic.
1304  unsigned DstRegS = MI->getOperand(0).getReg();
1305  unsigned SrcRegS = MI->getOperand(1).getReg();
1306  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1307    return false;
1308
1309  const TargetRegisterInfo *TRI = &getRegisterInfo();
1310  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1311                                              &ARM::DPRRegClass);
1312  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1313                                              &ARM::DPRRegClass);
1314  if (!DstRegD || !SrcRegD)
1315    return false;
1316
1317  // We want to widen this into a DstRegD = VMOVD SrcRegD copy.  This is only
1318  // legal if the COPY already defines the full DstRegD, and it isn't a
1319  // sub-register insertion.
1320  if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1321    return false;
1322
1323  // A dead copy shouldn't show up here, but reject it just in case.
1324  if (MI->getOperand(0).isDead())
1325    return false;
1326
1327  // All clear, widen the COPY.
1328  DEBUG(dbgs() << "widening:    " << *MI);
1329  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1330
1331  // Get rid of the old <imp-def> of DstRegD.  Leave it if it defines a Q-reg
1332  // or some other super-register.
1333  int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1334  if (ImpDefIdx != -1)
1335    MI->RemoveOperand(ImpDefIdx);
1336
1337  // Change the opcode and operands.
1338  MI->setDesc(get(ARM::VMOVD));
1339  MI->getOperand(0).setReg(DstRegD);
1340  MI->getOperand(1).setReg(SrcRegD);
1341  AddDefaultPred(MIB);
1342
1343  // We are now reading SrcRegD instead of SrcRegS.  This may upset the
1344  // register scavenger and machine verifier, so we need to indicate that we
1345  // are reading an undefined value from SrcRegD, but a proper value from
1346  // SrcRegS.
1347  MI->getOperand(1).setIsUndef();
1348  MIB.addReg(SrcRegS, RegState::Implicit);
1349
1350  // SrcRegD may actually contain an unrelated value in the ssub_1
1351  // sub-register.  Don't kill it.  Only kill the ssub_0 sub-register.
1352  if (MI->getOperand(1).isKill()) {
1353    MI->getOperand(1).setIsKill(false);
1354    MI->addRegisterKilled(SrcRegS, TRI, true);
1355  }
1356
1357  DEBUG(dbgs() << "replaced by: " << *MI);
1358  return true;
1359}
1360
1361/// Create a copy of a const pool value. Update CPI to the new index and return
1362/// the label UID.
1363static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1364  MachineConstantPool *MCP = MF.getConstantPool();
1365  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1366
1367  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1368  assert(MCPE.isMachineConstantPoolEntry() &&
1369         "Expecting a machine constantpool entry!");
1370  ARMConstantPoolValue *ACPV =
1371    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1372
1373  unsigned PCLabelId = AFI->createPICLabelUId();
1374  ARMConstantPoolValue *NewCPV = nullptr;
1375
1376  // FIXME: The below assumes PIC relocation model and that the function
1377  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1378  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1379  // instructions, so that's probably OK, but is PIC always correct when
1380  // we get here?
1381  if (ACPV->isGlobalValue())
1382    NewCPV = ARMConstantPoolConstant::Create(
1383        cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1384        4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1385  else if (ACPV->isExtSymbol())
1386    NewCPV = ARMConstantPoolSymbol::
1387      Create(MF.getFunction()->getContext(),
1388             cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1389  else if (ACPV->isBlockAddress())
1390    NewCPV = ARMConstantPoolConstant::
1391      Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1392             ARMCP::CPBlockAddress, 4);
1393  else if (ACPV->isLSDA())
1394    NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1395                                             ARMCP::CPLSDA, 4);
1396  else if (ACPV->isMachineBasicBlock())
1397    NewCPV = ARMConstantPoolMBB::
1398      Create(MF.getFunction()->getContext(),
1399             cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1400  else
1401    llvm_unreachable("Unexpected ARM constantpool value type!!");
1402  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1403  return PCLabelId;
1404}
1405
1406void ARMBaseInstrInfo::
1407reMaterialize(MachineBasicBlock &MBB,
1408              MachineBasicBlock::iterator I,
1409              unsigned DestReg, unsigned SubIdx,
1410              const MachineInstr *Orig,
1411              const TargetRegisterInfo &TRI) const {
1412  unsigned Opcode = Orig->getOpcode();
1413  switch (Opcode) {
1414  default: {
1415    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1416    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1417    MBB.insert(I, MI);
1418    break;
1419  }
1420  case ARM::tLDRpci_pic:
1421  case ARM::t2LDRpci_pic: {
1422    MachineFunction &MF = *MBB.getParent();
1423    unsigned CPI = Orig->getOperand(1).getIndex();
1424    unsigned PCLabelId = duplicateCPV(MF, CPI);
1425    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1426                                      DestReg)
1427      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1428    MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1429    break;
1430  }
1431  }
1432}
1433
1434MachineInstr *
1435ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1436  MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1437  switch(Orig->getOpcode()) {
1438  case ARM::tLDRpci_pic:
1439  case ARM::t2LDRpci_pic: {
1440    unsigned CPI = Orig->getOperand(1).getIndex();
1441    unsigned PCLabelId = duplicateCPV(MF, CPI);
1442    Orig->getOperand(1).setIndex(CPI);
1443    Orig->getOperand(2).setImm(PCLabelId);
1444    break;
1445  }
1446  }
1447  return MI;
1448}
1449
1450bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1451                                        const MachineInstr *MI1,
1452                                        const MachineRegisterInfo *MRI) const {
1453  unsigned Opcode = MI0->getOpcode();
1454  if (Opcode == ARM::t2LDRpci ||
1455      Opcode == ARM::t2LDRpci_pic ||
1456      Opcode == ARM::tLDRpci ||
1457      Opcode == ARM::tLDRpci_pic ||
1458      Opcode == ARM::LDRLIT_ga_pcrel ||
1459      Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1460      Opcode == ARM::tLDRLIT_ga_pcrel ||
1461      Opcode == ARM::MOV_ga_pcrel ||
1462      Opcode == ARM::MOV_ga_pcrel_ldr ||
1463      Opcode == ARM::t2MOV_ga_pcrel) {
1464    if (MI1->getOpcode() != Opcode)
1465      return false;
1466    if (MI0->getNumOperands() != MI1->getNumOperands())
1467      return false;
1468
1469    const MachineOperand &MO0 = MI0->getOperand(1);
1470    const MachineOperand &MO1 = MI1->getOperand(1);
1471    if (MO0.getOffset() != MO1.getOffset())
1472      return false;
1473
1474    if (Opcode == ARM::LDRLIT_ga_pcrel ||
1475        Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1476        Opcode == ARM::tLDRLIT_ga_pcrel ||
1477        Opcode == ARM::MOV_ga_pcrel ||
1478        Opcode == ARM::MOV_ga_pcrel_ldr ||
1479        Opcode == ARM::t2MOV_ga_pcrel)
1480      // Ignore the PC labels.
1481      return MO0.getGlobal() == MO1.getGlobal();
1482
1483    const MachineFunction *MF = MI0->getParent()->getParent();
1484    const MachineConstantPool *MCP = MF->getConstantPool();
1485    int CPI0 = MO0.getIndex();
1486    int CPI1 = MO1.getIndex();
1487    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1488    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1489    bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1490    bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1491    if (isARMCP0 && isARMCP1) {
1492      ARMConstantPoolValue *ACPV0 =
1493        static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1494      ARMConstantPoolValue *ACPV1 =
1495        static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1496      return ACPV0->hasSameValue(ACPV1);
1497    } else if (!isARMCP0 && !isARMCP1) {
1498      return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1499    }
1500    return false;
1501  } else if (Opcode == ARM::PICLDR) {
1502    if (MI1->getOpcode() != Opcode)
1503      return false;
1504    if (MI0->getNumOperands() != MI1->getNumOperands())
1505      return false;
1506
1507    unsigned Addr0 = MI0->getOperand(1).getReg();
1508    unsigned Addr1 = MI1->getOperand(1).getReg();
1509    if (Addr0 != Addr1) {
1510      if (!MRI ||
1511          !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1512          !TargetRegisterInfo::isVirtualRegister(Addr1))
1513        return false;
1514
1515      // This assumes SSA form.
1516      MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1517      MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1518      // Check if the loaded value, e.g. a constantpool of a global address, are
1519      // the same.
1520      if (!produceSameValue(Def0, Def1, MRI))
1521        return false;
1522    }
1523
1524    for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1525      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1526      const MachineOperand &MO0 = MI0->getOperand(i);
1527      const MachineOperand &MO1 = MI1->getOperand(i);
1528      if (!MO0.isIdenticalTo(MO1))
1529        return false;
1530    }
1531    return true;
1532  }
1533
1534  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1535}
1536
1537/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1538/// determine if two loads are loading from the same base address. It should
1539/// only return true if the base pointers are the same and the only differences
1540/// between the two addresses is the offset. It also returns the offsets by
1541/// reference.
1542///
1543/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1544/// is permanently disabled.
1545bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1546                                               int64_t &Offset1,
1547                                               int64_t &Offset2) const {
1548  // Don't worry about Thumb: just ARM and Thumb2.
1549  if (Subtarget.isThumb1Only()) return false;
1550
1551  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1552    return false;
1553
1554  switch (Load1->getMachineOpcode()) {
1555  default:
1556    return false;
1557  case ARM::LDRi12:
1558  case ARM::LDRBi12:
1559  case ARM::LDRD:
1560  case ARM::LDRH:
1561  case ARM::LDRSB:
1562  case ARM::LDRSH:
1563  case ARM::VLDRD:
1564  case ARM::VLDRS:
1565  case ARM::t2LDRi8:
1566  case ARM::t2LDRBi8:
1567  case ARM::t2LDRDi8:
1568  case ARM::t2LDRSHi8:
1569  case ARM::t2LDRi12:
1570  case ARM::t2LDRBi12:
1571  case ARM::t2LDRSHi12:
1572    break;
1573  }
1574
1575  switch (Load2->getMachineOpcode()) {
1576  default:
1577    return false;
1578  case ARM::LDRi12:
1579  case ARM::LDRBi12:
1580  case ARM::LDRD:
1581  case ARM::LDRH:
1582  case ARM::LDRSB:
1583  case ARM::LDRSH:
1584  case ARM::VLDRD:
1585  case ARM::VLDRS:
1586  case ARM::t2LDRi8:
1587  case ARM::t2LDRBi8:
1588  case ARM::t2LDRSHi8:
1589  case ARM::t2LDRi12:
1590  case ARM::t2LDRBi12:
1591  case ARM::t2LDRSHi12:
1592    break;
1593  }
1594
1595  // Check if base addresses and chain operands match.
1596  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1597      Load1->getOperand(4) != Load2->getOperand(4))
1598    return false;
1599
1600  // Index should be Reg0.
1601  if (Load1->getOperand(3) != Load2->getOperand(3))
1602    return false;
1603
1604  // Determine the offsets.
1605  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1606      isa<ConstantSDNode>(Load2->getOperand(1))) {
1607    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1608    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1609    return true;
1610  }
1611
1612  return false;
1613}
1614
1615/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1616/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1617/// be scheduled togther. On some targets if two loads are loading from
1618/// addresses in the same cache line, it's better if they are scheduled
1619/// together. This function takes two integers that represent the load offsets
1620/// from the common base address. It returns true if it decides it's desirable
1621/// to schedule the two loads together. "NumLoads" is the number of loads that
1622/// have already been scheduled after Load1.
1623///
1624/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1625/// is permanently disabled.
1626bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1627                                               int64_t Offset1, int64_t Offset2,
1628                                               unsigned NumLoads) const {
1629  // Don't worry about Thumb: just ARM and Thumb2.
1630  if (Subtarget.isThumb1Only()) return false;
1631
1632  assert(Offset2 > Offset1);
1633
1634  if ((Offset2 - Offset1) / 8 > 64)
1635    return false;
1636
1637  // Check if the machine opcodes are different. If they are different
1638  // then we consider them to not be of the same base address,
1639  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1640  // In this case, they are considered to be the same because they are different
1641  // encoding forms of the same basic instruction.
1642  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1643      !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1644         Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1645        (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1646         Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1647    return false;  // FIXME: overly conservative?
1648
1649  // Four loads in a row should be sufficient.
1650  if (NumLoads >= 3)
1651    return false;
1652
1653  return true;
1654}
1655
1656bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1657                                            const MachineBasicBlock *MBB,
1658                                            const MachineFunction &MF) const {
1659  // Debug info is never a scheduling boundary. It's necessary to be explicit
1660  // due to the special treatment of IT instructions below, otherwise a
1661  // dbg_value followed by an IT will result in the IT instruction being
1662  // considered a scheduling hazard, which is wrong. It should be the actual
1663  // instruction preceding the dbg_value instruction(s), just like it is
1664  // when debug info is not present.
1665  if (MI->isDebugValue())
1666    return false;
1667
1668  // Terminators and labels can't be scheduled around.
1669  if (MI->isTerminator() || MI->isPosition())
1670    return true;
1671
1672  // Treat the start of the IT block as a scheduling boundary, but schedule
1673  // t2IT along with all instructions following it.
1674  // FIXME: This is a big hammer. But the alternative is to add all potential
1675  // true and anti dependencies to IT block instructions as implicit operands
1676  // to the t2IT instruction. The added compile time and complexity does not
1677  // seem worth it.
1678  MachineBasicBlock::const_iterator I = MI;
1679  // Make sure to skip any dbg_value instructions
1680  while (++I != MBB->end() && I->isDebugValue())
1681    ;
1682  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1683    return true;
1684
1685  // Don't attempt to schedule around any instruction that defines
1686  // a stack-oriented pointer, as it's unlikely to be profitable. This
1687  // saves compile time, because it doesn't require every single
1688  // stack slot reference to depend on the instruction that does the
1689  // modification.
1690  // Calls don't actually change the stack pointer, even if they have imp-defs.
1691  // No ARM calling conventions change the stack pointer. (X86 calling
1692  // conventions sometimes do).
1693  if (!MI->isCall() && MI->definesRegister(ARM::SP))
1694    return true;
1695
1696  return false;
1697}
1698
1699bool ARMBaseInstrInfo::
1700isProfitableToIfCvt(MachineBasicBlock &MBB,
1701                    unsigned NumCycles, unsigned ExtraPredCycles,
1702                    BranchProbability Probability) const {
1703  if (!NumCycles)
1704    return false;
1705
1706  // If we are optimizing for size, see if the branch in the predecessor can be
1707  // lowered to cbn?z by the constant island lowering pass, and return false if
1708  // so. This results in a shorter instruction sequence.
1709  if (MBB.getParent()->getFunction()->optForSize()) {
1710    MachineBasicBlock *Pred = *MBB.pred_begin();
1711    if (!Pred->empty()) {
1712      MachineInstr *LastMI = &*Pred->rbegin();
1713      if (LastMI->getOpcode() == ARM::t2Bcc) {
1714        MachineBasicBlock::iterator CmpMI = LastMI;
1715        if (CmpMI != Pred->begin()) {
1716          --CmpMI;
1717          if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1718              CmpMI->getOpcode() == ARM::t2CMPri) {
1719            unsigned Reg = CmpMI->getOperand(0).getReg();
1720            unsigned PredReg = 0;
1721            ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1722            if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1723                isARMLowRegister(Reg))
1724              return false;
1725          }
1726        }
1727      }
1728    }
1729  }
1730
1731  // Attempt to estimate the relative costs of predication versus branching.
1732  // Here we scale up each component of UnpredCost to avoid precision issue when
1733  // scaling NumCycles by Probability.
1734  const unsigned ScalingUpFactor = 1024;
1735  unsigned UnpredCost = Probability.scale(NumCycles * ScalingUpFactor);
1736  UnpredCost += ScalingUpFactor; // The branch itself
1737  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1738
1739  return (NumCycles + ExtraPredCycles) * ScalingUpFactor <= UnpredCost;
1740}
1741
1742bool ARMBaseInstrInfo::
1743isProfitableToIfCvt(MachineBasicBlock &TMBB,
1744                    unsigned TCycles, unsigned TExtra,
1745                    MachineBasicBlock &FMBB,
1746                    unsigned FCycles, unsigned FExtra,
1747                    BranchProbability Probability) const {
1748  if (!TCycles || !FCycles)
1749    return false;
1750
1751  // Attempt to estimate the relative costs of predication versus branching.
1752  // Here we scale up each component of UnpredCost to avoid precision issue when
1753  // scaling TCycles/FCycles by Probability.
1754  const unsigned ScalingUpFactor = 1024;
1755  unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1756  unsigned FUnpredCost =
1757      Probability.getCompl().scale(FCycles * ScalingUpFactor);
1758  unsigned UnpredCost = TUnpredCost + FUnpredCost;
1759  UnpredCost += 1 * ScalingUpFactor; // The branch itself
1760  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1761
1762  return (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor <= UnpredCost;
1763}
1764
1765bool
1766ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1767                                            MachineBasicBlock &FMBB) const {
1768  // Reduce false anti-dependencies to let Swift's out-of-order execution
1769  // engine do its thing.
1770  return Subtarget.isSwift();
1771}
1772
1773/// getInstrPredicate - If instruction is predicated, returns its predicate
1774/// condition, otherwise returns AL. It also returns the condition code
1775/// register by reference.
1776ARMCC::CondCodes
1777llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1778  int PIdx = MI->findFirstPredOperandIdx();
1779  if (PIdx == -1) {
1780    PredReg = 0;
1781    return ARMCC::AL;
1782  }
1783
1784  PredReg = MI->getOperand(PIdx+1).getReg();
1785  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1786}
1787
1788
1789unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1790  if (Opc == ARM::B)
1791    return ARM::Bcc;
1792  if (Opc == ARM::tB)
1793    return ARM::tBcc;
1794  if (Opc == ARM::t2B)
1795    return ARM::t2Bcc;
1796
1797  llvm_unreachable("Unknown unconditional branch opcode!");
1798}
1799
1800MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr *MI,
1801                                                       bool NewMI,
1802                                                       unsigned OpIdx1,
1803                                                       unsigned OpIdx2) const {
1804  switch (MI->getOpcode()) {
1805  case ARM::MOVCCr:
1806  case ARM::t2MOVCCr: {
1807    // MOVCC can be commuted by inverting the condition.
1808    unsigned PredReg = 0;
1809    ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1810    // MOVCC AL can't be inverted. Shouldn't happen.
1811    if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1812      return nullptr;
1813    MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1814    if (!MI)
1815      return nullptr;
1816    // After swapping the MOVCC operands, also invert the condition.
1817    MI->getOperand(MI->findFirstPredOperandIdx())
1818      .setImm(ARMCC::getOppositeCondition(CC));
1819    return MI;
1820  }
1821  }
1822  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1823}
1824
1825/// Identify instructions that can be folded into a MOVCC instruction, and
1826/// return the defining instruction.
1827static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1828                                      const MachineRegisterInfo &MRI,
1829                                      const TargetInstrInfo *TII) {
1830  if (!TargetRegisterInfo::isVirtualRegister(Reg))
1831    return nullptr;
1832  if (!MRI.hasOneNonDBGUse(Reg))
1833    return nullptr;
1834  MachineInstr *MI = MRI.getVRegDef(Reg);
1835  if (!MI)
1836    return nullptr;
1837  // MI is folded into the MOVCC by predicating it.
1838  if (!MI->isPredicable())
1839    return nullptr;
1840  // Check if MI has any non-dead defs or physreg uses. This also detects
1841  // predicated instructions which will be reading CPSR.
1842  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1843    const MachineOperand &MO = MI->getOperand(i);
1844    // Reject frame index operands, PEI can't handle the predicated pseudos.
1845    if (MO.isFI() || MO.isCPI() || MO.isJTI())
1846      return nullptr;
1847    if (!MO.isReg())
1848      continue;
1849    // MI can't have any tied operands, that would conflict with predication.
1850    if (MO.isTied())
1851      return nullptr;
1852    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1853      return nullptr;
1854    if (MO.isDef() && !MO.isDead())
1855      return nullptr;
1856  }
1857  bool DontMoveAcrossStores = true;
1858  if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1859    return nullptr;
1860  return MI;
1861}
1862
1863bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1864                                     SmallVectorImpl<MachineOperand> &Cond,
1865                                     unsigned &TrueOp, unsigned &FalseOp,
1866                                     bool &Optimizable) const {
1867  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1868         "Unknown select instruction");
1869  // MOVCC operands:
1870  // 0: Def.
1871  // 1: True use.
1872  // 2: False use.
1873  // 3: Condition code.
1874  // 4: CPSR use.
1875  TrueOp = 1;
1876  FalseOp = 2;
1877  Cond.push_back(MI->getOperand(3));
1878  Cond.push_back(MI->getOperand(4));
1879  // We can always fold a def.
1880  Optimizable = true;
1881  return false;
1882}
1883
1884MachineInstr *
1885ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1886                                 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1887                                 bool PreferFalse) const {
1888  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1889         "Unknown select instruction");
1890  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1891  MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1892  bool Invert = !DefMI;
1893  if (!DefMI)
1894    DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1895  if (!DefMI)
1896    return nullptr;
1897
1898  // Find new register class to use.
1899  MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1900  unsigned       DestReg  = MI->getOperand(0).getReg();
1901  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1902  if (!MRI.constrainRegClass(DestReg, PreviousClass))
1903    return nullptr;
1904
1905  // Create a new predicated version of DefMI.
1906  // Rfalse is the first use.
1907  MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1908                                      DefMI->getDesc(), DestReg);
1909
1910  // Copy all the DefMI operands, excluding its (null) predicate.
1911  const MCInstrDesc &DefDesc = DefMI->getDesc();
1912  for (unsigned i = 1, e = DefDesc.getNumOperands();
1913       i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1914    NewMI.addOperand(DefMI->getOperand(i));
1915
1916  unsigned CondCode = MI->getOperand(3).getImm();
1917  if (Invert)
1918    NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1919  else
1920    NewMI.addImm(CondCode);
1921  NewMI.addOperand(MI->getOperand(4));
1922
1923  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1924  if (NewMI->hasOptionalDef())
1925    AddDefaultCC(NewMI);
1926
1927  // The output register value when the predicate is false is an implicit
1928  // register operand tied to the first def.
1929  // The tie makes the register allocator ensure the FalseReg is allocated the
1930  // same register as operand 0.
1931  FalseReg.setImplicit();
1932  NewMI.addOperand(FalseReg);
1933  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1934
1935  // Update SeenMIs set: register newly created MI and erase removed DefMI.
1936  SeenMIs.insert(NewMI);
1937  SeenMIs.erase(DefMI);
1938
1939  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1940  // DefMI would be invalid when tranferred inside the loop.  Checking for a
1941  // loop is expensive, but at least remove kill flags if they are in different
1942  // BBs.
1943  if (DefMI->getParent() != MI->getParent())
1944    NewMI->clearKillInfo();
1945
1946  // The caller will erase MI, but not DefMI.
1947  DefMI->eraseFromParent();
1948  return NewMI;
1949}
1950
1951/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1952/// instruction is encoded with an 'S' bit is determined by the optional CPSR
1953/// def operand.
1954///
1955/// This will go away once we can teach tblgen how to set the optional CPSR def
1956/// operand itself.
1957struct AddSubFlagsOpcodePair {
1958  uint16_t PseudoOpc;
1959  uint16_t MachineOpc;
1960};
1961
1962static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1963  {ARM::ADDSri, ARM::ADDri},
1964  {ARM::ADDSrr, ARM::ADDrr},
1965  {ARM::ADDSrsi, ARM::ADDrsi},
1966  {ARM::ADDSrsr, ARM::ADDrsr},
1967
1968  {ARM::SUBSri, ARM::SUBri},
1969  {ARM::SUBSrr, ARM::SUBrr},
1970  {ARM::SUBSrsi, ARM::SUBrsi},
1971  {ARM::SUBSrsr, ARM::SUBrsr},
1972
1973  {ARM::RSBSri, ARM::RSBri},
1974  {ARM::RSBSrsi, ARM::RSBrsi},
1975  {ARM::RSBSrsr, ARM::RSBrsr},
1976
1977  {ARM::t2ADDSri, ARM::t2ADDri},
1978  {ARM::t2ADDSrr, ARM::t2ADDrr},
1979  {ARM::t2ADDSrs, ARM::t2ADDrs},
1980
1981  {ARM::t2SUBSri, ARM::t2SUBri},
1982  {ARM::t2SUBSrr, ARM::t2SUBrr},
1983  {ARM::t2SUBSrs, ARM::t2SUBrs},
1984
1985  {ARM::t2RSBSri, ARM::t2RSBri},
1986  {ARM::t2RSBSrs, ARM::t2RSBrs},
1987};
1988
1989unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1990  for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1991    if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1992      return AddSubFlagsOpcodeMap[i].MachineOpc;
1993  return 0;
1994}
1995
1996void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1997                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1998                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1999                               ARMCC::CondCodes Pred, unsigned PredReg,
2000                               const ARMBaseInstrInfo &TII, unsigned MIFlags) {
2001  if (NumBytes == 0 && DestReg != BaseReg) {
2002    BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2003      .addReg(BaseReg, RegState::Kill)
2004      .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2005      .setMIFlags(MIFlags);
2006    return;
2007  }
2008
2009  bool isSub = NumBytes < 0;
2010  if (isSub) NumBytes = -NumBytes;
2011
2012  while (NumBytes) {
2013    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2014    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2015    assert(ThisVal && "Didn't extract field correctly");
2016
2017    // We will handle these bits from offset, clear them.
2018    NumBytes &= ~ThisVal;
2019
2020    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2021
2022    // Build the new ADD / SUB.
2023    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2024    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2025      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
2026      .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2027      .setMIFlags(MIFlags);
2028    BaseReg = DestReg;
2029  }
2030}
2031
2032bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
2033                                      MachineFunction &MF, MachineInstr *MI,
2034                                      unsigned NumBytes) {
2035  // This optimisation potentially adds lots of load and store
2036  // micro-operations, it's only really a great benefit to code-size.
2037  if (!MF.getFunction()->optForMinSize())
2038    return false;
2039
2040  // If only one register is pushed/popped, LLVM can use an LDR/STR
2041  // instead. We can't modify those so make sure we're dealing with an
2042  // instruction we understand.
2043  bool IsPop = isPopOpcode(MI->getOpcode());
2044  bool IsPush = isPushOpcode(MI->getOpcode());
2045  if (!IsPush && !IsPop)
2046    return false;
2047
2048  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2049                      MI->getOpcode() == ARM::VLDMDIA_UPD;
2050  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2051                     MI->getOpcode() == ARM::tPOP ||
2052                     MI->getOpcode() == ARM::tPOP_RET;
2053
2054  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2055                          MI->getOperand(1).getReg() == ARM::SP)) &&
2056         "trying to fold sp update into non-sp-updating push/pop");
2057
2058  // The VFP push & pop act on D-registers, so we can only fold an adjustment
2059  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2060  // if this is violated.
2061  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2062    return false;
2063
2064  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2065  // pred) so the list starts at 4. Thumb1 starts after the predicate.
2066  int RegListIdx = IsT1PushPop ? 2 : 4;
2067
2068  // Calculate the space we'll need in terms of registers.
2069  unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2070  unsigned RD0Reg, RegsNeeded;
2071  if (IsVFPPushPop) {
2072    RD0Reg = ARM::D0;
2073    RegsNeeded = NumBytes / 8;
2074  } else {
2075    RD0Reg = ARM::R0;
2076    RegsNeeded = NumBytes / 4;
2077  }
2078
2079  // We're going to have to strip all list operands off before
2080  // re-adding them since the order matters, so save the existing ones
2081  // for later.
2082  SmallVector<MachineOperand, 4> RegList;
2083  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2084    RegList.push_back(MI->getOperand(i));
2085
2086  const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2087  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2088
2089  // Now try to find enough space in the reglist to allocate NumBytes.
2090  for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2091       --CurReg) {
2092    if (!IsPop) {
2093      // Pushing any register is completely harmless, mark the
2094      // register involved as undef since we don't care about it in
2095      // the slightest.
2096      RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2097                                                  false, false, true));
2098      --RegsNeeded;
2099      continue;
2100    }
2101
2102    // However, we can only pop an extra register if it's not live. For
2103    // registers live within the function we might clobber a return value
2104    // register; the other way a register can be live here is if it's
2105    // callee-saved.
2106    if (isCalleeSavedRegister(CurReg, CSRegs) ||
2107        MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2108        MachineBasicBlock::LQR_Dead) {
2109      // VFP pops don't allow holes in the register list, so any skip is fatal
2110      // for our transformation. GPR pops do, so we should just keep looking.
2111      if (IsVFPPushPop)
2112        return false;
2113      else
2114        continue;
2115    }
2116
2117    // Mark the unimportant registers as <def,dead> in the POP.
2118    RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2119                                                true));
2120    --RegsNeeded;
2121  }
2122
2123  if (RegsNeeded > 0)
2124    return false;
2125
2126  // Finally we know we can profitably perform the optimisation so go
2127  // ahead: strip all existing registers off and add them back again
2128  // in the right order.
2129  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2130    MI->RemoveOperand(i);
2131
2132  // Add the complete list back in.
2133  MachineInstrBuilder MIB(MF, &*MI);
2134  for (int i = RegList.size() - 1; i >= 0; --i)
2135    MIB.addOperand(RegList[i]);
2136
2137  return true;
2138}
2139
2140bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2141                                unsigned FrameReg, int &Offset,
2142                                const ARMBaseInstrInfo &TII) {
2143  unsigned Opcode = MI.getOpcode();
2144  const MCInstrDesc &Desc = MI.getDesc();
2145  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2146  bool isSub = false;
2147
2148  // Memory operands in inline assembly always use AddrMode2.
2149  if (Opcode == ARM::INLINEASM)
2150    AddrMode = ARMII::AddrMode2;
2151
2152  if (Opcode == ARM::ADDri) {
2153    Offset += MI.getOperand(FrameRegIdx+1).getImm();
2154    if (Offset == 0) {
2155      // Turn it into a move.
2156      MI.setDesc(TII.get(ARM::MOVr));
2157      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2158      MI.RemoveOperand(FrameRegIdx+1);
2159      Offset = 0;
2160      return true;
2161    } else if (Offset < 0) {
2162      Offset = -Offset;
2163      isSub = true;
2164      MI.setDesc(TII.get(ARM::SUBri));
2165    }
2166
2167    // Common case: small offset, fits into instruction.
2168    if (ARM_AM::getSOImmVal(Offset) != -1) {
2169      // Replace the FrameIndex with sp / fp
2170      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2171      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2172      Offset = 0;
2173      return true;
2174    }
2175
2176    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2177    // as possible.
2178    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2179    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2180
2181    // We will handle these bits from offset, clear them.
2182    Offset &= ~ThisImmVal;
2183
2184    // Get the properly encoded SOImmVal field.
2185    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2186           "Bit extraction didn't work?");
2187    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2188 } else {
2189    unsigned ImmIdx = 0;
2190    int InstrOffs = 0;
2191    unsigned NumBits = 0;
2192    unsigned Scale = 1;
2193    switch (AddrMode) {
2194    case ARMII::AddrMode_i12: {
2195      ImmIdx = FrameRegIdx + 1;
2196      InstrOffs = MI.getOperand(ImmIdx).getImm();
2197      NumBits = 12;
2198      break;
2199    }
2200    case ARMII::AddrMode2: {
2201      ImmIdx = FrameRegIdx+2;
2202      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2203      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2204        InstrOffs *= -1;
2205      NumBits = 12;
2206      break;
2207    }
2208    case ARMII::AddrMode3: {
2209      ImmIdx = FrameRegIdx+2;
2210      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2211      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2212        InstrOffs *= -1;
2213      NumBits = 8;
2214      break;
2215    }
2216    case ARMII::AddrMode4:
2217    case ARMII::AddrMode6:
2218      // Can't fold any offset even if it's zero.
2219      return false;
2220    case ARMII::AddrMode5: {
2221      ImmIdx = FrameRegIdx+1;
2222      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2223      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2224        InstrOffs *= -1;
2225      NumBits = 8;
2226      Scale = 4;
2227      break;
2228    }
2229    default:
2230      llvm_unreachable("Unsupported addressing mode!");
2231    }
2232
2233    Offset += InstrOffs * Scale;
2234    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2235    if (Offset < 0) {
2236      Offset = -Offset;
2237      isSub = true;
2238    }
2239
2240    // Attempt to fold address comp. if opcode has offset bits
2241    if (NumBits > 0) {
2242      // Common case: small offset, fits into instruction.
2243      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2244      int ImmedOffset = Offset / Scale;
2245      unsigned Mask = (1 << NumBits) - 1;
2246      if ((unsigned)Offset <= Mask * Scale) {
2247        // Replace the FrameIndex with sp
2248        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2249        // FIXME: When addrmode2 goes away, this will simplify (like the
2250        // T2 version), as the LDR.i12 versions don't need the encoding
2251        // tricks for the offset value.
2252        if (isSub) {
2253          if (AddrMode == ARMII::AddrMode_i12)
2254            ImmedOffset = -ImmedOffset;
2255          else
2256            ImmedOffset |= 1 << NumBits;
2257        }
2258        ImmOp.ChangeToImmediate(ImmedOffset);
2259        Offset = 0;
2260        return true;
2261      }
2262
2263      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2264      ImmedOffset = ImmedOffset & Mask;
2265      if (isSub) {
2266        if (AddrMode == ARMII::AddrMode_i12)
2267          ImmedOffset = -ImmedOffset;
2268        else
2269          ImmedOffset |= 1 << NumBits;
2270      }
2271      ImmOp.ChangeToImmediate(ImmedOffset);
2272      Offset &= ~(Mask*Scale);
2273    }
2274  }
2275
2276  Offset = (isSub) ? -Offset : Offset;
2277  return Offset == 0;
2278}
2279
2280/// analyzeCompare - For a comparison instruction, return the source registers
2281/// in SrcReg and SrcReg2 if having two register operands, and the value it
2282/// compares against in CmpValue. Return true if the comparison instruction
2283/// can be analyzed.
2284bool ARMBaseInstrInfo::
2285analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2286               int &CmpMask, int &CmpValue) const {
2287  switch (MI->getOpcode()) {
2288  default: break;
2289  case ARM::CMPri:
2290  case ARM::t2CMPri:
2291    SrcReg = MI->getOperand(0).getReg();
2292    SrcReg2 = 0;
2293    CmpMask = ~0;
2294    CmpValue = MI->getOperand(1).getImm();
2295    return true;
2296  case ARM::CMPrr:
2297  case ARM::t2CMPrr:
2298    SrcReg = MI->getOperand(0).getReg();
2299    SrcReg2 = MI->getOperand(1).getReg();
2300    CmpMask = ~0;
2301    CmpValue = 0;
2302    return true;
2303  case ARM::TSTri:
2304  case ARM::t2TSTri:
2305    SrcReg = MI->getOperand(0).getReg();
2306    SrcReg2 = 0;
2307    CmpMask = MI->getOperand(1).getImm();
2308    CmpValue = 0;
2309    return true;
2310  }
2311
2312  return false;
2313}
2314
2315/// isSuitableForMask - Identify a suitable 'and' instruction that
2316/// operates on the given source register and applies the same mask
2317/// as a 'tst' instruction. Provide a limited look-through for copies.
2318/// When successful, MI will hold the found instruction.
2319static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2320                              int CmpMask, bool CommonUse) {
2321  switch (MI->getOpcode()) {
2322    case ARM::ANDri:
2323    case ARM::t2ANDri:
2324      if (CmpMask != MI->getOperand(2).getImm())
2325        return false;
2326      if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2327        return true;
2328      break;
2329  }
2330
2331  return false;
2332}
2333
2334/// getSwappedCondition - assume the flags are set by MI(a,b), return
2335/// the condition code if we modify the instructions such that flags are
2336/// set by MI(b,a).
2337inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2338  switch (CC) {
2339  default: return ARMCC::AL;
2340  case ARMCC::EQ: return ARMCC::EQ;
2341  case ARMCC::NE: return ARMCC::NE;
2342  case ARMCC::HS: return ARMCC::LS;
2343  case ARMCC::LO: return ARMCC::HI;
2344  case ARMCC::HI: return ARMCC::LO;
2345  case ARMCC::LS: return ARMCC::HS;
2346  case ARMCC::GE: return ARMCC::LE;
2347  case ARMCC::LT: return ARMCC::GT;
2348  case ARMCC::GT: return ARMCC::LT;
2349  case ARMCC::LE: return ARMCC::GE;
2350  }
2351}
2352
2353/// isRedundantFlagInstr - check whether the first instruction, whose only
2354/// purpose is to update flags, can be made redundant.
2355/// CMPrr can be made redundant by SUBrr if the operands are the same.
2356/// CMPri can be made redundant by SUBri if the operands are the same.
2357/// This function can be extended later on.
2358inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2359                                        unsigned SrcReg2, int ImmValue,
2360                                        MachineInstr *OI) {
2361  if ((CmpI->getOpcode() == ARM::CMPrr ||
2362       CmpI->getOpcode() == ARM::t2CMPrr) &&
2363      (OI->getOpcode() == ARM::SUBrr ||
2364       OI->getOpcode() == ARM::t2SUBrr) &&
2365      ((OI->getOperand(1).getReg() == SrcReg &&
2366        OI->getOperand(2).getReg() == SrcReg2) ||
2367       (OI->getOperand(1).getReg() == SrcReg2 &&
2368        OI->getOperand(2).getReg() == SrcReg)))
2369    return true;
2370
2371  if ((CmpI->getOpcode() == ARM::CMPri ||
2372       CmpI->getOpcode() == ARM::t2CMPri) &&
2373      (OI->getOpcode() == ARM::SUBri ||
2374       OI->getOpcode() == ARM::t2SUBri) &&
2375      OI->getOperand(1).getReg() == SrcReg &&
2376      OI->getOperand(2).getImm() == ImmValue)
2377    return true;
2378  return false;
2379}
2380
2381/// optimizeCompareInstr - Convert the instruction supplying the argument to the
2382/// comparison into one that sets the zero bit in the flags register;
2383/// Remove a redundant Compare instruction if an earlier instruction can set the
2384/// flags in the same way as Compare.
2385/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2386/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2387/// condition code of instructions which use the flags.
2388bool ARMBaseInstrInfo::
2389optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2390                     int CmpMask, int CmpValue,
2391                     const MachineRegisterInfo *MRI) const {
2392  // Get the unique definition of SrcReg.
2393  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2394  if (!MI) return false;
2395
2396  // Masked compares sometimes use the same register as the corresponding 'and'.
2397  if (CmpMask != ~0) {
2398    if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2399      MI = nullptr;
2400      for (MachineRegisterInfo::use_instr_iterator
2401           UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2402           UI != UE; ++UI) {
2403        if (UI->getParent() != CmpInstr->getParent()) continue;
2404        MachineInstr *PotentialAND = &*UI;
2405        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2406            isPredicated(PotentialAND))
2407          continue;
2408        MI = PotentialAND;
2409        break;
2410      }
2411      if (!MI) return false;
2412    }
2413  }
2414
2415  // Get ready to iterate backward from CmpInstr.
2416  MachineBasicBlock::iterator I = CmpInstr, E = MI,
2417                              B = CmpInstr->getParent()->begin();
2418
2419  // Early exit if CmpInstr is at the beginning of the BB.
2420  if (I == B) return false;
2421
2422  // There are two possible candidates which can be changed to set CPSR:
2423  // One is MI, the other is a SUB instruction.
2424  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2425  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2426  MachineInstr *Sub = nullptr;
2427  if (SrcReg2 != 0)
2428    // MI is not a candidate for CMPrr.
2429    MI = nullptr;
2430  else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2431    // Conservatively refuse to convert an instruction which isn't in the same
2432    // BB as the comparison.
2433    // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2434    // Thus we cannot return here.
2435    if (CmpInstr->getOpcode() == ARM::CMPri ||
2436       CmpInstr->getOpcode() == ARM::t2CMPri)
2437      MI = nullptr;
2438    else
2439      return false;
2440  }
2441
2442  // Check that CPSR isn't set between the comparison instruction and the one we
2443  // want to change. At the same time, search for Sub.
2444  const TargetRegisterInfo *TRI = &getRegisterInfo();
2445  --I;
2446  for (; I != E; --I) {
2447    const MachineInstr &Instr = *I;
2448
2449    if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2450        Instr.readsRegister(ARM::CPSR, TRI))
2451      // This instruction modifies or uses CPSR after the one we want to
2452      // change. We can't do this transformation.
2453      return false;
2454
2455    // Check whether CmpInstr can be made redundant by the current instruction.
2456    if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2457      Sub = &*I;
2458      break;
2459    }
2460
2461    if (I == B)
2462      // The 'and' is below the comparison instruction.
2463      return false;
2464  }
2465
2466  // Return false if no candidates exist.
2467  if (!MI && !Sub)
2468    return false;
2469
2470  // The single candidate is called MI.
2471  if (!MI) MI = Sub;
2472
2473  // We can't use a predicated instruction - it doesn't always write the flags.
2474  if (isPredicated(MI))
2475    return false;
2476
2477  switch (MI->getOpcode()) {
2478  default: break;
2479  case ARM::RSBrr:
2480  case ARM::RSBri:
2481  case ARM::RSCrr:
2482  case ARM::RSCri:
2483  case ARM::ADDrr:
2484  case ARM::ADDri:
2485  case ARM::ADCrr:
2486  case ARM::ADCri:
2487  case ARM::SUBrr:
2488  case ARM::SUBri:
2489  case ARM::SBCrr:
2490  case ARM::SBCri:
2491  case ARM::t2RSBri:
2492  case ARM::t2ADDrr:
2493  case ARM::t2ADDri:
2494  case ARM::t2ADCrr:
2495  case ARM::t2ADCri:
2496  case ARM::t2SUBrr:
2497  case ARM::t2SUBri:
2498  case ARM::t2SBCrr:
2499  case ARM::t2SBCri:
2500  case ARM::ANDrr:
2501  case ARM::ANDri:
2502  case ARM::t2ANDrr:
2503  case ARM::t2ANDri:
2504  case ARM::ORRrr:
2505  case ARM::ORRri:
2506  case ARM::t2ORRrr:
2507  case ARM::t2ORRri:
2508  case ARM::EORrr:
2509  case ARM::EORri:
2510  case ARM::t2EORrr:
2511  case ARM::t2EORri: {
2512    // Scan forward for the use of CPSR
2513    // When checking against MI: if it's a conditional code that requires
2514    // checking of the V bit or C bit, then this is not safe to do.
2515    // It is safe to remove CmpInstr if CPSR is redefined or killed.
2516    // If we are done with the basic block, we need to check whether CPSR is
2517    // live-out.
2518    SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2519        OperandsToUpdate;
2520    bool isSafe = false;
2521    I = CmpInstr;
2522    E = CmpInstr->getParent()->end();
2523    while (!isSafe && ++I != E) {
2524      const MachineInstr &Instr = *I;
2525      for (unsigned IO = 0, EO = Instr.getNumOperands();
2526           !isSafe && IO != EO; ++IO) {
2527        const MachineOperand &MO = Instr.getOperand(IO);
2528        if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2529          isSafe = true;
2530          break;
2531        }
2532        if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2533          continue;
2534        if (MO.isDef()) {
2535          isSafe = true;
2536          break;
2537        }
2538        // Condition code is after the operand before CPSR except for VSELs.
2539        ARMCC::CondCodes CC;
2540        bool IsInstrVSel = true;
2541        switch (Instr.getOpcode()) {
2542        default:
2543          IsInstrVSel = false;
2544          CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2545          break;
2546        case ARM::VSELEQD:
2547        case ARM::VSELEQS:
2548          CC = ARMCC::EQ;
2549          break;
2550        case ARM::VSELGTD:
2551        case ARM::VSELGTS:
2552          CC = ARMCC::GT;
2553          break;
2554        case ARM::VSELGED:
2555        case ARM::VSELGES:
2556          CC = ARMCC::GE;
2557          break;
2558        case ARM::VSELVSS:
2559        case ARM::VSELVSD:
2560          CC = ARMCC::VS;
2561          break;
2562        }
2563
2564        if (Sub) {
2565          ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2566          if (NewCC == ARMCC::AL)
2567            return false;
2568          // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2569          // on CMP needs to be updated to be based on SUB.
2570          // Push the condition code operands to OperandsToUpdate.
2571          // If it is safe to remove CmpInstr, the condition code of these
2572          // operands will be modified.
2573          if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2574              Sub->getOperand(2).getReg() == SrcReg) {
2575            // VSel doesn't support condition code update.
2576            if (IsInstrVSel)
2577              return false;
2578            OperandsToUpdate.push_back(
2579                std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2580          }
2581        } else {
2582          // No Sub, so this is x = <op> y, z; cmp x, 0.
2583          switch (CC) {
2584          case ARMCC::EQ: // Z
2585          case ARMCC::NE: // Z
2586          case ARMCC::MI: // N
2587          case ARMCC::PL: // N
2588          case ARMCC::AL: // none
2589            // CPSR can be used multiple times, we should continue.
2590            break;
2591          case ARMCC::HS: // C
2592          case ARMCC::LO: // C
2593          case ARMCC::VS: // V
2594          case ARMCC::VC: // V
2595          case ARMCC::HI: // C Z
2596          case ARMCC::LS: // C Z
2597          case ARMCC::GE: // N V
2598          case ARMCC::LT: // N V
2599          case ARMCC::GT: // Z N V
2600          case ARMCC::LE: // Z N V
2601            // The instruction uses the V bit or C bit which is not safe.
2602            return false;
2603          }
2604        }
2605      }
2606    }
2607
2608    // If CPSR is not killed nor re-defined, we should check whether it is
2609    // live-out. If it is live-out, do not optimize.
2610    if (!isSafe) {
2611      MachineBasicBlock *MBB = CmpInstr->getParent();
2612      for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2613               SE = MBB->succ_end(); SI != SE; ++SI)
2614        if ((*SI)->isLiveIn(ARM::CPSR))
2615          return false;
2616    }
2617
2618    // Toggle the optional operand to CPSR.
2619    MI->getOperand(5).setReg(ARM::CPSR);
2620    MI->getOperand(5).setIsDef(true);
2621    assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2622    CmpInstr->eraseFromParent();
2623
2624    // Modify the condition code of operands in OperandsToUpdate.
2625    // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2626    // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2627    for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2628      OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2629    return true;
2630  }
2631  }
2632
2633  return false;
2634}
2635
2636bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2637                                     MachineInstr *DefMI, unsigned Reg,
2638                                     MachineRegisterInfo *MRI) const {
2639  // Fold large immediates into add, sub, or, xor.
2640  unsigned DefOpc = DefMI->getOpcode();
2641  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2642    return false;
2643  if (!DefMI->getOperand(1).isImm())
2644    // Could be t2MOVi32imm <ga:xx>
2645    return false;
2646
2647  if (!MRI->hasOneNonDBGUse(Reg))
2648    return false;
2649
2650  const MCInstrDesc &DefMCID = DefMI->getDesc();
2651  if (DefMCID.hasOptionalDef()) {
2652    unsigned NumOps = DefMCID.getNumOperands();
2653    const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2654    if (MO.getReg() == ARM::CPSR && !MO.isDead())
2655      // If DefMI defines CPSR and it is not dead, it's obviously not safe
2656      // to delete DefMI.
2657      return false;
2658  }
2659
2660  const MCInstrDesc &UseMCID = UseMI->getDesc();
2661  if (UseMCID.hasOptionalDef()) {
2662    unsigned NumOps = UseMCID.getNumOperands();
2663    if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2664      // If the instruction sets the flag, do not attempt this optimization
2665      // since it may change the semantics of the code.
2666      return false;
2667  }
2668
2669  unsigned UseOpc = UseMI->getOpcode();
2670  unsigned NewUseOpc = 0;
2671  uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2672  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2673  bool Commute = false;
2674  switch (UseOpc) {
2675  default: return false;
2676  case ARM::SUBrr:
2677  case ARM::ADDrr:
2678  case ARM::ORRrr:
2679  case ARM::EORrr:
2680  case ARM::t2SUBrr:
2681  case ARM::t2ADDrr:
2682  case ARM::t2ORRrr:
2683  case ARM::t2EORrr: {
2684    Commute = UseMI->getOperand(2).getReg() != Reg;
2685    switch (UseOpc) {
2686    default: break;
2687    case ARM::SUBrr: {
2688      if (Commute)
2689        return false;
2690      ImmVal = -ImmVal;
2691      NewUseOpc = ARM::SUBri;
2692      // Fallthrough
2693    }
2694    case ARM::ADDrr:
2695    case ARM::ORRrr:
2696    case ARM::EORrr: {
2697      if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2698        return false;
2699      SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2700      SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2701      switch (UseOpc) {
2702      default: break;
2703      case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2704      case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2705      case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2706      }
2707      break;
2708    }
2709    case ARM::t2SUBrr: {
2710      if (Commute)
2711        return false;
2712      ImmVal = -ImmVal;
2713      NewUseOpc = ARM::t2SUBri;
2714      // Fallthrough
2715    }
2716    case ARM::t2ADDrr:
2717    case ARM::t2ORRrr:
2718    case ARM::t2EORrr: {
2719      if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2720        return false;
2721      SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2722      SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2723      switch (UseOpc) {
2724      default: break;
2725      case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2726      case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2727      case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2728      }
2729      break;
2730    }
2731    }
2732  }
2733  }
2734
2735  unsigned OpIdx = Commute ? 2 : 1;
2736  unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2737  bool isKill = UseMI->getOperand(OpIdx).isKill();
2738  unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2739  AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2740                                      UseMI, UseMI->getDebugLoc(),
2741                                      get(NewUseOpc), NewReg)
2742                              .addReg(Reg1, getKillRegState(isKill))
2743                              .addImm(SOImmValV1)));
2744  UseMI->setDesc(get(NewUseOpc));
2745  UseMI->getOperand(1).setReg(NewReg);
2746  UseMI->getOperand(1).setIsKill();
2747  UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2748  DefMI->eraseFromParent();
2749  return true;
2750}
2751
2752static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2753                                        const MachineInstr *MI) {
2754  switch (MI->getOpcode()) {
2755  default: {
2756    const MCInstrDesc &Desc = MI->getDesc();
2757    int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2758    assert(UOps >= 0 && "bad # UOps");
2759    return UOps;
2760  }
2761
2762  case ARM::LDRrs:
2763  case ARM::LDRBrs:
2764  case ARM::STRrs:
2765  case ARM::STRBrs: {
2766    unsigned ShOpVal = MI->getOperand(3).getImm();
2767    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2768    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2769    if (!isSub &&
2770        (ShImm == 0 ||
2771         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2772          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2773      return 1;
2774    return 2;
2775  }
2776
2777  case ARM::LDRH:
2778  case ARM::STRH: {
2779    if (!MI->getOperand(2).getReg())
2780      return 1;
2781
2782    unsigned ShOpVal = MI->getOperand(3).getImm();
2783    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2784    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2785    if (!isSub &&
2786        (ShImm == 0 ||
2787         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2788          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2789      return 1;
2790    return 2;
2791  }
2792
2793  case ARM::LDRSB:
2794  case ARM::LDRSH:
2795    return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2796
2797  case ARM::LDRSB_POST:
2798  case ARM::LDRSH_POST: {
2799    unsigned Rt = MI->getOperand(0).getReg();
2800    unsigned Rm = MI->getOperand(3).getReg();
2801    return (Rt == Rm) ? 4 : 3;
2802  }
2803
2804  case ARM::LDR_PRE_REG:
2805  case ARM::LDRB_PRE_REG: {
2806    unsigned Rt = MI->getOperand(0).getReg();
2807    unsigned Rm = MI->getOperand(3).getReg();
2808    if (Rt == Rm)
2809      return 3;
2810    unsigned ShOpVal = MI->getOperand(4).getImm();
2811    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2812    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2813    if (!isSub &&
2814        (ShImm == 0 ||
2815         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2816          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2817      return 2;
2818    return 3;
2819  }
2820
2821  case ARM::STR_PRE_REG:
2822  case ARM::STRB_PRE_REG: {
2823    unsigned ShOpVal = MI->getOperand(4).getImm();
2824    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2825    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2826    if (!isSub &&
2827        (ShImm == 0 ||
2828         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2829          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2830      return 2;
2831    return 3;
2832  }
2833
2834  case ARM::LDRH_PRE:
2835  case ARM::STRH_PRE: {
2836    unsigned Rt = MI->getOperand(0).getReg();
2837    unsigned Rm = MI->getOperand(3).getReg();
2838    if (!Rm)
2839      return 2;
2840    if (Rt == Rm)
2841      return 3;
2842    return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2843      ? 3 : 2;
2844  }
2845
2846  case ARM::LDR_POST_REG:
2847  case ARM::LDRB_POST_REG:
2848  case ARM::LDRH_POST: {
2849    unsigned Rt = MI->getOperand(0).getReg();
2850    unsigned Rm = MI->getOperand(3).getReg();
2851    return (Rt == Rm) ? 3 : 2;
2852  }
2853
2854  case ARM::LDR_PRE_IMM:
2855  case ARM::LDRB_PRE_IMM:
2856  case ARM::LDR_POST_IMM:
2857  case ARM::LDRB_POST_IMM:
2858  case ARM::STRB_POST_IMM:
2859  case ARM::STRB_POST_REG:
2860  case ARM::STRB_PRE_IMM:
2861  case ARM::STRH_POST:
2862  case ARM::STR_POST_IMM:
2863  case ARM::STR_POST_REG:
2864  case ARM::STR_PRE_IMM:
2865    return 2;
2866
2867  case ARM::LDRSB_PRE:
2868  case ARM::LDRSH_PRE: {
2869    unsigned Rm = MI->getOperand(3).getReg();
2870    if (Rm == 0)
2871      return 3;
2872    unsigned Rt = MI->getOperand(0).getReg();
2873    if (Rt == Rm)
2874      return 4;
2875    unsigned ShOpVal = MI->getOperand(4).getImm();
2876    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2877    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2878    if (!isSub &&
2879        (ShImm == 0 ||
2880         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2881          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2882      return 3;
2883    return 4;
2884  }
2885
2886  case ARM::LDRD: {
2887    unsigned Rt = MI->getOperand(0).getReg();
2888    unsigned Rn = MI->getOperand(2).getReg();
2889    unsigned Rm = MI->getOperand(3).getReg();
2890    if (Rm)
2891      return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2892    return (Rt == Rn) ? 3 : 2;
2893  }
2894
2895  case ARM::STRD: {
2896    unsigned Rm = MI->getOperand(3).getReg();
2897    if (Rm)
2898      return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2899    return 2;
2900  }
2901
2902  case ARM::LDRD_POST:
2903  case ARM::t2LDRD_POST:
2904    return 3;
2905
2906  case ARM::STRD_POST:
2907  case ARM::t2STRD_POST:
2908    return 4;
2909
2910  case ARM::LDRD_PRE: {
2911    unsigned Rt = MI->getOperand(0).getReg();
2912    unsigned Rn = MI->getOperand(3).getReg();
2913    unsigned Rm = MI->getOperand(4).getReg();
2914    if (Rm)
2915      return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2916    return (Rt == Rn) ? 4 : 3;
2917  }
2918
2919  case ARM::t2LDRD_PRE: {
2920    unsigned Rt = MI->getOperand(0).getReg();
2921    unsigned Rn = MI->getOperand(3).getReg();
2922    return (Rt == Rn) ? 4 : 3;
2923  }
2924
2925  case ARM::STRD_PRE: {
2926    unsigned Rm = MI->getOperand(4).getReg();
2927    if (Rm)
2928      return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2929    return 3;
2930  }
2931
2932  case ARM::t2STRD_PRE:
2933    return 3;
2934
2935  case ARM::t2LDR_POST:
2936  case ARM::t2LDRB_POST:
2937  case ARM::t2LDRB_PRE:
2938  case ARM::t2LDRSBi12:
2939  case ARM::t2LDRSBi8:
2940  case ARM::t2LDRSBpci:
2941  case ARM::t2LDRSBs:
2942  case ARM::t2LDRH_POST:
2943  case ARM::t2LDRH_PRE:
2944  case ARM::t2LDRSBT:
2945  case ARM::t2LDRSB_POST:
2946  case ARM::t2LDRSB_PRE:
2947  case ARM::t2LDRSH_POST:
2948  case ARM::t2LDRSH_PRE:
2949  case ARM::t2LDRSHi12:
2950  case ARM::t2LDRSHi8:
2951  case ARM::t2LDRSHpci:
2952  case ARM::t2LDRSHs:
2953    return 2;
2954
2955  case ARM::t2LDRDi8: {
2956    unsigned Rt = MI->getOperand(0).getReg();
2957    unsigned Rn = MI->getOperand(2).getReg();
2958    return (Rt == Rn) ? 3 : 2;
2959  }
2960
2961  case ARM::t2STRB_POST:
2962  case ARM::t2STRB_PRE:
2963  case ARM::t2STRBs:
2964  case ARM::t2STRDi8:
2965  case ARM::t2STRH_POST:
2966  case ARM::t2STRH_PRE:
2967  case ARM::t2STRHs:
2968  case ARM::t2STR_POST:
2969  case ARM::t2STR_PRE:
2970  case ARM::t2STRs:
2971    return 2;
2972  }
2973}
2974
2975// Return the number of 32-bit words loaded by LDM or stored by STM. If this
2976// can't be easily determined return 0 (missing MachineMemOperand).
2977//
2978// FIXME: The current MachineInstr design does not support relying on machine
2979// mem operands to determine the width of a memory access. Instead, we expect
2980// the target to provide this information based on the instruction opcode and
2981// operands. However, using MachineMemOperand is the best solution now for
2982// two reasons:
2983//
2984// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2985// operands. This is much more dangerous than using the MachineMemOperand
2986// sizes because CodeGen passes can insert/remove optional machine operands. In
2987// fact, it's totally incorrect for preRA passes and appears to be wrong for
2988// postRA passes as well.
2989//
2990// 2) getNumLDMAddresses is only used by the scheduling machine model and any
2991// machine model that calls this should handle the unknown (zero size) case.
2992//
2993// Long term, we should require a target hook that verifies MachineMemOperand
2994// sizes during MC lowering. That target hook should be local to MC lowering
2995// because we can't ensure that it is aware of other MI forms. Doing this will
2996// ensure that MachineMemOperands are correctly propagated through all passes.
2997unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2998  unsigned Size = 0;
2999  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
3000         E = MI->memoperands_end(); I != E; ++I) {
3001    Size += (*I)->getSize();
3002  }
3003  return Size / 4;
3004}
3005
3006unsigned
3007ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3008                                 const MachineInstr *MI) const {
3009  if (!ItinData || ItinData->isEmpty())
3010    return 1;
3011
3012  const MCInstrDesc &Desc = MI->getDesc();
3013  unsigned Class = Desc.getSchedClass();
3014  int ItinUOps = ItinData->getNumMicroOps(Class);
3015  if (ItinUOps >= 0) {
3016    if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3017      return getNumMicroOpsSwiftLdSt(ItinData, MI);
3018
3019    return ItinUOps;
3020  }
3021
3022  unsigned Opc = MI->getOpcode();
3023  switch (Opc) {
3024  default:
3025    llvm_unreachable("Unexpected multi-uops instruction!");
3026  case ARM::VLDMQIA:
3027  case ARM::VSTMQIA:
3028    return 2;
3029
3030  // The number of uOps for load / store multiple are determined by the number
3031  // registers.
3032  //
3033  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3034  // same cycle. The scheduling for the first load / store must be done
3035  // separately by assuming the address is not 64-bit aligned.
3036  //
3037  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3038  // is not 64-bit aligned, then AGU would take an extra cycle.  For VFP / NEON
3039  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3040  case ARM::VLDMDIA:
3041  case ARM::VLDMDIA_UPD:
3042  case ARM::VLDMDDB_UPD:
3043  case ARM::VLDMSIA:
3044  case ARM::VLDMSIA_UPD:
3045  case ARM::VLDMSDB_UPD:
3046  case ARM::VSTMDIA:
3047  case ARM::VSTMDIA_UPD:
3048  case ARM::VSTMDDB_UPD:
3049  case ARM::VSTMSIA:
3050  case ARM::VSTMSIA_UPD:
3051  case ARM::VSTMSDB_UPD: {
3052    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3053    return (NumRegs / 2) + (NumRegs % 2) + 1;
3054  }
3055
3056  case ARM::LDMIA_RET:
3057  case ARM::LDMIA:
3058  case ARM::LDMDA:
3059  case ARM::LDMDB:
3060  case ARM::LDMIB:
3061  case ARM::LDMIA_UPD:
3062  case ARM::LDMDA_UPD:
3063  case ARM::LDMDB_UPD:
3064  case ARM::LDMIB_UPD:
3065  case ARM::STMIA:
3066  case ARM::STMDA:
3067  case ARM::STMDB:
3068  case ARM::STMIB:
3069  case ARM::STMIA_UPD:
3070  case ARM::STMDA_UPD:
3071  case ARM::STMDB_UPD:
3072  case ARM::STMIB_UPD:
3073  case ARM::tLDMIA:
3074  case ARM::tLDMIA_UPD:
3075  case ARM::tSTMIA_UPD:
3076  case ARM::tPOP_RET:
3077  case ARM::tPOP:
3078  case ARM::tPUSH:
3079  case ARM::t2LDMIA_RET:
3080  case ARM::t2LDMIA:
3081  case ARM::t2LDMDB:
3082  case ARM::t2LDMIA_UPD:
3083  case ARM::t2LDMDB_UPD:
3084  case ARM::t2STMIA:
3085  case ARM::t2STMDB:
3086  case ARM::t2STMIA_UPD:
3087  case ARM::t2STMDB_UPD: {
3088    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3089    if (Subtarget.isSwift()) {
3090      int UOps = 1 + NumRegs;  // One for address computation, one for each ld / st.
3091      switch (Opc) {
3092      default: break;
3093      case ARM::VLDMDIA_UPD:
3094      case ARM::VLDMDDB_UPD:
3095      case ARM::VLDMSIA_UPD:
3096      case ARM::VLDMSDB_UPD:
3097      case ARM::VSTMDIA_UPD:
3098      case ARM::VSTMDDB_UPD:
3099      case ARM::VSTMSIA_UPD:
3100      case ARM::VSTMSDB_UPD:
3101      case ARM::LDMIA_UPD:
3102      case ARM::LDMDA_UPD:
3103      case ARM::LDMDB_UPD:
3104      case ARM::LDMIB_UPD:
3105      case ARM::STMIA_UPD:
3106      case ARM::STMDA_UPD:
3107      case ARM::STMDB_UPD:
3108      case ARM::STMIB_UPD:
3109      case ARM::tLDMIA_UPD:
3110      case ARM::tSTMIA_UPD:
3111      case ARM::t2LDMIA_UPD:
3112      case ARM::t2LDMDB_UPD:
3113      case ARM::t2STMIA_UPD:
3114      case ARM::t2STMDB_UPD:
3115        ++UOps; // One for base register writeback.
3116        break;
3117      case ARM::LDMIA_RET:
3118      case ARM::tPOP_RET:
3119      case ARM::t2LDMIA_RET:
3120        UOps += 2; // One for base reg wb, one for write to pc.
3121        break;
3122      }
3123      return UOps;
3124    } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3125      if (NumRegs < 4)
3126        return 2;
3127      // 4 registers would be issued: 2, 2.
3128      // 5 registers would be issued: 2, 2, 1.
3129      int A8UOps = (NumRegs / 2);
3130      if (NumRegs % 2)
3131        ++A8UOps;
3132      return A8UOps;
3133    } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3134      int A9UOps = (NumRegs / 2);
3135      // If there are odd number of registers or if it's not 64-bit aligned,
3136      // then it takes an extra AGU (Address Generation Unit) cycle.
3137      if ((NumRegs % 2) ||
3138          !MI->hasOneMemOperand() ||
3139          (*MI->memoperands_begin())->getAlignment() < 8)
3140        ++A9UOps;
3141      return A9UOps;
3142    } else {
3143      // Assume the worst.
3144      return NumRegs;
3145    }
3146  }
3147  }
3148}
3149
3150int
3151ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3152                                  const MCInstrDesc &DefMCID,
3153                                  unsigned DefClass,
3154                                  unsigned DefIdx, unsigned DefAlign) const {
3155  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3156  if (RegNo <= 0)
3157    // Def is the address writeback.
3158    return ItinData->getOperandCycle(DefClass, DefIdx);
3159
3160  int DefCycle;
3161  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3162    // (regno / 2) + (regno % 2) + 1
3163    DefCycle = RegNo / 2 + 1;
3164    if (RegNo % 2)
3165      ++DefCycle;
3166  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3167    DefCycle = RegNo;
3168    bool isSLoad = false;
3169
3170    switch (DefMCID.getOpcode()) {
3171    default: break;
3172    case ARM::VLDMSIA:
3173    case ARM::VLDMSIA_UPD:
3174    case ARM::VLDMSDB_UPD:
3175      isSLoad = true;
3176      break;
3177    }
3178
3179    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3180    // then it takes an extra cycle.
3181    if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3182      ++DefCycle;
3183  } else {
3184    // Assume the worst.
3185    DefCycle = RegNo + 2;
3186  }
3187
3188  return DefCycle;
3189}
3190
3191int
3192ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3193                                 const MCInstrDesc &DefMCID,
3194                                 unsigned DefClass,
3195                                 unsigned DefIdx, unsigned DefAlign) const {
3196  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3197  if (RegNo <= 0)
3198    // Def is the address writeback.
3199    return ItinData->getOperandCycle(DefClass, DefIdx);
3200
3201  int DefCycle;
3202  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3203    // 4 registers would be issued: 1, 2, 1.
3204    // 5 registers would be issued: 1, 2, 2.
3205    DefCycle = RegNo / 2;
3206    if (DefCycle < 1)
3207      DefCycle = 1;
3208    // Result latency is issue cycle + 2: E2.
3209    DefCycle += 2;
3210  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3211    DefCycle = (RegNo / 2);
3212    // If there are odd number of registers or if it's not 64-bit aligned,
3213    // then it takes an extra AGU (Address Generation Unit) cycle.
3214    if ((RegNo % 2) || DefAlign < 8)
3215      ++DefCycle;
3216    // Result latency is AGU cycles + 2.
3217    DefCycle += 2;
3218  } else {
3219    // Assume the worst.
3220    DefCycle = RegNo + 2;
3221  }
3222
3223  return DefCycle;
3224}
3225
3226int
3227ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3228                                  const MCInstrDesc &UseMCID,
3229                                  unsigned UseClass,
3230                                  unsigned UseIdx, unsigned UseAlign) const {
3231  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3232  if (RegNo <= 0)
3233    return ItinData->getOperandCycle(UseClass, UseIdx);
3234
3235  int UseCycle;
3236  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3237    // (regno / 2) + (regno % 2) + 1
3238    UseCycle = RegNo / 2 + 1;
3239    if (RegNo % 2)
3240      ++UseCycle;
3241  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3242    UseCycle = RegNo;
3243    bool isSStore = false;
3244
3245    switch (UseMCID.getOpcode()) {
3246    default: break;
3247    case ARM::VSTMSIA:
3248    case ARM::VSTMSIA_UPD:
3249    case ARM::VSTMSDB_UPD:
3250      isSStore = true;
3251      break;
3252    }
3253
3254    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3255    // then it takes an extra cycle.
3256    if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3257      ++UseCycle;
3258  } else {
3259    // Assume the worst.
3260    UseCycle = RegNo + 2;
3261  }
3262
3263  return UseCycle;
3264}
3265
3266int
3267ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3268                                 const MCInstrDesc &UseMCID,
3269                                 unsigned UseClass,
3270                                 unsigned UseIdx, unsigned UseAlign) const {
3271  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3272  if (RegNo <= 0)
3273    return ItinData->getOperandCycle(UseClass, UseIdx);
3274
3275  int UseCycle;
3276  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3277    UseCycle = RegNo / 2;
3278    if (UseCycle < 2)
3279      UseCycle = 2;
3280    // Read in E3.
3281    UseCycle += 2;
3282  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3283    UseCycle = (RegNo / 2);
3284    // If there are odd number of registers or if it's not 64-bit aligned,
3285    // then it takes an extra AGU (Address Generation Unit) cycle.
3286    if ((RegNo % 2) || UseAlign < 8)
3287      ++UseCycle;
3288  } else {
3289    // Assume the worst.
3290    UseCycle = 1;
3291  }
3292  return UseCycle;
3293}
3294
3295int
3296ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3297                                    const MCInstrDesc &DefMCID,
3298                                    unsigned DefIdx, unsigned DefAlign,
3299                                    const MCInstrDesc &UseMCID,
3300                                    unsigned UseIdx, unsigned UseAlign) const {
3301  unsigned DefClass = DefMCID.getSchedClass();
3302  unsigned UseClass = UseMCID.getSchedClass();
3303
3304  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3305    return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3306
3307  // This may be a def / use of a variable_ops instruction, the operand
3308  // latency might be determinable dynamically. Let the target try to
3309  // figure it out.
3310  int DefCycle = -1;
3311  bool LdmBypass = false;
3312  switch (DefMCID.getOpcode()) {
3313  default:
3314    DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3315    break;
3316
3317  case ARM::VLDMDIA:
3318  case ARM::VLDMDIA_UPD:
3319  case ARM::VLDMDDB_UPD:
3320  case ARM::VLDMSIA:
3321  case ARM::VLDMSIA_UPD:
3322  case ARM::VLDMSDB_UPD:
3323    DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3324    break;
3325
3326  case ARM::LDMIA_RET:
3327  case ARM::LDMIA:
3328  case ARM::LDMDA:
3329  case ARM::LDMDB:
3330  case ARM::LDMIB:
3331  case ARM::LDMIA_UPD:
3332  case ARM::LDMDA_UPD:
3333  case ARM::LDMDB_UPD:
3334  case ARM::LDMIB_UPD:
3335  case ARM::tLDMIA:
3336  case ARM::tLDMIA_UPD:
3337  case ARM::tPUSH:
3338  case ARM::t2LDMIA_RET:
3339  case ARM::t2LDMIA:
3340  case ARM::t2LDMDB:
3341  case ARM::t2LDMIA_UPD:
3342  case ARM::t2LDMDB_UPD:
3343    LdmBypass = 1;
3344    DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3345    break;
3346  }
3347
3348  if (DefCycle == -1)
3349    // We can't seem to determine the result latency of the def, assume it's 2.
3350    DefCycle = 2;
3351
3352  int UseCycle = -1;
3353  switch (UseMCID.getOpcode()) {
3354  default:
3355    UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3356    break;
3357
3358  case ARM::VSTMDIA:
3359  case ARM::VSTMDIA_UPD:
3360  case ARM::VSTMDDB_UPD:
3361  case ARM::VSTMSIA:
3362  case ARM::VSTMSIA_UPD:
3363  case ARM::VSTMSDB_UPD:
3364    UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3365    break;
3366
3367  case ARM::STMIA:
3368  case ARM::STMDA:
3369  case ARM::STMDB:
3370  case ARM::STMIB:
3371  case ARM::STMIA_UPD:
3372  case ARM::STMDA_UPD:
3373  case ARM::STMDB_UPD:
3374  case ARM::STMIB_UPD:
3375  case ARM::tSTMIA_UPD:
3376  case ARM::tPOP_RET:
3377  case ARM::tPOP:
3378  case ARM::t2STMIA:
3379  case ARM::t2STMDB:
3380  case ARM::t2STMIA_UPD:
3381  case ARM::t2STMDB_UPD:
3382    UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3383    break;
3384  }
3385
3386  if (UseCycle == -1)
3387    // Assume it's read in the first stage.
3388    UseCycle = 1;
3389
3390  UseCycle = DefCycle - UseCycle + 1;
3391  if (UseCycle > 0) {
3392    if (LdmBypass) {
3393      // It's a variable_ops instruction so we can't use DefIdx here. Just use
3394      // first def operand.
3395      if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3396                                          UseClass, UseIdx))
3397        --UseCycle;
3398    } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3399                                               UseClass, UseIdx)) {
3400      --UseCycle;
3401    }
3402  }
3403
3404  return UseCycle;
3405}
3406
3407static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3408                                           const MachineInstr *MI, unsigned Reg,
3409                                           unsigned &DefIdx, unsigned &Dist) {
3410  Dist = 0;
3411
3412  MachineBasicBlock::const_iterator I = MI; ++I;
3413  MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3414  assert(II->isInsideBundle() && "Empty bundle?");
3415
3416  int Idx = -1;
3417  while (II->isInsideBundle()) {
3418    Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3419    if (Idx != -1)
3420      break;
3421    --II;
3422    ++Dist;
3423  }
3424
3425  assert(Idx != -1 && "Cannot find bundled definition!");
3426  DefIdx = Idx;
3427  return &*II;
3428}
3429
3430static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3431                                           const MachineInstr *MI, unsigned Reg,
3432                                           unsigned &UseIdx, unsigned &Dist) {
3433  Dist = 0;
3434
3435  MachineBasicBlock::const_instr_iterator II = ++MI->getIterator();
3436  assert(II->isInsideBundle() && "Empty bundle?");
3437  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3438
3439  // FIXME: This doesn't properly handle multiple uses.
3440  int Idx = -1;
3441  while (II != E && II->isInsideBundle()) {
3442    Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3443    if (Idx != -1)
3444      break;
3445    if (II->getOpcode() != ARM::t2IT)
3446      ++Dist;
3447    ++II;
3448  }
3449
3450  if (Idx == -1) {
3451    Dist = 0;
3452    return nullptr;
3453  }
3454
3455  UseIdx = Idx;
3456  return &*II;
3457}
3458
3459/// Return the number of cycles to add to (or subtract from) the static
3460/// itinerary based on the def opcode and alignment. The caller will ensure that
3461/// adjusted latency is at least one cycle.
3462static int adjustDefLatency(const ARMSubtarget &Subtarget,
3463                            const MachineInstr *DefMI,
3464                            const MCInstrDesc *DefMCID, unsigned DefAlign) {
3465  int Adjust = 0;
3466  if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3467    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3468    // variants are one cycle cheaper.
3469    switch (DefMCID->getOpcode()) {
3470    default: break;
3471    case ARM::LDRrs:
3472    case ARM::LDRBrs: {
3473      unsigned ShOpVal = DefMI->getOperand(3).getImm();
3474      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3475      if (ShImm == 0 ||
3476          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3477        --Adjust;
3478      break;
3479    }
3480    case ARM::t2LDRs:
3481    case ARM::t2LDRBs:
3482    case ARM::t2LDRHs:
3483    case ARM::t2LDRSHs: {
3484      // Thumb2 mode: lsl only.
3485      unsigned ShAmt = DefMI->getOperand(3).getImm();
3486      if (ShAmt == 0 || ShAmt == 2)
3487        --Adjust;
3488      break;
3489    }
3490    }
3491  } else if (Subtarget.isSwift()) {
3492    // FIXME: Properly handle all of the latency adjustments for address
3493    // writeback.
3494    switch (DefMCID->getOpcode()) {
3495    default: break;
3496    case ARM::LDRrs:
3497    case ARM::LDRBrs: {
3498      unsigned ShOpVal = DefMI->getOperand(3).getImm();
3499      bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3500      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3501      if (!isSub &&
3502          (ShImm == 0 ||
3503           ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3504            ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3505        Adjust -= 2;
3506      else if (!isSub &&
3507               ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3508        --Adjust;
3509      break;
3510    }
3511    case ARM::t2LDRs:
3512    case ARM::t2LDRBs:
3513    case ARM::t2LDRHs:
3514    case ARM::t2LDRSHs: {
3515      // Thumb2 mode: lsl only.
3516      unsigned ShAmt = DefMI->getOperand(3).getImm();
3517      if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3518        Adjust -= 2;
3519      break;
3520    }
3521    }
3522  }
3523
3524  if (DefAlign < 8 && Subtarget.isLikeA9()) {
3525    switch (DefMCID->getOpcode()) {
3526    default: break;
3527    case ARM::VLD1q8:
3528    case ARM::VLD1q16:
3529    case ARM::VLD1q32:
3530    case ARM::VLD1q64:
3531    case ARM::VLD1q8wb_fixed:
3532    case ARM::VLD1q16wb_fixed:
3533    case ARM::VLD1q32wb_fixed:
3534    case ARM::VLD1q64wb_fixed:
3535    case ARM::VLD1q8wb_register:
3536    case ARM::VLD1q16wb_register:
3537    case ARM::VLD1q32wb_register:
3538    case ARM::VLD1q64wb_register:
3539    case ARM::VLD2d8:
3540    case ARM::VLD2d16:
3541    case ARM::VLD2d32:
3542    case ARM::VLD2q8:
3543    case ARM::VLD2q16:
3544    case ARM::VLD2q32:
3545    case ARM::VLD2d8wb_fixed:
3546    case ARM::VLD2d16wb_fixed:
3547    case ARM::VLD2d32wb_fixed:
3548    case ARM::VLD2q8wb_fixed:
3549    case ARM::VLD2q16wb_fixed:
3550    case ARM::VLD2q32wb_fixed:
3551    case ARM::VLD2d8wb_register:
3552    case ARM::VLD2d16wb_register:
3553    case ARM::VLD2d32wb_register:
3554    case ARM::VLD2q8wb_register:
3555    case ARM::VLD2q16wb_register:
3556    case ARM::VLD2q32wb_register:
3557    case ARM::VLD3d8:
3558    case ARM::VLD3d16:
3559    case ARM::VLD3d32:
3560    case ARM::VLD1d64T:
3561    case ARM::VLD3d8_UPD:
3562    case ARM::VLD3d16_UPD:
3563    case ARM::VLD3d32_UPD:
3564    case ARM::VLD1d64Twb_fixed:
3565    case ARM::VLD1d64Twb_register:
3566    case ARM::VLD3q8_UPD:
3567    case ARM::VLD3q16_UPD:
3568    case ARM::VLD3q32_UPD:
3569    case ARM::VLD4d8:
3570    case ARM::VLD4d16:
3571    case ARM::VLD4d32:
3572    case ARM::VLD1d64Q:
3573    case ARM::VLD4d8_UPD:
3574    case ARM::VLD4d16_UPD:
3575    case ARM::VLD4d32_UPD:
3576    case ARM::VLD1d64Qwb_fixed:
3577    case ARM::VLD1d64Qwb_register:
3578    case ARM::VLD4q8_UPD:
3579    case ARM::VLD4q16_UPD:
3580    case ARM::VLD4q32_UPD:
3581    case ARM::VLD1DUPq8:
3582    case ARM::VLD1DUPq16:
3583    case ARM::VLD1DUPq32:
3584    case ARM::VLD1DUPq8wb_fixed:
3585    case ARM::VLD1DUPq16wb_fixed:
3586    case ARM::VLD1DUPq32wb_fixed:
3587    case ARM::VLD1DUPq8wb_register:
3588    case ARM::VLD1DUPq16wb_register:
3589    case ARM::VLD1DUPq32wb_register:
3590    case ARM::VLD2DUPd8:
3591    case ARM::VLD2DUPd16:
3592    case ARM::VLD2DUPd32:
3593    case ARM::VLD2DUPd8wb_fixed:
3594    case ARM::VLD2DUPd16wb_fixed:
3595    case ARM::VLD2DUPd32wb_fixed:
3596    case ARM::VLD2DUPd8wb_register:
3597    case ARM::VLD2DUPd16wb_register:
3598    case ARM::VLD2DUPd32wb_register:
3599    case ARM::VLD4DUPd8:
3600    case ARM::VLD4DUPd16:
3601    case ARM::VLD4DUPd32:
3602    case ARM::VLD4DUPd8_UPD:
3603    case ARM::VLD4DUPd16_UPD:
3604    case ARM::VLD4DUPd32_UPD:
3605    case ARM::VLD1LNd8:
3606    case ARM::VLD1LNd16:
3607    case ARM::VLD1LNd32:
3608    case ARM::VLD1LNd8_UPD:
3609    case ARM::VLD1LNd16_UPD:
3610    case ARM::VLD1LNd32_UPD:
3611    case ARM::VLD2LNd8:
3612    case ARM::VLD2LNd16:
3613    case ARM::VLD2LNd32:
3614    case ARM::VLD2LNq16:
3615    case ARM::VLD2LNq32:
3616    case ARM::VLD2LNd8_UPD:
3617    case ARM::VLD2LNd16_UPD:
3618    case ARM::VLD2LNd32_UPD:
3619    case ARM::VLD2LNq16_UPD:
3620    case ARM::VLD2LNq32_UPD:
3621    case ARM::VLD4LNd8:
3622    case ARM::VLD4LNd16:
3623    case ARM::VLD4LNd32:
3624    case ARM::VLD4LNq16:
3625    case ARM::VLD4LNq32:
3626    case ARM::VLD4LNd8_UPD:
3627    case ARM::VLD4LNd16_UPD:
3628    case ARM::VLD4LNd32_UPD:
3629    case ARM::VLD4LNq16_UPD:
3630    case ARM::VLD4LNq32_UPD:
3631      // If the address is not 64-bit aligned, the latencies of these
3632      // instructions increases by one.
3633      ++Adjust;
3634      break;
3635    }
3636  }
3637  return Adjust;
3638}
3639
3640
3641
3642int
3643ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3644                                    const MachineInstr *DefMI, unsigned DefIdx,
3645                                    const MachineInstr *UseMI,
3646                                    unsigned UseIdx) const {
3647  // No operand latency. The caller may fall back to getInstrLatency.
3648  if (!ItinData || ItinData->isEmpty())
3649    return -1;
3650
3651  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3652  unsigned Reg = DefMO.getReg();
3653  const MCInstrDesc *DefMCID = &DefMI->getDesc();
3654  const MCInstrDesc *UseMCID = &UseMI->getDesc();
3655
3656  unsigned DefAdj = 0;
3657  if (DefMI->isBundle()) {
3658    DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3659    DefMCID = &DefMI->getDesc();
3660  }
3661  if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3662      DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3663    return 1;
3664  }
3665
3666  unsigned UseAdj = 0;
3667  if (UseMI->isBundle()) {
3668    unsigned NewUseIdx;
3669    const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3670                                                   Reg, NewUseIdx, UseAdj);
3671    if (!NewUseMI)
3672      return -1;
3673
3674    UseMI = NewUseMI;
3675    UseIdx = NewUseIdx;
3676    UseMCID = &UseMI->getDesc();
3677  }
3678
3679  if (Reg == ARM::CPSR) {
3680    if (DefMI->getOpcode() == ARM::FMSTAT) {
3681      // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3682      return Subtarget.isLikeA9() ? 1 : 20;
3683    }
3684
3685    // CPSR set and branch can be paired in the same cycle.
3686    if (UseMI->isBranch())
3687      return 0;
3688
3689    // Otherwise it takes the instruction latency (generally one).
3690    unsigned Latency = getInstrLatency(ItinData, DefMI);
3691
3692    // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3693    // its uses. Instructions which are otherwise scheduled between them may
3694    // incur a code size penalty (not able to use the CPSR setting 16-bit
3695    // instructions).
3696    if (Latency > 0 && Subtarget.isThumb2()) {
3697      const MachineFunction *MF = DefMI->getParent()->getParent();
3698      // FIXME: Use Function::optForSize().
3699      if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3700        --Latency;
3701    }
3702    return Latency;
3703  }
3704
3705  if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3706    return -1;
3707
3708  unsigned DefAlign = DefMI->hasOneMemOperand()
3709    ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3710  unsigned UseAlign = UseMI->hasOneMemOperand()
3711    ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3712
3713  // Get the itinerary's latency if possible, and handle variable_ops.
3714  int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3715                                  *UseMCID, UseIdx, UseAlign);
3716  // Unable to find operand latency. The caller may resort to getInstrLatency.
3717  if (Latency < 0)
3718    return Latency;
3719
3720  // Adjust for IT block position.
3721  int Adj = DefAdj + UseAdj;
3722
3723  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3724  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3725  if (Adj >= 0 || (int)Latency > -Adj) {
3726    return Latency + Adj;
3727  }
3728  // Return the itinerary latency, which may be zero but not less than zero.
3729  return Latency;
3730}
3731
3732int
3733ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3734                                    SDNode *DefNode, unsigned DefIdx,
3735                                    SDNode *UseNode, unsigned UseIdx) const {
3736  if (!DefNode->isMachineOpcode())
3737    return 1;
3738
3739  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3740
3741  if (isZeroCost(DefMCID.Opcode))
3742    return 0;
3743
3744  if (!ItinData || ItinData->isEmpty())
3745    return DefMCID.mayLoad() ? 3 : 1;
3746
3747  if (!UseNode->isMachineOpcode()) {
3748    int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3749    if (Subtarget.isLikeA9() || Subtarget.isSwift())
3750      return Latency <= 2 ? 1 : Latency - 1;
3751    else
3752      return Latency <= 3 ? 1 : Latency - 2;
3753  }
3754
3755  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3756  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3757  unsigned DefAlign = !DefMN->memoperands_empty()
3758    ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3759  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3760  unsigned UseAlign = !UseMN->memoperands_empty()
3761    ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3762  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3763                                  UseMCID, UseIdx, UseAlign);
3764
3765  if (Latency > 1 &&
3766      (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3767       Subtarget.isCortexA7())) {
3768    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3769    // variants are one cycle cheaper.
3770    switch (DefMCID.getOpcode()) {
3771    default: break;
3772    case ARM::LDRrs:
3773    case ARM::LDRBrs: {
3774      unsigned ShOpVal =
3775        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3776      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3777      if (ShImm == 0 ||
3778          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3779        --Latency;
3780      break;
3781    }
3782    case ARM::t2LDRs:
3783    case ARM::t2LDRBs:
3784    case ARM::t2LDRHs:
3785    case ARM::t2LDRSHs: {
3786      // Thumb2 mode: lsl only.
3787      unsigned ShAmt =
3788        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3789      if (ShAmt == 0 || ShAmt == 2)
3790        --Latency;
3791      break;
3792    }
3793    }
3794  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3795    // FIXME: Properly handle all of the latency adjustments for address
3796    // writeback.
3797    switch (DefMCID.getOpcode()) {
3798    default: break;
3799    case ARM::LDRrs:
3800    case ARM::LDRBrs: {
3801      unsigned ShOpVal =
3802        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3803      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3804      if (ShImm == 0 ||
3805          ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3806           ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3807        Latency -= 2;
3808      else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3809        --Latency;
3810      break;
3811    }
3812    case ARM::t2LDRs:
3813    case ARM::t2LDRBs:
3814    case ARM::t2LDRHs:
3815    case ARM::t2LDRSHs: {
3816      // Thumb2 mode: lsl 0-3 only.
3817      Latency -= 2;
3818      break;
3819    }
3820    }
3821  }
3822
3823  if (DefAlign < 8 && Subtarget.isLikeA9())
3824    switch (DefMCID.getOpcode()) {
3825    default: break;
3826    case ARM::VLD1q8:
3827    case ARM::VLD1q16:
3828    case ARM::VLD1q32:
3829    case ARM::VLD1q64:
3830    case ARM::VLD1q8wb_register:
3831    case ARM::VLD1q16wb_register:
3832    case ARM::VLD1q32wb_register:
3833    case ARM::VLD1q64wb_register:
3834    case ARM::VLD1q8wb_fixed:
3835    case ARM::VLD1q16wb_fixed:
3836    case ARM::VLD1q32wb_fixed:
3837    case ARM::VLD1q64wb_fixed:
3838    case ARM::VLD2d8:
3839    case ARM::VLD2d16:
3840    case ARM::VLD2d32:
3841    case ARM::VLD2q8Pseudo:
3842    case ARM::VLD2q16Pseudo:
3843    case ARM::VLD2q32Pseudo:
3844    case ARM::VLD2d8wb_fixed:
3845    case ARM::VLD2d16wb_fixed:
3846    case ARM::VLD2d32wb_fixed:
3847    case ARM::VLD2q8PseudoWB_fixed:
3848    case ARM::VLD2q16PseudoWB_fixed:
3849    case ARM::VLD2q32PseudoWB_fixed:
3850    case ARM::VLD2d8wb_register:
3851    case ARM::VLD2d16wb_register:
3852    case ARM::VLD2d32wb_register:
3853    case ARM::VLD2q8PseudoWB_register:
3854    case ARM::VLD2q16PseudoWB_register:
3855    case ARM::VLD2q32PseudoWB_register:
3856    case ARM::VLD3d8Pseudo:
3857    case ARM::VLD3d16Pseudo:
3858    case ARM::VLD3d32Pseudo:
3859    case ARM::VLD1d64TPseudo:
3860    case ARM::VLD1d64TPseudoWB_fixed:
3861    case ARM::VLD3d8Pseudo_UPD:
3862    case ARM::VLD3d16Pseudo_UPD:
3863    case ARM::VLD3d32Pseudo_UPD:
3864    case ARM::VLD3q8Pseudo_UPD:
3865    case ARM::VLD3q16Pseudo_UPD:
3866    case ARM::VLD3q32Pseudo_UPD:
3867    case ARM::VLD3q8oddPseudo:
3868    case ARM::VLD3q16oddPseudo:
3869    case ARM::VLD3q32oddPseudo:
3870    case ARM::VLD3q8oddPseudo_UPD:
3871    case ARM::VLD3q16oddPseudo_UPD:
3872    case ARM::VLD3q32oddPseudo_UPD:
3873    case ARM::VLD4d8Pseudo:
3874    case ARM::VLD4d16Pseudo:
3875    case ARM::VLD4d32Pseudo:
3876    case ARM::VLD1d64QPseudo:
3877    case ARM::VLD1d64QPseudoWB_fixed:
3878    case ARM::VLD4d8Pseudo_UPD:
3879    case ARM::VLD4d16Pseudo_UPD:
3880    case ARM::VLD4d32Pseudo_UPD:
3881    case ARM::VLD4q8Pseudo_UPD:
3882    case ARM::VLD4q16Pseudo_UPD:
3883    case ARM::VLD4q32Pseudo_UPD:
3884    case ARM::VLD4q8oddPseudo:
3885    case ARM::VLD4q16oddPseudo:
3886    case ARM::VLD4q32oddPseudo:
3887    case ARM::VLD4q8oddPseudo_UPD:
3888    case ARM::VLD4q16oddPseudo_UPD:
3889    case ARM::VLD4q32oddPseudo_UPD:
3890    case ARM::VLD1DUPq8:
3891    case ARM::VLD1DUPq16:
3892    case ARM::VLD1DUPq32:
3893    case ARM::VLD1DUPq8wb_fixed:
3894    case ARM::VLD1DUPq16wb_fixed:
3895    case ARM::VLD1DUPq32wb_fixed:
3896    case ARM::VLD1DUPq8wb_register:
3897    case ARM::VLD1DUPq16wb_register:
3898    case ARM::VLD1DUPq32wb_register:
3899    case ARM::VLD2DUPd8:
3900    case ARM::VLD2DUPd16:
3901    case ARM::VLD2DUPd32:
3902    case ARM::VLD2DUPd8wb_fixed:
3903    case ARM::VLD2DUPd16wb_fixed:
3904    case ARM::VLD2DUPd32wb_fixed:
3905    case ARM::VLD2DUPd8wb_register:
3906    case ARM::VLD2DUPd16wb_register:
3907    case ARM::VLD2DUPd32wb_register:
3908    case ARM::VLD4DUPd8Pseudo:
3909    case ARM::VLD4DUPd16Pseudo:
3910    case ARM::VLD4DUPd32Pseudo:
3911    case ARM::VLD4DUPd8Pseudo_UPD:
3912    case ARM::VLD4DUPd16Pseudo_UPD:
3913    case ARM::VLD4DUPd32Pseudo_UPD:
3914    case ARM::VLD1LNq8Pseudo:
3915    case ARM::VLD1LNq16Pseudo:
3916    case ARM::VLD1LNq32Pseudo:
3917    case ARM::VLD1LNq8Pseudo_UPD:
3918    case ARM::VLD1LNq16Pseudo_UPD:
3919    case ARM::VLD1LNq32Pseudo_UPD:
3920    case ARM::VLD2LNd8Pseudo:
3921    case ARM::VLD2LNd16Pseudo:
3922    case ARM::VLD2LNd32Pseudo:
3923    case ARM::VLD2LNq16Pseudo:
3924    case ARM::VLD2LNq32Pseudo:
3925    case ARM::VLD2LNd8Pseudo_UPD:
3926    case ARM::VLD2LNd16Pseudo_UPD:
3927    case ARM::VLD2LNd32Pseudo_UPD:
3928    case ARM::VLD2LNq16Pseudo_UPD:
3929    case ARM::VLD2LNq32Pseudo_UPD:
3930    case ARM::VLD4LNd8Pseudo:
3931    case ARM::VLD4LNd16Pseudo:
3932    case ARM::VLD4LNd32Pseudo:
3933    case ARM::VLD4LNq16Pseudo:
3934    case ARM::VLD4LNq32Pseudo:
3935    case ARM::VLD4LNd8Pseudo_UPD:
3936    case ARM::VLD4LNd16Pseudo_UPD:
3937    case ARM::VLD4LNd32Pseudo_UPD:
3938    case ARM::VLD4LNq16Pseudo_UPD:
3939    case ARM::VLD4LNq32Pseudo_UPD:
3940      // If the address is not 64-bit aligned, the latencies of these
3941      // instructions increases by one.
3942      ++Latency;
3943      break;
3944    }
3945
3946  return Latency;
3947}
3948
3949unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3950   if (MI->isCopyLike() || MI->isInsertSubreg() ||
3951      MI->isRegSequence() || MI->isImplicitDef())
3952    return 0;
3953
3954  if (MI->isBundle())
3955    return 0;
3956
3957  const MCInstrDesc &MCID = MI->getDesc();
3958
3959  if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3960    // When predicated, CPSR is an additional source operand for CPSR updating
3961    // instructions, this apparently increases their latencies.
3962    return 1;
3963  }
3964  return 0;
3965}
3966
3967unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3968                                           const MachineInstr *MI,
3969                                           unsigned *PredCost) const {
3970  if (MI->isCopyLike() || MI->isInsertSubreg() ||
3971      MI->isRegSequence() || MI->isImplicitDef())
3972    return 1;
3973
3974  // An instruction scheduler typically runs on unbundled instructions, however
3975  // other passes may query the latency of a bundled instruction.
3976  if (MI->isBundle()) {
3977    unsigned Latency = 0;
3978    MachineBasicBlock::const_instr_iterator I = MI->getIterator();
3979    MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3980    while (++I != E && I->isInsideBundle()) {
3981      if (I->getOpcode() != ARM::t2IT)
3982        Latency += getInstrLatency(ItinData, &*I, PredCost);
3983    }
3984    return Latency;
3985  }
3986
3987  const MCInstrDesc &MCID = MI->getDesc();
3988  if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3989    // When predicated, CPSR is an additional source operand for CPSR updating
3990    // instructions, this apparently increases their latencies.
3991    *PredCost = 1;
3992  }
3993  // Be sure to call getStageLatency for an empty itinerary in case it has a
3994  // valid MinLatency property.
3995  if (!ItinData)
3996    return MI->mayLoad() ? 3 : 1;
3997
3998  unsigned Class = MCID.getSchedClass();
3999
4000  // For instructions with variable uops, use uops as latency.
4001  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4002    return getNumMicroOps(ItinData, MI);
4003
4004  // For the common case, fall back on the itinerary's latency.
4005  unsigned Latency = ItinData->getStageLatency(Class);
4006
4007  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4008  unsigned DefAlign = MI->hasOneMemOperand()
4009    ? (*MI->memoperands_begin())->getAlignment() : 0;
4010  int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
4011  if (Adj >= 0 || (int)Latency > -Adj) {
4012    return Latency + Adj;
4013  }
4014  return Latency;
4015}
4016
4017int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4018                                      SDNode *Node) const {
4019  if (!Node->isMachineOpcode())
4020    return 1;
4021
4022  if (!ItinData || ItinData->isEmpty())
4023    return 1;
4024
4025  unsigned Opcode = Node->getMachineOpcode();
4026  switch (Opcode) {
4027  default:
4028    return ItinData->getStageLatency(get(Opcode).getSchedClass());
4029  case ARM::VLDMQIA:
4030  case ARM::VSTMQIA:
4031    return 2;
4032  }
4033}
4034
4035bool ARMBaseInstrInfo::
4036hasHighOperandLatency(const TargetSchedModel &SchedModel,
4037                      const MachineRegisterInfo *MRI,
4038                      const MachineInstr *DefMI, unsigned DefIdx,
4039                      const MachineInstr *UseMI, unsigned UseIdx) const {
4040  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4041  unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
4042  if (Subtarget.isCortexA8() &&
4043      (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4044    // CortexA8 VFP instructions are not pipelined.
4045    return true;
4046
4047  // Hoist VFP / NEON instructions with 4 or higher latency.
4048  unsigned Latency
4049    = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);
4050  if (Latency <= 3)
4051    return false;
4052  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4053         UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4054}
4055
4056bool ARMBaseInstrInfo::
4057hasLowDefLatency(const TargetSchedModel &SchedModel,
4058                 const MachineInstr *DefMI, unsigned DefIdx) const {
4059  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4060  if (!ItinData || ItinData->isEmpty())
4061    return false;
4062
4063  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4064  if (DDomain == ARMII::DomainGeneral) {
4065    unsigned DefClass = DefMI->getDesc().getSchedClass();
4066    int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4067    return (DefCycle != -1 && DefCycle <= 2);
4068  }
4069  return false;
4070}
4071
4072bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4073                                         StringRef &ErrInfo) const {
4074  if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4075    ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4076    return false;
4077  }
4078  return true;
4079}
4080
4081// LoadStackGuard has so far only been implemented for MachO. Different code
4082// sequence is needed for other targets.
4083void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4084                                                unsigned LoadImmOpc,
4085                                                unsigned LoadOpc,
4086                                                Reloc::Model RM) const {
4087  MachineBasicBlock &MBB = *MI->getParent();
4088  DebugLoc DL = MI->getDebugLoc();
4089  unsigned Reg = MI->getOperand(0).getReg();
4090  const GlobalValue *GV =
4091      cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4092  MachineInstrBuilder MIB;
4093
4094  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4095      .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4096
4097  if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4098    MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4099    MIB.addReg(Reg, RegState::Kill).addImm(0);
4100    unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4101    MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4102        MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
4103    MIB.addMemOperand(MMO);
4104    AddDefaultPred(MIB);
4105  }
4106
4107  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4108  MIB.addReg(Reg, RegState::Kill).addImm(0);
4109  MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4110  AddDefaultPred(MIB);
4111}
4112
4113bool
4114ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4115                                     unsigned &AddSubOpc,
4116                                     bool &NegAcc, bool &HasLane) const {
4117  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4118  if (I == MLxEntryMap.end())
4119    return false;
4120
4121  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4122  MulOpc = Entry.MulOpc;
4123  AddSubOpc = Entry.AddSubOpc;
4124  NegAcc = Entry.NegAcc;
4125  HasLane = Entry.HasLane;
4126  return true;
4127}
4128
4129//===----------------------------------------------------------------------===//
4130// Execution domains.
4131//===----------------------------------------------------------------------===//
4132//
4133// Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4134// and some can go down both.  The vmov instructions go down the VFP pipeline,
4135// but they can be changed to vorr equivalents that are executed by the NEON
4136// pipeline.
4137//
4138// We use the following execution domain numbering:
4139//
4140enum ARMExeDomain {
4141  ExeGeneric = 0,
4142  ExeVFP = 1,
4143  ExeNEON = 2
4144};
4145//
4146// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4147//
4148std::pair<uint16_t, uint16_t>
4149ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4150  // If we don't have access to NEON instructions then we won't be able
4151  // to swizzle anything to the NEON domain. Check to make sure.
4152  if (Subtarget.hasNEON()) {
4153    // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4154    // if they are not predicated.
4155    if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4156      return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4157
4158    // CortexA9 is particularly picky about mixing the two and wants these
4159    // converted.
4160    if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4161        (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4162         MI->getOpcode() == ARM::VMOVS))
4163      return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4164  }
4165  // No other instructions can be swizzled, so just determine their domain.
4166  unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4167
4168  if (Domain & ARMII::DomainNEON)
4169    return std::make_pair(ExeNEON, 0);
4170
4171  // Certain instructions can go either way on Cortex-A8.
4172  // Treat them as NEON instructions.
4173  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4174    return std::make_pair(ExeNEON, 0);
4175
4176  if (Domain & ARMII::DomainVFP)
4177    return std::make_pair(ExeVFP, 0);
4178
4179  return std::make_pair(ExeGeneric, 0);
4180}
4181
4182static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4183                                            unsigned SReg, unsigned &Lane) {
4184  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4185  Lane = 0;
4186
4187  if (DReg != ARM::NoRegister)
4188   return DReg;
4189
4190  Lane = 1;
4191  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4192
4193  assert(DReg && "S-register with no D super-register?");
4194  return DReg;
4195}
4196
4197/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4198/// set ImplicitSReg to a register number that must be marked as implicit-use or
4199/// zero if no register needs to be defined as implicit-use.
4200///
4201/// If the function cannot determine if an SPR should be marked implicit use or
4202/// not, it returns false.
4203///
4204/// This function handles cases where an instruction is being modified from taking
4205/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4206/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4207/// lane of the DPR).
4208///
4209/// If the other SPR is defined, an implicit-use of it should be added. Else,
4210/// (including the case where the DPR itself is defined), it should not.
4211///
4212static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4213                                       MachineInstr *MI,
4214                                       unsigned DReg, unsigned Lane,
4215                                       unsigned &ImplicitSReg) {
4216  // If the DPR is defined or used already, the other SPR lane will be chained
4217  // correctly, so there is nothing to be done.
4218  if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4219    ImplicitSReg = 0;
4220    return true;
4221  }
4222
4223  // Otherwise we need to go searching to see if the SPR is set explicitly.
4224  ImplicitSReg = TRI->getSubReg(DReg,
4225                                (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4226  MachineBasicBlock::LivenessQueryResult LQR =
4227    MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4228
4229  if (LQR == MachineBasicBlock::LQR_Live)
4230    return true;
4231  else if (LQR == MachineBasicBlock::LQR_Unknown)
4232    return false;
4233
4234  // If the register is known not to be live, there is no need to add an
4235  // implicit-use.
4236  ImplicitSReg = 0;
4237  return true;
4238}
4239
4240void
4241ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4242  unsigned DstReg, SrcReg, DReg;
4243  unsigned Lane;
4244  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4245  const TargetRegisterInfo *TRI = &getRegisterInfo();
4246  switch (MI->getOpcode()) {
4247    default:
4248      llvm_unreachable("cannot handle opcode!");
4249      break;
4250    case ARM::VMOVD:
4251      if (Domain != ExeNEON)
4252        break;
4253
4254      // Zap the predicate operands.
4255      assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4256
4257      // Make sure we've got NEON instructions.
4258      assert(Subtarget.hasNEON() && "VORRd requires NEON");
4259
4260      // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4261      DstReg = MI->getOperand(0).getReg();
4262      SrcReg = MI->getOperand(1).getReg();
4263
4264      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4265        MI->RemoveOperand(i-1);
4266
4267      // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4268      MI->setDesc(get(ARM::VORRd));
4269      AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4270                        .addReg(SrcReg)
4271                        .addReg(SrcReg));
4272      break;
4273    case ARM::VMOVRS:
4274      if (Domain != ExeNEON)
4275        break;
4276      assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4277
4278      // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4279      DstReg = MI->getOperand(0).getReg();
4280      SrcReg = MI->getOperand(1).getReg();
4281
4282      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4283        MI->RemoveOperand(i-1);
4284
4285      DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4286
4287      // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4288      // Note that DSrc has been widened and the other lane may be undef, which
4289      // contaminates the entire register.
4290      MI->setDesc(get(ARM::VGETLNi32));
4291      AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4292                        .addReg(DReg, RegState::Undef)
4293                        .addImm(Lane));
4294
4295      // The old source should be an implicit use, otherwise we might think it
4296      // was dead before here.
4297      MIB.addReg(SrcReg, RegState::Implicit);
4298      break;
4299    case ARM::VMOVSR: {
4300      if (Domain != ExeNEON)
4301        break;
4302      assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4303
4304      // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4305      DstReg = MI->getOperand(0).getReg();
4306      SrcReg = MI->getOperand(1).getReg();
4307
4308      DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4309
4310      unsigned ImplicitSReg;
4311      if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4312        break;
4313
4314      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4315        MI->RemoveOperand(i-1);
4316
4317      // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4318      // Again DDst may be undefined at the beginning of this instruction.
4319      MI->setDesc(get(ARM::VSETLNi32));
4320      MIB.addReg(DReg, RegState::Define)
4321         .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4322         .addReg(SrcReg)
4323         .addImm(Lane);
4324      AddDefaultPred(MIB);
4325
4326      // The narrower destination must be marked as set to keep previous chains
4327      // in place.
4328      MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4329      if (ImplicitSReg != 0)
4330        MIB.addReg(ImplicitSReg, RegState::Implicit);
4331      break;
4332    }
4333    case ARM::VMOVS: {
4334      if (Domain != ExeNEON)
4335        break;
4336
4337      // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4338      DstReg = MI->getOperand(0).getReg();
4339      SrcReg = MI->getOperand(1).getReg();
4340
4341      unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4342      DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4343      DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4344
4345      unsigned ImplicitSReg;
4346      if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4347        break;
4348
4349      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4350        MI->RemoveOperand(i-1);
4351
4352      if (DSrc == DDst) {
4353        // Destination can be:
4354        //     %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4355        MI->setDesc(get(ARM::VDUPLN32d));
4356        MIB.addReg(DDst, RegState::Define)
4357           .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4358           .addImm(SrcLane);
4359        AddDefaultPred(MIB);
4360
4361        // Neither the source or the destination are naturally represented any
4362        // more, so add them in manually.
4363        MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4364        MIB.addReg(SrcReg, RegState::Implicit);
4365        if (ImplicitSReg != 0)
4366          MIB.addReg(ImplicitSReg, RegState::Implicit);
4367        break;
4368      }
4369
4370      // In general there's no single instruction that can perform an S <-> S
4371      // move in NEON space, but a pair of VEXT instructions *can* do the
4372      // job. It turns out that the VEXTs needed will only use DSrc once, with
4373      // the position based purely on the combination of lane-0 and lane-1
4374      // involved. For example
4375      //     vmov s0, s2 -> vext.32 d0, d0, d1, #1  vext.32 d0, d0, d0, #1
4376      //     vmov s1, s3 -> vext.32 d0, d1, d0, #1  vext.32 d0, d0, d0, #1
4377      //     vmov s0, s3 -> vext.32 d0, d0, d0, #1  vext.32 d0, d1, d0, #1
4378      //     vmov s1, s2 -> vext.32 d0, d0, d0, #1  vext.32 d0, d0, d1, #1
4379      //
4380      // Pattern of the MachineInstrs is:
4381      //     %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4382      MachineInstrBuilder NewMIB;
4383      NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4384                       get(ARM::VEXTd32), DDst);
4385
4386      // On the first instruction, both DSrc and DDst may be <undef> if present.
4387      // Specifically when the original instruction didn't have them as an
4388      // <imp-use>.
4389      unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4390      bool CurUndef = !MI->readsRegister(CurReg, TRI);
4391      NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4392
4393      CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4394      CurUndef = !MI->readsRegister(CurReg, TRI);
4395      NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4396
4397      NewMIB.addImm(1);
4398      AddDefaultPred(NewMIB);
4399
4400      if (SrcLane == DstLane)
4401        NewMIB.addReg(SrcReg, RegState::Implicit);
4402
4403      MI->setDesc(get(ARM::VEXTd32));
4404      MIB.addReg(DDst, RegState::Define);
4405
4406      // On the second instruction, DDst has definitely been defined above, so
4407      // it is not <undef>. DSrc, if present, can be <undef> as above.
4408      CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4409      CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4410      MIB.addReg(CurReg, getUndefRegState(CurUndef));
4411
4412      CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4413      CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4414      MIB.addReg(CurReg, getUndefRegState(CurUndef));
4415
4416      MIB.addImm(1);
4417      AddDefaultPred(MIB);
4418
4419      if (SrcLane != DstLane)
4420        MIB.addReg(SrcReg, RegState::Implicit);
4421
4422      // As before, the original destination is no longer represented, add it
4423      // implicitly.
4424      MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4425      if (ImplicitSReg != 0)
4426        MIB.addReg(ImplicitSReg, RegState::Implicit);
4427      break;
4428    }
4429  }
4430
4431}
4432
4433//===----------------------------------------------------------------------===//
4434// Partial register updates
4435//===----------------------------------------------------------------------===//
4436//
4437// Swift renames NEON registers with 64-bit granularity.  That means any
4438// instruction writing an S-reg implicitly reads the containing D-reg.  The
4439// problem is mostly avoided by translating f32 operations to v2f32 operations
4440// on D-registers, but f32 loads are still a problem.
4441//
4442// These instructions can load an f32 into a NEON register:
4443//
4444// VLDRS - Only writes S, partial D update.
4445// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4446// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4447//
4448// FCONSTD can be used as a dependency-breaking instruction.
4449unsigned ARMBaseInstrInfo::
4450getPartialRegUpdateClearance(const MachineInstr *MI,
4451                             unsigned OpNum,
4452                             const TargetRegisterInfo *TRI) const {
4453  if (!SwiftPartialUpdateClearance ||
4454      !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4455    return 0;
4456
4457  assert(TRI && "Need TRI instance");
4458
4459  const MachineOperand &MO = MI->getOperand(OpNum);
4460  if (MO.readsReg())
4461    return 0;
4462  unsigned Reg = MO.getReg();
4463  int UseOp = -1;
4464
4465  switch(MI->getOpcode()) {
4466    // Normal instructions writing only an S-register.
4467  case ARM::VLDRS:
4468  case ARM::FCONSTS:
4469  case ARM::VMOVSR:
4470  case ARM::VMOVv8i8:
4471  case ARM::VMOVv4i16:
4472  case ARM::VMOVv2i32:
4473  case ARM::VMOVv2f32:
4474  case ARM::VMOVv1i64:
4475    UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4476    break;
4477
4478    // Explicitly reads the dependency.
4479  case ARM::VLD1LNd32:
4480    UseOp = 3;
4481    break;
4482  default:
4483    return 0;
4484  }
4485
4486  // If this instruction actually reads a value from Reg, there is no unwanted
4487  // dependency.
4488  if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4489    return 0;
4490
4491  // We must be able to clobber the whole D-reg.
4492  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4493    // Virtual register must be a foo:ssub_0<def,undef> operand.
4494    if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4495      return 0;
4496  } else if (ARM::SPRRegClass.contains(Reg)) {
4497    // Physical register: MI must define the full D-reg.
4498    unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4499                                             &ARM::DPRRegClass);
4500    if (!DReg || !MI->definesRegister(DReg, TRI))
4501      return 0;
4502  }
4503
4504  // MI has an unwanted D-register dependency.
4505  // Avoid defs in the previous N instructrions.
4506  return SwiftPartialUpdateClearance;
4507}
4508
4509// Break a partial register dependency after getPartialRegUpdateClearance
4510// returned non-zero.
4511void ARMBaseInstrInfo::
4512breakPartialRegDependency(MachineBasicBlock::iterator MI,
4513                          unsigned OpNum,
4514                          const TargetRegisterInfo *TRI) const {
4515  assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4516  assert(TRI && "Need TRI instance");
4517
4518  const MachineOperand &MO = MI->getOperand(OpNum);
4519  unsigned Reg = MO.getReg();
4520  assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4521         "Can't break virtual register dependencies.");
4522  unsigned DReg = Reg;
4523
4524  // If MI defines an S-reg, find the corresponding D super-register.
4525  if (ARM::SPRRegClass.contains(Reg)) {
4526    DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4527    assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4528  }
4529
4530  assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4531  assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4532
4533  // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4534  // the full D-register by loading the same value to both lanes.  The
4535  // instruction is micro-coded with 2 uops, so don't do this until we can
4536  // properly schedule micro-coded instructions.  The dispatcher stalls cause
4537  // too big regressions.
4538
4539  // Insert the dependency-breaking FCONSTD before MI.
4540  // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4541  AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4542                         get(ARM::FCONSTD), DReg).addImm(96));
4543  MI->addRegisterKilled(DReg, TRI, true);
4544}
4545
4546bool ARMBaseInstrInfo::hasNOP() const {
4547  return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4548}
4549
4550bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4551  if (MI->getNumOperands() < 4)
4552    return true;
4553  unsigned ShOpVal = MI->getOperand(3).getImm();
4554  unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4555  // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4556  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4557      ((ShImm == 1 || ShImm == 2) &&
4558       ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4559    return true;
4560
4561  return false;
4562}
4563
4564bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4565    const MachineInstr &MI, unsigned DefIdx,
4566    SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4567  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4568  assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4569
4570  switch (MI.getOpcode()) {
4571  case ARM::VMOVDRR:
4572    // dX = VMOVDRR rY, rZ
4573    // is the same as:
4574    // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4575    // Populate the InputRegs accordingly.
4576    // rY
4577    const MachineOperand *MOReg = &MI.getOperand(1);
4578    InputRegs.push_back(
4579        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4580    // rZ
4581    MOReg = &MI.getOperand(2);
4582    InputRegs.push_back(
4583        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4584    return true;
4585  }
4586  llvm_unreachable("Target dependent opcode missing");
4587}
4588
4589bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4590    const MachineInstr &MI, unsigned DefIdx,
4591    RegSubRegPairAndIdx &InputReg) const {
4592  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4593  assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4594
4595  switch (MI.getOpcode()) {
4596  case ARM::VMOVRRD:
4597    // rX, rY = VMOVRRD dZ
4598    // is the same as:
4599    // rX = EXTRACT_SUBREG dZ, ssub_0
4600    // rY = EXTRACT_SUBREG dZ, ssub_1
4601    const MachineOperand &MOReg = MI.getOperand(2);
4602    InputReg.Reg = MOReg.getReg();
4603    InputReg.SubReg = MOReg.getSubReg();
4604    InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4605    return true;
4606  }
4607  llvm_unreachable("Target dependent opcode missing");
4608}
4609
4610bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4611    const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4612    RegSubRegPairAndIdx &InsertedReg) const {
4613  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4614  assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4615
4616  switch (MI.getOpcode()) {
4617  case ARM::VSETLNi32:
4618    // dX = VSETLNi32 dY, rZ, imm
4619    const MachineOperand &MOBaseReg = MI.getOperand(1);
4620    const MachineOperand &MOInsertedReg = MI.getOperand(2);
4621    const MachineOperand &MOIndex = MI.getOperand(3);
4622    BaseReg.Reg = MOBaseReg.getReg();
4623    BaseReg.SubReg = MOBaseReg.getSubReg();
4624
4625    InsertedReg.Reg = MOInsertedReg.getReg();
4626    InsertedReg.SubReg = MOInsertedReg.getSubReg();
4627    InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4628    return true;
4629  }
4630  llvm_unreachable("Target dependent opcode missing");
4631}
4632