/external/llvm/lib/MC/MCParser/ |
H A D | MCTargetAsmParser.cpp | 15 const MCSubtargetInfo &STI) 17 STI(&STI) 26 STI = &STICopy; 31 return *STI; 14 MCTargetAsmParser(MCTargetOptions const &MCOptions, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 30 const MCSubtargetInfo &STI) override; 34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 42 const MCSubtargetInfo &STI, raw_ostream &O); 44 const MCSubtargetInfo &STI, raw_ostream &O); 47 const MCSubtargetInfo &STI, raw_ostream &O); 49 const MCSubtargetInfo &STI, raw_ostream &O); 51 const MCSubtargetInfo &STI, raw_ostream &O); 53 const MCSubtargetInfo &STI, raw_ostream &O); 55 const MCSubtargetInfo &STI, raw_ostrea [all...] |
H A D | ARMInstPrinter.cpp | 70 StringRef Annot, const MCSubtargetInfo &STI) { 96 if (STI.getFeatureBits()[ARM::HasV8Ops]) { 102 printInstruction(MI, STI, O); 106 printPredicateOperand(MI, 1, STI, O); 121 printSBitModifierOperand(MI, 6, STI, O); 122 printPredicateOperand(MI, 4, STI, O); 143 printSBitModifierOperand(MI, 5, STI, O); 144 printPredicateOperand(MI, 3, STI, O); 168 printPredicateOperand(MI, 2, STI, O); 172 printRegisterList(MI, 4, STI, 69 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) argument 319 printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument 359 printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 32 const MCSubtargetInfo &STI) override; 36 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 42 const MCSubtargetInfo &STI, 51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 56 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 62 const MCSubtargetInfo &STI, raw_ostream &O) { 67 const MCSubtargetInfo &STI, raw_ostream &O); 69 const MCSubtargetInfo &STI, raw_ostrea 61 printPostIncOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument 88 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 105 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 111 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 bool isMips32r6(const MCSubtargetInfo &STI) const; 51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 56 const MCSubtargetInfo &STI) const override; 62 const MCSubtargetInfo &STI) const; 69 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 86 const MCSubtargetInfo &STI) const; 90 const MCSubtargetInfo &STI) cons [all...] |
H A D | MipsMCCodeEmitter.cpp | 115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { 116 return STI.getFeatureBits()[Mips::FeatureMicroMips]; 119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { 120 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 128 const MCSubtargetInfo &STI, 134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { 135 EmitInstruction(Val >> 16, 2, STI, OS); 136 EmitInstruction(Val, 2, STI, OS); 150 const MCSubtargetInfo &STI) const 173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); [all...] |
H A D | MipsNaClELFStreamer.cpp | 94 const MCSubtargetInfo &STI) { 100 MipsELFStreamer::EmitInstruction(MaskInst, STI); 105 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) { argument 109 emitMask(AddrReg, IndirectBranchMaskReg, STI); 110 MipsELFStreamer::EmitInstruction(MI, STI); 117 const MCSubtargetInfo &STI, bool MaskBefore, 123 emitMask(BaseReg, LoadStoreStackMaskReg, STI); 125 MipsELFStreamer::EmitInstruction(MI, STI); 130 emitMask(SPReg, LoadStoreStackMaskReg, STI); 139 const MCSubtargetInfo &STI) overrid 93 emitMask(unsigned AddrReg, unsigned MaskReg, const MCSubtargetInfo &STI) argument 116 sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) argument [all...] |
/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.h | 32 const MCSubtargetInfo &STI) override; 33 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 35 bool isV9(const MCSubtargetInfo &STI) const; 38 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 40 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 44 const MCSubtargetInfo &STI, raw_ostream &O); 47 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 49 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 51 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 53 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, [all...] |
H A D | SparcInstPrinter.cpp | 37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { 38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; 47 StringRef Annot, const MCSubtargetInfo &STI) { 48 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) 49 printInstruction(MI, STI, O); 54 const MCSubtargetInfo &STI, 75 O << "\tjmp "; printMemOperand(MI, 1, STI, O); 78 O << "\tcall "; printMemOperand(MI, 1, STI, O); 84 if (isV9(STI) 46 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) argument 53 printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) argument 107 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 126 printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument 149 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 173 printGetPCX(const MCInst *MI, unsigned opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI) const override; 48 const MCSubtargetInfo &STI) const; 54 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 91 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCShuffler.h | 30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, argument 32 : HexagonShuffler(MCII, STI) { 35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, argument 38 : HexagonShuffler(MCII, STI) { 56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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H A D | HexagonMCCodeEmitter.h | 38 const MCSubtargetInfo &STI) const; 49 MCSubtargetInfo const &STI) const override; 53 const MCSubtargetInfo &STI, 60 MCSubtargetInfo const &STI) const; 65 MCSubtargetInfo const &STI) const;
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/external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyMCCodeEmitter.cpp | 44 const MCSubtargetInfo &STI) const; 50 const MCSubtargetInfo &STI) const; 54 const MCSubtargetInfo &STI) const; 58 const MCSubtargetInfo &STI) const override; 70 const MCSubtargetInfo &STI) const { 87 const MCSubtargetInfo &STI) const { 95 const MCSubtargetInfo &STI) const {
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 53 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 59 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 80 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 33 const MCSubtargetInfo &STI) const; 37 const MCSubtargetInfo &STI) const { 43 const MCSubtargetInfo &STI) const {
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/external/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.h | 49 bool isSI(const MCSubtargetInfo &STI); 50 bool isCI(const MCSubtargetInfo &STI); 51 bool isVI(const MCSubtargetInfo &STI); 54 /// \p STI otherwise return \p Reg. 55 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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H A D | AMDGPUBaseInfo.cpp | 125 bool isSI(const MCSubtargetInfo &STI) { argument 126 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; 129 bool isCI(const MCSubtargetInfo &STI) { argument 130 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; 133 bool isVI(const MCSubtargetInfo &STI) { argument 134 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 137 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) { argument 142 assert(!isSI(STI)); 143 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi; 146 assert(!isSI(STI)); [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.h | 32 const MCSubtargetInfo *&STI); 53 const MCSubtargetInfo *&STI); 55 X86AsmInstrumentation(const MCSubtargetInfo *&STI); 61 const MCSubtargetInfo *&STI; member in class:llvm::X86AsmInstrumentation
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.h | 26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 27 : MCDisassembler(STI, Ctx) {}
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 64 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 88 const MCSubtargetInfo &STI) const; 95 const MCSubtargetInfo &STI) const; 101 const MCSubtargetInfo &STI) const; 107 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return STI.getFeatureBits()[ARM::ModeThumb]; 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 const Triple &TT = STI.getTargetTriple(); 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) cons 587 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 57 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {} 86 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler 104 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 46 const MCSubtargetInfo &STI) const override; 52 const MCSubtargetInfo &STI) const; 58 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 84 const MCSubtargetInfo &STI) const { 85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 105 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); [all...] |
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI, 36 const MCSubtargetInfo &STI,
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H A D | AMDGPUMCTargetDesc.cpp | 69 const MCSubtargetInfo &STI) { 74 const MCSubtargetInfo &STI, 76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 77 return createSIMCCodeEmitter(MCII, STI, Ctx); 79 return createR600MCCodeEmitter(MCII, STI, Ctx); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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