| /external/eigen/bench/ |
| H A D | check_cache_queries.cpp | 58 int cache_id = 0; local
62 EIGEN_CPUID(abcd,0x4,cache_id);
71 cout << "cache[" << cache_id << "].type = " << cache_type << "\n";
72 cout << "cache[" << cache_id << "].level = " << cache_level << "\n";
73 cout << "cache[" << cache_id << "].ways = " << ways << "\n";
74 cout << "cache[" << cache_id << "].partitions = " << partitions << "\n";
75 cout << "cache[" << cache_id << "].line_size = " << line_size << "\n";
76 cout << "cache[" << cache_id << "].sets = " << sets << "\n";
77 cout << "cache[" << cache_id << "].size = " << cache_size << "\n";
79 cache_id
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_state_cache.c | 35 * consumers can query the hash table of state using a cache_id,
57 GLuint hash = item->cache_id, i;
75 return a->cache_id == b->cache_id &&
130 * Returns the buffer object matching cache_id and key, or NULL.
134 enum brw_cache_id cache_id,
143 lookup.cache_id = cache_id;
157 brw->state.dirty.cache |= (1 << cache_id);
208 if (item->cache_id !
133 brw_search_cache(struct brw_cache *cache, enum brw_cache_id cache_id, const void *key, GLuint key_size, uint32_t *inout_offset, void *out_aux) argument
262 brw_upload_cache(struct brw_cache *cache, enum brw_cache_id cache_id, const void *key, GLuint key_size, const void *data, GLuint data_size, const void *aux, GLuint aux_size, uint32_t *out_offset, void *out_aux) argument
[all...] |
| H A D | brw_state.h | 155 enum brw_cache_id cache_id,
165 enum brw_cache_id cache_id,
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| H A D | brw_vs.c | 323 if (c->cache_id == BRW_VS_PROG) {
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| H A D | brw_context.h | 604 * Effectively part of the key, cache_id identifies what kind of state
608 enum brw_cache_id cache_id; member in struct:brw_cache_item
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| H A D | brw_wm.c | 398 if (c->cache_id == BRW_WM_PROG) {
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| H A D | brw_state_dump.c | 509 switch (item->cache_id) {
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| /external/webp/src/dec/ |
| H A D | frame.c | 76 const int cache_id = ctx->id_; local
177 const int y_offset = cache_id * 16 * dec->cache_y_stride_;
178 const int uv_offset = cache_id * 8 * dec->cache_uv_stride_;
205 const int cache_id = ctx->id_; local
208 uint8_t* const y_dst = dec->cache_y_ + cache_id * 16 * y_bps + mb_x * 16;
230 uint8_t* const u_dst = dec->cache_u_ + cache_id * 8 * uv_bps + mb_x * 8;
231 uint8_t* const v_dst = dec->cache_v_ + cache_id * 8 * uv_bps + mb_x * 8;
388 const int cache_id = ctx->id_; local
391 uint8_t* const u_dst = dec->cache_u_ + cache_id * 8 * uv_bps + mb_x * 8;
392 uint8_t* const v_dst = dec->cache_v_ + cache_id *
416 const int cache_id = ctx->id_; local
[all...] |
| /external/kernel-headers/original/uapi/linux/ |
| H A D | atmmpc.h | 34 __be32 cache_id; member in struct:eg_ctrl_info
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| /external/mesa3d/src/gallium/drivers/r600/ |
| H A D | evergreen_compute_internal.h | 111 void evergreen_set_const_cache(struct r600_pipe_compute *pipe, int cache_id, struct r600_resource* cbo, int size, int offset);
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| H A D | evergreen_compute_internal.c | 604 int cache_id,
612 get_empty_res(pipe, COMPUTE_RESOURCE_CONST_MEM, cache_id);
616 assert(cache_id < 16);
618 evergreen_reg_set(res, SQ_ALU_CONST_BUFFER_SIZE_LS_0 + cache_id*4, size);
619 evergreen_reg_set(res, SQ_ALU_CONST_CACHE_LS_0 + cache_id*4, offset >> 8);
602 evergreen_set_const_cache( struct r600_pipe_compute *pipe, int cache_id, struct r600_resource* cbo, int size, int offset) argument
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| /external/eigen/Eigen/src/Core/util/ |
| H A D | Memory.h | 789 int cache_id = 0; local
793 EIGEN_CPUID(abcd,0x4,cache_id);
813 cache_id++;
814 } while(cache_type>0 && cache_id<16);
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| /external/webrtc/webrtc/base/ |
| H A D | physicalsocketserver.cc | 690 int cache_id = id_; local
693 if (((ff & DE_CONNECT) != 0) && (id_ == cache_id)) {
703 if (((ff & DE_ACCEPT) != 0) && (id_ == cache_id)) {
711 if (((ff & DE_WRITE) != 0) && (id_ == cache_id)) {
715 if (((ff & DE_CLOSE) != 0) && (id_ == cache_id)) {
|