/external/llvm/lib/CodeGen/ |
H A D | DeadMachineInstructionElim.cpp | 46 bool isDead(const MachineInstr *MI) const; 55 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { function in class:DeadMachineInstructionElim 123 if (isDead(MI)) {
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H A D | MachineInstrBundle.cpp | 174 if (MO.isDead()) { 180 if (!MO.isDead()) 185 if (!MO.isDead()) { 202 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); local 203 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | 330 if (!MO.isDead())
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H A D | LivePhysRegs.cpp | 98 if (Reg.second->isReg() && Reg.second->isDead())
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H A D | MachineCSE.cpp | 257 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end())) 545 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead()) 550 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
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H A D | PHIElimination.cpp | 236 bool isDead = MPhi->getOperand(0).isDead(); local 304 if (isDead) { 332 if (DestLI.endIndex().isDead()) {
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H A D | MachineInstr.cpp | 177 bool isKill, bool isDead, bool isUndef, 197 IsDead = isDead; 318 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 344 if (isDead()) { 930 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 1228 /// the specified register or -1 if it is not found. If isDead is true, defs 1232 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, argument 1252 if (Found && (!isDead || MO.isDead())) 176 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument [all...] |
H A D | TailDuplication.cpp | 103 void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, 232 bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken(); local 234 UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs); 237 if (isDead) { 464 TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, argument 487 if (isDead) {
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H A D | RegAllocFast.cpp | 649 } else if (MO.isDead()) { 660 } else if (MO.isDead()) { 676 bool Dead = MO.isDead(); 946 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 1028 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
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H A D | VirtRegMap.cpp | 389 if (MO.isDead()) 401 } else if (!MO.isDead()) {
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H A D | LiveInterval.cpp | 62 assert(!Def.isDead() && "Cannot define a value at the dead slot"); 534 bool isDead = true; 537 isDead = false; 540 if (isDead) {
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H A D | MachineLICM.cpp | 395 if (!MO.isDead()) 911 } else if (!MO.isDead()) { 1365 if (MO.isReg() && MO.isDef() && !MO.isDead())
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H A D | PeepholeOptimizer.cpp | 908 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) { 1347 if (MO.isImplicit() && MO.isDead()) 1710 if (MO.isImplicit() && MO.isDead())
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H A D | MachineVerifier.cpp | 1146 if (MO->isDead()) 1175 if (MO->isDead()) { 1588 if (S.end.isDead()) { 1627 if (!S.end.isDead()) {
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyStoreResults.cpp | 118 assert(!MI.getOperand(0).isDead() && "Dead flag set on store result");
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 292 bool isDead() const { function in class:llvm::MachineOperand 542 /// operand. Note: This method ignores isKill and isDead properties. 572 bool isKill = false, bool isDead = false, 598 bool isKill = false, bool isDead = false, 604 assert(!(isDead && !isDef) && "Dead flag on non-def"); 610 Op.IsDead = isDead;
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H A D | MachineInstr.h | 915 /// -1 if it is not found. If isDead is true, defs that are not dead are 921 bool isDead = false, bool Overlap = false, 926 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 928 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 93 if (MO.isReg() && MO.isDead() && MO.isDef()) {
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H A D | AArch64ExpandPseudoInsts.cpp | 118 const bool DstIsDead = MI.getOperand(0).isDead(); 183 const bool DstIsDead = MI.getOperand(0).isDead(); 366 const bool DstIsDead = MI.getOperand(0).isDead(); 535 bool DstIsDead = MI.getOperand(0).isDead();
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/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | ExprInspectionChecker.cpp | 167 if (!SymReaper.isDead(Sym))
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H A D | SimpleStreamChecker.cpp | 192 bool IsSymDead = SymReaper.isDead(Sym);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 406 bool isDead = false) { 407 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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H A D | Thumb2SizeReduction.cpp | 721 if (HasCC && MI->getOperand(NumOps-1).isDead()) 816 if (HasCC && MI->getOperand(NumOps-1).isDead()) 884 if (!MO.isDead()) 994 if (MO && !MO->isDead())
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H A D | ARMExpandPseudoInsts.cpp | 390 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 524 DstIsDead = MI.getOperand(OpIdx).isDead(); 656 bool DstIsDead = MI.getOperand(0).isDead(); 1000 bool DstIsDead = MI.getOperand(0).isDead(); 1022 bool DstIsDead = MI.getOperand(0).isDead(); 1075 bool DstIsDead = MI.getOperand(0).isDead(); 1137 bool DstIsDead = MI.getOperand(OpIdx).isDead();
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIShrinkInstructions.cpp | 196 Orig.isDead(),
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 234 false /*isDead*/, 323 Src.isKill(), Src.isDead(), Src.isUndef(),
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