Searched refs:EmitI (Results 1 - 4 of 4) sorted by relevance

/art/compiler/utils/mips/
H A Dassembler_mips.cc138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { function in class:art::mips::MipsAssembler
191 EmitI(0x9, rs, rt, imm16);
287 EmitI(0xc, rs, rt, imm16);
295 EmitI(0xd, rs, rt, imm16);
303 EmitI(0xe, rs, rt, imm16);
418 EmitI(0x20, rs, rt, imm16);
422 EmitI(0x21, rs, rt, imm16);
426 EmitI(0x23, rs, rt, imm16);
431 EmitI(0x22, rs, rt, imm16);
436 EmitI(
[all...]
H A Dassembler_mips.h764 void EmitI(int opcode, Register rs, Register rt, uint16_t imm);
/art/compiler/utils/mips64/
H A Dassembler_mips64.cc131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { function in class:art::mips64::Mips64Assembler
184 EmitI(0x9, rs, rt, imm16);
192 EmitI(0x19, rs, rt, imm16);
256 EmitI(0xc, rs, rt, imm16);
264 EmitI(0xd, rs, rt, imm16);
272 EmitI(0xe, rs, rt, imm16);
322 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
327 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
332 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
337 EmitI(
[all...]
H A Dassembler_mips64.h678 void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);

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