Searched defs:DstR (Results 1 - 3 of 3) sorted by relevance
| /external/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 338 const unsigned DstR = MI->getOperand(0).getReg(); local
341 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
369 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3);
370 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1);
380 const MachineOperand &SrcR = MI->getOperand(SrcR1 == DstR ? 1 : 3);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 978 unsigned DstR = MI->getOperand(0).getReg(); local
979 if (MRI->getRegClass(DstR) == DoubleRC) {
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| H A D | HexagonExpandCondsets.cpp | 158 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
680 /// destination register DstR:DstSR, and using the predicate register from
684 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) {
698 .addReg(DstR, RegState::Define, DstSR)
683 genTfrFor(MachineOperand &SrcOp, unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) argument
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