1/* 2 * This file was generated automatically by gen-mterp.py for 'arm64'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: arm64/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 Art assembly interpreter notes: 26 27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28 handle invoke, allows higher-level code to create frame & shadow frame. 29 30 Once that's working, support direct entry code & eliminate shadow frame (and 31 excess locals allocation. 32 33 Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the 34 base of the vreg array within the shadow frame. Access the other fields, 35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36 the shadow frame mechanism of double-storing object references - via xFP & 37 number_of_vregs_. 38 39 */ 40 41/* 42ARM64 Runtime register usage conventions. 43 44 r0 : w0 is 32-bit return register and x0 is 64-bit. 45 r0-r7 : Argument registers. 46 r8-r15 : Caller save registers (used as temporary registers). 47 r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by 48 the linker, by the trampolines and other stubs (the backend uses 49 these as temporary registers). 50 r18 : Caller save register (used as temporary register). 51 r19 : Pointer to thread-local storage. 52 r20-r29: Callee save registers. 53 r30 : (lr) is reserved (the link register). 54 rsp : (sp) is reserved (the stack pointer). 55 rzr : (zr) is reserved (the zero register). 56 57 Floating-point registers 58 v0-v31 59 60 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). 61 This is analogous to the C/C++ (hard-float) calling convention. 62 v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. 63 Also used as temporary and codegen scratch registers. 64 65 v0-v7 and v16-v31 : trashed across C calls. 66 v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). 67 68 v16-v31: Used as codegen temp/scratch. 69 v8-v15 : Can be used for promotion. 70 71 Must maintain 16-byte stack alignment. 72 73Mterp notes: 74 75The following registers have fixed assignments: 76 77 reg nick purpose 78 x20 xPC interpreted program counter, used for fetching instructions 79 x21 xFP interpreted frame pointer, used for accessing locals and args 80 x22 xSELF self (Thread) pointer 81 x23 xINST first 16-bit code unit of current instruction 82 x24 xIBASE interpreted instruction base pointer, used for computed goto 83 x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). 84 x26 wPROFILE jit profile hotness countdown 85 x16 ip scratch reg 86 x17 ip2 scratch reg (used by macros) 87 88Macros are provided for common operations. They MUST NOT alter unspecified registers or condition 89codes. 90*/ 91 92/* 93 * This is a #include, not a %include, because we want the C pre-processor 94 * to expand the macros into assembler assignment statements. 95 */ 96#include "asm_support.h" 97 98#define MTERP_PROFILE_BRANCHES 1 99#define MTERP_LOGGING 0 100 101/* During bringup, we'll use the shadow frame model instead of xFP */ 102/* single-purpose registers, given names for clarity */ 103#define xPC x20 104#define xFP x21 105#define xSELF x22 106#define xINST x23 107#define wINST w23 108#define xIBASE x24 109#define xREFS x25 110#define wPROFILE w26 111#define xPROFILE x26 112#define ip x16 113#define ip2 x17 114 115/* 116 * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, 117 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 118 */ 119#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 120#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 121#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 122#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 123#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 124#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 125#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 126#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 127#define OFF_FP_SHADOWFRAME OFF_FP(0) 128 129/* 130 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 131 * be done *before* something throws. 132 * 133 * It's okay to do this more than once. 134 * 135 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 136 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 137 * offset into the code_items_[] array. For effiency, we will "export" the 138 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 139 * to convert to a dex pc when needed. 140 */ 141.macro EXPORT_PC 142 str xPC, [xFP, #OFF_FP_DEX_PC_PTR] 143.endm 144 145/* 146 * Fetch the next instruction from xPC into wINST. Does not advance xPC. 147 */ 148.macro FETCH_INST 149 ldrh wINST, [xPC] 150.endm 151 152/* 153 * Fetch the next instruction from the specified offset. Advances xPC 154 * to point to the next instruction. "_count" is in 16-bit code units. 155 * 156 * Because of the limited size of immediate constants on ARM, this is only 157 * suitable for small forward movements (i.e. don't try to implement "goto" 158 * with this). 159 * 160 * This must come AFTER anything that can throw an exception, or the 161 * exception catch may miss. (This also implies that it must come after 162 * EXPORT_PC.) 163 */ 164.macro FETCH_ADVANCE_INST count 165 ldrh wINST, [xPC, #((\count)*2)]! 166.endm 167 168/* 169 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 170 * src and dest registers are parameterized (not hard-wired to xPC and xINST). 171 */ 172.macro PREFETCH_ADVANCE_INST dreg, sreg, count 173 ldrh \dreg, [\sreg, #((\count)*2)]! 174.endm 175 176/* 177 * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load 178 * xINST ahead of possible exception point. Be sure to manually advance xPC 179 * later. 180 */ 181.macro PREFETCH_INST count 182 ldrh wINST, [xPC, #((\count)*2)] 183.endm 184 185/* Advance xPC by some number of code units. */ 186.macro ADVANCE count 187 add xPC, xPC, #((\count)*2) 188.endm 189 190/* 191 * Fetch the next instruction from an offset specified by _reg and advance xPC. 192 * xPC to point to the next instruction. "_reg" must specify the distance 193 * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. 194 * 195 */ 196.macro FETCH_ADVANCE_INST_RB reg 197 add xPC, xPC, \reg, sxtw 198 ldrh wINST, [xPC] 199.endm 200 201/* 202 * Fetch a half-word code unit from an offset past the current PC. The 203 * "_count" value is in 16-bit code units. Does not advance xPC. 204 * 205 * The "_S" variant works the same but treats the value as signed. 206 */ 207.macro FETCH reg, count 208 ldrh \reg, [xPC, #((\count)*2)] 209.endm 210 211.macro FETCH_S reg, count 212 ldrsh \reg, [xPC, #((\count)*2)] 213.endm 214 215/* 216 * Fetch one byte from an offset past the current PC. Pass in the same 217 * "_count" as you would for FETCH, and an additional 0/1 indicating which 218 * byte of the halfword you want (lo/hi). 219 */ 220.macro FETCH_B reg, count, byte 221 ldrb \reg, [xPC, #((\count)*2+(\byte))] 222.endm 223 224/* 225 * Put the instruction's opcode field into the specified register. 226 */ 227.macro GET_INST_OPCODE reg 228 and \reg, xINST, #255 229.endm 230 231/* 232 * Put the prefetched instruction's opcode field into the specified register. 233 */ 234.macro GET_PREFETCHED_OPCODE oreg, ireg 235 and \oreg, \ireg, #255 236.endm 237 238/* 239 * Begin executing the opcode in _reg. Clobbers reg 240 */ 241 242.macro GOTO_OPCODE reg 243 add \reg, xIBASE, \reg, lsl #7 244 br \reg 245.endm 246.macro GOTO_OPCODE_BASE base,reg 247 add \reg, \base, \reg, lsl #7 248 br \reg 249.endm 250 251/* 252 * Get/set the 32-bit value from a Dalvik register. 253 */ 254.macro GET_VREG reg, vreg 255 ldr \reg, [xFP, \vreg, uxtw #2] 256.endm 257.macro SET_VREG reg, vreg 258 str \reg, [xFP, \vreg, uxtw #2] 259 str wzr, [xREFS, \vreg, uxtw #2] 260.endm 261.macro SET_VREG_OBJECT reg, vreg, tmpreg 262 str \reg, [xFP, \vreg, uxtw #2] 263 str \reg, [xREFS, \vreg, uxtw #2] 264.endm 265 266/* 267 * Get/set the 64-bit value from a Dalvik register. 268 * TUNING: can we do better here? 269 */ 270.macro GET_VREG_WIDE reg, vreg 271 add ip2, xFP, \vreg, lsl #2 272 ldr \reg, [ip2] 273.endm 274.macro SET_VREG_WIDE reg, vreg 275 add ip2, xFP, \vreg, lsl #2 276 str \reg, [ip2] 277 add ip2, xREFS, \vreg, lsl #2 278 str xzr, [ip2] 279.endm 280 281/* 282 * Convert a virtual register index into an address. 283 */ 284.macro VREG_INDEX_TO_ADDR reg, vreg 285 add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ 286.endm 287 288/* 289 * Refresh handler table. 290 */ 291.macro REFRESH_IBASE 292 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 293.endm 294 295/* File: arm64/entry.S */ 296/* 297 * Copyright (C) 2016 The Android Open Source Project 298 * 299 * Licensed under the Apache License, Version 2.0 (the "License"); 300 * you may not use this file except in compliance with the License. 301 * You may obtain a copy of the License at 302 * 303 * http://www.apache.org/licenses/LICENSE-2.0 304 * 305 * Unless required by applicable law or agreed to in writing, software 306 * distributed under the License is distributed on an "AS IS" BASIS, 307 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 308 * See the License for the specific language governing permissions and 309 * limitations under the License. 310 */ 311 312 .text 313 314/* 315 * Interpreter entry point. 316 * On entry: 317 * x0 Thread* self/ 318 * x1 code_item 319 * x2 ShadowFrame 320 * x3 JValue* result_register 321 * 322 */ 323 .global ExecuteMterpImpl 324 .type ExecuteMterpImpl, %function 325 .balign 16 326 327ExecuteMterpImpl: 328 .cfi_startproc 329 stp xPROFILE, x27, [sp, #-80]! 330 stp xIBASE, xREFS, [sp, #16] 331 stp xSELF, xINST, [sp, #32] 332 stp xPC, xFP, [sp, #48] 333 stp fp, lr, [sp, #64] 334 add fp, sp, #64 335 336 /* Remember the return register */ 337 str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] 338 339 /* Remember the code_item */ 340 str x1, [x2, #SHADOWFRAME_CODE_ITEM_OFFSET] 341 342 /* set up "named" registers */ 343 mov xSELF, x0 344 ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] 345 add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. 346 add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame 347 ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. 348 add xPC, x1, #CODEITEM_INSNS_OFFSET // Point to base of insns[] 349 add xPC, xPC, w0, lsl #1 // Create direct pointer to 1st dex opcode 350 EXPORT_PC 351 352 /* Starting ibase */ 353 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 354 355 /* Set up for backwards branches & osr profiling */ 356 ldr x0, [xFP, #OFF_FP_METHOD] 357 add x1, xFP, #OFF_FP_SHADOWFRAME 358 bl MterpSetUpHotnessCountdown 359 mov wPROFILE, w0 // Starting hotness countdown to xPROFILE 360 361 /* start executing the instruction at rPC */ 362 FETCH_INST // load wINST from rPC 363 GET_INST_OPCODE ip // extract opcode from wINST 364 GOTO_OPCODE ip // jump to next instruction 365 /* NOTE: no fallthrough */ 366 367 368 .global artMterpAsmInstructionStart 369 .type artMterpAsmInstructionStart, %function 370artMterpAsmInstructionStart = .L_op_nop 371 .text 372 373/* ------------------------------ */ 374 .balign 128 375.L_op_nop: /* 0x00 */ 376/* File: arm64/op_nop.S */ 377 FETCH_ADVANCE_INST 1 // advance to next instr, load rINST 378 GET_INST_OPCODE ip // ip<- opcode from rINST 379 GOTO_OPCODE ip // execute it 380 381/* ------------------------------ */ 382 .balign 128 383.L_op_move: /* 0x01 */ 384/* File: arm64/op_move.S */ 385 /* for move, move-object, long-to-int */ 386 /* op vA, vB */ 387 lsr w1, wINST, #12 // x1<- B from 15:12 388 ubfx w0, wINST, #8, #4 // x0<- A from 11:8 389 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 390 GET_VREG w2, w1 // x2<- fp[B] 391 GET_INST_OPCODE ip // ip<- opcode from wINST 392 .if 0 393 SET_VREG_OBJECT w2, w0 // fp[A]<- x2 394 .else 395 SET_VREG w2, w0 // fp[A]<- x2 396 .endif 397 GOTO_OPCODE ip // execute next instruction 398 399/* ------------------------------ */ 400 .balign 128 401.L_op_move_from16: /* 0x02 */ 402/* File: arm64/op_move_from16.S */ 403 /* for: move/from16, move-object/from16 */ 404 /* op vAA, vBBBB */ 405 FETCH w1, 1 // r1<- BBBB 406 lsr w0, wINST, #8 // r0<- AA 407 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 408 GET_VREG w2, w1 // r2<- fp[BBBB] 409 GET_INST_OPCODE ip // extract opcode from wINST 410 .if 0 411 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 412 .else 413 SET_VREG w2, w0 // fp[AA]<- r2 414 .endif 415 GOTO_OPCODE ip // jump to next instruction 416 417/* ------------------------------ */ 418 .balign 128 419.L_op_move_16: /* 0x03 */ 420/* File: arm64/op_move_16.S */ 421 /* for: move/16, move-object/16 */ 422 /* op vAAAA, vBBBB */ 423 FETCH w1, 2 // w1<- BBBB 424 FETCH w0, 1 // w0<- AAAA 425 FETCH_ADVANCE_INST 3 // advance xPC, load xINST 426 GET_VREG w2, w1 // w2<- fp[BBBB] 427 GET_INST_OPCODE ip // extract opcode from xINST 428 .if 0 429 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 430 .else 431 SET_VREG w2, w0 // fp[AAAA]<- w2 432 .endif 433 GOTO_OPCODE ip // jump to next instruction 434 435/* ------------------------------ */ 436 .balign 128 437.L_op_move_wide: /* 0x04 */ 438/* File: arm64/op_move_wide.S */ 439 /* move-wide vA, vB */ 440 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 441 lsr w3, wINST, #12 // w3<- B 442 ubfx w2, wINST, #8, #4 // w2<- A 443 GET_VREG_WIDE x3, w3 444 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 445 GET_INST_OPCODE ip // extract opcode from wINST 446 SET_VREG_WIDE x3, w2 447 GOTO_OPCODE ip // jump to next instruction 448 449/* ------------------------------ */ 450 .balign 128 451.L_op_move_wide_from16: /* 0x05 */ 452/* File: arm64/op_move_wide_from16.S */ 453 /* move-wide/from16 vAA, vBBBB */ 454 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 455 FETCH w3, 1 // w3<- BBBB 456 lsr w2, wINST, #8 // w2<- AA 457 GET_VREG_WIDE x3, w3 458 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 459 GET_INST_OPCODE ip // extract opcode from wINST 460 SET_VREG_WIDE x3, w2 461 GOTO_OPCODE ip // jump to next instruction 462 463/* ------------------------------ */ 464 .balign 128 465.L_op_move_wide_16: /* 0x06 */ 466/* File: arm64/op_move_wide_16.S */ 467 /* move-wide/16 vAAAA, vBBBB */ 468 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 469 FETCH w3, 2 // w3<- BBBB 470 FETCH w2, 1 // w2<- AAAA 471 GET_VREG_WIDE x3, w3 472 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 473 SET_VREG_WIDE x3, w2 474 GET_INST_OPCODE ip // extract opcode from rINST 475 GOTO_OPCODE ip // jump to next instruction 476 477/* ------------------------------ */ 478 .balign 128 479.L_op_move_object: /* 0x07 */ 480/* File: arm64/op_move_object.S */ 481/* File: arm64/op_move.S */ 482 /* for move, move-object, long-to-int */ 483 /* op vA, vB */ 484 lsr w1, wINST, #12 // x1<- B from 15:12 485 ubfx w0, wINST, #8, #4 // x0<- A from 11:8 486 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 487 GET_VREG w2, w1 // x2<- fp[B] 488 GET_INST_OPCODE ip // ip<- opcode from wINST 489 .if 1 490 SET_VREG_OBJECT w2, w0 // fp[A]<- x2 491 .else 492 SET_VREG w2, w0 // fp[A]<- x2 493 .endif 494 GOTO_OPCODE ip // execute next instruction 495 496 497/* ------------------------------ */ 498 .balign 128 499.L_op_move_object_from16: /* 0x08 */ 500/* File: arm64/op_move_object_from16.S */ 501/* File: arm64/op_move_from16.S */ 502 /* for: move/from16, move-object/from16 */ 503 /* op vAA, vBBBB */ 504 FETCH w1, 1 // r1<- BBBB 505 lsr w0, wINST, #8 // r0<- AA 506 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 507 GET_VREG w2, w1 // r2<- fp[BBBB] 508 GET_INST_OPCODE ip // extract opcode from wINST 509 .if 1 510 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 511 .else 512 SET_VREG w2, w0 // fp[AA]<- r2 513 .endif 514 GOTO_OPCODE ip // jump to next instruction 515 516 517/* ------------------------------ */ 518 .balign 128 519.L_op_move_object_16: /* 0x09 */ 520/* File: arm64/op_move_object_16.S */ 521/* File: arm64/op_move_16.S */ 522 /* for: move/16, move-object/16 */ 523 /* op vAAAA, vBBBB */ 524 FETCH w1, 2 // w1<- BBBB 525 FETCH w0, 1 // w0<- AAAA 526 FETCH_ADVANCE_INST 3 // advance xPC, load xINST 527 GET_VREG w2, w1 // w2<- fp[BBBB] 528 GET_INST_OPCODE ip // extract opcode from xINST 529 .if 1 530 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 531 .else 532 SET_VREG w2, w0 // fp[AAAA]<- w2 533 .endif 534 GOTO_OPCODE ip // jump to next instruction 535 536 537/* ------------------------------ */ 538 .balign 128 539.L_op_move_result: /* 0x0a */ 540/* File: arm64/op_move_result.S */ 541 /* for: move-result, move-result-object */ 542 /* op vAA */ 543 lsr w2, wINST, #8 // r2<- AA 544 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 545 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 546 ldr w0, [x0] // r0 <- result.i. 547 GET_INST_OPCODE ip // extract opcode from wINST 548 .if 0 549 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 550 .else 551 SET_VREG w0, w2 // fp[AA]<- r0 552 .endif 553 GOTO_OPCODE ip // jump to next instruction 554 555/* ------------------------------ */ 556 .balign 128 557.L_op_move_result_wide: /* 0x0b */ 558/* File: arm64/op_move_result_wide.S */ 559 /* for: move-result-wide */ 560 /* op vAA */ 561 lsr w2, wINST, #8 // r2<- AA 562 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 563 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 564 ldr x0, [x0] // r0 <- result.i. 565 GET_INST_OPCODE ip // extract opcode from wINST 566 SET_VREG_WIDE x0, x2 // fp[AA]<- r0 567 GOTO_OPCODE ip // jump to next instruction 568 569/* ------------------------------ */ 570 .balign 128 571.L_op_move_result_object: /* 0x0c */ 572/* File: arm64/op_move_result_object.S */ 573/* File: arm64/op_move_result.S */ 574 /* for: move-result, move-result-object */ 575 /* op vAA */ 576 lsr w2, wINST, #8 // r2<- AA 577 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 578 ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. 579 ldr w0, [x0] // r0 <- result.i. 580 GET_INST_OPCODE ip // extract opcode from wINST 581 .if 1 582 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 583 .else 584 SET_VREG w0, w2 // fp[AA]<- r0 585 .endif 586 GOTO_OPCODE ip // jump to next instruction 587 588 589/* ------------------------------ */ 590 .balign 128 591.L_op_move_exception: /* 0x0d */ 592/* File: arm64/op_move_exception.S */ 593 /* move-exception vAA */ 594 lsr w2, wINST, #8 // w2<- AA 595 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 596 mov x1, #0 // w1<- 0 597 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 598 SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj 599 GET_INST_OPCODE ip // extract opcode from rINST 600 str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception 601 GOTO_OPCODE ip // jump to next instruction 602 603/* ------------------------------ */ 604 .balign 128 605.L_op_return_void: /* 0x0e */ 606/* File: arm64/op_return_void.S */ 607 .extern MterpThreadFenceForConstructor 608 bl MterpThreadFenceForConstructor 609 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 610 mov x0, xSELF 611 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 612 b.ne .Lop_return_void_check 613.Lop_return_void_return: 614 mov x0, #0 615 b MterpReturn 616.Lop_return_void_check: 617 bl MterpSuspendCheck // (self) 618 b .Lop_return_void_return 619 620/* ------------------------------ */ 621 .balign 128 622.L_op_return: /* 0x0f */ 623/* File: arm64/op_return.S */ 624 /* 625 * Return a 32-bit value. 626 * 627 * for: return, return-object 628 */ 629 /* op vAA */ 630 .extern MterpThreadFenceForConstructor 631 bl MterpThreadFenceForConstructor 632 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 633 mov x0, xSELF 634 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 635 b.ne .Lop_return_check 636.Lop_return_return: 637 lsr w2, wINST, #8 // r2<- AA 638 GET_VREG w0, w2 // r0<- vAA 639 b MterpReturn 640.Lop_return_check: 641 bl MterpSuspendCheck // (self) 642 b .Lop_return_return 643 644/* ------------------------------ */ 645 .balign 128 646.L_op_return_wide: /* 0x10 */ 647/* File: arm64/op_return_wide.S */ 648 /* 649 * Return a 64-bit value. 650 */ 651 /* return-wide vAA */ 652 /* op vAA */ 653 .extern MterpThreadFenceForConstructor 654 bl MterpThreadFenceForConstructor 655 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 656 mov x0, xSELF 657 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 658 b.ne .Lop_return_wide_check 659.Lop_return_wide_return: 660 lsr w2, wINST, #8 // w2<- AA 661 GET_VREG_WIDE x0, w2 // x0<- vAA 662 b MterpReturn 663.Lop_return_wide_check: 664 bl MterpSuspendCheck // (self) 665 b .Lop_return_wide_return 666 667/* ------------------------------ */ 668 .balign 128 669.L_op_return_object: /* 0x11 */ 670/* File: arm64/op_return_object.S */ 671/* File: arm64/op_return.S */ 672 /* 673 * Return a 32-bit value. 674 * 675 * for: return, return-object 676 */ 677 /* op vAA */ 678 .extern MterpThreadFenceForConstructor 679 bl MterpThreadFenceForConstructor 680 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 681 mov x0, xSELF 682 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 683 b.ne .Lop_return_object_check 684.Lop_return_object_return: 685 lsr w2, wINST, #8 // r2<- AA 686 GET_VREG w0, w2 // r0<- vAA 687 b MterpReturn 688.Lop_return_object_check: 689 bl MterpSuspendCheck // (self) 690 b .Lop_return_object_return 691 692 693/* ------------------------------ */ 694 .balign 128 695.L_op_const_4: /* 0x12 */ 696/* File: arm64/op_const_4.S */ 697 /* const/4 vA, #+B */ 698 lsl w1, wINST, #16 // w1<- Bxxx0000 699 ubfx w0, wINST, #8, #4 // w0<- A 700 FETCH_ADVANCE_INST 1 // advance xPC, load wINST 701 asr w1, w1, #28 // w1<- sssssssB (sign-extended) 702 GET_INST_OPCODE ip // ip<- opcode from xINST 703 SET_VREG w1, w0 // fp[A]<- w1 704 GOTO_OPCODE ip // execute next instruction 705 706/* ------------------------------ */ 707 .balign 128 708.L_op_const_16: /* 0x13 */ 709/* File: arm64/op_const_16.S */ 710 /* const/16 vAA, #+BBBB */ 711 FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended 712 lsr w3, wINST, #8 // w3<- AA 713 FETCH_ADVANCE_INST 2 // advance xPC, load wINST 714 SET_VREG w0, w3 // vAA<- w0 715 GET_INST_OPCODE ip // extract opcode from wINST 716 GOTO_OPCODE ip // jump to next instruction 717 718/* ------------------------------ */ 719 .balign 128 720.L_op_const: /* 0x14 */ 721/* File: arm64/op_const.S */ 722 /* const vAA, #+BBBBbbbb */ 723 lsr w3, wINST, #8 // w3<- AA 724 FETCH w0, 1 // w0<- bbbb (low 725 FETCH w1, 2 // w1<- BBBB (high 726 FETCH_ADVANCE_INST 3 // advance rPC, load wINST 727 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 728 GET_INST_OPCODE ip // extract opcode from wINST 729 SET_VREG w0, w3 // vAA<- w0 730 GOTO_OPCODE ip // jump to next instruction 731 732/* ------------------------------ */ 733 .balign 128 734.L_op_const_high16: /* 0x15 */ 735/* File: arm64/op_const_high16.S */ 736 /* const/high16 vAA, #+BBBB0000 */ 737 FETCH w0, 1 // r0<- 0000BBBB (zero-extended 738 lsr w3, wINST, #8 // r3<- AA 739 lsl w0, w0, #16 // r0<- BBBB0000 740 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 741 SET_VREG w0, w3 // vAA<- r0 742 GET_INST_OPCODE ip // extract opcode from rINST 743 GOTO_OPCODE ip // jump to next instruction 744 745/* ------------------------------ */ 746 .balign 128 747.L_op_const_wide_16: /* 0x16 */ 748/* File: arm64/op_const_wide_16.S */ 749 /* const-wide/16 vAA, #+BBBB */ 750 FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended 751 lsr w3, wINST, #8 // w3<- AA 752 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 753 sbfm x0, x0, 0, 31 754 GET_INST_OPCODE ip // extract opcode from rINST 755 SET_VREG_WIDE x0, w3 756 GOTO_OPCODE ip // jump to next instruction 757 758/* ------------------------------ */ 759 .balign 128 760.L_op_const_wide_32: /* 0x17 */ 761/* File: arm64/op_const_wide_32.S */ 762 /* const-wide/32 vAA, #+BBBBbbbb */ 763 FETCH w0, 1 // w0<- 0000bbbb (low) 764 lsr w3, wINST, #8 // w3<- AA 765 FETCH_S w2, 2 // w2<- ssssBBBB (high) 766 FETCH_ADVANCE_INST 3 // advance rPC, load wINST 767 GET_INST_OPCODE ip // extract opcode from wINST 768 orr w0, w0, w2, lsl #16 // w0<- BBBBbbbb 769 sbfm x0, x0, 0, 31 770 SET_VREG_WIDE x0, w3 771 GOTO_OPCODE ip // jump to next instruction 772 773/* ------------------------------ */ 774 .balign 128 775.L_op_const_wide: /* 0x18 */ 776/* File: arm64/op_const_wide.S */ 777 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 778 FETCH w0, 1 // w0<- bbbb (low) 779 FETCH w1, 2 // w1<- BBBB (low middle) 780 FETCH w2, 3 // w2<- hhhh (high middle) 781 FETCH w3, 4 // w3<- HHHH (high) 782 lsr w4, wINST, #8 // r4<- AA 783 FETCH_ADVANCE_INST 5 // advance rPC, load wINST 784 GET_INST_OPCODE ip // extract opcode from wINST 785 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 786 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb 787 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb 788 SET_VREG_WIDE x0, w4 789 GOTO_OPCODE ip // jump to next instruction 790 791/* ------------------------------ */ 792 .balign 128 793.L_op_const_wide_high16: /* 0x19 */ 794/* File: arm64/op_const_wide_high16.S */ 795 /* const-wide/high16 vAA, #+BBBB000000000000 */ 796 FETCH w0, 1 // w0<- 0000BBBB (zero-extended) 797 lsr w1, wINST, #8 // w1<- AA 798 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 799 lsl x0, x0, #48 800 SET_VREG_WIDE x0, w1 801 GET_INST_OPCODE ip // extract opcode from wINST 802 GOTO_OPCODE ip // jump to next instruction 803 804/* ------------------------------ */ 805 .balign 128 806.L_op_const_string: /* 0x1a */ 807/* File: arm64/op_const_string.S */ 808 /* const/string vAA, String//BBBB */ 809 EXPORT_PC 810 FETCH w0, 1 // w0<- BBBB 811 lsr w1, wINST, #8 // w1<- AA 812 add x2, xFP, #OFF_FP_SHADOWFRAME 813 mov x3, xSELF 814 bl MterpConstString // (index, tgt_reg, shadow_frame, self) 815 PREFETCH_INST 2 // load rINST 816 cbnz w0, MterpPossibleException // let reference interpreter deal with it. 817 ADVANCE 2 // advance rPC 818 GET_INST_OPCODE ip // extract opcode from rINST 819 GOTO_OPCODE ip // jump to next instruction 820 821/* ------------------------------ */ 822 .balign 128 823.L_op_const_string_jumbo: /* 0x1b */ 824/* File: arm64/op_const_string_jumbo.S */ 825 /* const/string vAA, String//BBBBBBBB */ 826 EXPORT_PC 827 FETCH w0, 1 // w0<- bbbb (low 828 FETCH w2, 2 // w2<- BBBB (high 829 lsr w1, wINST, #8 // w1<- AA 830 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb 831 add x2, xFP, #OFF_FP_SHADOWFRAME 832 mov x3, xSELF 833 bl MterpConstString // (index, tgt_reg, shadow_frame, self) 834 PREFETCH_INST 3 // advance rPC 835 cbnz w0, MterpPossibleException // let reference interpreter deal with it. 836 ADVANCE 3 // advance rPC 837 GET_INST_OPCODE ip // extract opcode from rINST 838 GOTO_OPCODE ip // jump to next instruction 839 840/* ------------------------------ */ 841 .balign 128 842.L_op_const_class: /* 0x1c */ 843/* File: arm64/op_const_class.S */ 844 /* const/class vAA, Class//BBBB */ 845 EXPORT_PC 846 FETCH w0, 1 // w0<- BBBB 847 lsr w1, wINST, #8 // w1<- AA 848 add x2, xFP, #OFF_FP_SHADOWFRAME 849 mov x3, xSELF 850 bl MterpConstClass // (index, tgt_reg, shadow_frame, self) 851 PREFETCH_INST 2 852 cbnz w0, MterpPossibleException 853 ADVANCE 2 854 GET_INST_OPCODE ip // extract opcode from rINST 855 GOTO_OPCODE ip // jump to next instruction 856 857/* ------------------------------ */ 858 .balign 128 859.L_op_monitor_enter: /* 0x1d */ 860/* File: arm64/op_monitor_enter.S */ 861 /* 862 * Synchronize on an object. 863 */ 864 /* monitor-enter vAA */ 865 EXPORT_PC 866 lsr w2, wINST, #8 // w2<- AA 867 GET_VREG w0, w2 // w0<- vAA (object) 868 mov x1, xSELF // w1<- self 869 bl artLockObjectFromCode 870 cbnz w0, MterpException 871 FETCH_ADVANCE_INST 1 872 GET_INST_OPCODE ip // extract opcode from rINST 873 GOTO_OPCODE ip // jump to next instruction 874 875/* ------------------------------ */ 876 .balign 128 877.L_op_monitor_exit: /* 0x1e */ 878/* File: arm64/op_monitor_exit.S */ 879 /* 880 * Unlock an object. 881 * 882 * Exceptions that occur when unlocking a monitor need to appear as 883 * if they happened at the following instruction. See the Dalvik 884 * instruction spec. 885 */ 886 /* monitor-exit vAA */ 887 EXPORT_PC 888 lsr w2, wINST, #8 // w2<- AA 889 GET_VREG w0, w2 // w0<- vAA (object) 890 mov x1, xSELF // w0<- self 891 bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) 892 cbnz w0, MterpException 893 FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST 894 GET_INST_OPCODE ip // extract opcode from rINST 895 GOTO_OPCODE ip // jump to next instruction 896 897/* ------------------------------ */ 898 .balign 128 899.L_op_check_cast: /* 0x1f */ 900/* File: arm64/op_check_cast.S */ 901 /* 902 * Check to see if a cast from one class to another is allowed. 903 */ 904 /* check-cast vAA, class//BBBB */ 905 EXPORT_PC 906 FETCH w0, 1 // w0<- BBBB 907 lsr w1, wINST, #8 // w1<- AA 908 VREG_INDEX_TO_ADDR x1, w1 // w1<- &object 909 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method 910 mov x3, xSELF // w3<- self 911 bl MterpCheckCast // (index, &obj, method, self) 912 PREFETCH_INST 2 913 cbnz w0, MterpPossibleException 914 ADVANCE 2 915 GET_INST_OPCODE ip // extract opcode from rINST 916 GOTO_OPCODE ip // jump to next instruction 917 918/* ------------------------------ */ 919 .balign 128 920.L_op_instance_of: /* 0x20 */ 921/* File: arm64/op_instance_of.S */ 922 /* 923 * Check to see if an object reference is an instance of a class. 924 * 925 * Most common situation is a non-null object, being compared against 926 * an already-resolved class. 927 */ 928 /* instance-of vA, vB, class//CCCC */ 929 EXPORT_PC 930 FETCH w0, 1 // w0<- CCCC 931 lsr w1, wINST, #12 // w1<- B 932 VREG_INDEX_TO_ADDR x1, w1 // w1<- &object 933 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method 934 mov x3, xSELF // w3<- self 935 bl MterpInstanceOf // (index, &obj, method, self) 936 ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] 937 lsr w2, wINST, #8 // w2<- A+ 938 and w2, w2, #15 // w2<- A 939 PREFETCH_INST 2 940 cbnz x1, MterpException 941 ADVANCE 2 // advance rPC 942 SET_VREG w0, w2 // vA<- w0 943 GET_INST_OPCODE ip // extract opcode from rINST 944 GOTO_OPCODE ip // jump to next instruction 945 946/* ------------------------------ */ 947 .balign 128 948.L_op_array_length: /* 0x21 */ 949/* File: arm64/op_array_length.S */ 950 /* 951 * Return the length of an array. 952 */ 953 lsr w1, wINST, #12 // w1<- B 954 ubfx w2, wINST, #8, #4 // w2<- A 955 GET_VREG w0, w1 // w0<- vB (object ref) 956 cbz w0, common_errNullObject // yup, fail 957 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 958 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length 959 GET_INST_OPCODE ip // extract opcode from rINST 960 SET_VREG w3, w2 // vB<- length 961 GOTO_OPCODE ip // jump to next instruction 962 963/* ------------------------------ */ 964 .balign 128 965.L_op_new_instance: /* 0x22 */ 966/* File: arm64/op_new_instance.S */ 967 /* 968 * Create a new instance of a class. 969 */ 970 /* new-instance vAA, class//BBBB */ 971 EXPORT_PC 972 add x0, xFP, #OFF_FP_SHADOWFRAME 973 mov x1, xSELF 974 mov w2, wINST 975 bl MterpNewInstance // (shadow_frame, self, inst_data) 976 cbz w0, MterpPossibleException 977 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 978 GET_INST_OPCODE ip // extract opcode from rINST 979 GOTO_OPCODE ip // jump to next instruction 980 981/* ------------------------------ */ 982 .balign 128 983.L_op_new_array: /* 0x23 */ 984/* File: arm64/op_new_array.S */ 985 /* 986 * Allocate an array of objects, specified with the array class 987 * and a count. 988 * 989 * The verifier guarantees that this is an array class, so we don't 990 * check for it here. 991 */ 992 /* new-array vA, vB, class//CCCC */ 993 EXPORT_PC 994 add x0, xFP, #OFF_FP_SHADOWFRAME 995 mov x1, xPC 996 mov w2, wINST 997 mov x3, xSELF 998 bl MterpNewArray 999 cbz w0, MterpPossibleException 1000 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1001 GET_INST_OPCODE ip // extract opcode from rINST 1002 GOTO_OPCODE ip // jump to next instruction 1003 1004/* ------------------------------ */ 1005 .balign 128 1006.L_op_filled_new_array: /* 0x24 */ 1007/* File: arm64/op_filled_new_array.S */ 1008 /* 1009 * Create a new array with elements filled from registers. 1010 * 1011 * for: filled-new-array, filled-new-array/range 1012 */ 1013 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1014 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1015 .extern MterpFilledNewArray 1016 EXPORT_PC 1017 add x0, xFP, #OFF_FP_SHADOWFRAME 1018 mov x1, xPC 1019 mov x2, xSELF 1020 bl MterpFilledNewArray 1021 cbz w0, MterpPossibleException 1022 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1023 GET_INST_OPCODE ip // extract opcode from rINST 1024 GOTO_OPCODE ip // jump to next instruction 1025 1026/* ------------------------------ */ 1027 .balign 128 1028.L_op_filled_new_array_range: /* 0x25 */ 1029/* File: arm64/op_filled_new_array_range.S */ 1030/* File: arm64/op_filled_new_array.S */ 1031 /* 1032 * Create a new array with elements filled from registers. 1033 * 1034 * for: filled-new-array, filled-new-array/range 1035 */ 1036 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1037 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1038 .extern MterpFilledNewArrayRange 1039 EXPORT_PC 1040 add x0, xFP, #OFF_FP_SHADOWFRAME 1041 mov x1, xPC 1042 mov x2, xSELF 1043 bl MterpFilledNewArrayRange 1044 cbz w0, MterpPossibleException 1045 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1046 GET_INST_OPCODE ip // extract opcode from rINST 1047 GOTO_OPCODE ip // jump to next instruction 1048 1049 1050/* ------------------------------ */ 1051 .balign 128 1052.L_op_fill_array_data: /* 0x26 */ 1053/* File: arm64/op_fill_array_data.S */ 1054 /* fill-array-data vAA, +BBBBBBBB */ 1055 EXPORT_PC 1056 FETCH w0, 1 // w0<- bbbb (lo) 1057 FETCH w1, 2 // w1<- BBBB (hi) 1058 lsr w3, wINST, #8 // w3<- AA 1059 orr w1, w0, w1, lsl #16 // w1<- BBBBbbbb 1060 GET_VREG w0, w3 // w0<- vAA (array object) 1061 add x1, xPC, w1, lsl #1 // w1<- PC + BBBBbbbb*2 (array data off.) 1062 bl MterpFillArrayData // (obj, payload) 1063 cbz w0, MterpPossibleException // exception? 1064 FETCH_ADVANCE_INST 3 // advance rPC, load rINST 1065 GET_INST_OPCODE ip // extract opcode from rINST 1066 GOTO_OPCODE ip // jump to next instruction 1067 1068/* ------------------------------ */ 1069 .balign 128 1070.L_op_throw: /* 0x27 */ 1071/* File: arm64/op_throw.S */ 1072 /* 1073 * Throw an exception object in the current thread. 1074 */ 1075 /* throw vAA */ 1076 EXPORT_PC 1077 lsr w2, wINST, #8 // r2<- AA 1078 GET_VREG w1, w2 // r1<- vAA (exception object) 1079 cbz w1, common_errNullObject 1080 str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj 1081 b MterpException 1082 1083/* ------------------------------ */ 1084 .balign 128 1085.L_op_goto: /* 0x28 */ 1086/* File: arm64/op_goto.S */ 1087 /* 1088 * Unconditional branch, 8-bit offset. 1089 * 1090 * The branch distance is a signed code-unit offset, which we need to 1091 * double to get a byte offset. 1092 */ 1093 /* goto +AA */ 1094 sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) 1095 b MterpCommonTakenBranchNoFlags 1096 1097/* ------------------------------ */ 1098 .balign 128 1099.L_op_goto_16: /* 0x29 */ 1100/* File: arm64/op_goto_16.S */ 1101 /* 1102 * Unconditional branch, 16-bit offset. 1103 * 1104 * The branch distance is a signed code-unit offset, which we need to 1105 * double to get a byte offset. 1106 */ 1107 /* goto/16 +AAAA */ 1108 FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) 1109 b MterpCommonTakenBranchNoFlags 1110 1111/* ------------------------------ */ 1112 .balign 128 1113.L_op_goto_32: /* 0x2a */ 1114/* File: arm64/op_goto_32.S */ 1115 /* 1116 * Unconditional branch, 32-bit offset. 1117 * 1118 * The branch distance is a signed code-unit offset, which we need to 1119 * double to get a byte offset. 1120 * 1121 * Unlike most opcodes, this one is allowed to branch to itself, so 1122 * our "backward branch" test must be "<=0" instead of "<0". Because 1123 * we need the V bit set, we'll use an adds to convert from Dalvik 1124 * offset to byte offset. 1125 */ 1126 /* goto/32 +AAAAAAAA */ 1127 FETCH w0, 1 // w0<- aaaa (lo) 1128 FETCH w1, 2 // w1<- AAAA (hi) 1129 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa 1130 b MterpCommonTakenBranchNoFlags 1131 1132/* ------------------------------ */ 1133 .balign 128 1134.L_op_packed_switch: /* 0x2b */ 1135/* File: arm64/op_packed_switch.S */ 1136 /* 1137 * Handle a packed-switch or sparse-switch instruction. In both cases 1138 * we decode it and hand it off to a helper function. 1139 * 1140 * We don't really expect backward branches in a switch statement, but 1141 * they're perfectly legal, so we check for them here. 1142 * 1143 * for: packed-switch, sparse-switch 1144 */ 1145 /* op vAA, +BBBB */ 1146 FETCH w0, 1 // w0<- bbbb (lo) 1147 FETCH w1, 2 // w1<- BBBB (hi) 1148 lsr w3, wINST, #8 // w3<- AA 1149 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 1150 GET_VREG w1, w3 // w1<- vAA 1151 add x0, xPC, w0, lsl #1 // w0<- PC + BBBBbbbb*2 1152 bl MterpDoPackedSwitch // w0<- code-unit branch offset 1153 sbfm xINST, x0, 0, 31 1154 b MterpCommonTakenBranchNoFlags 1155 1156/* ------------------------------ */ 1157 .balign 128 1158.L_op_sparse_switch: /* 0x2c */ 1159/* File: arm64/op_sparse_switch.S */ 1160/* File: arm64/op_packed_switch.S */ 1161 /* 1162 * Handle a packed-switch or sparse-switch instruction. In both cases 1163 * we decode it and hand it off to a helper function. 1164 * 1165 * We don't really expect backward branches in a switch statement, but 1166 * they're perfectly legal, so we check for them here. 1167 * 1168 * for: packed-switch, sparse-switch 1169 */ 1170 /* op vAA, +BBBB */ 1171 FETCH w0, 1 // w0<- bbbb (lo) 1172 FETCH w1, 2 // w1<- BBBB (hi) 1173 lsr w3, wINST, #8 // w3<- AA 1174 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb 1175 GET_VREG w1, w3 // w1<- vAA 1176 add x0, xPC, w0, lsl #1 // w0<- PC + BBBBbbbb*2 1177 bl MterpDoSparseSwitch // w0<- code-unit branch offset 1178 sbfm xINST, x0, 0, 31 1179 b MterpCommonTakenBranchNoFlags 1180 1181 1182/* ------------------------------ */ 1183 .balign 128 1184.L_op_cmpl_float: /* 0x2d */ 1185/* File: arm64/op_cmpl_float.S */ 1186/* File: arm64/fcmp.S */ 1187 /* 1188 * Compare two floating-point values. Puts 0, 1, or -1 into the 1189 * destination register based on the results of the comparison. 1190 */ 1191 /* op vAA, vBB, vCC */ 1192 FETCH w0, 1 // w0<- CCBB 1193 lsr w4, wINST, #8 // w4<- AA 1194 and w2, w0, #255 // w2<- BB 1195 lsr w3, w0, #8 // w3<- CC 1196 GET_VREG s1, w2 1197 GET_VREG s2, w3 1198 mov w0, #-1 1199 fcmp s1, s2 1200 csneg w0, w0, w0, le 1201 csel w0, wzr, w0, eq 1202 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1203 GET_INST_OPCODE ip // extract opcode from rINST 1204 SET_VREG w0, w4 // vAA<- w0 1205 GOTO_OPCODE ip // jump to next instruction 1206 1207 1208/* ------------------------------ */ 1209 .balign 128 1210.L_op_cmpg_float: /* 0x2e */ 1211/* File: arm64/op_cmpg_float.S */ 1212/* File: arm64/fcmp.S */ 1213 /* 1214 * Compare two floating-point values. Puts 0, 1, or -1 into the 1215 * destination register based on the results of the comparison. 1216 */ 1217 /* op vAA, vBB, vCC */ 1218 FETCH w0, 1 // w0<- CCBB 1219 lsr w4, wINST, #8 // w4<- AA 1220 and w2, w0, #255 // w2<- BB 1221 lsr w3, w0, #8 // w3<- CC 1222 GET_VREG s1, w2 1223 GET_VREG s2, w3 1224 mov w0, #1 1225 fcmp s1, s2 1226 csneg w0, w0, w0, pl 1227 csel w0, wzr, w0, eq 1228 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1229 GET_INST_OPCODE ip // extract opcode from rINST 1230 SET_VREG w0, w4 // vAA<- w0 1231 GOTO_OPCODE ip // jump to next instruction 1232 1233 1234/* ------------------------------ */ 1235 .balign 128 1236.L_op_cmpl_double: /* 0x2f */ 1237/* File: arm64/op_cmpl_double.S */ 1238/* File: arm64/fcmp.S */ 1239 /* 1240 * Compare two floating-point values. Puts 0, 1, or -1 into the 1241 * destination register based on the results of the comparison. 1242 */ 1243 /* op vAA, vBB, vCC */ 1244 FETCH w0, 1 // w0<- CCBB 1245 lsr w4, wINST, #8 // w4<- AA 1246 and w2, w0, #255 // w2<- BB 1247 lsr w3, w0, #8 // w3<- CC 1248 GET_VREG_WIDE d1, w2 1249 GET_VREG_WIDE d2, w3 1250 mov w0, #-1 1251 fcmp d1, d2 1252 csneg w0, w0, w0, le 1253 csel w0, wzr, w0, eq 1254 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1255 GET_INST_OPCODE ip // extract opcode from rINST 1256 SET_VREG w0, w4 // vAA<- w0 1257 GOTO_OPCODE ip // jump to next instruction 1258 1259 1260/* ------------------------------ */ 1261 .balign 128 1262.L_op_cmpg_double: /* 0x30 */ 1263/* File: arm64/op_cmpg_double.S */ 1264/* File: arm64/fcmp.S */ 1265 /* 1266 * Compare two floating-point values. Puts 0, 1, or -1 into the 1267 * destination register based on the results of the comparison. 1268 */ 1269 /* op vAA, vBB, vCC */ 1270 FETCH w0, 1 // w0<- CCBB 1271 lsr w4, wINST, #8 // w4<- AA 1272 and w2, w0, #255 // w2<- BB 1273 lsr w3, w0, #8 // w3<- CC 1274 GET_VREG_WIDE d1, w2 1275 GET_VREG_WIDE d2, w3 1276 mov w0, #1 1277 fcmp d1, d2 1278 csneg w0, w0, w0, pl 1279 csel w0, wzr, w0, eq 1280 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1281 GET_INST_OPCODE ip // extract opcode from rINST 1282 SET_VREG w0, w4 // vAA<- w0 1283 GOTO_OPCODE ip // jump to next instruction 1284 1285 1286/* ------------------------------ */ 1287 .balign 128 1288.L_op_cmp_long: /* 0x31 */ 1289/* File: arm64/op_cmp_long.S */ 1290 FETCH w0, 1 // w0<- CCBB 1291 lsr w4, wINST, #8 // w4<- AA 1292 and w2, w0, #255 // w2<- BB 1293 lsr w3, w0, #8 // w3<- CC 1294 GET_VREG_WIDE x1, w2 1295 GET_VREG_WIDE x2, w3 1296 cmp x1, x2 1297 csinc w0, wzr, wzr, eq 1298 csneg w0, w0, w0, ge 1299 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1300 SET_VREG w0, w4 1301 GET_INST_OPCODE ip // extract opcode from wINST 1302 GOTO_OPCODE ip // jump to next instruction 1303 1304/* ------------------------------ */ 1305 .balign 128 1306.L_op_if_eq: /* 0x32 */ 1307/* File: arm64/op_if_eq.S */ 1308/* File: arm64/bincmp.S */ 1309 /* 1310 * Generic two-operand compare-and-branch operation. Provide a "condition" 1311 * fragment that specifies the comparison to perform. 1312 * 1313 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1314 */ 1315 /* if-cmp vA, vB, +CCCC */ 1316 lsr w1, wINST, #12 // w1<- B 1317 ubfx w0, wINST, #8, #4 // w0<- A 1318 GET_VREG w3, w1 // w3<- vB 1319 GET_VREG w2, w0 // w2<- vA 1320 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1321 cmp w2, w3 // compare (vA, vB) 1322 b.eq MterpCommonTakenBranchNoFlags 1323 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1324 b.eq .L_check_not_taken_osr 1325 FETCH_ADVANCE_INST 2 1326 GET_INST_OPCODE ip // extract opcode from wINST 1327 GOTO_OPCODE ip // jump to next instruction 1328 1329 1330/* ------------------------------ */ 1331 .balign 128 1332.L_op_if_ne: /* 0x33 */ 1333/* File: arm64/op_if_ne.S */ 1334/* File: arm64/bincmp.S */ 1335 /* 1336 * Generic two-operand compare-and-branch operation. Provide a "condition" 1337 * fragment that specifies the comparison to perform. 1338 * 1339 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1340 */ 1341 /* if-cmp vA, vB, +CCCC */ 1342 lsr w1, wINST, #12 // w1<- B 1343 ubfx w0, wINST, #8, #4 // w0<- A 1344 GET_VREG w3, w1 // w3<- vB 1345 GET_VREG w2, w0 // w2<- vA 1346 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1347 cmp w2, w3 // compare (vA, vB) 1348 b.ne MterpCommonTakenBranchNoFlags 1349 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1350 b.eq .L_check_not_taken_osr 1351 FETCH_ADVANCE_INST 2 1352 GET_INST_OPCODE ip // extract opcode from wINST 1353 GOTO_OPCODE ip // jump to next instruction 1354 1355 1356/* ------------------------------ */ 1357 .balign 128 1358.L_op_if_lt: /* 0x34 */ 1359/* File: arm64/op_if_lt.S */ 1360/* File: arm64/bincmp.S */ 1361 /* 1362 * Generic two-operand compare-and-branch operation. Provide a "condition" 1363 * fragment that specifies the comparison to perform. 1364 * 1365 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1366 */ 1367 /* if-cmp vA, vB, +CCCC */ 1368 lsr w1, wINST, #12 // w1<- B 1369 ubfx w0, wINST, #8, #4 // w0<- A 1370 GET_VREG w3, w1 // w3<- vB 1371 GET_VREG w2, w0 // w2<- vA 1372 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1373 cmp w2, w3 // compare (vA, vB) 1374 b.lt MterpCommonTakenBranchNoFlags 1375 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1376 b.eq .L_check_not_taken_osr 1377 FETCH_ADVANCE_INST 2 1378 GET_INST_OPCODE ip // extract opcode from wINST 1379 GOTO_OPCODE ip // jump to next instruction 1380 1381 1382/* ------------------------------ */ 1383 .balign 128 1384.L_op_if_ge: /* 0x35 */ 1385/* File: arm64/op_if_ge.S */ 1386/* File: arm64/bincmp.S */ 1387 /* 1388 * Generic two-operand compare-and-branch operation. Provide a "condition" 1389 * fragment that specifies the comparison to perform. 1390 * 1391 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1392 */ 1393 /* if-cmp vA, vB, +CCCC */ 1394 lsr w1, wINST, #12 // w1<- B 1395 ubfx w0, wINST, #8, #4 // w0<- A 1396 GET_VREG w3, w1 // w3<- vB 1397 GET_VREG w2, w0 // w2<- vA 1398 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1399 cmp w2, w3 // compare (vA, vB) 1400 b.ge MterpCommonTakenBranchNoFlags 1401 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1402 b.eq .L_check_not_taken_osr 1403 FETCH_ADVANCE_INST 2 1404 GET_INST_OPCODE ip // extract opcode from wINST 1405 GOTO_OPCODE ip // jump to next instruction 1406 1407 1408/* ------------------------------ */ 1409 .balign 128 1410.L_op_if_gt: /* 0x36 */ 1411/* File: arm64/op_if_gt.S */ 1412/* File: arm64/bincmp.S */ 1413 /* 1414 * Generic two-operand compare-and-branch operation. Provide a "condition" 1415 * fragment that specifies the comparison to perform. 1416 * 1417 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1418 */ 1419 /* if-cmp vA, vB, +CCCC */ 1420 lsr w1, wINST, #12 // w1<- B 1421 ubfx w0, wINST, #8, #4 // w0<- A 1422 GET_VREG w3, w1 // w3<- vB 1423 GET_VREG w2, w0 // w2<- vA 1424 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1425 cmp w2, w3 // compare (vA, vB) 1426 b.gt MterpCommonTakenBranchNoFlags 1427 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1428 b.eq .L_check_not_taken_osr 1429 FETCH_ADVANCE_INST 2 1430 GET_INST_OPCODE ip // extract opcode from wINST 1431 GOTO_OPCODE ip // jump to next instruction 1432 1433 1434/* ------------------------------ */ 1435 .balign 128 1436.L_op_if_le: /* 0x37 */ 1437/* File: arm64/op_if_le.S */ 1438/* File: arm64/bincmp.S */ 1439 /* 1440 * Generic two-operand compare-and-branch operation. Provide a "condition" 1441 * fragment that specifies the comparison to perform. 1442 * 1443 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1444 */ 1445 /* if-cmp vA, vB, +CCCC */ 1446 lsr w1, wINST, #12 // w1<- B 1447 ubfx w0, wINST, #8, #4 // w0<- A 1448 GET_VREG w3, w1 // w3<- vB 1449 GET_VREG w2, w0 // w2<- vA 1450 FETCH_S wINST, 1 // wINST<- branch offset, in code units 1451 cmp w2, w3 // compare (vA, vB) 1452 b.le MterpCommonTakenBranchNoFlags 1453 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1454 b.eq .L_check_not_taken_osr 1455 FETCH_ADVANCE_INST 2 1456 GET_INST_OPCODE ip // extract opcode from wINST 1457 GOTO_OPCODE ip // jump to next instruction 1458 1459 1460/* ------------------------------ */ 1461 .balign 128 1462.L_op_if_eqz: /* 0x38 */ 1463/* File: arm64/op_if_eqz.S */ 1464/* File: arm64/zcmp.S */ 1465 /* 1466 * Generic one-operand compare-and-branch operation. Provide a "condition" 1467 * fragment that specifies the comparison to perform. 1468 * 1469 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1470 */ 1471 /* if-cmp vAA, +BBBB */ 1472 lsr w0, wINST, #8 // w0<- AA 1473 GET_VREG w2, w0 // w2<- vAA 1474 FETCH_S wINST, 1 // w1<- branch offset, in code units 1475 cmp w2, #0 // compare (vA, 0) 1476 b.eq MterpCommonTakenBranchNoFlags 1477 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1478 b.eq .L_check_not_taken_osr 1479 FETCH_ADVANCE_INST 2 1480 GET_INST_OPCODE ip // extract opcode from wINST 1481 GOTO_OPCODE ip // jump to next instruction 1482 1483 1484/* ------------------------------ */ 1485 .balign 128 1486.L_op_if_nez: /* 0x39 */ 1487/* File: arm64/op_if_nez.S */ 1488/* File: arm64/zcmp.S */ 1489 /* 1490 * Generic one-operand compare-and-branch operation. Provide a "condition" 1491 * fragment that specifies the comparison to perform. 1492 * 1493 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1494 */ 1495 /* if-cmp vAA, +BBBB */ 1496 lsr w0, wINST, #8 // w0<- AA 1497 GET_VREG w2, w0 // w2<- vAA 1498 FETCH_S wINST, 1 // w1<- branch offset, in code units 1499 cmp w2, #0 // compare (vA, 0) 1500 b.ne MterpCommonTakenBranchNoFlags 1501 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1502 b.eq .L_check_not_taken_osr 1503 FETCH_ADVANCE_INST 2 1504 GET_INST_OPCODE ip // extract opcode from wINST 1505 GOTO_OPCODE ip // jump to next instruction 1506 1507 1508/* ------------------------------ */ 1509 .balign 128 1510.L_op_if_ltz: /* 0x3a */ 1511/* File: arm64/op_if_ltz.S */ 1512/* File: arm64/zcmp.S */ 1513 /* 1514 * Generic one-operand compare-and-branch operation. Provide a "condition" 1515 * fragment that specifies the comparison to perform. 1516 * 1517 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1518 */ 1519 /* if-cmp vAA, +BBBB */ 1520 lsr w0, wINST, #8 // w0<- AA 1521 GET_VREG w2, w0 // w2<- vAA 1522 FETCH_S wINST, 1 // w1<- branch offset, in code units 1523 cmp w2, #0 // compare (vA, 0) 1524 b.lt MterpCommonTakenBranchNoFlags 1525 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1526 b.eq .L_check_not_taken_osr 1527 FETCH_ADVANCE_INST 2 1528 GET_INST_OPCODE ip // extract opcode from wINST 1529 GOTO_OPCODE ip // jump to next instruction 1530 1531 1532/* ------------------------------ */ 1533 .balign 128 1534.L_op_if_gez: /* 0x3b */ 1535/* File: arm64/op_if_gez.S */ 1536/* File: arm64/zcmp.S */ 1537 /* 1538 * Generic one-operand compare-and-branch operation. Provide a "condition" 1539 * fragment that specifies the comparison to perform. 1540 * 1541 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1542 */ 1543 /* if-cmp vAA, +BBBB */ 1544 lsr w0, wINST, #8 // w0<- AA 1545 GET_VREG w2, w0 // w2<- vAA 1546 FETCH_S wINST, 1 // w1<- branch offset, in code units 1547 cmp w2, #0 // compare (vA, 0) 1548 b.ge MterpCommonTakenBranchNoFlags 1549 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1550 b.eq .L_check_not_taken_osr 1551 FETCH_ADVANCE_INST 2 1552 GET_INST_OPCODE ip // extract opcode from wINST 1553 GOTO_OPCODE ip // jump to next instruction 1554 1555 1556/* ------------------------------ */ 1557 .balign 128 1558.L_op_if_gtz: /* 0x3c */ 1559/* File: arm64/op_if_gtz.S */ 1560/* File: arm64/zcmp.S */ 1561 /* 1562 * Generic one-operand compare-and-branch operation. Provide a "condition" 1563 * fragment that specifies the comparison to perform. 1564 * 1565 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1566 */ 1567 /* if-cmp vAA, +BBBB */ 1568 lsr w0, wINST, #8 // w0<- AA 1569 GET_VREG w2, w0 // w2<- vAA 1570 FETCH_S wINST, 1 // w1<- branch offset, in code units 1571 cmp w2, #0 // compare (vA, 0) 1572 b.gt MterpCommonTakenBranchNoFlags 1573 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1574 b.eq .L_check_not_taken_osr 1575 FETCH_ADVANCE_INST 2 1576 GET_INST_OPCODE ip // extract opcode from wINST 1577 GOTO_OPCODE ip // jump to next instruction 1578 1579 1580/* ------------------------------ */ 1581 .balign 128 1582.L_op_if_lez: /* 0x3d */ 1583/* File: arm64/op_if_lez.S */ 1584/* File: arm64/zcmp.S */ 1585 /* 1586 * Generic one-operand compare-and-branch operation. Provide a "condition" 1587 * fragment that specifies the comparison to perform. 1588 * 1589 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1590 */ 1591 /* if-cmp vAA, +BBBB */ 1592 lsr w0, wINST, #8 // w0<- AA 1593 GET_VREG w2, w0 // w2<- vAA 1594 FETCH_S wINST, 1 // w1<- branch offset, in code units 1595 cmp w2, #0 // compare (vA, 0) 1596 b.le MterpCommonTakenBranchNoFlags 1597 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 1598 b.eq .L_check_not_taken_osr 1599 FETCH_ADVANCE_INST 2 1600 GET_INST_OPCODE ip // extract opcode from wINST 1601 GOTO_OPCODE ip // jump to next instruction 1602 1603 1604/* ------------------------------ */ 1605 .balign 128 1606.L_op_unused_3e: /* 0x3e */ 1607/* File: arm64/op_unused_3e.S */ 1608/* File: arm64/unused.S */ 1609/* 1610 * Bail to reference interpreter to throw. 1611 */ 1612 b MterpFallback 1613 1614 1615/* ------------------------------ */ 1616 .balign 128 1617.L_op_unused_3f: /* 0x3f */ 1618/* File: arm64/op_unused_3f.S */ 1619/* File: arm64/unused.S */ 1620/* 1621 * Bail to reference interpreter to throw. 1622 */ 1623 b MterpFallback 1624 1625 1626/* ------------------------------ */ 1627 .balign 128 1628.L_op_unused_40: /* 0x40 */ 1629/* File: arm64/op_unused_40.S */ 1630/* File: arm64/unused.S */ 1631/* 1632 * Bail to reference interpreter to throw. 1633 */ 1634 b MterpFallback 1635 1636 1637/* ------------------------------ */ 1638 .balign 128 1639.L_op_unused_41: /* 0x41 */ 1640/* File: arm64/op_unused_41.S */ 1641/* File: arm64/unused.S */ 1642/* 1643 * Bail to reference interpreter to throw. 1644 */ 1645 b MterpFallback 1646 1647 1648/* ------------------------------ */ 1649 .balign 128 1650.L_op_unused_42: /* 0x42 */ 1651/* File: arm64/op_unused_42.S */ 1652/* File: arm64/unused.S */ 1653/* 1654 * Bail to reference interpreter to throw. 1655 */ 1656 b MterpFallback 1657 1658 1659/* ------------------------------ */ 1660 .balign 128 1661.L_op_unused_43: /* 0x43 */ 1662/* File: arm64/op_unused_43.S */ 1663/* File: arm64/unused.S */ 1664/* 1665 * Bail to reference interpreter to throw. 1666 */ 1667 b MterpFallback 1668 1669 1670/* ------------------------------ */ 1671 .balign 128 1672.L_op_aget: /* 0x44 */ 1673/* File: arm64/op_aget.S */ 1674 /* 1675 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1676 * 1677 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1678 * instructions. We use a pair of FETCH_Bs instead. 1679 * 1680 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1681 * 1682 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1683 * If this changes, specialize. 1684 */ 1685 /* op vAA, vBB, vCC */ 1686 FETCH_B w2, 1, 0 // w2<- BB 1687 lsr w9, wINST, #8 // w9<- AA 1688 FETCH_B w3, 1, 1 // w3<- CC 1689 GET_VREG w0, w2 // w0<- vBB (array object) 1690 GET_VREG w1, w3 // w1<- vCC (requested index) 1691 cbz x0, common_errNullObject // bail if null array object. 1692 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1693 add x0, x0, w1, uxtw #2 // w0<- arrayObj + index*width 1694 cmp w1, w3 // compare unsigned index, length 1695 bcs common_errArrayIndex // index >= length, bail 1696 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1697 ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1698 GET_INST_OPCODE ip // extract opcode from rINST 1699 SET_VREG w2, w9 // vAA<- w2 1700 GOTO_OPCODE ip // jump to next instruction 1701 1702/* ------------------------------ */ 1703 .balign 128 1704.L_op_aget_wide: /* 0x45 */ 1705/* File: arm64/op_aget_wide.S */ 1706 /* 1707 * Array get, 64 bits. vAA <- vBB[vCC]. 1708 * 1709 */ 1710 /* aget-wide vAA, vBB, vCC */ 1711 FETCH w0, 1 // w0<- CCBB 1712 lsr w4, wINST, #8 // w4<- AA 1713 and w2, w0, #255 // w2<- BB 1714 lsr w3, w0, #8 // w3<- CC 1715 GET_VREG w0, w2 // w0<- vBB (array object) 1716 GET_VREG w1, w3 // w1<- vCC (requested index) 1717 cbz w0, common_errNullObject // yes, bail 1718 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1719 add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width 1720 cmp w1, w3 // compare unsigned index, length 1721 bcs common_errArrayIndex // index >= length, bail 1722 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1723 ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] 1724 GET_INST_OPCODE ip // extract opcode from wINST 1725 SET_VREG_WIDE x2, w4 1726 GOTO_OPCODE ip // jump to next instruction 1727 1728/* ------------------------------ */ 1729 .balign 128 1730.L_op_aget_object: /* 0x46 */ 1731/* File: arm64/op_aget_object.S */ 1732 /* 1733 * Array object get. vAA <- vBB[vCC]. 1734 * 1735 * for: aget-object 1736 */ 1737 /* op vAA, vBB, vCC */ 1738 FETCH_B w2, 1, 0 // w2<- BB 1739 FETCH_B w3, 1, 1 // w3<- CC 1740 EXPORT_PC 1741 GET_VREG w0, w2 // w0<- vBB (array object) 1742 GET_VREG w1, w3 // w1<- vCC (requested index) 1743 bl artAGetObjectFromMterp // (array, index) 1744 ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] 1745 lsr w2, wINST, #8 // w9<- AA 1746 PREFETCH_INST 2 1747 cbnz w1, MterpException 1748 SET_VREG_OBJECT w0, w2 1749 ADVANCE 2 1750 GET_INST_OPCODE ip 1751 GOTO_OPCODE ip // jump to next instruction 1752 1753/* ------------------------------ */ 1754 .balign 128 1755.L_op_aget_boolean: /* 0x47 */ 1756/* File: arm64/op_aget_boolean.S */ 1757/* File: arm64/op_aget.S */ 1758 /* 1759 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1760 * 1761 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1762 * instructions. We use a pair of FETCH_Bs instead. 1763 * 1764 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1765 * 1766 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1767 * If this changes, specialize. 1768 */ 1769 /* op vAA, vBB, vCC */ 1770 FETCH_B w2, 1, 0 // w2<- BB 1771 lsr w9, wINST, #8 // w9<- AA 1772 FETCH_B w3, 1, 1 // w3<- CC 1773 GET_VREG w0, w2 // w0<- vBB (array object) 1774 GET_VREG w1, w3 // w1<- vCC (requested index) 1775 cbz x0, common_errNullObject // bail if null array object. 1776 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1777 add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width 1778 cmp w1, w3 // compare unsigned index, length 1779 bcs common_errArrayIndex // index >= length, bail 1780 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1781 ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1782 GET_INST_OPCODE ip // extract opcode from rINST 1783 SET_VREG w2, w9 // vAA<- w2 1784 GOTO_OPCODE ip // jump to next instruction 1785 1786 1787/* ------------------------------ */ 1788 .balign 128 1789.L_op_aget_byte: /* 0x48 */ 1790/* File: arm64/op_aget_byte.S */ 1791/* File: arm64/op_aget.S */ 1792 /* 1793 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1794 * 1795 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1796 * instructions. We use a pair of FETCH_Bs instead. 1797 * 1798 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1799 * 1800 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1801 * If this changes, specialize. 1802 */ 1803 /* op vAA, vBB, vCC */ 1804 FETCH_B w2, 1, 0 // w2<- BB 1805 lsr w9, wINST, #8 // w9<- AA 1806 FETCH_B w3, 1, 1 // w3<- CC 1807 GET_VREG w0, w2 // w0<- vBB (array object) 1808 GET_VREG w1, w3 // w1<- vCC (requested index) 1809 cbz x0, common_errNullObject // bail if null array object. 1810 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1811 add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width 1812 cmp w1, w3 // compare unsigned index, length 1813 bcs common_errArrayIndex // index >= length, bail 1814 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1815 ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1816 GET_INST_OPCODE ip // extract opcode from rINST 1817 SET_VREG w2, w9 // vAA<- w2 1818 GOTO_OPCODE ip // jump to next instruction 1819 1820 1821/* ------------------------------ */ 1822 .balign 128 1823.L_op_aget_char: /* 0x49 */ 1824/* File: arm64/op_aget_char.S */ 1825/* File: arm64/op_aget.S */ 1826 /* 1827 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1828 * 1829 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1830 * instructions. We use a pair of FETCH_Bs instead. 1831 * 1832 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1833 * 1834 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1835 * If this changes, specialize. 1836 */ 1837 /* op vAA, vBB, vCC */ 1838 FETCH_B w2, 1, 0 // w2<- BB 1839 lsr w9, wINST, #8 // w9<- AA 1840 FETCH_B w3, 1, 1 // w3<- CC 1841 GET_VREG w0, w2 // w0<- vBB (array object) 1842 GET_VREG w1, w3 // w1<- vCC (requested index) 1843 cbz x0, common_errNullObject // bail if null array object. 1844 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1845 add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width 1846 cmp w1, w3 // compare unsigned index, length 1847 bcs common_errArrayIndex // index >= length, bail 1848 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1849 ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1850 GET_INST_OPCODE ip // extract opcode from rINST 1851 SET_VREG w2, w9 // vAA<- w2 1852 GOTO_OPCODE ip // jump to next instruction 1853 1854 1855/* ------------------------------ */ 1856 .balign 128 1857.L_op_aget_short: /* 0x4a */ 1858/* File: arm64/op_aget_short.S */ 1859/* File: arm64/op_aget.S */ 1860 /* 1861 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1862 * 1863 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1864 * instructions. We use a pair of FETCH_Bs instead. 1865 * 1866 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1867 * 1868 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1869 * If this changes, specialize. 1870 */ 1871 /* op vAA, vBB, vCC */ 1872 FETCH_B w2, 1, 0 // w2<- BB 1873 lsr w9, wINST, #8 // w9<- AA 1874 FETCH_B w3, 1, 1 // w3<- CC 1875 GET_VREG w0, w2 // w0<- vBB (array object) 1876 GET_VREG w1, w3 // w1<- vCC (requested index) 1877 cbz x0, common_errNullObject // bail if null array object. 1878 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1879 add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width 1880 cmp w1, w3 // compare unsigned index, length 1881 bcs common_errArrayIndex // index >= length, bail 1882 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1883 ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] 1884 GET_INST_OPCODE ip // extract opcode from rINST 1885 SET_VREG w2, w9 // vAA<- w2 1886 GOTO_OPCODE ip // jump to next instruction 1887 1888 1889/* ------------------------------ */ 1890 .balign 128 1891.L_op_aput: /* 0x4b */ 1892/* File: arm64/op_aput.S */ 1893 /* 1894 * Array put, 32 bits or less. vBB[vCC] <- vAA. 1895 * 1896 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1897 * instructions. We use a pair of FETCH_Bs instead. 1898 * 1899 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 1900 * 1901 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 1902 * If this changes, specialize. 1903 */ 1904 /* op vAA, vBB, vCC */ 1905 FETCH_B w2, 1, 0 // w2<- BB 1906 lsr w9, wINST, #8 // w9<- AA 1907 FETCH_B w3, 1, 1 // w3<- CC 1908 GET_VREG w0, w2 // w0<- vBB (array object) 1909 GET_VREG w1, w3 // w1<- vCC (requested index) 1910 cbz w0, common_errNullObject // bail if null 1911 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1912 add x0, x0, w1, lsl #2 // w0<- arrayObj + index*width 1913 cmp w1, w3 // compare unsigned index, length 1914 bcs common_errArrayIndex // index >= length, bail 1915 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1916 GET_VREG w2, w9 // w2<- vAA 1917 GET_INST_OPCODE ip // extract opcode from rINST 1918 str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 1919 GOTO_OPCODE ip // jump to next instruction 1920 1921/* ------------------------------ */ 1922 .balign 128 1923.L_op_aput_wide: /* 0x4c */ 1924/* File: arm64/op_aput_wide.S */ 1925 /* 1926 * Array put, 64 bits. vBB[vCC] <- vAA. 1927 * 1928 */ 1929 /* aput-wide vAA, vBB, vCC */ 1930 FETCH w0, 1 // w0<- CCBB 1931 lsr w4, wINST, #8 // w4<- AA 1932 and w2, w0, #255 // w2<- BB 1933 lsr w3, w0, #8 // w3<- CC 1934 GET_VREG w0, w2 // w0<- vBB (array object) 1935 GET_VREG w1, w3 // w1<- vCC (requested index) 1936 cbz w0, common_errNullObject // bail if null 1937 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1938 add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width 1939 cmp w1, w3 // compare unsigned index, length 1940 bcs common_errArrayIndex // index >= length, bail 1941 GET_VREG_WIDE x1, w4 1942 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 1943 GET_INST_OPCODE ip // extract opcode from wINST 1944 str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] 1945 GOTO_OPCODE ip // jump to next instruction 1946 1947/* ------------------------------ */ 1948 .balign 128 1949.L_op_aput_object: /* 0x4d */ 1950/* File: arm64/op_aput_object.S */ 1951 /* 1952 * Store an object into an array. vBB[vCC] <- vAA. 1953 */ 1954 /* op vAA, vBB, vCC */ 1955 EXPORT_PC 1956 add x0, xFP, #OFF_FP_SHADOWFRAME 1957 mov x1, xPC 1958 mov w2, wINST 1959 bl MterpAputObject 1960 cbz w0, MterpPossibleException 1961 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1962 GET_INST_OPCODE ip // extract opcode from rINST 1963 GOTO_OPCODE ip // jump to next instruction 1964 1965/* ------------------------------ */ 1966 .balign 128 1967.L_op_aput_boolean: /* 0x4e */ 1968/* File: arm64/op_aput_boolean.S */ 1969/* File: arm64/op_aput.S */ 1970 /* 1971 * Array put, 32 bits or less. vBB[vCC] <- vAA. 1972 * 1973 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1974 * instructions. We use a pair of FETCH_Bs instead. 1975 * 1976 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 1977 * 1978 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 1979 * If this changes, specialize. 1980 */ 1981 /* op vAA, vBB, vCC */ 1982 FETCH_B w2, 1, 0 // w2<- BB 1983 lsr w9, wINST, #8 // w9<- AA 1984 FETCH_B w3, 1, 1 // w3<- CC 1985 GET_VREG w0, w2 // w0<- vBB (array object) 1986 GET_VREG w1, w3 // w1<- vCC (requested index) 1987 cbz w0, common_errNullObject // bail if null 1988 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 1989 add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width 1990 cmp w1, w3 // compare unsigned index, length 1991 bcs common_errArrayIndex // index >= length, bail 1992 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 1993 GET_VREG w2, w9 // w2<- vAA 1994 GET_INST_OPCODE ip // extract opcode from rINST 1995 strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 1996 GOTO_OPCODE ip // jump to next instruction 1997 1998 1999/* ------------------------------ */ 2000 .balign 128 2001.L_op_aput_byte: /* 0x4f */ 2002/* File: arm64/op_aput_byte.S */ 2003/* File: arm64/op_aput.S */ 2004 /* 2005 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2006 * 2007 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2008 * instructions. We use a pair of FETCH_Bs instead. 2009 * 2010 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2011 * 2012 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2013 * If this changes, specialize. 2014 */ 2015 /* op vAA, vBB, vCC */ 2016 FETCH_B w2, 1, 0 // w2<- BB 2017 lsr w9, wINST, #8 // w9<- AA 2018 FETCH_B w3, 1, 1 // w3<- CC 2019 GET_VREG w0, w2 // w0<- vBB (array object) 2020 GET_VREG w1, w3 // w1<- vCC (requested index) 2021 cbz w0, common_errNullObject // bail if null 2022 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2023 add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width 2024 cmp w1, w3 // compare unsigned index, length 2025 bcs common_errArrayIndex // index >= length, bail 2026 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2027 GET_VREG w2, w9 // w2<- vAA 2028 GET_INST_OPCODE ip // extract opcode from rINST 2029 strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2030 GOTO_OPCODE ip // jump to next instruction 2031 2032 2033/* ------------------------------ */ 2034 .balign 128 2035.L_op_aput_char: /* 0x50 */ 2036/* File: arm64/op_aput_char.S */ 2037/* File: arm64/op_aput.S */ 2038 /* 2039 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2040 * 2041 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2042 * instructions. We use a pair of FETCH_Bs instead. 2043 * 2044 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2045 * 2046 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2047 * If this changes, specialize. 2048 */ 2049 /* op vAA, vBB, vCC */ 2050 FETCH_B w2, 1, 0 // w2<- BB 2051 lsr w9, wINST, #8 // w9<- AA 2052 FETCH_B w3, 1, 1 // w3<- CC 2053 GET_VREG w0, w2 // w0<- vBB (array object) 2054 GET_VREG w1, w3 // w1<- vCC (requested index) 2055 cbz w0, common_errNullObject // bail if null 2056 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2057 add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width 2058 cmp w1, w3 // compare unsigned index, length 2059 bcs common_errArrayIndex // index >= length, bail 2060 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2061 GET_VREG w2, w9 // w2<- vAA 2062 GET_INST_OPCODE ip // extract opcode from rINST 2063 strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2064 GOTO_OPCODE ip // jump to next instruction 2065 2066 2067/* ------------------------------ */ 2068 .balign 128 2069.L_op_aput_short: /* 0x51 */ 2070/* File: arm64/op_aput_short.S */ 2071/* File: arm64/op_aput.S */ 2072 /* 2073 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2074 * 2075 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2076 * instructions. We use a pair of FETCH_Bs instead. 2077 * 2078 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2079 * 2080 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2081 * If this changes, specialize. 2082 */ 2083 /* op vAA, vBB, vCC */ 2084 FETCH_B w2, 1, 0 // w2<- BB 2085 lsr w9, wINST, #8 // w9<- AA 2086 FETCH_B w3, 1, 1 // w3<- CC 2087 GET_VREG w0, w2 // w0<- vBB (array object) 2088 GET_VREG w1, w3 // w1<- vCC (requested index) 2089 cbz w0, common_errNullObject // bail if null 2090 ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length 2091 add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width 2092 cmp w1, w3 // compare unsigned index, length 2093 bcs common_errArrayIndex // index >= length, bail 2094 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2095 GET_VREG w2, w9 // w2<- vAA 2096 GET_INST_OPCODE ip // extract opcode from rINST 2097 strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 2098 GOTO_OPCODE ip // jump to next instruction 2099 2100 2101/* ------------------------------ */ 2102 .balign 128 2103.L_op_iget: /* 0x52 */ 2104/* File: arm64/op_iget.S */ 2105 /* 2106 * General instance field get. 2107 * 2108 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2109 */ 2110 EXPORT_PC 2111 FETCH w0, 1 // w0<- field ref CCCC 2112 lsr w1, wINST, #12 // w1<- B 2113 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2114 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2115 mov x3, xSELF // w3<- self 2116 bl artGet32InstanceFromCode 2117 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2118 2119 ubfx w2, wINST, #8, #4 // w2<- A 2120 PREFETCH_INST 2 2121 cbnz x3, MterpPossibleException // bail out 2122 .if 0 2123 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2124 .else 2125 SET_VREG w0, w2 // fp[A]<- w0 2126 .endif 2127 ADVANCE 2 2128 GET_INST_OPCODE ip // extract opcode from rINST 2129 GOTO_OPCODE ip // jump to next instruction 2130 2131/* ------------------------------ */ 2132 .balign 128 2133.L_op_iget_wide: /* 0x53 */ 2134/* File: arm64/op_iget_wide.S */ 2135 /* 2136 * 64-bit instance field get. 2137 * 2138 * for: iget-wide 2139 */ 2140 EXPORT_PC 2141 FETCH w0, 1 // w0<- field ref CCCC 2142 lsr w1, wINST, #12 // w1<- B 2143 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2144 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2145 mov x3, xSELF // w3<- self 2146 bl artGet64InstanceFromCode 2147 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2148 ubfx w2, wINST, #8, #4 // w2<- A 2149 PREFETCH_INST 2 2150 cmp w3, #0 2151 cbnz w3, MterpException // bail out 2152 SET_VREG_WIDE x0, w2 2153 ADVANCE 2 2154 GET_INST_OPCODE ip // extract opcode from wINST 2155 GOTO_OPCODE ip // jump to next instruction 2156 2157/* ------------------------------ */ 2158 .balign 128 2159.L_op_iget_object: /* 0x54 */ 2160/* File: arm64/op_iget_object.S */ 2161/* File: arm64/op_iget.S */ 2162 /* 2163 * General instance field get. 2164 * 2165 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2166 */ 2167 EXPORT_PC 2168 FETCH w0, 1 // w0<- field ref CCCC 2169 lsr w1, wINST, #12 // w1<- B 2170 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2171 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2172 mov x3, xSELF // w3<- self 2173 bl artGetObjInstanceFromCode 2174 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2175 2176 ubfx w2, wINST, #8, #4 // w2<- A 2177 PREFETCH_INST 2 2178 cbnz x3, MterpPossibleException // bail out 2179 .if 1 2180 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2181 .else 2182 SET_VREG w0, w2 // fp[A]<- w0 2183 .endif 2184 ADVANCE 2 2185 GET_INST_OPCODE ip // extract opcode from rINST 2186 GOTO_OPCODE ip // jump to next instruction 2187 2188 2189/* ------------------------------ */ 2190 .balign 128 2191.L_op_iget_boolean: /* 0x55 */ 2192/* File: arm64/op_iget_boolean.S */ 2193/* File: arm64/op_iget.S */ 2194 /* 2195 * General instance field get. 2196 * 2197 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2198 */ 2199 EXPORT_PC 2200 FETCH w0, 1 // w0<- field ref CCCC 2201 lsr w1, wINST, #12 // w1<- B 2202 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2203 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2204 mov x3, xSELF // w3<- self 2205 bl artGetBooleanInstanceFromCode 2206 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2207 uxtb w0, w0 2208 ubfx w2, wINST, #8, #4 // w2<- A 2209 PREFETCH_INST 2 2210 cbnz x3, MterpPossibleException // bail out 2211 .if 0 2212 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2213 .else 2214 SET_VREG w0, w2 // fp[A]<- w0 2215 .endif 2216 ADVANCE 2 2217 GET_INST_OPCODE ip // extract opcode from rINST 2218 GOTO_OPCODE ip // jump to next instruction 2219 2220 2221/* ------------------------------ */ 2222 .balign 128 2223.L_op_iget_byte: /* 0x56 */ 2224/* File: arm64/op_iget_byte.S */ 2225/* File: arm64/op_iget.S */ 2226 /* 2227 * General instance field get. 2228 * 2229 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2230 */ 2231 EXPORT_PC 2232 FETCH w0, 1 // w0<- field ref CCCC 2233 lsr w1, wINST, #12 // w1<- B 2234 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2235 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2236 mov x3, xSELF // w3<- self 2237 bl artGetByteInstanceFromCode 2238 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2239 sxtb w0, w0 2240 ubfx w2, wINST, #8, #4 // w2<- A 2241 PREFETCH_INST 2 2242 cbnz x3, MterpPossibleException // bail out 2243 .if 0 2244 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2245 .else 2246 SET_VREG w0, w2 // fp[A]<- w0 2247 .endif 2248 ADVANCE 2 2249 GET_INST_OPCODE ip // extract opcode from rINST 2250 GOTO_OPCODE ip // jump to next instruction 2251 2252 2253/* ------------------------------ */ 2254 .balign 128 2255.L_op_iget_char: /* 0x57 */ 2256/* File: arm64/op_iget_char.S */ 2257/* File: arm64/op_iget.S */ 2258 /* 2259 * General instance field get. 2260 * 2261 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2262 */ 2263 EXPORT_PC 2264 FETCH w0, 1 // w0<- field ref CCCC 2265 lsr w1, wINST, #12 // w1<- B 2266 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2267 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2268 mov x3, xSELF // w3<- self 2269 bl artGetCharInstanceFromCode 2270 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2271 uxth w0, w0 2272 ubfx w2, wINST, #8, #4 // w2<- A 2273 PREFETCH_INST 2 2274 cbnz x3, MterpPossibleException // bail out 2275 .if 0 2276 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2277 .else 2278 SET_VREG w0, w2 // fp[A]<- w0 2279 .endif 2280 ADVANCE 2 2281 GET_INST_OPCODE ip // extract opcode from rINST 2282 GOTO_OPCODE ip // jump to next instruction 2283 2284 2285/* ------------------------------ */ 2286 .balign 128 2287.L_op_iget_short: /* 0x58 */ 2288/* File: arm64/op_iget_short.S */ 2289/* File: arm64/op_iget.S */ 2290 /* 2291 * General instance field get. 2292 * 2293 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2294 */ 2295 EXPORT_PC 2296 FETCH w0, 1 // w0<- field ref CCCC 2297 lsr w1, wINST, #12 // w1<- B 2298 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2299 ldr x2, [xFP, #OFF_FP_METHOD] // w2<- referrer 2300 mov x3, xSELF // w3<- self 2301 bl artGetShortInstanceFromCode 2302 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2303 sxth w0, w0 2304 ubfx w2, wINST, #8, #4 // w2<- A 2305 PREFETCH_INST 2 2306 cbnz x3, MterpPossibleException // bail out 2307 .if 0 2308 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 2309 .else 2310 SET_VREG w0, w2 // fp[A]<- w0 2311 .endif 2312 ADVANCE 2 2313 GET_INST_OPCODE ip // extract opcode from rINST 2314 GOTO_OPCODE ip // jump to next instruction 2315 2316 2317/* ------------------------------ */ 2318 .balign 128 2319.L_op_iput: /* 0x59 */ 2320/* File: arm64/op_iput.S */ 2321 /* 2322 * General 32-bit instance field put. 2323 * 2324 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2325 */ 2326 /* op vA, vB, field//CCCC */ 2327 .extern artSet32InstanceFromMterp 2328 EXPORT_PC 2329 FETCH w0, 1 // w0<- field ref CCCC 2330 lsr w1, wINST, #12 // w1<- B 2331 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2332 ubfx w2, wINST, #8, #4 // w2<- A 2333 GET_VREG w2, w2 // w2<- fp[A] 2334 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2335 PREFETCH_INST 2 2336 bl artSet32InstanceFromMterp 2337 cbnz w0, MterpPossibleException 2338 ADVANCE 2 // advance rPC 2339 GET_INST_OPCODE ip // extract opcode from rINST 2340 GOTO_OPCODE ip // jump to next instruction 2341 2342/* ------------------------------ */ 2343 .balign 128 2344.L_op_iput_wide: /* 0x5a */ 2345/* File: arm64/op_iput_wide.S */ 2346 /* iput-wide vA, vB, field//CCCC */ 2347 .extern artSet64InstanceFromMterp 2348 EXPORT_PC 2349 FETCH w0, 1 // w0<- field ref CCCC 2350 lsr w1, wINST, #12 // w1<- B 2351 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2352 ubfx w2, wINST, #8, #4 // w2<- A 2353 VREG_INDEX_TO_ADDR x2, x2 // w2<- &fp[A] 2354 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2355 PREFETCH_INST 2 2356 bl artSet64InstanceFromMterp 2357 cbnz w0, MterpPossibleException 2358 ADVANCE 2 // advance rPC 2359 GET_INST_OPCODE ip // extract opcode from wINST 2360 GOTO_OPCODE ip // jump to next instruction 2361 2362/* ------------------------------ */ 2363 .balign 128 2364.L_op_iput_object: /* 0x5b */ 2365/* File: arm64/op_iput_object.S */ 2366 EXPORT_PC 2367 add x0, xFP, #OFF_FP_SHADOWFRAME 2368 mov x1, xPC 2369 mov w2, wINST 2370 mov x3, xSELF 2371 bl MterpIputObject 2372 cbz w0, MterpException 2373 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2374 GET_INST_OPCODE ip // extract opcode from rINST 2375 GOTO_OPCODE ip // jump to next instruction 2376 2377/* ------------------------------ */ 2378 .balign 128 2379.L_op_iput_boolean: /* 0x5c */ 2380/* File: arm64/op_iput_boolean.S */ 2381/* File: arm64/op_iput.S */ 2382 /* 2383 * General 32-bit instance field put. 2384 * 2385 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2386 */ 2387 /* op vA, vB, field//CCCC */ 2388 .extern artSet8InstanceFromMterp 2389 EXPORT_PC 2390 FETCH w0, 1 // w0<- field ref CCCC 2391 lsr w1, wINST, #12 // w1<- B 2392 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2393 ubfx w2, wINST, #8, #4 // w2<- A 2394 GET_VREG w2, w2 // w2<- fp[A] 2395 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2396 PREFETCH_INST 2 2397 bl artSet8InstanceFromMterp 2398 cbnz w0, MterpPossibleException 2399 ADVANCE 2 // advance rPC 2400 GET_INST_OPCODE ip // extract opcode from rINST 2401 GOTO_OPCODE ip // jump to next instruction 2402 2403 2404/* ------------------------------ */ 2405 .balign 128 2406.L_op_iput_byte: /* 0x5d */ 2407/* File: arm64/op_iput_byte.S */ 2408/* File: arm64/op_iput.S */ 2409 /* 2410 * General 32-bit instance field put. 2411 * 2412 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2413 */ 2414 /* op vA, vB, field//CCCC */ 2415 .extern artSet8InstanceFromMterp 2416 EXPORT_PC 2417 FETCH w0, 1 // w0<- field ref CCCC 2418 lsr w1, wINST, #12 // w1<- B 2419 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2420 ubfx w2, wINST, #8, #4 // w2<- A 2421 GET_VREG w2, w2 // w2<- fp[A] 2422 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2423 PREFETCH_INST 2 2424 bl artSet8InstanceFromMterp 2425 cbnz w0, MterpPossibleException 2426 ADVANCE 2 // advance rPC 2427 GET_INST_OPCODE ip // extract opcode from rINST 2428 GOTO_OPCODE ip // jump to next instruction 2429 2430 2431/* ------------------------------ */ 2432 .balign 128 2433.L_op_iput_char: /* 0x5e */ 2434/* File: arm64/op_iput_char.S */ 2435/* File: arm64/op_iput.S */ 2436 /* 2437 * General 32-bit instance field put. 2438 * 2439 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2440 */ 2441 /* op vA, vB, field//CCCC */ 2442 .extern artSet16InstanceFromMterp 2443 EXPORT_PC 2444 FETCH w0, 1 // w0<- field ref CCCC 2445 lsr w1, wINST, #12 // w1<- B 2446 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2447 ubfx w2, wINST, #8, #4 // w2<- A 2448 GET_VREG w2, w2 // w2<- fp[A] 2449 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2450 PREFETCH_INST 2 2451 bl artSet16InstanceFromMterp 2452 cbnz w0, MterpPossibleException 2453 ADVANCE 2 // advance rPC 2454 GET_INST_OPCODE ip // extract opcode from rINST 2455 GOTO_OPCODE ip // jump to next instruction 2456 2457 2458/* ------------------------------ */ 2459 .balign 128 2460.L_op_iput_short: /* 0x5f */ 2461/* File: arm64/op_iput_short.S */ 2462/* File: arm64/op_iput.S */ 2463 /* 2464 * General 32-bit instance field put. 2465 * 2466 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2467 */ 2468 /* op vA, vB, field//CCCC */ 2469 .extern artSet16InstanceFromMterp 2470 EXPORT_PC 2471 FETCH w0, 1 // w0<- field ref CCCC 2472 lsr w1, wINST, #12 // w1<- B 2473 GET_VREG w1, w1 // w1<- fp[B], the object pointer 2474 ubfx w2, wINST, #8, #4 // w2<- A 2475 GET_VREG w2, w2 // w2<- fp[A] 2476 ldr x3, [xFP, #OFF_FP_METHOD] // w3<- referrer 2477 PREFETCH_INST 2 2478 bl artSet16InstanceFromMterp 2479 cbnz w0, MterpPossibleException 2480 ADVANCE 2 // advance rPC 2481 GET_INST_OPCODE ip // extract opcode from rINST 2482 GOTO_OPCODE ip // jump to next instruction 2483 2484 2485/* ------------------------------ */ 2486 .balign 128 2487.L_op_sget: /* 0x60 */ 2488/* File: arm64/op_sget.S */ 2489 /* 2490 * General SGET handler wrapper. 2491 * 2492 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2493 */ 2494 /* op vAA, field//BBBB */ 2495 2496 .extern artGet32StaticFromCode 2497 EXPORT_PC 2498 FETCH w0, 1 // w0<- field ref BBBB 2499 ldr x1, [xFP, #OFF_FP_METHOD] 2500 mov x2, xSELF 2501 bl artGet32StaticFromCode 2502 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2503 lsr w2, wINST, #8 // w2<- AA 2504 2505 PREFETCH_INST 2 2506 cbnz x3, MterpException // bail out 2507.if 0 2508 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2509.else 2510 SET_VREG w0, w2 // fp[AA]<- w0 2511.endif 2512 ADVANCE 2 2513 GET_INST_OPCODE ip // extract opcode from rINST 2514 GOTO_OPCODE ip 2515 2516/* ------------------------------ */ 2517 .balign 128 2518.L_op_sget_wide: /* 0x61 */ 2519/* File: arm64/op_sget_wide.S */ 2520 /* 2521 * SGET_WIDE handler wrapper. 2522 * 2523 */ 2524 /* sget-wide vAA, field//BBBB */ 2525 2526 .extern artGet64StaticFromCode 2527 EXPORT_PC 2528 FETCH w0, 1 // w0<- field ref BBBB 2529 ldr x1, [xFP, #OFF_FP_METHOD] 2530 mov x2, xSELF 2531 bl artGet64StaticFromCode 2532 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2533 lsr w4, wINST, #8 // w4<- AA 2534 cbnz x3, MterpException // bail out 2535 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 2536 SET_VREG_WIDE x0, w4 2537 GET_INST_OPCODE ip // extract opcode from wINST 2538 GOTO_OPCODE ip // jump to next instruction 2539 2540/* ------------------------------ */ 2541 .balign 128 2542.L_op_sget_object: /* 0x62 */ 2543/* File: arm64/op_sget_object.S */ 2544/* File: arm64/op_sget.S */ 2545 /* 2546 * General SGET handler wrapper. 2547 * 2548 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2549 */ 2550 /* op vAA, field//BBBB */ 2551 2552 .extern artGetObjStaticFromCode 2553 EXPORT_PC 2554 FETCH w0, 1 // w0<- field ref BBBB 2555 ldr x1, [xFP, #OFF_FP_METHOD] 2556 mov x2, xSELF 2557 bl artGetObjStaticFromCode 2558 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2559 lsr w2, wINST, #8 // w2<- AA 2560 2561 PREFETCH_INST 2 2562 cbnz x3, MterpException // bail out 2563.if 1 2564 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2565.else 2566 SET_VREG w0, w2 // fp[AA]<- w0 2567.endif 2568 ADVANCE 2 2569 GET_INST_OPCODE ip // extract opcode from rINST 2570 GOTO_OPCODE ip 2571 2572 2573/* ------------------------------ */ 2574 .balign 128 2575.L_op_sget_boolean: /* 0x63 */ 2576/* File: arm64/op_sget_boolean.S */ 2577/* File: arm64/op_sget.S */ 2578 /* 2579 * General SGET handler wrapper. 2580 * 2581 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2582 */ 2583 /* op vAA, field//BBBB */ 2584 2585 .extern artGetBooleanStaticFromCode 2586 EXPORT_PC 2587 FETCH w0, 1 // w0<- field ref BBBB 2588 ldr x1, [xFP, #OFF_FP_METHOD] 2589 mov x2, xSELF 2590 bl artGetBooleanStaticFromCode 2591 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2592 lsr w2, wINST, #8 // w2<- AA 2593 uxtb w0, w0 2594 PREFETCH_INST 2 2595 cbnz x3, MterpException // bail out 2596.if 0 2597 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2598.else 2599 SET_VREG w0, w2 // fp[AA]<- w0 2600.endif 2601 ADVANCE 2 2602 GET_INST_OPCODE ip // extract opcode from rINST 2603 GOTO_OPCODE ip 2604 2605 2606/* ------------------------------ */ 2607 .balign 128 2608.L_op_sget_byte: /* 0x64 */ 2609/* File: arm64/op_sget_byte.S */ 2610/* File: arm64/op_sget.S */ 2611 /* 2612 * General SGET handler wrapper. 2613 * 2614 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2615 */ 2616 /* op vAA, field//BBBB */ 2617 2618 .extern artGetByteStaticFromCode 2619 EXPORT_PC 2620 FETCH w0, 1 // w0<- field ref BBBB 2621 ldr x1, [xFP, #OFF_FP_METHOD] 2622 mov x2, xSELF 2623 bl artGetByteStaticFromCode 2624 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2625 lsr w2, wINST, #8 // w2<- AA 2626 sxtb w0, w0 2627 PREFETCH_INST 2 2628 cbnz x3, MterpException // bail out 2629.if 0 2630 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2631.else 2632 SET_VREG w0, w2 // fp[AA]<- w0 2633.endif 2634 ADVANCE 2 2635 GET_INST_OPCODE ip // extract opcode from rINST 2636 GOTO_OPCODE ip 2637 2638 2639/* ------------------------------ */ 2640 .balign 128 2641.L_op_sget_char: /* 0x65 */ 2642/* File: arm64/op_sget_char.S */ 2643/* File: arm64/op_sget.S */ 2644 /* 2645 * General SGET handler wrapper. 2646 * 2647 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2648 */ 2649 /* op vAA, field//BBBB */ 2650 2651 .extern artGetCharStaticFromCode 2652 EXPORT_PC 2653 FETCH w0, 1 // w0<- field ref BBBB 2654 ldr x1, [xFP, #OFF_FP_METHOD] 2655 mov x2, xSELF 2656 bl artGetCharStaticFromCode 2657 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2658 lsr w2, wINST, #8 // w2<- AA 2659 uxth w0, w0 2660 PREFETCH_INST 2 2661 cbnz x3, MterpException // bail out 2662.if 0 2663 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2664.else 2665 SET_VREG w0, w2 // fp[AA]<- w0 2666.endif 2667 ADVANCE 2 2668 GET_INST_OPCODE ip // extract opcode from rINST 2669 GOTO_OPCODE ip 2670 2671 2672/* ------------------------------ */ 2673 .balign 128 2674.L_op_sget_short: /* 0x66 */ 2675/* File: arm64/op_sget_short.S */ 2676/* File: arm64/op_sget.S */ 2677 /* 2678 * General SGET handler wrapper. 2679 * 2680 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2681 */ 2682 /* op vAA, field//BBBB */ 2683 2684 .extern artGetShortStaticFromCode 2685 EXPORT_PC 2686 FETCH w0, 1 // w0<- field ref BBBB 2687 ldr x1, [xFP, #OFF_FP_METHOD] 2688 mov x2, xSELF 2689 bl artGetShortStaticFromCode 2690 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 2691 lsr w2, wINST, #8 // w2<- AA 2692 sxth w0, w0 2693 PREFETCH_INST 2 2694 cbnz x3, MterpException // bail out 2695.if 0 2696 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0 2697.else 2698 SET_VREG w0, w2 // fp[AA]<- w0 2699.endif 2700 ADVANCE 2 2701 GET_INST_OPCODE ip // extract opcode from rINST 2702 GOTO_OPCODE ip 2703 2704 2705/* ------------------------------ */ 2706 .balign 128 2707.L_op_sput: /* 0x67 */ 2708/* File: arm64/op_sput.S */ 2709 /* 2710 * General SPUT handler wrapper. 2711 * 2712 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2713 */ 2714 /* op vAA, field//BBBB */ 2715 EXPORT_PC 2716 FETCH w0, 1 // r0<- field ref BBBB 2717 lsr w3, wINST, #8 // r3<- AA 2718 GET_VREG w1, w3 // r1<= fp[AA] 2719 ldr x2, [xFP, #OFF_FP_METHOD] 2720 mov x3, xSELF 2721 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2722 bl artSet32StaticFromCode 2723 cbnz w0, MterpException // 0 on success 2724 ADVANCE 2 // Past exception point - now advance rPC 2725 GET_INST_OPCODE ip // extract opcode from rINST 2726 GOTO_OPCODE ip // jump to next instruction 2727 2728/* ------------------------------ */ 2729 .balign 128 2730.L_op_sput_wide: /* 0x68 */ 2731/* File: arm64/op_sput_wide.S */ 2732 /* 2733 * SPUT_WIDE handler wrapper. 2734 * 2735 */ 2736 /* sput-wide vAA, field//BBBB */ 2737 .extern artSet64IndirectStaticFromMterp 2738 EXPORT_PC 2739 FETCH w0, 1 // w0<- field ref BBBB 2740 ldr x1, [xFP, #OFF_FP_METHOD] 2741 lsr w2, wINST, #8 // w3<- AA 2742 VREG_INDEX_TO_ADDR x2, w2 2743 mov x3, xSELF 2744 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2745 bl artSet64IndirectStaticFromMterp 2746 cbnz w0, MterpException // 0 on success, -1 on failure 2747 ADVANCE 2 // Past exception point - now advance rPC 2748 GET_INST_OPCODE ip // extract opcode from wINST 2749 GOTO_OPCODE ip // jump to next instruction 2750 2751/* ------------------------------ */ 2752 .balign 128 2753.L_op_sput_object: /* 0x69 */ 2754/* File: arm64/op_sput_object.S */ 2755 EXPORT_PC 2756 add x0, xFP, #OFF_FP_SHADOWFRAME 2757 mov x1, xPC 2758 mov x2, xINST 2759 mov x3, xSELF 2760 bl MterpSputObject 2761 cbz w0, MterpException 2762 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 2763 GET_INST_OPCODE ip // extract opcode from rINST 2764 GOTO_OPCODE ip // jump to next instruction 2765 2766/* ------------------------------ */ 2767 .balign 128 2768.L_op_sput_boolean: /* 0x6a */ 2769/* File: arm64/op_sput_boolean.S */ 2770/* File: arm64/op_sput.S */ 2771 /* 2772 * General SPUT handler wrapper. 2773 * 2774 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2775 */ 2776 /* op vAA, field//BBBB */ 2777 EXPORT_PC 2778 FETCH w0, 1 // r0<- field ref BBBB 2779 lsr w3, wINST, #8 // r3<- AA 2780 GET_VREG w1, w3 // r1<= fp[AA] 2781 ldr x2, [xFP, #OFF_FP_METHOD] 2782 mov x3, xSELF 2783 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2784 bl artSet8StaticFromCode 2785 cbnz w0, MterpException // 0 on success 2786 ADVANCE 2 // Past exception point - now advance rPC 2787 GET_INST_OPCODE ip // extract opcode from rINST 2788 GOTO_OPCODE ip // jump to next instruction 2789 2790 2791/* ------------------------------ */ 2792 .balign 128 2793.L_op_sput_byte: /* 0x6b */ 2794/* File: arm64/op_sput_byte.S */ 2795/* File: arm64/op_sput.S */ 2796 /* 2797 * General SPUT handler wrapper. 2798 * 2799 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2800 */ 2801 /* op vAA, field//BBBB */ 2802 EXPORT_PC 2803 FETCH w0, 1 // r0<- field ref BBBB 2804 lsr w3, wINST, #8 // r3<- AA 2805 GET_VREG w1, w3 // r1<= fp[AA] 2806 ldr x2, [xFP, #OFF_FP_METHOD] 2807 mov x3, xSELF 2808 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2809 bl artSet8StaticFromCode 2810 cbnz w0, MterpException // 0 on success 2811 ADVANCE 2 // Past exception point - now advance rPC 2812 GET_INST_OPCODE ip // extract opcode from rINST 2813 GOTO_OPCODE ip // jump to next instruction 2814 2815 2816/* ------------------------------ */ 2817 .balign 128 2818.L_op_sput_char: /* 0x6c */ 2819/* File: arm64/op_sput_char.S */ 2820/* File: arm64/op_sput.S */ 2821 /* 2822 * General SPUT handler wrapper. 2823 * 2824 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2825 */ 2826 /* op vAA, field//BBBB */ 2827 EXPORT_PC 2828 FETCH w0, 1 // r0<- field ref BBBB 2829 lsr w3, wINST, #8 // r3<- AA 2830 GET_VREG w1, w3 // r1<= fp[AA] 2831 ldr x2, [xFP, #OFF_FP_METHOD] 2832 mov x3, xSELF 2833 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2834 bl artSet16StaticFromCode 2835 cbnz w0, MterpException // 0 on success 2836 ADVANCE 2 // Past exception point - now advance rPC 2837 GET_INST_OPCODE ip // extract opcode from rINST 2838 GOTO_OPCODE ip // jump to next instruction 2839 2840 2841/* ------------------------------ */ 2842 .balign 128 2843.L_op_sput_short: /* 0x6d */ 2844/* File: arm64/op_sput_short.S */ 2845/* File: arm64/op_sput.S */ 2846 /* 2847 * General SPUT handler wrapper. 2848 * 2849 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2850 */ 2851 /* op vAA, field//BBBB */ 2852 EXPORT_PC 2853 FETCH w0, 1 // r0<- field ref BBBB 2854 lsr w3, wINST, #8 // r3<- AA 2855 GET_VREG w1, w3 // r1<= fp[AA] 2856 ldr x2, [xFP, #OFF_FP_METHOD] 2857 mov x3, xSELF 2858 PREFETCH_INST 2 // Get next inst, but don't advance rPC 2859 bl artSet16StaticFromCode 2860 cbnz w0, MterpException // 0 on success 2861 ADVANCE 2 // Past exception point - now advance rPC 2862 GET_INST_OPCODE ip // extract opcode from rINST 2863 GOTO_OPCODE ip // jump to next instruction 2864 2865 2866/* ------------------------------ */ 2867 .balign 128 2868.L_op_invoke_virtual: /* 0x6e */ 2869/* File: arm64/op_invoke_virtual.S */ 2870/* File: arm64/invoke.S */ 2871 /* 2872 * Generic invoke handler wrapper. 2873 */ 2874 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2875 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2876 .extern MterpInvokeVirtual 2877 EXPORT_PC 2878 mov x0, xSELF 2879 add x1, xFP, #OFF_FP_SHADOWFRAME 2880 mov x2, xPC 2881 mov x3, xINST 2882 bl MterpInvokeVirtual 2883 cbz w0, MterpException 2884 FETCH_ADVANCE_INST 3 2885 bl MterpShouldSwitchInterpreters 2886 cbnz w0, MterpFallback 2887 GET_INST_OPCODE ip 2888 GOTO_OPCODE ip 2889 2890 2891 /* 2892 * Handle a virtual method call. 2893 * 2894 * for: invoke-virtual, invoke-virtual/range 2895 */ 2896 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2897 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2898 2899/* ------------------------------ */ 2900 .balign 128 2901.L_op_invoke_super: /* 0x6f */ 2902/* File: arm64/op_invoke_super.S */ 2903/* File: arm64/invoke.S */ 2904 /* 2905 * Generic invoke handler wrapper. 2906 */ 2907 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2908 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2909 .extern MterpInvokeSuper 2910 EXPORT_PC 2911 mov x0, xSELF 2912 add x1, xFP, #OFF_FP_SHADOWFRAME 2913 mov x2, xPC 2914 mov x3, xINST 2915 bl MterpInvokeSuper 2916 cbz w0, MterpException 2917 FETCH_ADVANCE_INST 3 2918 bl MterpShouldSwitchInterpreters 2919 cbnz w0, MterpFallback 2920 GET_INST_OPCODE ip 2921 GOTO_OPCODE ip 2922 2923 2924 /* 2925 * Handle a "super" method call. 2926 * 2927 * for: invoke-super, invoke-super/range 2928 */ 2929 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2930 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2931 2932/* ------------------------------ */ 2933 .balign 128 2934.L_op_invoke_direct: /* 0x70 */ 2935/* File: arm64/op_invoke_direct.S */ 2936/* File: arm64/invoke.S */ 2937 /* 2938 * Generic invoke handler wrapper. 2939 */ 2940 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2941 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2942 .extern MterpInvokeDirect 2943 EXPORT_PC 2944 mov x0, xSELF 2945 add x1, xFP, #OFF_FP_SHADOWFRAME 2946 mov x2, xPC 2947 mov x3, xINST 2948 bl MterpInvokeDirect 2949 cbz w0, MterpException 2950 FETCH_ADVANCE_INST 3 2951 bl MterpShouldSwitchInterpreters 2952 cbnz w0, MterpFallback 2953 GET_INST_OPCODE ip 2954 GOTO_OPCODE ip 2955 2956 2957 2958/* ------------------------------ */ 2959 .balign 128 2960.L_op_invoke_static: /* 0x71 */ 2961/* File: arm64/op_invoke_static.S */ 2962/* File: arm64/invoke.S */ 2963 /* 2964 * Generic invoke handler wrapper. 2965 */ 2966 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2967 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2968 .extern MterpInvokeStatic 2969 EXPORT_PC 2970 mov x0, xSELF 2971 add x1, xFP, #OFF_FP_SHADOWFRAME 2972 mov x2, xPC 2973 mov x3, xINST 2974 bl MterpInvokeStatic 2975 cbz w0, MterpException 2976 FETCH_ADVANCE_INST 3 2977 bl MterpShouldSwitchInterpreters 2978 cbnz w0, MterpFallback 2979 GET_INST_OPCODE ip 2980 GOTO_OPCODE ip 2981 2982 2983 2984 2985/* ------------------------------ */ 2986 .balign 128 2987.L_op_invoke_interface: /* 0x72 */ 2988/* File: arm64/op_invoke_interface.S */ 2989/* File: arm64/invoke.S */ 2990 /* 2991 * Generic invoke handler wrapper. 2992 */ 2993 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2994 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2995 .extern MterpInvokeInterface 2996 EXPORT_PC 2997 mov x0, xSELF 2998 add x1, xFP, #OFF_FP_SHADOWFRAME 2999 mov x2, xPC 3000 mov x3, xINST 3001 bl MterpInvokeInterface 3002 cbz w0, MterpException 3003 FETCH_ADVANCE_INST 3 3004 bl MterpShouldSwitchInterpreters 3005 cbnz w0, MterpFallback 3006 GET_INST_OPCODE ip 3007 GOTO_OPCODE ip 3008 3009 3010 /* 3011 * Handle an interface method call. 3012 * 3013 * for: invoke-interface, invoke-interface/range 3014 */ 3015 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3016 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3017 3018/* ------------------------------ */ 3019 .balign 128 3020.L_op_return_void_no_barrier: /* 0x73 */ 3021/* File: arm64/op_return_void_no_barrier.S */ 3022 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] 3023 mov x0, xSELF 3024 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 3025 b.ne .Lop_return_void_no_barrier_check 3026.Lop_return_void_no_barrier_return: 3027 mov x0, #0 3028 b MterpReturn 3029.Lop_return_void_no_barrier_check: 3030 bl MterpSuspendCheck // (self) 3031 b .Lop_return_void_no_barrier_return 3032 3033/* ------------------------------ */ 3034 .balign 128 3035.L_op_invoke_virtual_range: /* 0x74 */ 3036/* File: arm64/op_invoke_virtual_range.S */ 3037/* File: arm64/invoke.S */ 3038 /* 3039 * Generic invoke handler wrapper. 3040 */ 3041 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3042 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3043 .extern MterpInvokeVirtualRange 3044 EXPORT_PC 3045 mov x0, xSELF 3046 add x1, xFP, #OFF_FP_SHADOWFRAME 3047 mov x2, xPC 3048 mov x3, xINST 3049 bl MterpInvokeVirtualRange 3050 cbz w0, MterpException 3051 FETCH_ADVANCE_INST 3 3052 bl MterpShouldSwitchInterpreters 3053 cbnz w0, MterpFallback 3054 GET_INST_OPCODE ip 3055 GOTO_OPCODE ip 3056 3057 3058 3059/* ------------------------------ */ 3060 .balign 128 3061.L_op_invoke_super_range: /* 0x75 */ 3062/* File: arm64/op_invoke_super_range.S */ 3063/* File: arm64/invoke.S */ 3064 /* 3065 * Generic invoke handler wrapper. 3066 */ 3067 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3068 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3069 .extern MterpInvokeSuperRange 3070 EXPORT_PC 3071 mov x0, xSELF 3072 add x1, xFP, #OFF_FP_SHADOWFRAME 3073 mov x2, xPC 3074 mov x3, xINST 3075 bl MterpInvokeSuperRange 3076 cbz w0, MterpException 3077 FETCH_ADVANCE_INST 3 3078 bl MterpShouldSwitchInterpreters 3079 cbnz w0, MterpFallback 3080 GET_INST_OPCODE ip 3081 GOTO_OPCODE ip 3082 3083 3084 3085/* ------------------------------ */ 3086 .balign 128 3087.L_op_invoke_direct_range: /* 0x76 */ 3088/* File: arm64/op_invoke_direct_range.S */ 3089/* File: arm64/invoke.S */ 3090 /* 3091 * Generic invoke handler wrapper. 3092 */ 3093 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3094 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3095 .extern MterpInvokeDirectRange 3096 EXPORT_PC 3097 mov x0, xSELF 3098 add x1, xFP, #OFF_FP_SHADOWFRAME 3099 mov x2, xPC 3100 mov x3, xINST 3101 bl MterpInvokeDirectRange 3102 cbz w0, MterpException 3103 FETCH_ADVANCE_INST 3 3104 bl MterpShouldSwitchInterpreters 3105 cbnz w0, MterpFallback 3106 GET_INST_OPCODE ip 3107 GOTO_OPCODE ip 3108 3109 3110 3111/* ------------------------------ */ 3112 .balign 128 3113.L_op_invoke_static_range: /* 0x77 */ 3114/* File: arm64/op_invoke_static_range.S */ 3115/* File: arm64/invoke.S */ 3116 /* 3117 * Generic invoke handler wrapper. 3118 */ 3119 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3120 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3121 .extern MterpInvokeStaticRange 3122 EXPORT_PC 3123 mov x0, xSELF 3124 add x1, xFP, #OFF_FP_SHADOWFRAME 3125 mov x2, xPC 3126 mov x3, xINST 3127 bl MterpInvokeStaticRange 3128 cbz w0, MterpException 3129 FETCH_ADVANCE_INST 3 3130 bl MterpShouldSwitchInterpreters 3131 cbnz w0, MterpFallback 3132 GET_INST_OPCODE ip 3133 GOTO_OPCODE ip 3134 3135 3136 3137/* ------------------------------ */ 3138 .balign 128 3139.L_op_invoke_interface_range: /* 0x78 */ 3140/* File: arm64/op_invoke_interface_range.S */ 3141/* File: arm64/invoke.S */ 3142 /* 3143 * Generic invoke handler wrapper. 3144 */ 3145 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3146 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3147 .extern MterpInvokeInterfaceRange 3148 EXPORT_PC 3149 mov x0, xSELF 3150 add x1, xFP, #OFF_FP_SHADOWFRAME 3151 mov x2, xPC 3152 mov x3, xINST 3153 bl MterpInvokeInterfaceRange 3154 cbz w0, MterpException 3155 FETCH_ADVANCE_INST 3 3156 bl MterpShouldSwitchInterpreters 3157 cbnz w0, MterpFallback 3158 GET_INST_OPCODE ip 3159 GOTO_OPCODE ip 3160 3161 3162 3163/* ------------------------------ */ 3164 .balign 128 3165.L_op_unused_79: /* 0x79 */ 3166/* File: arm64/op_unused_79.S */ 3167/* File: arm64/unused.S */ 3168/* 3169 * Bail to reference interpreter to throw. 3170 */ 3171 b MterpFallback 3172 3173 3174/* ------------------------------ */ 3175 .balign 128 3176.L_op_unused_7a: /* 0x7a */ 3177/* File: arm64/op_unused_7a.S */ 3178/* File: arm64/unused.S */ 3179/* 3180 * Bail to reference interpreter to throw. 3181 */ 3182 b MterpFallback 3183 3184 3185/* ------------------------------ */ 3186 .balign 128 3187.L_op_neg_int: /* 0x7b */ 3188/* File: arm64/op_neg_int.S */ 3189/* File: arm64/unop.S */ 3190 /* 3191 * Generic 32-bit unary operation. Provide an "instr" line that 3192 * specifies an instruction that performs "result = op w0". 3193 * This could be an ARM instruction or a function call. 3194 * 3195 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3196 * int-to-byte, int-to-char, int-to-short 3197 */ 3198 /* unop vA, vB */ 3199 lsr w3, wINST, #12 // w3<- B 3200 GET_VREG w0, w3 // w0<- vB 3201 ubfx w9, wINST, #8, #4 // w9<- A 3202 // optional op; may set condition codes 3203 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3204 sub w0, wzr, w0 // w0<- op, w0-w3 changed 3205 GET_INST_OPCODE ip // extract opcode from rINST 3206 SET_VREG w0, w9 // vAA<- w0 3207 GOTO_OPCODE ip // jump to next instruction 3208 /* 8-9 instructions */ 3209 3210 3211/* ------------------------------ */ 3212 .balign 128 3213.L_op_not_int: /* 0x7c */ 3214/* File: arm64/op_not_int.S */ 3215/* File: arm64/unop.S */ 3216 /* 3217 * Generic 32-bit unary operation. Provide an "instr" line that 3218 * specifies an instruction that performs "result = op w0". 3219 * This could be an ARM instruction or a function call. 3220 * 3221 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3222 * int-to-byte, int-to-char, int-to-short 3223 */ 3224 /* unop vA, vB */ 3225 lsr w3, wINST, #12 // w3<- B 3226 GET_VREG w0, w3 // w0<- vB 3227 ubfx w9, wINST, #8, #4 // w9<- A 3228 // optional op; may set condition codes 3229 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3230 mvn w0, w0 // w0<- op, w0-w3 changed 3231 GET_INST_OPCODE ip // extract opcode from rINST 3232 SET_VREG w0, w9 // vAA<- w0 3233 GOTO_OPCODE ip // jump to next instruction 3234 /* 8-9 instructions */ 3235 3236 3237/* ------------------------------ */ 3238 .balign 128 3239.L_op_neg_long: /* 0x7d */ 3240/* File: arm64/op_neg_long.S */ 3241/* File: arm64/unopWide.S */ 3242 /* 3243 * Generic 64-bit unary operation. Provide an "instr" line that 3244 * specifies an instruction that performs "result = op x0". 3245 * 3246 * For: neg-long, not-long 3247 */ 3248 /* unop vA, vB */ 3249 lsr w3, wINST, #12 // w3<- B 3250 ubfx w4, wINST, #8, #4 // w4<- A 3251 GET_VREG_WIDE x0, w3 3252 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3253 3254 sub x0, xzr, x0 3255 GET_INST_OPCODE ip // extract opcode from wINST 3256 SET_VREG_WIDE x0, w4 3257 GOTO_OPCODE ip // jump to next instruction 3258 /* 10-11 instructions */ 3259 3260 3261/* ------------------------------ */ 3262 .balign 128 3263.L_op_not_long: /* 0x7e */ 3264/* File: arm64/op_not_long.S */ 3265/* File: arm64/unopWide.S */ 3266 /* 3267 * Generic 64-bit unary operation. Provide an "instr" line that 3268 * specifies an instruction that performs "result = op x0". 3269 * 3270 * For: neg-long, not-long 3271 */ 3272 /* unop vA, vB */ 3273 lsr w3, wINST, #12 // w3<- B 3274 ubfx w4, wINST, #8, #4 // w4<- A 3275 GET_VREG_WIDE x0, w3 3276 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3277 3278 mvn x0, x0 3279 GET_INST_OPCODE ip // extract opcode from wINST 3280 SET_VREG_WIDE x0, w4 3281 GOTO_OPCODE ip // jump to next instruction 3282 /* 10-11 instructions */ 3283 3284 3285/* ------------------------------ */ 3286 .balign 128 3287.L_op_neg_float: /* 0x7f */ 3288/* File: arm64/op_neg_float.S */ 3289/* File: arm64/unop.S */ 3290 /* 3291 * Generic 32-bit unary operation. Provide an "instr" line that 3292 * specifies an instruction that performs "result = op w0". 3293 * This could be an ARM instruction or a function call. 3294 * 3295 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3296 * int-to-byte, int-to-char, int-to-short 3297 */ 3298 /* unop vA, vB */ 3299 lsr w3, wINST, #12 // w3<- B 3300 GET_VREG w0, w3 // w0<- vB 3301 ubfx w9, wINST, #8, #4 // w9<- A 3302 mov w4, #0x80000000 // optional op; may set condition codes 3303 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3304 add w0, w0, w4 // w0<- op, w0-w3 changed 3305 GET_INST_OPCODE ip // extract opcode from rINST 3306 SET_VREG w0, w9 // vAA<- w0 3307 GOTO_OPCODE ip // jump to next instruction 3308 /* 8-9 instructions */ 3309 3310 3311/* ------------------------------ */ 3312 .balign 128 3313.L_op_neg_double: /* 0x80 */ 3314/* File: arm64/op_neg_double.S */ 3315/* File: arm64/unopWide.S */ 3316 /* 3317 * Generic 64-bit unary operation. Provide an "instr" line that 3318 * specifies an instruction that performs "result = op x0". 3319 * 3320 * For: neg-long, not-long 3321 */ 3322 /* unop vA, vB */ 3323 lsr w3, wINST, #12 // w3<- B 3324 ubfx w4, wINST, #8, #4 // w4<- A 3325 GET_VREG_WIDE x0, w3 3326 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3327 mov x1, #0x8000000000000000 3328 add x0, x0, x1 3329 GET_INST_OPCODE ip // extract opcode from wINST 3330 SET_VREG_WIDE x0, w4 3331 GOTO_OPCODE ip // jump to next instruction 3332 /* 10-11 instructions */ 3333 3334 3335/* ------------------------------ */ 3336 .balign 128 3337.L_op_int_to_long: /* 0x81 */ 3338/* File: arm64/op_int_to_long.S */ 3339/* File: arm64/funopWider.S */ 3340 /* 3341 * Generic 32bit-to-64bit floating point unary operation. Provide an 3342 * "instr" line that specifies an instruction that performs "x0 = op w0". 3343 * 3344 * For: int-to-double, float-to-double, float-to-long 3345 */ 3346 /* unop vA, vB */ 3347 lsr w3, wINST, #12 // w3<- B 3348 lsr w4, wINST, #8 // w4<- A+ 3349 GET_VREG w0, w3 3350 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3351 and w4, w4, #15 // w4<- A 3352 sbfm x0, x0, 0, 31 // d0<- op 3353 GET_INST_OPCODE ip // extract opcode from wINST 3354 SET_VREG_WIDE x0, w4 // vA<- d0 3355 GOTO_OPCODE ip // jump to next instruction 3356 3357 3358/* ------------------------------ */ 3359 .balign 128 3360.L_op_int_to_float: /* 0x82 */ 3361/* File: arm64/op_int_to_float.S */ 3362/* File: arm64/funopNarrow.S */ 3363 /* 3364 * Generic 32bit-to-32bit floating point unary operation. Provide an 3365 * "instr" line that specifies an instruction that performs "s0 = op w0". 3366 * 3367 * For: int-to-float, float-to-int 3368 * TODO: refactor all of the conversions - parameterize width and use same template. 3369 */ 3370 /* unop vA, vB */ 3371 lsr w3, wINST, #12 // w3<- B 3372 lsr w4, wINST, #8 // w4<- A+ 3373 GET_VREG w0, w3 3374 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3375 and w4, w4, #15 // w4<- A 3376 scvtf s0, w0 // d0<- op 3377 GET_INST_OPCODE ip // extract opcode from wINST 3378 SET_VREG s0, w4 // vA<- d0 3379 GOTO_OPCODE ip // jump to next instruction 3380 3381 3382/* ------------------------------ */ 3383 .balign 128 3384.L_op_int_to_double: /* 0x83 */ 3385/* File: arm64/op_int_to_double.S */ 3386/* File: arm64/funopWider.S */ 3387 /* 3388 * Generic 32bit-to-64bit floating point unary operation. Provide an 3389 * "instr" line that specifies an instruction that performs "d0 = op w0". 3390 * 3391 * For: int-to-double, float-to-double, float-to-long 3392 */ 3393 /* unop vA, vB */ 3394 lsr w3, wINST, #12 // w3<- B 3395 lsr w4, wINST, #8 // w4<- A+ 3396 GET_VREG w0, w3 3397 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3398 and w4, w4, #15 // w4<- A 3399 scvtf d0, w0 // d0<- op 3400 GET_INST_OPCODE ip // extract opcode from wINST 3401 SET_VREG_WIDE d0, w4 // vA<- d0 3402 GOTO_OPCODE ip // jump to next instruction 3403 3404 3405/* ------------------------------ */ 3406 .balign 128 3407.L_op_long_to_int: /* 0x84 */ 3408/* File: arm64/op_long_to_int.S */ 3409/* File: arm64/funopNarrower.S */ 3410 /* 3411 * Generic 64bit-to-32bit floating point unary operation. Provide an 3412 * "instr" line that specifies an instruction that performs "w0 = op x0". 3413 * 3414 * For: int-to-double, float-to-double, float-to-long 3415 */ 3416 /* unop vA, vB */ 3417 lsr w3, wINST, #12 // w3<- B 3418 lsr w4, wINST, #8 // w4<- A+ 3419 GET_VREG_WIDE x0, w3 3420 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3421 and w4, w4, #15 // w4<- A 3422 // d0<- op 3423 GET_INST_OPCODE ip // extract opcode from wINST 3424 SET_VREG w0, w4 // vA<- d0 3425 GOTO_OPCODE ip // jump to next instruction 3426 3427 3428/* ------------------------------ */ 3429 .balign 128 3430.L_op_long_to_float: /* 0x85 */ 3431/* File: arm64/op_long_to_float.S */ 3432/* File: arm64/funopNarrower.S */ 3433 /* 3434 * Generic 64bit-to-32bit floating point unary operation. Provide an 3435 * "instr" line that specifies an instruction that performs "s0 = op x0". 3436 * 3437 * For: int-to-double, float-to-double, float-to-long 3438 */ 3439 /* unop vA, vB */ 3440 lsr w3, wINST, #12 // w3<- B 3441 lsr w4, wINST, #8 // w4<- A+ 3442 GET_VREG_WIDE x0, w3 3443 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3444 and w4, w4, #15 // w4<- A 3445 scvtf s0, x0 // d0<- op 3446 GET_INST_OPCODE ip // extract opcode from wINST 3447 SET_VREG s0, w4 // vA<- d0 3448 GOTO_OPCODE ip // jump to next instruction 3449 3450 3451/* ------------------------------ */ 3452 .balign 128 3453.L_op_long_to_double: /* 0x86 */ 3454/* File: arm64/op_long_to_double.S */ 3455/* File: arm64/funopWide.S */ 3456 /* 3457 * Generic 64bit-to-64bit floating point unary operation. Provide an 3458 * "instr" line that specifies an instruction that performs "d0 = op x0". 3459 * 3460 * For: long-to-double, double-to-long 3461 */ 3462 /* unop vA, vB */ 3463 lsr w3, wINST, #12 // w3<- B 3464 lsr w4, wINST, #8 // w4<- A+ 3465 GET_VREG_WIDE x0, w3 3466 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3467 and w4, w4, #15 // w4<- A 3468 scvtf d0, x0 // d0<- op 3469 GET_INST_OPCODE ip // extract opcode from wINST 3470 SET_VREG_WIDE d0, w4 // vA<- d0 3471 GOTO_OPCODE ip // jump to next instruction 3472 3473 3474/* ------------------------------ */ 3475 .balign 128 3476.L_op_float_to_int: /* 0x87 */ 3477/* File: arm64/op_float_to_int.S */ 3478/* File: arm64/funopNarrow.S */ 3479 /* 3480 * Generic 32bit-to-32bit floating point unary operation. Provide an 3481 * "instr" line that specifies an instruction that performs "w0 = op s0". 3482 * 3483 * For: int-to-float, float-to-int 3484 * TODO: refactor all of the conversions - parameterize width and use same template. 3485 */ 3486 /* unop vA, vB */ 3487 lsr w3, wINST, #12 // w3<- B 3488 lsr w4, wINST, #8 // w4<- A+ 3489 GET_VREG s0, w3 3490 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3491 and w4, w4, #15 // w4<- A 3492 fcvtzs w0, s0 // d0<- op 3493 GET_INST_OPCODE ip // extract opcode from wINST 3494 SET_VREG w0, w4 // vA<- d0 3495 GOTO_OPCODE ip // jump to next instruction 3496 3497 3498/* ------------------------------ */ 3499 .balign 128 3500.L_op_float_to_long: /* 0x88 */ 3501/* File: arm64/op_float_to_long.S */ 3502/* File: arm64/funopWider.S */ 3503 /* 3504 * Generic 32bit-to-64bit floating point unary operation. Provide an 3505 * "instr" line that specifies an instruction that performs "x0 = op s0". 3506 * 3507 * For: int-to-double, float-to-double, float-to-long 3508 */ 3509 /* unop vA, vB */ 3510 lsr w3, wINST, #12 // w3<- B 3511 lsr w4, wINST, #8 // w4<- A+ 3512 GET_VREG s0, w3 3513 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3514 and w4, w4, #15 // w4<- A 3515 fcvtzs x0, s0 // d0<- op 3516 GET_INST_OPCODE ip // extract opcode from wINST 3517 SET_VREG_WIDE x0, w4 // vA<- d0 3518 GOTO_OPCODE ip // jump to next instruction 3519 3520 3521/* ------------------------------ */ 3522 .balign 128 3523.L_op_float_to_double: /* 0x89 */ 3524/* File: arm64/op_float_to_double.S */ 3525/* File: arm64/funopWider.S */ 3526 /* 3527 * Generic 32bit-to-64bit floating point unary operation. Provide an 3528 * "instr" line that specifies an instruction that performs "d0 = op s0". 3529 * 3530 * For: int-to-double, float-to-double, float-to-long 3531 */ 3532 /* unop vA, vB */ 3533 lsr w3, wINST, #12 // w3<- B 3534 lsr w4, wINST, #8 // w4<- A+ 3535 GET_VREG s0, w3 3536 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3537 and w4, w4, #15 // w4<- A 3538 fcvt d0, s0 // d0<- op 3539 GET_INST_OPCODE ip // extract opcode from wINST 3540 SET_VREG_WIDE d0, w4 // vA<- d0 3541 GOTO_OPCODE ip // jump to next instruction 3542 3543 3544/* ------------------------------ */ 3545 .balign 128 3546.L_op_double_to_int: /* 0x8a */ 3547/* File: arm64/op_double_to_int.S */ 3548/* File: arm64/funopNarrower.S */ 3549 /* 3550 * Generic 64bit-to-32bit floating point unary operation. Provide an 3551 * "instr" line that specifies an instruction that performs "w0 = op d0". 3552 * 3553 * For: int-to-double, float-to-double, float-to-long 3554 */ 3555 /* unop vA, vB */ 3556 lsr w3, wINST, #12 // w3<- B 3557 lsr w4, wINST, #8 // w4<- A+ 3558 GET_VREG_WIDE d0, w3 3559 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3560 and w4, w4, #15 // w4<- A 3561 fcvtzs w0, d0 // d0<- op 3562 GET_INST_OPCODE ip // extract opcode from wINST 3563 SET_VREG w0, w4 // vA<- d0 3564 GOTO_OPCODE ip // jump to next instruction 3565 3566 3567/* ------------------------------ */ 3568 .balign 128 3569.L_op_double_to_long: /* 0x8b */ 3570/* File: arm64/op_double_to_long.S */ 3571/* File: arm64/funopWide.S */ 3572 /* 3573 * Generic 64bit-to-64bit floating point unary operation. Provide an 3574 * "instr" line that specifies an instruction that performs "x0 = op d0". 3575 * 3576 * For: long-to-double, double-to-long 3577 */ 3578 /* unop vA, vB */ 3579 lsr w3, wINST, #12 // w3<- B 3580 lsr w4, wINST, #8 // w4<- A+ 3581 GET_VREG_WIDE d0, w3 3582 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3583 and w4, w4, #15 // w4<- A 3584 fcvtzs x0, d0 // d0<- op 3585 GET_INST_OPCODE ip // extract opcode from wINST 3586 SET_VREG_WIDE x0, w4 // vA<- d0 3587 GOTO_OPCODE ip // jump to next instruction 3588 3589 3590/* ------------------------------ */ 3591 .balign 128 3592.L_op_double_to_float: /* 0x8c */ 3593/* File: arm64/op_double_to_float.S */ 3594/* File: arm64/funopNarrower.S */ 3595 /* 3596 * Generic 64bit-to-32bit floating point unary operation. Provide an 3597 * "instr" line that specifies an instruction that performs "s0 = op d0". 3598 * 3599 * For: int-to-double, float-to-double, float-to-long 3600 */ 3601 /* unop vA, vB */ 3602 lsr w3, wINST, #12 // w3<- B 3603 lsr w4, wINST, #8 // w4<- A+ 3604 GET_VREG_WIDE d0, w3 3605 FETCH_ADVANCE_INST 1 // advance rPC, load wINST 3606 and w4, w4, #15 // w4<- A 3607 fcvt s0, d0 // d0<- op 3608 GET_INST_OPCODE ip // extract opcode from wINST 3609 SET_VREG s0, w4 // vA<- d0 3610 GOTO_OPCODE ip // jump to next instruction 3611 3612 3613/* ------------------------------ */ 3614 .balign 128 3615.L_op_int_to_byte: /* 0x8d */ 3616/* File: arm64/op_int_to_byte.S */ 3617/* File: arm64/unop.S */ 3618 /* 3619 * Generic 32-bit unary operation. Provide an "instr" line that 3620 * specifies an instruction that performs "result = op w0". 3621 * This could be an ARM instruction or a function call. 3622 * 3623 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3624 * int-to-byte, int-to-char, int-to-short 3625 */ 3626 /* unop vA, vB */ 3627 lsr w3, wINST, #12 // w3<- B 3628 GET_VREG w0, w3 // w0<- vB 3629 ubfx w9, wINST, #8, #4 // w9<- A 3630 // optional op; may set condition codes 3631 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3632 sxtb w0, w0 // w0<- op, w0-w3 changed 3633 GET_INST_OPCODE ip // extract opcode from rINST 3634 SET_VREG w0, w9 // vAA<- w0 3635 GOTO_OPCODE ip // jump to next instruction 3636 /* 8-9 instructions */ 3637 3638 3639/* ------------------------------ */ 3640 .balign 128 3641.L_op_int_to_char: /* 0x8e */ 3642/* File: arm64/op_int_to_char.S */ 3643/* File: arm64/unop.S */ 3644 /* 3645 * Generic 32-bit unary operation. Provide an "instr" line that 3646 * specifies an instruction that performs "result = op w0". 3647 * This could be an ARM instruction or a function call. 3648 * 3649 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3650 * int-to-byte, int-to-char, int-to-short 3651 */ 3652 /* unop vA, vB */ 3653 lsr w3, wINST, #12 // w3<- B 3654 GET_VREG w0, w3 // w0<- vB 3655 ubfx w9, wINST, #8, #4 // w9<- A 3656 // optional op; may set condition codes 3657 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3658 uxth w0, w0 // w0<- op, w0-w3 changed 3659 GET_INST_OPCODE ip // extract opcode from rINST 3660 SET_VREG w0, w9 // vAA<- w0 3661 GOTO_OPCODE ip // jump to next instruction 3662 /* 8-9 instructions */ 3663 3664 3665/* ------------------------------ */ 3666 .balign 128 3667.L_op_int_to_short: /* 0x8f */ 3668/* File: arm64/op_int_to_short.S */ 3669/* File: arm64/unop.S */ 3670 /* 3671 * Generic 32-bit unary operation. Provide an "instr" line that 3672 * specifies an instruction that performs "result = op w0". 3673 * This could be an ARM instruction or a function call. 3674 * 3675 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3676 * int-to-byte, int-to-char, int-to-short 3677 */ 3678 /* unop vA, vB */ 3679 lsr w3, wINST, #12 // w3<- B 3680 GET_VREG w0, w3 // w0<- vB 3681 ubfx w9, wINST, #8, #4 // w9<- A 3682 // optional op; may set condition codes 3683 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 3684 sxth w0, w0 // w0<- op, w0-w3 changed 3685 GET_INST_OPCODE ip // extract opcode from rINST 3686 SET_VREG w0, w9 // vAA<- w0 3687 GOTO_OPCODE ip // jump to next instruction 3688 /* 8-9 instructions */ 3689 3690 3691/* ------------------------------ */ 3692 .balign 128 3693.L_op_add_int: /* 0x90 */ 3694/* File: arm64/op_add_int.S */ 3695/* File: arm64/binop.S */ 3696 /* 3697 * Generic 32-bit binary operation. Provide an "instr" line that 3698 * specifies an instruction that performs "result = w0 op w1". 3699 * This could be an ARM instruction or a function call. (If the result 3700 * comes back in a register other than w0, you can override "result".) 3701 * 3702 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3703 * vCC (w1). Useful for integer division and modulus. Note that we 3704 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3705 * handles it correctly. 3706 * 3707 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3708 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3709 * mul-float, div-float, rem-float 3710 */ 3711 /* binop vAA, vBB, vCC */ 3712 FETCH w0, 1 // w0<- CCBB 3713 lsr w9, wINST, #8 // w9<- AA 3714 lsr w3, w0, #8 // w3<- CC 3715 and w2, w0, #255 // w2<- BB 3716 GET_VREG w1, w3 // w1<- vCC 3717 GET_VREG w0, w2 // w0<- vBB 3718 .if 0 3719 cbz w1, common_errDivideByZero // is second operand zero? 3720 .endif 3721 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3722 // optional op; may set condition codes 3723 add w0, w0, w1 // w0<- op, w0-w3 changed 3724 GET_INST_OPCODE ip // extract opcode from rINST 3725 SET_VREG w0, w9 // vAA<- w0 3726 GOTO_OPCODE ip // jump to next instruction 3727 /* 11-14 instructions */ 3728 3729 3730/* ------------------------------ */ 3731 .balign 128 3732.L_op_sub_int: /* 0x91 */ 3733/* File: arm64/op_sub_int.S */ 3734/* File: arm64/binop.S */ 3735 /* 3736 * Generic 32-bit binary operation. Provide an "instr" line that 3737 * specifies an instruction that performs "result = w0 op w1". 3738 * This could be an ARM instruction or a function call. (If the result 3739 * comes back in a register other than w0, you can override "result".) 3740 * 3741 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3742 * vCC (w1). Useful for integer division and modulus. Note that we 3743 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3744 * handles it correctly. 3745 * 3746 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3747 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3748 * mul-float, div-float, rem-float 3749 */ 3750 /* binop vAA, vBB, vCC */ 3751 FETCH w0, 1 // w0<- CCBB 3752 lsr w9, wINST, #8 // w9<- AA 3753 lsr w3, w0, #8 // w3<- CC 3754 and w2, w0, #255 // w2<- BB 3755 GET_VREG w1, w3 // w1<- vCC 3756 GET_VREG w0, w2 // w0<- vBB 3757 .if 0 3758 cbz w1, common_errDivideByZero // is second operand zero? 3759 .endif 3760 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3761 // optional op; may set condition codes 3762 sub w0, w0, w1 // w0<- op, w0-w3 changed 3763 GET_INST_OPCODE ip // extract opcode from rINST 3764 SET_VREG w0, w9 // vAA<- w0 3765 GOTO_OPCODE ip // jump to next instruction 3766 /* 11-14 instructions */ 3767 3768 3769/* ------------------------------ */ 3770 .balign 128 3771.L_op_mul_int: /* 0x92 */ 3772/* File: arm64/op_mul_int.S */ 3773/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 3774/* File: arm64/binop.S */ 3775 /* 3776 * Generic 32-bit binary operation. Provide an "instr" line that 3777 * specifies an instruction that performs "result = w0 op w1". 3778 * This could be an ARM instruction or a function call. (If the result 3779 * comes back in a register other than w0, you can override "result".) 3780 * 3781 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3782 * vCC (w1). Useful for integer division and modulus. Note that we 3783 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3784 * handles it correctly. 3785 * 3786 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3787 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3788 * mul-float, div-float, rem-float 3789 */ 3790 /* binop vAA, vBB, vCC */ 3791 FETCH w0, 1 // w0<- CCBB 3792 lsr w9, wINST, #8 // w9<- AA 3793 lsr w3, w0, #8 // w3<- CC 3794 and w2, w0, #255 // w2<- BB 3795 GET_VREG w1, w3 // w1<- vCC 3796 GET_VREG w0, w2 // w0<- vBB 3797 .if 0 3798 cbz w1, common_errDivideByZero // is second operand zero? 3799 .endif 3800 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3801 // optional op; may set condition codes 3802 mul w0, w1, w0 // w0<- op, w0-w3 changed 3803 GET_INST_OPCODE ip // extract opcode from rINST 3804 SET_VREG w0, w9 // vAA<- w0 3805 GOTO_OPCODE ip // jump to next instruction 3806 /* 11-14 instructions */ 3807 3808 3809/* ------------------------------ */ 3810 .balign 128 3811.L_op_div_int: /* 0x93 */ 3812/* File: arm64/op_div_int.S */ 3813/* File: arm64/binop.S */ 3814 /* 3815 * Generic 32-bit binary operation. Provide an "instr" line that 3816 * specifies an instruction that performs "result = w0 op w1". 3817 * This could be an ARM instruction or a function call. (If the result 3818 * comes back in a register other than w0, you can override "result".) 3819 * 3820 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3821 * vCC (w1). Useful for integer division and modulus. Note that we 3822 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3823 * handles it correctly. 3824 * 3825 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3826 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3827 * mul-float, div-float, rem-float 3828 */ 3829 /* binop vAA, vBB, vCC */ 3830 FETCH w0, 1 // w0<- CCBB 3831 lsr w9, wINST, #8 // w9<- AA 3832 lsr w3, w0, #8 // w3<- CC 3833 and w2, w0, #255 // w2<- BB 3834 GET_VREG w1, w3 // w1<- vCC 3835 GET_VREG w0, w2 // w0<- vBB 3836 .if 1 3837 cbz w1, common_errDivideByZero // is second operand zero? 3838 .endif 3839 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3840 // optional op; may set condition codes 3841 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 3842 GET_INST_OPCODE ip // extract opcode from rINST 3843 SET_VREG w0, w9 // vAA<- w0 3844 GOTO_OPCODE ip // jump to next instruction 3845 /* 11-14 instructions */ 3846 3847 3848/* ------------------------------ */ 3849 .balign 128 3850.L_op_rem_int: /* 0x94 */ 3851/* File: arm64/op_rem_int.S */ 3852/* File: arm64/binop.S */ 3853 /* 3854 * Generic 32-bit binary operation. Provide an "instr" line that 3855 * specifies an instruction that performs "result = w0 op w1". 3856 * This could be an ARM instruction or a function call. (If the result 3857 * comes back in a register other than w0, you can override "result".) 3858 * 3859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3860 * vCC (w1). Useful for integer division and modulus. Note that we 3861 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3862 * handles it correctly. 3863 * 3864 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3865 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3866 * mul-float, div-float, rem-float 3867 */ 3868 /* binop vAA, vBB, vCC */ 3869 FETCH w0, 1 // w0<- CCBB 3870 lsr w9, wINST, #8 // w9<- AA 3871 lsr w3, w0, #8 // w3<- CC 3872 and w2, w0, #255 // w2<- BB 3873 GET_VREG w1, w3 // w1<- vCC 3874 GET_VREG w0, w2 // w0<- vBB 3875 .if 1 3876 cbz w1, common_errDivideByZero // is second operand zero? 3877 .endif 3878 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3879 sdiv w2, w0, w1 // optional op; may set condition codes 3880 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed 3881 GET_INST_OPCODE ip // extract opcode from rINST 3882 SET_VREG w0, w9 // vAA<- w0 3883 GOTO_OPCODE ip // jump to next instruction 3884 /* 11-14 instructions */ 3885 3886 3887/* ------------------------------ */ 3888 .balign 128 3889.L_op_and_int: /* 0x95 */ 3890/* File: arm64/op_and_int.S */ 3891/* File: arm64/binop.S */ 3892 /* 3893 * Generic 32-bit binary operation. Provide an "instr" line that 3894 * specifies an instruction that performs "result = w0 op w1". 3895 * This could be an ARM instruction or a function call. (If the result 3896 * comes back in a register other than w0, you can override "result".) 3897 * 3898 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3899 * vCC (w1). Useful for integer division and modulus. Note that we 3900 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3901 * handles it correctly. 3902 * 3903 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3904 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3905 * mul-float, div-float, rem-float 3906 */ 3907 /* binop vAA, vBB, vCC */ 3908 FETCH w0, 1 // w0<- CCBB 3909 lsr w9, wINST, #8 // w9<- AA 3910 lsr w3, w0, #8 // w3<- CC 3911 and w2, w0, #255 // w2<- BB 3912 GET_VREG w1, w3 // w1<- vCC 3913 GET_VREG w0, w2 // w0<- vBB 3914 .if 0 3915 cbz w1, common_errDivideByZero // is second operand zero? 3916 .endif 3917 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3918 // optional op; may set condition codes 3919 and w0, w0, w1 // w0<- op, w0-w3 changed 3920 GET_INST_OPCODE ip // extract opcode from rINST 3921 SET_VREG w0, w9 // vAA<- w0 3922 GOTO_OPCODE ip // jump to next instruction 3923 /* 11-14 instructions */ 3924 3925 3926/* ------------------------------ */ 3927 .balign 128 3928.L_op_or_int: /* 0x96 */ 3929/* File: arm64/op_or_int.S */ 3930/* File: arm64/binop.S */ 3931 /* 3932 * Generic 32-bit binary operation. Provide an "instr" line that 3933 * specifies an instruction that performs "result = w0 op w1". 3934 * This could be an ARM instruction or a function call. (If the result 3935 * comes back in a register other than w0, you can override "result".) 3936 * 3937 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3938 * vCC (w1). Useful for integer division and modulus. Note that we 3939 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3940 * handles it correctly. 3941 * 3942 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3943 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3944 * mul-float, div-float, rem-float 3945 */ 3946 /* binop vAA, vBB, vCC */ 3947 FETCH w0, 1 // w0<- CCBB 3948 lsr w9, wINST, #8 // w9<- AA 3949 lsr w3, w0, #8 // w3<- CC 3950 and w2, w0, #255 // w2<- BB 3951 GET_VREG w1, w3 // w1<- vCC 3952 GET_VREG w0, w2 // w0<- vBB 3953 .if 0 3954 cbz w1, common_errDivideByZero // is second operand zero? 3955 .endif 3956 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3957 // optional op; may set condition codes 3958 orr w0, w0, w1 // w0<- op, w0-w3 changed 3959 GET_INST_OPCODE ip // extract opcode from rINST 3960 SET_VREG w0, w9 // vAA<- w0 3961 GOTO_OPCODE ip // jump to next instruction 3962 /* 11-14 instructions */ 3963 3964 3965/* ------------------------------ */ 3966 .balign 128 3967.L_op_xor_int: /* 0x97 */ 3968/* File: arm64/op_xor_int.S */ 3969/* File: arm64/binop.S */ 3970 /* 3971 * Generic 32-bit binary operation. Provide an "instr" line that 3972 * specifies an instruction that performs "result = w0 op w1". 3973 * This could be an ARM instruction or a function call. (If the result 3974 * comes back in a register other than w0, you can override "result".) 3975 * 3976 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3977 * vCC (w1). Useful for integer division and modulus. Note that we 3978 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3979 * handles it correctly. 3980 * 3981 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3982 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3983 * mul-float, div-float, rem-float 3984 */ 3985 /* binop vAA, vBB, vCC */ 3986 FETCH w0, 1 // w0<- CCBB 3987 lsr w9, wINST, #8 // w9<- AA 3988 lsr w3, w0, #8 // w3<- CC 3989 and w2, w0, #255 // w2<- BB 3990 GET_VREG w1, w3 // w1<- vCC 3991 GET_VREG w0, w2 // w0<- vBB 3992 .if 0 3993 cbz w1, common_errDivideByZero // is second operand zero? 3994 .endif 3995 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 3996 // optional op; may set condition codes 3997 eor w0, w0, w1 // w0<- op, w0-w3 changed 3998 GET_INST_OPCODE ip // extract opcode from rINST 3999 SET_VREG w0, w9 // vAA<- w0 4000 GOTO_OPCODE ip // jump to next instruction 4001 /* 11-14 instructions */ 4002 4003 4004/* ------------------------------ */ 4005 .balign 128 4006.L_op_shl_int: /* 0x98 */ 4007/* File: arm64/op_shl_int.S */ 4008/* File: arm64/binop.S */ 4009 /* 4010 * Generic 32-bit binary operation. Provide an "instr" line that 4011 * specifies an instruction that performs "result = w0 op w1". 4012 * This could be an ARM instruction or a function call. (If the result 4013 * comes back in a register other than w0, you can override "result".) 4014 * 4015 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4016 * vCC (w1). Useful for integer division and modulus. Note that we 4017 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4018 * handles it correctly. 4019 * 4020 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4021 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4022 * mul-float, div-float, rem-float 4023 */ 4024 /* binop vAA, vBB, vCC */ 4025 FETCH w0, 1 // w0<- CCBB 4026 lsr w9, wINST, #8 // w9<- AA 4027 lsr w3, w0, #8 // w3<- CC 4028 and w2, w0, #255 // w2<- BB 4029 GET_VREG w1, w3 // w1<- vCC 4030 GET_VREG w0, w2 // w0<- vBB 4031 .if 0 4032 cbz w1, common_errDivideByZero // is second operand zero? 4033 .endif 4034 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4035 and w1, w1, #31 // optional op; may set condition codes 4036 lsl w0, w0, w1 // w0<- op, w0-w3 changed 4037 GET_INST_OPCODE ip // extract opcode from rINST 4038 SET_VREG w0, w9 // vAA<- w0 4039 GOTO_OPCODE ip // jump to next instruction 4040 /* 11-14 instructions */ 4041 4042 4043/* ------------------------------ */ 4044 .balign 128 4045.L_op_shr_int: /* 0x99 */ 4046/* File: arm64/op_shr_int.S */ 4047/* File: arm64/binop.S */ 4048 /* 4049 * Generic 32-bit binary operation. Provide an "instr" line that 4050 * specifies an instruction that performs "result = w0 op w1". 4051 * This could be an ARM instruction or a function call. (If the result 4052 * comes back in a register other than w0, you can override "result".) 4053 * 4054 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4055 * vCC (w1). Useful for integer division and modulus. Note that we 4056 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4057 * handles it correctly. 4058 * 4059 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4060 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4061 * mul-float, div-float, rem-float 4062 */ 4063 /* binop vAA, vBB, vCC */ 4064 FETCH w0, 1 // w0<- CCBB 4065 lsr w9, wINST, #8 // w9<- AA 4066 lsr w3, w0, #8 // w3<- CC 4067 and w2, w0, #255 // w2<- BB 4068 GET_VREG w1, w3 // w1<- vCC 4069 GET_VREG w0, w2 // w0<- vBB 4070 .if 0 4071 cbz w1, common_errDivideByZero // is second operand zero? 4072 .endif 4073 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4074 and w1, w1, #31 // optional op; may set condition codes 4075 asr w0, w0, w1 // w0<- op, w0-w3 changed 4076 GET_INST_OPCODE ip // extract opcode from rINST 4077 SET_VREG w0, w9 // vAA<- w0 4078 GOTO_OPCODE ip // jump to next instruction 4079 /* 11-14 instructions */ 4080 4081 4082/* ------------------------------ */ 4083 .balign 128 4084.L_op_ushr_int: /* 0x9a */ 4085/* File: arm64/op_ushr_int.S */ 4086/* File: arm64/binop.S */ 4087 /* 4088 * Generic 32-bit binary operation. Provide an "instr" line that 4089 * specifies an instruction that performs "result = w0 op w1". 4090 * This could be an ARM instruction or a function call. (If the result 4091 * comes back in a register other than w0, you can override "result".) 4092 * 4093 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4094 * vCC (w1). Useful for integer division and modulus. Note that we 4095 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4096 * handles it correctly. 4097 * 4098 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4099 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4100 * mul-float, div-float, rem-float 4101 */ 4102 /* binop vAA, vBB, vCC */ 4103 FETCH w0, 1 // w0<- CCBB 4104 lsr w9, wINST, #8 // w9<- AA 4105 lsr w3, w0, #8 // w3<- CC 4106 and w2, w0, #255 // w2<- BB 4107 GET_VREG w1, w3 // w1<- vCC 4108 GET_VREG w0, w2 // w0<- vBB 4109 .if 0 4110 cbz w1, common_errDivideByZero // is second operand zero? 4111 .endif 4112 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4113 and w1, w1, #31 // optional op; may set condition codes 4114 lsr w0, w0, w1 // w0<- op, w0-w3 changed 4115 GET_INST_OPCODE ip // extract opcode from rINST 4116 SET_VREG w0, w9 // vAA<- w0 4117 GOTO_OPCODE ip // jump to next instruction 4118 /* 11-14 instructions */ 4119 4120 4121/* ------------------------------ */ 4122 .balign 128 4123.L_op_add_long: /* 0x9b */ 4124/* File: arm64/op_add_long.S */ 4125/* File: arm64/binopWide.S */ 4126 /* 4127 * Generic 64-bit binary operation. Provide an "instr" line that 4128 * specifies an instruction that performs "result = x1 op x2". 4129 * This could be an ARM instruction or a function call. (If the result 4130 * comes back in a register other than x0, you can override "result".) 4131 * 4132 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4133 * vCC (w1). Useful for integer division and modulus. 4134 * 4135 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4136 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4137 */ 4138 /* binop vAA, vBB, vCC */ 4139 FETCH w0, 1 // w0<- CCBB 4140 lsr w4, wINST, #8 // w4<- AA 4141 lsr w2, w0, #8 // w2<- CC 4142 and w1, w0, #255 // w1<- BB 4143 GET_VREG_WIDE x2, w2 // w2<- vCC 4144 GET_VREG_WIDE x1, w1 // w1<- vBB 4145 .if 0 4146 cbz x2, common_errDivideByZero // is second operand zero? 4147 .endif 4148 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4149 4150 add x0, x1, x2 // x0<- op, w0-w4 changed 4151 GET_INST_OPCODE ip // extract opcode from rINST 4152 SET_VREG_WIDE x0, w4 // vAA<- x0 4153 GOTO_OPCODE ip // jump to next instruction 4154 /* 11-14 instructions */ 4155 4156 4157/* ------------------------------ */ 4158 .balign 128 4159.L_op_sub_long: /* 0x9c */ 4160/* File: arm64/op_sub_long.S */ 4161/* File: arm64/binopWide.S */ 4162 /* 4163 * Generic 64-bit binary operation. Provide an "instr" line that 4164 * specifies an instruction that performs "result = x1 op x2". 4165 * This could be an ARM instruction or a function call. (If the result 4166 * comes back in a register other than x0, you can override "result".) 4167 * 4168 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4169 * vCC (w1). Useful for integer division and modulus. 4170 * 4171 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4172 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4173 */ 4174 /* binop vAA, vBB, vCC */ 4175 FETCH w0, 1 // w0<- CCBB 4176 lsr w4, wINST, #8 // w4<- AA 4177 lsr w2, w0, #8 // w2<- CC 4178 and w1, w0, #255 // w1<- BB 4179 GET_VREG_WIDE x2, w2 // w2<- vCC 4180 GET_VREG_WIDE x1, w1 // w1<- vBB 4181 .if 0 4182 cbz x2, common_errDivideByZero // is second operand zero? 4183 .endif 4184 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4185 4186 sub x0, x1, x2 // x0<- op, w0-w4 changed 4187 GET_INST_OPCODE ip // extract opcode from rINST 4188 SET_VREG_WIDE x0, w4 // vAA<- x0 4189 GOTO_OPCODE ip // jump to next instruction 4190 /* 11-14 instructions */ 4191 4192 4193/* ------------------------------ */ 4194 .balign 128 4195.L_op_mul_long: /* 0x9d */ 4196/* File: arm64/op_mul_long.S */ 4197/* File: arm64/binopWide.S */ 4198 /* 4199 * Generic 64-bit binary operation. Provide an "instr" line that 4200 * specifies an instruction that performs "result = x1 op x2". 4201 * This could be an ARM instruction or a function call. (If the result 4202 * comes back in a register other than x0, you can override "result".) 4203 * 4204 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4205 * vCC (w1). Useful for integer division and modulus. 4206 * 4207 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4208 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4209 */ 4210 /* binop vAA, vBB, vCC */ 4211 FETCH w0, 1 // w0<- CCBB 4212 lsr w4, wINST, #8 // w4<- AA 4213 lsr w2, w0, #8 // w2<- CC 4214 and w1, w0, #255 // w1<- BB 4215 GET_VREG_WIDE x2, w2 // w2<- vCC 4216 GET_VREG_WIDE x1, w1 // w1<- vBB 4217 .if 0 4218 cbz x2, common_errDivideByZero // is second operand zero? 4219 .endif 4220 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4221 4222 mul x0, x1, x2 // x0<- op, w0-w4 changed 4223 GET_INST_OPCODE ip // extract opcode from rINST 4224 SET_VREG_WIDE x0, w4 // vAA<- x0 4225 GOTO_OPCODE ip // jump to next instruction 4226 /* 11-14 instructions */ 4227 4228 4229/* ------------------------------ */ 4230 .balign 128 4231.L_op_div_long: /* 0x9e */ 4232/* File: arm64/op_div_long.S */ 4233/* File: arm64/binopWide.S */ 4234 /* 4235 * Generic 64-bit binary operation. Provide an "instr" line that 4236 * specifies an instruction that performs "result = x1 op x2". 4237 * This could be an ARM instruction or a function call. (If the result 4238 * comes back in a register other than x0, you can override "result".) 4239 * 4240 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4241 * vCC (w1). Useful for integer division and modulus. 4242 * 4243 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4244 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4245 */ 4246 /* binop vAA, vBB, vCC */ 4247 FETCH w0, 1 // w0<- CCBB 4248 lsr w4, wINST, #8 // w4<- AA 4249 lsr w2, w0, #8 // w2<- CC 4250 and w1, w0, #255 // w1<- BB 4251 GET_VREG_WIDE x2, w2 // w2<- vCC 4252 GET_VREG_WIDE x1, w1 // w1<- vBB 4253 .if 1 4254 cbz x2, common_errDivideByZero // is second operand zero? 4255 .endif 4256 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4257 4258 sdiv x0, x1, x2 // x0<- op, w0-w4 changed 4259 GET_INST_OPCODE ip // extract opcode from rINST 4260 SET_VREG_WIDE x0, w4 // vAA<- x0 4261 GOTO_OPCODE ip // jump to next instruction 4262 /* 11-14 instructions */ 4263 4264 4265/* ------------------------------ */ 4266 .balign 128 4267.L_op_rem_long: /* 0x9f */ 4268/* File: arm64/op_rem_long.S */ 4269/* File: arm64/binopWide.S */ 4270 /* 4271 * Generic 64-bit binary operation. Provide an "instr" line that 4272 * specifies an instruction that performs "result = x1 op x2". 4273 * This could be an ARM instruction or a function call. (If the result 4274 * comes back in a register other than x0, you can override "result".) 4275 * 4276 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4277 * vCC (w1). Useful for integer division and modulus. 4278 * 4279 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4280 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4281 */ 4282 /* binop vAA, vBB, vCC */ 4283 FETCH w0, 1 // w0<- CCBB 4284 lsr w4, wINST, #8 // w4<- AA 4285 lsr w2, w0, #8 // w2<- CC 4286 and w1, w0, #255 // w1<- BB 4287 GET_VREG_WIDE x2, w2 // w2<- vCC 4288 GET_VREG_WIDE x1, w1 // w1<- vBB 4289 .if 1 4290 cbz x2, common_errDivideByZero // is second operand zero? 4291 .endif 4292 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4293 sdiv x3, x1, x2 4294 msub x0, x3, x2, x1 // x0<- op, w0-w4 changed 4295 GET_INST_OPCODE ip // extract opcode from rINST 4296 SET_VREG_WIDE x0, w4 // vAA<- x0 4297 GOTO_OPCODE ip // jump to next instruction 4298 /* 11-14 instructions */ 4299 4300 4301/* ------------------------------ */ 4302 .balign 128 4303.L_op_and_long: /* 0xa0 */ 4304/* File: arm64/op_and_long.S */ 4305/* File: arm64/binopWide.S */ 4306 /* 4307 * Generic 64-bit binary operation. Provide an "instr" line that 4308 * specifies an instruction that performs "result = x1 op x2". 4309 * This could be an ARM instruction or a function call. (If the result 4310 * comes back in a register other than x0, you can override "result".) 4311 * 4312 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4313 * vCC (w1). Useful for integer division and modulus. 4314 * 4315 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4316 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4317 */ 4318 /* binop vAA, vBB, vCC */ 4319 FETCH w0, 1 // w0<- CCBB 4320 lsr w4, wINST, #8 // w4<- AA 4321 lsr w2, w0, #8 // w2<- CC 4322 and w1, w0, #255 // w1<- BB 4323 GET_VREG_WIDE x2, w2 // w2<- vCC 4324 GET_VREG_WIDE x1, w1 // w1<- vBB 4325 .if 0 4326 cbz x2, common_errDivideByZero // is second operand zero? 4327 .endif 4328 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4329 4330 and x0, x1, x2 // x0<- op, w0-w4 changed 4331 GET_INST_OPCODE ip // extract opcode from rINST 4332 SET_VREG_WIDE x0, w4 // vAA<- x0 4333 GOTO_OPCODE ip // jump to next instruction 4334 /* 11-14 instructions */ 4335 4336 4337/* ------------------------------ */ 4338 .balign 128 4339.L_op_or_long: /* 0xa1 */ 4340/* File: arm64/op_or_long.S */ 4341/* File: arm64/binopWide.S */ 4342 /* 4343 * Generic 64-bit binary operation. Provide an "instr" line that 4344 * specifies an instruction that performs "result = x1 op x2". 4345 * This could be an ARM instruction or a function call. (If the result 4346 * comes back in a register other than x0, you can override "result".) 4347 * 4348 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4349 * vCC (w1). Useful for integer division and modulus. 4350 * 4351 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4352 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4353 */ 4354 /* binop vAA, vBB, vCC */ 4355 FETCH w0, 1 // w0<- CCBB 4356 lsr w4, wINST, #8 // w4<- AA 4357 lsr w2, w0, #8 // w2<- CC 4358 and w1, w0, #255 // w1<- BB 4359 GET_VREG_WIDE x2, w2 // w2<- vCC 4360 GET_VREG_WIDE x1, w1 // w1<- vBB 4361 .if 0 4362 cbz x2, common_errDivideByZero // is second operand zero? 4363 .endif 4364 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4365 4366 orr x0, x1, x2 // x0<- op, w0-w4 changed 4367 GET_INST_OPCODE ip // extract opcode from rINST 4368 SET_VREG_WIDE x0, w4 // vAA<- x0 4369 GOTO_OPCODE ip // jump to next instruction 4370 /* 11-14 instructions */ 4371 4372 4373/* ------------------------------ */ 4374 .balign 128 4375.L_op_xor_long: /* 0xa2 */ 4376/* File: arm64/op_xor_long.S */ 4377/* File: arm64/binopWide.S */ 4378 /* 4379 * Generic 64-bit binary operation. Provide an "instr" line that 4380 * specifies an instruction that performs "result = x1 op x2". 4381 * This could be an ARM instruction or a function call. (If the result 4382 * comes back in a register other than x0, you can override "result".) 4383 * 4384 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4385 * vCC (w1). Useful for integer division and modulus. 4386 * 4387 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4388 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4389 */ 4390 /* binop vAA, vBB, vCC */ 4391 FETCH w0, 1 // w0<- CCBB 4392 lsr w4, wINST, #8 // w4<- AA 4393 lsr w2, w0, #8 // w2<- CC 4394 and w1, w0, #255 // w1<- BB 4395 GET_VREG_WIDE x2, w2 // w2<- vCC 4396 GET_VREG_WIDE x1, w1 // w1<- vBB 4397 .if 0 4398 cbz x2, common_errDivideByZero // is second operand zero? 4399 .endif 4400 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4401 4402 eor x0, x1, x2 // x0<- op, w0-w4 changed 4403 GET_INST_OPCODE ip // extract opcode from rINST 4404 SET_VREG_WIDE x0, w4 // vAA<- x0 4405 GOTO_OPCODE ip // jump to next instruction 4406 /* 11-14 instructions */ 4407 4408 4409/* ------------------------------ */ 4410 .balign 128 4411.L_op_shl_long: /* 0xa3 */ 4412/* File: arm64/op_shl_long.S */ 4413/* File: arm64/shiftWide.S */ 4414 /* 4415 * 64-bit shift operation. 4416 * 4417 * For: shl-long, shr-long, ushr-long 4418 */ 4419 /* binop vAA, vBB, vCC */ 4420 FETCH w0, 1 // w0<- CCBB 4421 lsr w3, wINST, #8 // w3<- AA 4422 lsr w2, w0, #8 // w2<- CC 4423 GET_VREG w2, w2 // w2<- vCC (shift count) 4424 and w1, w0, #255 // w1<- BB 4425 GET_VREG_WIDE x1, w1 // x1<- vBB 4426 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4427 and x2, x2, #63 // Mask low 6 4428 lsl x0, x1, x2 // Do the shift. 4429 GET_INST_OPCODE ip // extract opcode from rINST 4430 SET_VREG_WIDE x0, w3 // vAA<- x0 4431 GOTO_OPCODE ip // jump to next instruction 4432 /* 11-14 instructions */ 4433 4434 4435/* ------------------------------ */ 4436 .balign 128 4437.L_op_shr_long: /* 0xa4 */ 4438/* File: arm64/op_shr_long.S */ 4439/* File: arm64/shiftWide.S */ 4440 /* 4441 * 64-bit shift operation. 4442 * 4443 * For: shl-long, shr-long, ushr-long 4444 */ 4445 /* binop vAA, vBB, vCC */ 4446 FETCH w0, 1 // w0<- CCBB 4447 lsr w3, wINST, #8 // w3<- AA 4448 lsr w2, w0, #8 // w2<- CC 4449 GET_VREG w2, w2 // w2<- vCC (shift count) 4450 and w1, w0, #255 // w1<- BB 4451 GET_VREG_WIDE x1, w1 // x1<- vBB 4452 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4453 and x2, x2, #63 // Mask low 6 4454 asr x0, x1, x2 // Do the shift. 4455 GET_INST_OPCODE ip // extract opcode from rINST 4456 SET_VREG_WIDE x0, w3 // vAA<- x0 4457 GOTO_OPCODE ip // jump to next instruction 4458 /* 11-14 instructions */ 4459 4460 4461/* ------------------------------ */ 4462 .balign 128 4463.L_op_ushr_long: /* 0xa5 */ 4464/* File: arm64/op_ushr_long.S */ 4465/* File: arm64/shiftWide.S */ 4466 /* 4467 * 64-bit shift operation. 4468 * 4469 * For: shl-long, shr-long, ushr-long 4470 */ 4471 /* binop vAA, vBB, vCC */ 4472 FETCH w0, 1 // w0<- CCBB 4473 lsr w3, wINST, #8 // w3<- AA 4474 lsr w2, w0, #8 // w2<- CC 4475 GET_VREG w2, w2 // w2<- vCC (shift count) 4476 and w1, w0, #255 // w1<- BB 4477 GET_VREG_WIDE x1, w1 // x1<- vBB 4478 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4479 and x2, x2, #63 // Mask low 6 4480 lsr x0, x1, x2 // Do the shift. 4481 GET_INST_OPCODE ip // extract opcode from rINST 4482 SET_VREG_WIDE x0, w3 // vAA<- x0 4483 GOTO_OPCODE ip // jump to next instruction 4484 /* 11-14 instructions */ 4485 4486 4487/* ------------------------------ */ 4488 .balign 128 4489.L_op_add_float: /* 0xa6 */ 4490/* File: arm64/op_add_float.S */ 4491/* File: arm64/fbinop.S */ 4492 /*: 4493 * Generic 32-bit floating-point operation. 4494 * 4495 * For: add-float, sub-float, mul-float, div-float 4496 * form: <op> s0, s0, s1 4497 */ 4498 /* floatop vAA, vBB, vCC */ 4499 FETCH w0, 1 // r0<- CCBB 4500 lsr w1, w0, #8 // r2<- CC 4501 and w0, w0, #255 // r1<- BB 4502 GET_VREG s1, w1 4503 GET_VREG s0, w0 4504 fadd s0, s0, s1 // s0<- op 4505 lsr w1, wINST, #8 // r1<- AA 4506 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4507 GET_INST_OPCODE ip // extract opcode from rINST 4508 SET_VREG s0, w1 4509 GOTO_OPCODE ip // jump to next instruction 4510 4511 4512/* ------------------------------ */ 4513 .balign 128 4514.L_op_sub_float: /* 0xa7 */ 4515/* File: arm64/op_sub_float.S */ 4516/* File: arm64/fbinop.S */ 4517 /*: 4518 * Generic 32-bit floating-point operation. 4519 * 4520 * For: add-float, sub-float, mul-float, div-float 4521 * form: <op> s0, s0, s1 4522 */ 4523 /* floatop vAA, vBB, vCC */ 4524 FETCH w0, 1 // r0<- CCBB 4525 lsr w1, w0, #8 // r2<- CC 4526 and w0, w0, #255 // r1<- BB 4527 GET_VREG s1, w1 4528 GET_VREG s0, w0 4529 fsub s0, s0, s1 // s0<- op 4530 lsr w1, wINST, #8 // r1<- AA 4531 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4532 GET_INST_OPCODE ip // extract opcode from rINST 4533 SET_VREG s0, w1 4534 GOTO_OPCODE ip // jump to next instruction 4535 4536 4537/* ------------------------------ */ 4538 .balign 128 4539.L_op_mul_float: /* 0xa8 */ 4540/* File: arm64/op_mul_float.S */ 4541/* File: arm64/fbinop.S */ 4542 /*: 4543 * Generic 32-bit floating-point operation. 4544 * 4545 * For: add-float, sub-float, mul-float, div-float 4546 * form: <op> s0, s0, s1 4547 */ 4548 /* floatop vAA, vBB, vCC */ 4549 FETCH w0, 1 // r0<- CCBB 4550 lsr w1, w0, #8 // r2<- CC 4551 and w0, w0, #255 // r1<- BB 4552 GET_VREG s1, w1 4553 GET_VREG s0, w0 4554 fmul s0, s0, s1 // s0<- op 4555 lsr w1, wINST, #8 // r1<- AA 4556 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4557 GET_INST_OPCODE ip // extract opcode from rINST 4558 SET_VREG s0, w1 4559 GOTO_OPCODE ip // jump to next instruction 4560 4561 4562/* ------------------------------ */ 4563 .balign 128 4564.L_op_div_float: /* 0xa9 */ 4565/* File: arm64/op_div_float.S */ 4566/* File: arm64/fbinop.S */ 4567 /*: 4568 * Generic 32-bit floating-point operation. 4569 * 4570 * For: add-float, sub-float, mul-float, div-float 4571 * form: <op> s0, s0, s1 4572 */ 4573 /* floatop vAA, vBB, vCC */ 4574 FETCH w0, 1 // r0<- CCBB 4575 lsr w1, w0, #8 // r2<- CC 4576 and w0, w0, #255 // r1<- BB 4577 GET_VREG s1, w1 4578 GET_VREG s0, w0 4579 fdiv s0, s0, s1 // s0<- op 4580 lsr w1, wINST, #8 // r1<- AA 4581 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4582 GET_INST_OPCODE ip // extract opcode from rINST 4583 SET_VREG s0, w1 4584 GOTO_OPCODE ip // jump to next instruction 4585 4586 4587/* ------------------------------ */ 4588 .balign 128 4589.L_op_rem_float: /* 0xaa */ 4590/* File: arm64/op_rem_float.S */ 4591/* EABI doesn't define a float remainder function, but libm does */ 4592/* File: arm64/fbinop.S */ 4593 /*: 4594 * Generic 32-bit floating-point operation. 4595 * 4596 * For: add-float, sub-float, mul-float, div-float 4597 * form: <op> s0, s0, s1 4598 */ 4599 /* floatop vAA, vBB, vCC */ 4600 FETCH w0, 1 // r0<- CCBB 4601 lsr w1, w0, #8 // r2<- CC 4602 and w0, w0, #255 // r1<- BB 4603 GET_VREG s1, w1 4604 GET_VREG s0, w0 4605 bl fmodf // s0<- op 4606 lsr w1, wINST, #8 // r1<- AA 4607 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4608 GET_INST_OPCODE ip // extract opcode from rINST 4609 SET_VREG s0, w1 4610 GOTO_OPCODE ip // jump to next instruction 4611 4612 4613/* ------------------------------ */ 4614 .balign 128 4615.L_op_add_double: /* 0xab */ 4616/* File: arm64/op_add_double.S */ 4617/* File: arm64/binopWide.S */ 4618 /* 4619 * Generic 64-bit binary operation. Provide an "instr" line that 4620 * specifies an instruction that performs "result = x1 op x2". 4621 * This could be an ARM instruction or a function call. (If the result 4622 * comes back in a register other than x0, you can override "result".) 4623 * 4624 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4625 * vCC (w1). Useful for integer division and modulus. 4626 * 4627 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4628 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4629 */ 4630 /* binop vAA, vBB, vCC */ 4631 FETCH w0, 1 // w0<- CCBB 4632 lsr w4, wINST, #8 // w4<- AA 4633 lsr w2, w0, #8 // w2<- CC 4634 and w1, w0, #255 // w1<- BB 4635 GET_VREG_WIDE d2, w2 // w2<- vCC 4636 GET_VREG_WIDE d1, w1 // w1<- vBB 4637 .if 0 4638 cbz d2, common_errDivideByZero // is second operand zero? 4639 .endif 4640 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4641 4642 fadd d0, d1, d2 // d0<- op, w0-w4 changed 4643 GET_INST_OPCODE ip // extract opcode from rINST 4644 SET_VREG_WIDE d0, w4 // vAA<- d0 4645 GOTO_OPCODE ip // jump to next instruction 4646 /* 11-14 instructions */ 4647 4648 4649/* ------------------------------ */ 4650 .balign 128 4651.L_op_sub_double: /* 0xac */ 4652/* File: arm64/op_sub_double.S */ 4653/* File: arm64/binopWide.S */ 4654 /* 4655 * Generic 64-bit binary operation. Provide an "instr" line that 4656 * specifies an instruction that performs "result = x1 op x2". 4657 * This could be an ARM instruction or a function call. (If the result 4658 * comes back in a register other than x0, you can override "result".) 4659 * 4660 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4661 * vCC (w1). Useful for integer division and modulus. 4662 * 4663 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4664 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4665 */ 4666 /* binop vAA, vBB, vCC */ 4667 FETCH w0, 1 // w0<- CCBB 4668 lsr w4, wINST, #8 // w4<- AA 4669 lsr w2, w0, #8 // w2<- CC 4670 and w1, w0, #255 // w1<- BB 4671 GET_VREG_WIDE d2, w2 // w2<- vCC 4672 GET_VREG_WIDE d1, w1 // w1<- vBB 4673 .if 0 4674 cbz d2, common_errDivideByZero // is second operand zero? 4675 .endif 4676 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4677 4678 fsub d0, d1, d2 // d0<- op, w0-w4 changed 4679 GET_INST_OPCODE ip // extract opcode from rINST 4680 SET_VREG_WIDE d0, w4 // vAA<- d0 4681 GOTO_OPCODE ip // jump to next instruction 4682 /* 11-14 instructions */ 4683 4684 4685/* ------------------------------ */ 4686 .balign 128 4687.L_op_mul_double: /* 0xad */ 4688/* File: arm64/op_mul_double.S */ 4689/* File: arm64/binopWide.S */ 4690 /* 4691 * Generic 64-bit binary operation. Provide an "instr" line that 4692 * specifies an instruction that performs "result = x1 op x2". 4693 * This could be an ARM instruction or a function call. (If the result 4694 * comes back in a register other than x0, you can override "result".) 4695 * 4696 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4697 * vCC (w1). Useful for integer division and modulus. 4698 * 4699 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4700 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4701 */ 4702 /* binop vAA, vBB, vCC */ 4703 FETCH w0, 1 // w0<- CCBB 4704 lsr w4, wINST, #8 // w4<- AA 4705 lsr w2, w0, #8 // w2<- CC 4706 and w1, w0, #255 // w1<- BB 4707 GET_VREG_WIDE d2, w2 // w2<- vCC 4708 GET_VREG_WIDE d1, w1 // w1<- vBB 4709 .if 0 4710 cbz d2, common_errDivideByZero // is second operand zero? 4711 .endif 4712 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4713 4714 fmul d0, d1, d2 // d0<- op, w0-w4 changed 4715 GET_INST_OPCODE ip // extract opcode from rINST 4716 SET_VREG_WIDE d0, w4 // vAA<- d0 4717 GOTO_OPCODE ip // jump to next instruction 4718 /* 11-14 instructions */ 4719 4720 4721/* ------------------------------ */ 4722 .balign 128 4723.L_op_div_double: /* 0xae */ 4724/* File: arm64/op_div_double.S */ 4725/* File: arm64/binopWide.S */ 4726 /* 4727 * Generic 64-bit binary operation. Provide an "instr" line that 4728 * specifies an instruction that performs "result = x1 op x2". 4729 * This could be an ARM instruction or a function call. (If the result 4730 * comes back in a register other than x0, you can override "result".) 4731 * 4732 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4733 * vCC (w1). Useful for integer division and modulus. 4734 * 4735 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4736 * xor-long, add-double, sub-double, mul-double, div-double, rem-double 4737 */ 4738 /* binop vAA, vBB, vCC */ 4739 FETCH w0, 1 // w0<- CCBB 4740 lsr w4, wINST, #8 // w4<- AA 4741 lsr w2, w0, #8 // w2<- CC 4742 and w1, w0, #255 // w1<- BB 4743 GET_VREG_WIDE d2, w2 // w2<- vCC 4744 GET_VREG_WIDE d1, w1 // w1<- vBB 4745 .if 0 4746 cbz d2, common_errDivideByZero // is second operand zero? 4747 .endif 4748 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4749 4750 fdiv d0, d1, d2 // d0<- op, w0-w4 changed 4751 GET_INST_OPCODE ip // extract opcode from rINST 4752 SET_VREG_WIDE d0, w4 // vAA<- d0 4753 GOTO_OPCODE ip // jump to next instruction 4754 /* 11-14 instructions */ 4755 4756 4757/* ------------------------------ */ 4758 .balign 128 4759.L_op_rem_double: /* 0xaf */ 4760/* File: arm64/op_rem_double.S */ 4761 /* rem vAA, vBB, vCC */ 4762 FETCH w0, 1 // w0<- CCBB 4763 lsr w2, w0, #8 // w2<- CC 4764 and w1, w0, #255 // w1<- BB 4765 GET_VREG_WIDE d1, w2 // d1<- vCC 4766 GET_VREG_WIDE d0, w1 // d0<- vBB 4767 bl fmod 4768 lsr w4, wINST, #8 // w4<- AA 4769 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 4770 GET_INST_OPCODE ip // extract opcode from rINST 4771 SET_VREG_WIDE d0, w4 // vAA<- result 4772 GOTO_OPCODE ip // jump to next instruction 4773 /* 11-14 instructions */ 4774 4775/* ------------------------------ */ 4776 .balign 128 4777.L_op_add_int_2addr: /* 0xb0 */ 4778/* File: arm64/op_add_int_2addr.S */ 4779/* File: arm64/binop2addr.S */ 4780 /* 4781 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4782 * that specifies an instruction that performs "result = w0 op w1". 4783 * This could be an ARM instruction or a function call. (If the result 4784 * comes back in a register other than w0, you can override "result".) 4785 * 4786 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4787 * vCC (w1). Useful for integer division and modulus. 4788 * 4789 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4790 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4791 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4792 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4793 */ 4794 /* binop/2addr vA, vB */ 4795 lsr w3, wINST, #12 // w3<- B 4796 ubfx w9, wINST, #8, #4 // w9<- A 4797 GET_VREG w1, w3 // w1<- vB 4798 GET_VREG w0, w9 // w0<- vA 4799 .if 0 4800 cbz w1, common_errDivideByZero 4801 .endif 4802 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4803 // optional op; may set condition codes 4804 add w0, w0, w1 // w0<- op, w0-w3 changed 4805 GET_INST_OPCODE ip // extract opcode from rINST 4806 SET_VREG w0, w9 // vAA<- w0 4807 GOTO_OPCODE ip // jump to next instruction 4808 /* 10-13 instructions */ 4809 4810 4811/* ------------------------------ */ 4812 .balign 128 4813.L_op_sub_int_2addr: /* 0xb1 */ 4814/* File: arm64/op_sub_int_2addr.S */ 4815/* File: arm64/binop2addr.S */ 4816 /* 4817 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4818 * that specifies an instruction that performs "result = w0 op w1". 4819 * This could be an ARM instruction or a function call. (If the result 4820 * comes back in a register other than w0, you can override "result".) 4821 * 4822 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4823 * vCC (w1). Useful for integer division and modulus. 4824 * 4825 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4826 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4827 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4828 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4829 */ 4830 /* binop/2addr vA, vB */ 4831 lsr w3, wINST, #12 // w3<- B 4832 ubfx w9, wINST, #8, #4 // w9<- A 4833 GET_VREG w1, w3 // w1<- vB 4834 GET_VREG w0, w9 // w0<- vA 4835 .if 0 4836 cbz w1, common_errDivideByZero 4837 .endif 4838 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4839 // optional op; may set condition codes 4840 sub w0, w0, w1 // w0<- op, w0-w3 changed 4841 GET_INST_OPCODE ip // extract opcode from rINST 4842 SET_VREG w0, w9 // vAA<- w0 4843 GOTO_OPCODE ip // jump to next instruction 4844 /* 10-13 instructions */ 4845 4846 4847/* ------------------------------ */ 4848 .balign 128 4849.L_op_mul_int_2addr: /* 0xb2 */ 4850/* File: arm64/op_mul_int_2addr.S */ 4851/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 4852/* File: arm64/binop2addr.S */ 4853 /* 4854 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4855 * that specifies an instruction that performs "result = w0 op w1". 4856 * This could be an ARM instruction or a function call. (If the result 4857 * comes back in a register other than w0, you can override "result".) 4858 * 4859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4860 * vCC (w1). Useful for integer division and modulus. 4861 * 4862 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4863 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4864 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4865 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4866 */ 4867 /* binop/2addr vA, vB */ 4868 lsr w3, wINST, #12 // w3<- B 4869 ubfx w9, wINST, #8, #4 // w9<- A 4870 GET_VREG w1, w3 // w1<- vB 4871 GET_VREG w0, w9 // w0<- vA 4872 .if 0 4873 cbz w1, common_errDivideByZero 4874 .endif 4875 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4876 // optional op; may set condition codes 4877 mul w0, w1, w0 // w0<- op, w0-w3 changed 4878 GET_INST_OPCODE ip // extract opcode from rINST 4879 SET_VREG w0, w9 // vAA<- w0 4880 GOTO_OPCODE ip // jump to next instruction 4881 /* 10-13 instructions */ 4882 4883 4884/* ------------------------------ */ 4885 .balign 128 4886.L_op_div_int_2addr: /* 0xb3 */ 4887/* File: arm64/op_div_int_2addr.S */ 4888/* File: arm64/binop2addr.S */ 4889 /* 4890 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4891 * that specifies an instruction that performs "result = w0 op w1". 4892 * This could be an ARM instruction or a function call. (If the result 4893 * comes back in a register other than w0, you can override "result".) 4894 * 4895 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4896 * vCC (w1). Useful for integer division and modulus. 4897 * 4898 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4899 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4900 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4901 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4902 */ 4903 /* binop/2addr vA, vB */ 4904 lsr w3, wINST, #12 // w3<- B 4905 ubfx w9, wINST, #8, #4 // w9<- A 4906 GET_VREG w1, w3 // w1<- vB 4907 GET_VREG w0, w9 // w0<- vA 4908 .if 1 4909 cbz w1, common_errDivideByZero 4910 .endif 4911 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4912 // optional op; may set condition codes 4913 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 4914 GET_INST_OPCODE ip // extract opcode from rINST 4915 SET_VREG w0, w9 // vAA<- w0 4916 GOTO_OPCODE ip // jump to next instruction 4917 /* 10-13 instructions */ 4918 4919 4920/* ------------------------------ */ 4921 .balign 128 4922.L_op_rem_int_2addr: /* 0xb4 */ 4923/* File: arm64/op_rem_int_2addr.S */ 4924/* File: arm64/binop2addr.S */ 4925 /* 4926 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4927 * that specifies an instruction that performs "result = w0 op w1". 4928 * This could be an ARM instruction or a function call. (If the result 4929 * comes back in a register other than w0, you can override "result".) 4930 * 4931 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4932 * vCC (w1). Useful for integer division and modulus. 4933 * 4934 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4935 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4936 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4937 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4938 */ 4939 /* binop/2addr vA, vB */ 4940 lsr w3, wINST, #12 // w3<- B 4941 ubfx w9, wINST, #8, #4 // w9<- A 4942 GET_VREG w1, w3 // w1<- vB 4943 GET_VREG w0, w9 // w0<- vA 4944 .if 1 4945 cbz w1, common_errDivideByZero 4946 .endif 4947 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4948 sdiv w2, w0, w1 // optional op; may set condition codes 4949 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed 4950 GET_INST_OPCODE ip // extract opcode from rINST 4951 SET_VREG w0, w9 // vAA<- w0 4952 GOTO_OPCODE ip // jump to next instruction 4953 /* 10-13 instructions */ 4954 4955 4956/* ------------------------------ */ 4957 .balign 128 4958.L_op_and_int_2addr: /* 0xb5 */ 4959/* File: arm64/op_and_int_2addr.S */ 4960/* File: arm64/binop2addr.S */ 4961 /* 4962 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4963 * that specifies an instruction that performs "result = w0 op w1". 4964 * This could be an ARM instruction or a function call. (If the result 4965 * comes back in a register other than w0, you can override "result".) 4966 * 4967 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4968 * vCC (w1). Useful for integer division and modulus. 4969 * 4970 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 4971 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 4972 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 4973 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 4974 */ 4975 /* binop/2addr vA, vB */ 4976 lsr w3, wINST, #12 // w3<- B 4977 ubfx w9, wINST, #8, #4 // w9<- A 4978 GET_VREG w1, w3 // w1<- vB 4979 GET_VREG w0, w9 // w0<- vA 4980 .if 0 4981 cbz w1, common_errDivideByZero 4982 .endif 4983 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 4984 // optional op; may set condition codes 4985 and w0, w0, w1 // w0<- op, w0-w3 changed 4986 GET_INST_OPCODE ip // extract opcode from rINST 4987 SET_VREG w0, w9 // vAA<- w0 4988 GOTO_OPCODE ip // jump to next instruction 4989 /* 10-13 instructions */ 4990 4991 4992/* ------------------------------ */ 4993 .balign 128 4994.L_op_or_int_2addr: /* 0xb6 */ 4995/* File: arm64/op_or_int_2addr.S */ 4996/* File: arm64/binop2addr.S */ 4997 /* 4998 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 4999 * that specifies an instruction that performs "result = w0 op w1". 5000 * This could be an ARM instruction or a function call. (If the result 5001 * comes back in a register other than w0, you can override "result".) 5002 * 5003 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5004 * vCC (w1). Useful for integer division and modulus. 5005 * 5006 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5007 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5008 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5009 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5010 */ 5011 /* binop/2addr vA, vB */ 5012 lsr w3, wINST, #12 // w3<- B 5013 ubfx w9, wINST, #8, #4 // w9<- A 5014 GET_VREG w1, w3 // w1<- vB 5015 GET_VREG w0, w9 // w0<- vA 5016 .if 0 5017 cbz w1, common_errDivideByZero 5018 .endif 5019 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5020 // optional op; may set condition codes 5021 orr w0, w0, w1 // w0<- op, w0-w3 changed 5022 GET_INST_OPCODE ip // extract opcode from rINST 5023 SET_VREG w0, w9 // vAA<- w0 5024 GOTO_OPCODE ip // jump to next instruction 5025 /* 10-13 instructions */ 5026 5027 5028/* ------------------------------ */ 5029 .balign 128 5030.L_op_xor_int_2addr: /* 0xb7 */ 5031/* File: arm64/op_xor_int_2addr.S */ 5032/* File: arm64/binop2addr.S */ 5033 /* 5034 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5035 * that specifies an instruction that performs "result = w0 op w1". 5036 * This could be an ARM instruction or a function call. (If the result 5037 * comes back in a register other than w0, you can override "result".) 5038 * 5039 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5040 * vCC (w1). Useful for integer division and modulus. 5041 * 5042 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5043 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5044 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5045 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5046 */ 5047 /* binop/2addr vA, vB */ 5048 lsr w3, wINST, #12 // w3<- B 5049 ubfx w9, wINST, #8, #4 // w9<- A 5050 GET_VREG w1, w3 // w1<- vB 5051 GET_VREG w0, w9 // w0<- vA 5052 .if 0 5053 cbz w1, common_errDivideByZero 5054 .endif 5055 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5056 // optional op; may set condition codes 5057 eor w0, w0, w1 // w0<- op, w0-w3 changed 5058 GET_INST_OPCODE ip // extract opcode from rINST 5059 SET_VREG w0, w9 // vAA<- w0 5060 GOTO_OPCODE ip // jump to next instruction 5061 /* 10-13 instructions */ 5062 5063 5064/* ------------------------------ */ 5065 .balign 128 5066.L_op_shl_int_2addr: /* 0xb8 */ 5067/* File: arm64/op_shl_int_2addr.S */ 5068/* File: arm64/binop2addr.S */ 5069 /* 5070 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5071 * that specifies an instruction that performs "result = w0 op w1". 5072 * This could be an ARM instruction or a function call. (If the result 5073 * comes back in a register other than w0, you can override "result".) 5074 * 5075 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5076 * vCC (w1). Useful for integer division and modulus. 5077 * 5078 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5079 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5080 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5081 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5082 */ 5083 /* binop/2addr vA, vB */ 5084 lsr w3, wINST, #12 // w3<- B 5085 ubfx w9, wINST, #8, #4 // w9<- A 5086 GET_VREG w1, w3 // w1<- vB 5087 GET_VREG w0, w9 // w0<- vA 5088 .if 0 5089 cbz w1, common_errDivideByZero 5090 .endif 5091 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5092 and w1, w1, #31 // optional op; may set condition codes 5093 lsl w0, w0, w1 // w0<- op, w0-w3 changed 5094 GET_INST_OPCODE ip // extract opcode from rINST 5095 SET_VREG w0, w9 // vAA<- w0 5096 GOTO_OPCODE ip // jump to next instruction 5097 /* 10-13 instructions */ 5098 5099 5100/* ------------------------------ */ 5101 .balign 128 5102.L_op_shr_int_2addr: /* 0xb9 */ 5103/* File: arm64/op_shr_int_2addr.S */ 5104/* File: arm64/binop2addr.S */ 5105 /* 5106 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5107 * that specifies an instruction that performs "result = w0 op w1". 5108 * This could be an ARM instruction or a function call. (If the result 5109 * comes back in a register other than w0, you can override "result".) 5110 * 5111 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5112 * vCC (w1). Useful for integer division and modulus. 5113 * 5114 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5115 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5116 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5117 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5118 */ 5119 /* binop/2addr vA, vB */ 5120 lsr w3, wINST, #12 // w3<- B 5121 ubfx w9, wINST, #8, #4 // w9<- A 5122 GET_VREG w1, w3 // w1<- vB 5123 GET_VREG w0, w9 // w0<- vA 5124 .if 0 5125 cbz w1, common_errDivideByZero 5126 .endif 5127 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5128 and w1, w1, #31 // optional op; may set condition codes 5129 asr w0, w0, w1 // w0<- op, w0-w3 changed 5130 GET_INST_OPCODE ip // extract opcode from rINST 5131 SET_VREG w0, w9 // vAA<- w0 5132 GOTO_OPCODE ip // jump to next instruction 5133 /* 10-13 instructions */ 5134 5135 5136/* ------------------------------ */ 5137 .balign 128 5138.L_op_ushr_int_2addr: /* 0xba */ 5139/* File: arm64/op_ushr_int_2addr.S */ 5140/* File: arm64/binop2addr.S */ 5141 /* 5142 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5143 * that specifies an instruction that performs "result = w0 op w1". 5144 * This could be an ARM instruction or a function call. (If the result 5145 * comes back in a register other than w0, you can override "result".) 5146 * 5147 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5148 * vCC (w1). Useful for integer division and modulus. 5149 * 5150 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5151 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5152 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5153 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5154 */ 5155 /* binop/2addr vA, vB */ 5156 lsr w3, wINST, #12 // w3<- B 5157 ubfx w9, wINST, #8, #4 // w9<- A 5158 GET_VREG w1, w3 // w1<- vB 5159 GET_VREG w0, w9 // w0<- vA 5160 .if 0 5161 cbz w1, common_errDivideByZero 5162 .endif 5163 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5164 and w1, w1, #31 // optional op; may set condition codes 5165 lsr w0, w0, w1 // w0<- op, w0-w3 changed 5166 GET_INST_OPCODE ip // extract opcode from rINST 5167 SET_VREG w0, w9 // vAA<- w0 5168 GOTO_OPCODE ip // jump to next instruction 5169 /* 10-13 instructions */ 5170 5171 5172/* ------------------------------ */ 5173 .balign 128 5174.L_op_add_long_2addr: /* 0xbb */ 5175/* File: arm64/op_add_long_2addr.S */ 5176/* File: arm64/binopWide2addr.S */ 5177 /* 5178 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5179 * that specifies an instruction that performs "x0 = x0 op x1". 5180 * This must not be a function call, as we keep w2 live across it. 5181 * 5182 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5183 * vCC (w1). Useful for integer division and modulus. 5184 * 5185 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5186 * and-long/2addr, or-long/2addr, xor-long/2addr, 5187 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5188 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5189 */ 5190 /* binop/2addr vA, vB */ 5191 lsr w1, wINST, #12 // w1<- B 5192 ubfx w2, wINST, #8, #4 // w2<- A 5193 GET_VREG_WIDE x1, w1 // x1<- vB 5194 GET_VREG_WIDE x0, w2 // x0<- vA 5195 .if 0 5196 cbz x1, common_errDivideByZero 5197 .endif 5198 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5199 5200 add x0, x0, x1 // result<- op 5201 GET_INST_OPCODE ip // extract opcode from rINST 5202 SET_VREG_WIDE x0, w2 // vAA<- result 5203 GOTO_OPCODE ip // jump to next instruction 5204 /* 10-13 instructions */ 5205 5206 5207/* ------------------------------ */ 5208 .balign 128 5209.L_op_sub_long_2addr: /* 0xbc */ 5210/* File: arm64/op_sub_long_2addr.S */ 5211/* File: arm64/binopWide2addr.S */ 5212 /* 5213 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5214 * that specifies an instruction that performs "x0 = x0 op x1". 5215 * This must not be a function call, as we keep w2 live across it. 5216 * 5217 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5218 * vCC (w1). Useful for integer division and modulus. 5219 * 5220 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5221 * and-long/2addr, or-long/2addr, xor-long/2addr, 5222 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5223 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5224 */ 5225 /* binop/2addr vA, vB */ 5226 lsr w1, wINST, #12 // w1<- B 5227 ubfx w2, wINST, #8, #4 // w2<- A 5228 GET_VREG_WIDE x1, w1 // x1<- vB 5229 GET_VREG_WIDE x0, w2 // x0<- vA 5230 .if 0 5231 cbz x1, common_errDivideByZero 5232 .endif 5233 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5234 5235 sub x0, x0, x1 // result<- op 5236 GET_INST_OPCODE ip // extract opcode from rINST 5237 SET_VREG_WIDE x0, w2 // vAA<- result 5238 GOTO_OPCODE ip // jump to next instruction 5239 /* 10-13 instructions */ 5240 5241 5242/* ------------------------------ */ 5243 .balign 128 5244.L_op_mul_long_2addr: /* 0xbd */ 5245/* File: arm64/op_mul_long_2addr.S */ 5246/* File: arm64/binopWide2addr.S */ 5247 /* 5248 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5249 * that specifies an instruction that performs "x0 = x0 op x1". 5250 * This must not be a function call, as we keep w2 live across it. 5251 * 5252 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5253 * vCC (w1). Useful for integer division and modulus. 5254 * 5255 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5256 * and-long/2addr, or-long/2addr, xor-long/2addr, 5257 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5258 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5259 */ 5260 /* binop/2addr vA, vB */ 5261 lsr w1, wINST, #12 // w1<- B 5262 ubfx w2, wINST, #8, #4 // w2<- A 5263 GET_VREG_WIDE x1, w1 // x1<- vB 5264 GET_VREG_WIDE x0, w2 // x0<- vA 5265 .if 0 5266 cbz x1, common_errDivideByZero 5267 .endif 5268 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5269 5270 mul x0, x0, x1 // result<- op 5271 GET_INST_OPCODE ip // extract opcode from rINST 5272 SET_VREG_WIDE x0, w2 // vAA<- result 5273 GOTO_OPCODE ip // jump to next instruction 5274 /* 10-13 instructions */ 5275 5276 5277/* ------------------------------ */ 5278 .balign 128 5279.L_op_div_long_2addr: /* 0xbe */ 5280/* File: arm64/op_div_long_2addr.S */ 5281/* File: arm64/binopWide2addr.S */ 5282 /* 5283 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5284 * that specifies an instruction that performs "x0 = x0 op x1". 5285 * This must not be a function call, as we keep w2 live across it. 5286 * 5287 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5288 * vCC (w1). Useful for integer division and modulus. 5289 * 5290 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5291 * and-long/2addr, or-long/2addr, xor-long/2addr, 5292 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5293 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5294 */ 5295 /* binop/2addr vA, vB */ 5296 lsr w1, wINST, #12 // w1<- B 5297 ubfx w2, wINST, #8, #4 // w2<- A 5298 GET_VREG_WIDE x1, w1 // x1<- vB 5299 GET_VREG_WIDE x0, w2 // x0<- vA 5300 .if 1 5301 cbz x1, common_errDivideByZero 5302 .endif 5303 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5304 5305 sdiv x0, x0, x1 // result<- op 5306 GET_INST_OPCODE ip // extract opcode from rINST 5307 SET_VREG_WIDE x0, w2 // vAA<- result 5308 GOTO_OPCODE ip // jump to next instruction 5309 /* 10-13 instructions */ 5310 5311 5312/* ------------------------------ */ 5313 .balign 128 5314.L_op_rem_long_2addr: /* 0xbf */ 5315/* File: arm64/op_rem_long_2addr.S */ 5316/* File: arm64/binopWide2addr.S */ 5317 /* 5318 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5319 * that specifies an instruction that performs "x0 = x0 op x1". 5320 * This must not be a function call, as we keep w2 live across it. 5321 * 5322 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5323 * vCC (w1). Useful for integer division and modulus. 5324 * 5325 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5326 * and-long/2addr, or-long/2addr, xor-long/2addr, 5327 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5328 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5329 */ 5330 /* binop/2addr vA, vB */ 5331 lsr w1, wINST, #12 // w1<- B 5332 ubfx w2, wINST, #8, #4 // w2<- A 5333 GET_VREG_WIDE x1, w1 // x1<- vB 5334 GET_VREG_WIDE x0, w2 // x0<- vA 5335 .if 1 5336 cbz x1, common_errDivideByZero 5337 .endif 5338 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5339 sdiv x3, x0, x1 5340 msub x0, x3, x1, x0 // result<- op 5341 GET_INST_OPCODE ip // extract opcode from rINST 5342 SET_VREG_WIDE x0, w2 // vAA<- result 5343 GOTO_OPCODE ip // jump to next instruction 5344 /* 10-13 instructions */ 5345 5346 5347/* ------------------------------ */ 5348 .balign 128 5349.L_op_and_long_2addr: /* 0xc0 */ 5350/* File: arm64/op_and_long_2addr.S */ 5351/* File: arm64/binopWide2addr.S */ 5352 /* 5353 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5354 * that specifies an instruction that performs "x0 = x0 op x1". 5355 * This must not be a function call, as we keep w2 live across it. 5356 * 5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358 * vCC (w1). Useful for integer division and modulus. 5359 * 5360 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5361 * and-long/2addr, or-long/2addr, xor-long/2addr, 5362 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5363 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5364 */ 5365 /* binop/2addr vA, vB */ 5366 lsr w1, wINST, #12 // w1<- B 5367 ubfx w2, wINST, #8, #4 // w2<- A 5368 GET_VREG_WIDE x1, w1 // x1<- vB 5369 GET_VREG_WIDE x0, w2 // x0<- vA 5370 .if 0 5371 cbz x1, common_errDivideByZero 5372 .endif 5373 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5374 5375 and x0, x0, x1 // result<- op 5376 GET_INST_OPCODE ip // extract opcode from rINST 5377 SET_VREG_WIDE x0, w2 // vAA<- result 5378 GOTO_OPCODE ip // jump to next instruction 5379 /* 10-13 instructions */ 5380 5381 5382/* ------------------------------ */ 5383 .balign 128 5384.L_op_or_long_2addr: /* 0xc1 */ 5385/* File: arm64/op_or_long_2addr.S */ 5386/* File: arm64/binopWide2addr.S */ 5387 /* 5388 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5389 * that specifies an instruction that performs "x0 = x0 op x1". 5390 * This must not be a function call, as we keep w2 live across it. 5391 * 5392 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5393 * vCC (w1). Useful for integer division and modulus. 5394 * 5395 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5396 * and-long/2addr, or-long/2addr, xor-long/2addr, 5397 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5398 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5399 */ 5400 /* binop/2addr vA, vB */ 5401 lsr w1, wINST, #12 // w1<- B 5402 ubfx w2, wINST, #8, #4 // w2<- A 5403 GET_VREG_WIDE x1, w1 // x1<- vB 5404 GET_VREG_WIDE x0, w2 // x0<- vA 5405 .if 0 5406 cbz x1, common_errDivideByZero 5407 .endif 5408 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5409 5410 orr x0, x0, x1 // result<- op 5411 GET_INST_OPCODE ip // extract opcode from rINST 5412 SET_VREG_WIDE x0, w2 // vAA<- result 5413 GOTO_OPCODE ip // jump to next instruction 5414 /* 10-13 instructions */ 5415 5416 5417/* ------------------------------ */ 5418 .balign 128 5419.L_op_xor_long_2addr: /* 0xc2 */ 5420/* File: arm64/op_xor_long_2addr.S */ 5421/* File: arm64/binopWide2addr.S */ 5422 /* 5423 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5424 * that specifies an instruction that performs "x0 = x0 op x1". 5425 * This must not be a function call, as we keep w2 live across it. 5426 * 5427 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5428 * vCC (w1). Useful for integer division and modulus. 5429 * 5430 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5431 * and-long/2addr, or-long/2addr, xor-long/2addr, 5432 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5433 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5434 */ 5435 /* binop/2addr vA, vB */ 5436 lsr w1, wINST, #12 // w1<- B 5437 ubfx w2, wINST, #8, #4 // w2<- A 5438 GET_VREG_WIDE x1, w1 // x1<- vB 5439 GET_VREG_WIDE x0, w2 // x0<- vA 5440 .if 0 5441 cbz x1, common_errDivideByZero 5442 .endif 5443 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5444 5445 eor x0, x0, x1 // result<- op 5446 GET_INST_OPCODE ip // extract opcode from rINST 5447 SET_VREG_WIDE x0, w2 // vAA<- result 5448 GOTO_OPCODE ip // jump to next instruction 5449 /* 10-13 instructions */ 5450 5451 5452/* ------------------------------ */ 5453 .balign 128 5454.L_op_shl_long_2addr: /* 0xc3 */ 5455/* File: arm64/op_shl_long_2addr.S */ 5456/* File: arm64/shiftWide2addr.S */ 5457 /* 5458 * Generic 64-bit shift operation. 5459 */ 5460 /* binop/2addr vA, vB */ 5461 lsr w1, wINST, #12 // w1<- B 5462 ubfx w2, wINST, #8, #4 // w2<- A 5463 GET_VREG w1, w1 // x1<- vB 5464 GET_VREG_WIDE x0, w2 // x0<- vA 5465 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5466 and x1, x1, #63 // Mask low 6 bits. 5467 lsl x0, x0, x1 5468 GET_INST_OPCODE ip // extract opcode from rINST 5469 SET_VREG_WIDE x0, w2 // vAA<- result 5470 GOTO_OPCODE ip // jump to next instruction 5471 /* 10-13 instructions */ 5472 5473 5474/* ------------------------------ */ 5475 .balign 128 5476.L_op_shr_long_2addr: /* 0xc4 */ 5477/* File: arm64/op_shr_long_2addr.S */ 5478/* File: arm64/shiftWide2addr.S */ 5479 /* 5480 * Generic 64-bit shift operation. 5481 */ 5482 /* binop/2addr vA, vB */ 5483 lsr w1, wINST, #12 // w1<- B 5484 ubfx w2, wINST, #8, #4 // w2<- A 5485 GET_VREG w1, w1 // x1<- vB 5486 GET_VREG_WIDE x0, w2 // x0<- vA 5487 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5488 and x1, x1, #63 // Mask low 6 bits. 5489 asr x0, x0, x1 5490 GET_INST_OPCODE ip // extract opcode from rINST 5491 SET_VREG_WIDE x0, w2 // vAA<- result 5492 GOTO_OPCODE ip // jump to next instruction 5493 /* 10-13 instructions */ 5494 5495 5496/* ------------------------------ */ 5497 .balign 128 5498.L_op_ushr_long_2addr: /* 0xc5 */ 5499/* File: arm64/op_ushr_long_2addr.S */ 5500/* File: arm64/shiftWide2addr.S */ 5501 /* 5502 * Generic 64-bit shift operation. 5503 */ 5504 /* binop/2addr vA, vB */ 5505 lsr w1, wINST, #12 // w1<- B 5506 ubfx w2, wINST, #8, #4 // w2<- A 5507 GET_VREG w1, w1 // x1<- vB 5508 GET_VREG_WIDE x0, w2 // x0<- vA 5509 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5510 and x1, x1, #63 // Mask low 6 bits. 5511 lsr x0, x0, x1 5512 GET_INST_OPCODE ip // extract opcode from rINST 5513 SET_VREG_WIDE x0, w2 // vAA<- result 5514 GOTO_OPCODE ip // jump to next instruction 5515 /* 10-13 instructions */ 5516 5517 5518/* ------------------------------ */ 5519 .balign 128 5520.L_op_add_float_2addr: /* 0xc6 */ 5521/* File: arm64/op_add_float_2addr.S */ 5522/* File: arm64/fbinop2addr.S */ 5523 /* 5524 * Generic 32-bit floating point "/2addr" binary operation. Provide 5525 * an "instr" line that specifies an instruction that performs 5526 * "s2 = s0 op s1". 5527 * 5528 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5529 */ 5530 /* binop/2addr vA, vB */ 5531 lsr w3, wINST, #12 // w3<- B 5532 lsr w9, wINST, #8 // w9<- A+ 5533 and w9, w9, #15 // w9<- A 5534 GET_VREG s1, w3 5535 GET_VREG s0, w9 5536 fadd s2, s0, s1 // s2<- op 5537 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5538 GET_INST_OPCODE ip // extract opcode from rINST 5539 SET_VREG s2, w9 5540 GOTO_OPCODE ip // jump to next instruction 5541 5542 5543/* ------------------------------ */ 5544 .balign 128 5545.L_op_sub_float_2addr: /* 0xc7 */ 5546/* File: arm64/op_sub_float_2addr.S */ 5547/* File: arm64/fbinop2addr.S */ 5548 /* 5549 * Generic 32-bit floating point "/2addr" binary operation. Provide 5550 * an "instr" line that specifies an instruction that performs 5551 * "s2 = s0 op s1". 5552 * 5553 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5554 */ 5555 /* binop/2addr vA, vB */ 5556 lsr w3, wINST, #12 // w3<- B 5557 lsr w9, wINST, #8 // w9<- A+ 5558 and w9, w9, #15 // w9<- A 5559 GET_VREG s1, w3 5560 GET_VREG s0, w9 5561 fsub s2, s0, s1 // s2<- op 5562 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5563 GET_INST_OPCODE ip // extract opcode from rINST 5564 SET_VREG s2, w9 5565 GOTO_OPCODE ip // jump to next instruction 5566 5567 5568/* ------------------------------ */ 5569 .balign 128 5570.L_op_mul_float_2addr: /* 0xc8 */ 5571/* File: arm64/op_mul_float_2addr.S */ 5572/* File: arm64/fbinop2addr.S */ 5573 /* 5574 * Generic 32-bit floating point "/2addr" binary operation. Provide 5575 * an "instr" line that specifies an instruction that performs 5576 * "s2 = s0 op s1". 5577 * 5578 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5579 */ 5580 /* binop/2addr vA, vB */ 5581 lsr w3, wINST, #12 // w3<- B 5582 lsr w9, wINST, #8 // w9<- A+ 5583 and w9, w9, #15 // w9<- A 5584 GET_VREG s1, w3 5585 GET_VREG s0, w9 5586 fmul s2, s0, s1 // s2<- op 5587 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5588 GET_INST_OPCODE ip // extract opcode from rINST 5589 SET_VREG s2, w9 5590 GOTO_OPCODE ip // jump to next instruction 5591 5592 5593/* ------------------------------ */ 5594 .balign 128 5595.L_op_div_float_2addr: /* 0xc9 */ 5596/* File: arm64/op_div_float_2addr.S */ 5597/* File: arm64/fbinop2addr.S */ 5598 /* 5599 * Generic 32-bit floating point "/2addr" binary operation. Provide 5600 * an "instr" line that specifies an instruction that performs 5601 * "s2 = s0 op s1". 5602 * 5603 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5604 */ 5605 /* binop/2addr vA, vB */ 5606 lsr w3, wINST, #12 // w3<- B 5607 lsr w9, wINST, #8 // w9<- A+ 5608 and w9, w9, #15 // w9<- A 5609 GET_VREG s1, w3 5610 GET_VREG s0, w9 5611 fdiv s2, s0, s1 // s2<- op 5612 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5613 GET_INST_OPCODE ip // extract opcode from rINST 5614 SET_VREG s2, w9 5615 GOTO_OPCODE ip // jump to next instruction 5616 5617 5618/* ------------------------------ */ 5619 .balign 128 5620.L_op_rem_float_2addr: /* 0xca */ 5621/* File: arm64/op_rem_float_2addr.S */ 5622 /* rem vA, vB */ 5623 lsr w3, wINST, #12 // w3<- B 5624 lsr w9, wINST, #8 // w9<- A+ 5625 and w9, w9, #15 // w9<- A 5626 GET_VREG s1, w3 5627 GET_VREG s0, w9 5628 bl fmodf 5629 lsr w9, wINST, #8 // w9<- A+ 5630 and w9, w9, #15 // w9<- A 5631 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5632 GET_INST_OPCODE ip // extract opcode from rINST 5633 SET_VREG s0, w9 5634 GOTO_OPCODE ip // jump to next instruction 5635 5636/* ------------------------------ */ 5637 .balign 128 5638.L_op_add_double_2addr: /* 0xcb */ 5639/* File: arm64/op_add_double_2addr.S */ 5640/* File: arm64/binopWide2addr.S */ 5641 /* 5642 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5643 * that specifies an instruction that performs "x0 = x0 op x1". 5644 * This must not be a function call, as we keep w2 live across it. 5645 * 5646 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5647 * vCC (w1). Useful for integer division and modulus. 5648 * 5649 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5650 * and-long/2addr, or-long/2addr, xor-long/2addr, 5651 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5652 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5653 */ 5654 /* binop/2addr vA, vB */ 5655 lsr w1, wINST, #12 // w1<- B 5656 ubfx w2, wINST, #8, #4 // w2<- A 5657 GET_VREG_WIDE d1, w1 // x1<- vB 5658 GET_VREG_WIDE d0, w2 // x0<- vA 5659 .if 0 5660 cbz d1, common_errDivideByZero 5661 .endif 5662 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5663 5664 fadd d0, d0, d1 // result<- op 5665 GET_INST_OPCODE ip // extract opcode from rINST 5666 SET_VREG_WIDE d0, w2 // vAA<- result 5667 GOTO_OPCODE ip // jump to next instruction 5668 /* 10-13 instructions */ 5669 5670 5671/* ------------------------------ */ 5672 .balign 128 5673.L_op_sub_double_2addr: /* 0xcc */ 5674/* File: arm64/op_sub_double_2addr.S */ 5675/* File: arm64/binopWide2addr.S */ 5676 /* 5677 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5678 * that specifies an instruction that performs "x0 = x0 op x1". 5679 * This must not be a function call, as we keep w2 live across it. 5680 * 5681 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5682 * vCC (w1). Useful for integer division and modulus. 5683 * 5684 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5685 * and-long/2addr, or-long/2addr, xor-long/2addr, 5686 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5687 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5688 */ 5689 /* binop/2addr vA, vB */ 5690 lsr w1, wINST, #12 // w1<- B 5691 ubfx w2, wINST, #8, #4 // w2<- A 5692 GET_VREG_WIDE d1, w1 // x1<- vB 5693 GET_VREG_WIDE d0, w2 // x0<- vA 5694 .if 0 5695 cbz d1, common_errDivideByZero 5696 .endif 5697 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5698 5699 fsub d0, d0, d1 // result<- op 5700 GET_INST_OPCODE ip // extract opcode from rINST 5701 SET_VREG_WIDE d0, w2 // vAA<- result 5702 GOTO_OPCODE ip // jump to next instruction 5703 /* 10-13 instructions */ 5704 5705 5706/* ------------------------------ */ 5707 .balign 128 5708.L_op_mul_double_2addr: /* 0xcd */ 5709/* File: arm64/op_mul_double_2addr.S */ 5710/* File: arm64/binopWide2addr.S */ 5711 /* 5712 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5713 * that specifies an instruction that performs "x0 = x0 op x1". 5714 * This must not be a function call, as we keep w2 live across it. 5715 * 5716 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5717 * vCC (w1). Useful for integer division and modulus. 5718 * 5719 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5720 * and-long/2addr, or-long/2addr, xor-long/2addr, 5721 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5722 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5723 */ 5724 /* binop/2addr vA, vB */ 5725 lsr w1, wINST, #12 // w1<- B 5726 ubfx w2, wINST, #8, #4 // w2<- A 5727 GET_VREG_WIDE d1, w1 // x1<- vB 5728 GET_VREG_WIDE d0, w2 // x0<- vA 5729 .if 0 5730 cbz d1, common_errDivideByZero 5731 .endif 5732 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5733 5734 fmul d0, d0, d1 // result<- op 5735 GET_INST_OPCODE ip // extract opcode from rINST 5736 SET_VREG_WIDE d0, w2 // vAA<- result 5737 GOTO_OPCODE ip // jump to next instruction 5738 /* 10-13 instructions */ 5739 5740 5741/* ------------------------------ */ 5742 .balign 128 5743.L_op_div_double_2addr: /* 0xce */ 5744/* File: arm64/op_div_double_2addr.S */ 5745/* File: arm64/binopWide2addr.S */ 5746 /* 5747 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5748 * that specifies an instruction that performs "x0 = x0 op x1". 5749 * This must not be a function call, as we keep w2 live across it. 5750 * 5751 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5752 * vCC (w1). Useful for integer division and modulus. 5753 * 5754 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5755 * and-long/2addr, or-long/2addr, xor-long/2addr, 5756 * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, 5757 * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr 5758 */ 5759 /* binop/2addr vA, vB */ 5760 lsr w1, wINST, #12 // w1<- B 5761 ubfx w2, wINST, #8, #4 // w2<- A 5762 GET_VREG_WIDE d1, w1 // x1<- vB 5763 GET_VREG_WIDE d0, w2 // x0<- vA 5764 .if 0 5765 cbz d1, common_errDivideByZero 5766 .endif 5767 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5768 5769 fdiv d0, d0, d1 // result<- op 5770 GET_INST_OPCODE ip // extract opcode from rINST 5771 SET_VREG_WIDE d0, w2 // vAA<- result 5772 GOTO_OPCODE ip // jump to next instruction 5773 /* 10-13 instructions */ 5774 5775 5776/* ------------------------------ */ 5777 .balign 128 5778.L_op_rem_double_2addr: /* 0xcf */ 5779/* File: arm64/op_rem_double_2addr.S */ 5780 /* rem vA, vB */ 5781 lsr w1, wINST, #12 // w1<- B 5782 ubfx w2, wINST, #8, #4 // w2<- A 5783 GET_VREG_WIDE d1, w1 // d1<- vB 5784 GET_VREG_WIDE d0, w2 // d0<- vA 5785 bl fmod 5786 ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) 5787 FETCH_ADVANCE_INST 1 // advance rPC, load rINST 5788 GET_INST_OPCODE ip // extract opcode from rINST 5789 SET_VREG_WIDE d0, w2 // vAA<- result 5790 GOTO_OPCODE ip // jump to next instruction 5791 /* 10-13 instructions */ 5792 5793/* ------------------------------ */ 5794 .balign 128 5795.L_op_add_int_lit16: /* 0xd0 */ 5796/* File: arm64/op_add_int_lit16.S */ 5797/* File: arm64/binopLit16.S */ 5798 /* 5799 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5800 * that specifies an instruction that performs "result = w0 op w1". 5801 * This could be an ARM instruction or a function call. (If the result 5802 * comes back in a register other than w0, you can override "result".) 5803 * 5804 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5805 * vCC (w1). Useful for integer division and modulus. 5806 * 5807 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5808 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5809 */ 5810 /* binop/lit16 vA, vB, #+CCCC */ 5811 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5812 lsr w2, wINST, #12 // w2<- B 5813 ubfx w9, wINST, #8, #4 // w9<- A 5814 GET_VREG w0, w2 // w0<- vB 5815 .if 0 5816 cbz w1, common_errDivideByZero 5817 .endif 5818 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5819 5820 add w0, w0, w1 // w0<- op, w0-w3 changed 5821 GET_INST_OPCODE ip // extract opcode from rINST 5822 SET_VREG w0, w9 // vAA<- w0 5823 GOTO_OPCODE ip // jump to next instruction 5824 /* 10-13 instructions */ 5825 5826 5827/* ------------------------------ */ 5828 .balign 128 5829.L_op_rsub_int: /* 0xd1 */ 5830/* File: arm64/op_rsub_int.S */ 5831/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 5832/* File: arm64/binopLit16.S */ 5833 /* 5834 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5835 * that specifies an instruction that performs "result = w0 op w1". 5836 * This could be an ARM instruction or a function call. (If the result 5837 * comes back in a register other than w0, you can override "result".) 5838 * 5839 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5840 * vCC (w1). Useful for integer division and modulus. 5841 * 5842 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5843 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5844 */ 5845 /* binop/lit16 vA, vB, #+CCCC */ 5846 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5847 lsr w2, wINST, #12 // w2<- B 5848 ubfx w9, wINST, #8, #4 // w9<- A 5849 GET_VREG w0, w2 // w0<- vB 5850 .if 0 5851 cbz w1, common_errDivideByZero 5852 .endif 5853 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5854 5855 sub w0, w1, w0 // w0<- op, w0-w3 changed 5856 GET_INST_OPCODE ip // extract opcode from rINST 5857 SET_VREG w0, w9 // vAA<- w0 5858 GOTO_OPCODE ip // jump to next instruction 5859 /* 10-13 instructions */ 5860 5861 5862/* ------------------------------ */ 5863 .balign 128 5864.L_op_mul_int_lit16: /* 0xd2 */ 5865/* File: arm64/op_mul_int_lit16.S */ 5866/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 5867/* File: arm64/binopLit16.S */ 5868 /* 5869 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5870 * that specifies an instruction that performs "result = w0 op w1". 5871 * This could be an ARM instruction or a function call. (If the result 5872 * comes back in a register other than w0, you can override "result".) 5873 * 5874 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5875 * vCC (w1). Useful for integer division and modulus. 5876 * 5877 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5878 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5879 */ 5880 /* binop/lit16 vA, vB, #+CCCC */ 5881 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5882 lsr w2, wINST, #12 // w2<- B 5883 ubfx w9, wINST, #8, #4 // w9<- A 5884 GET_VREG w0, w2 // w0<- vB 5885 .if 0 5886 cbz w1, common_errDivideByZero 5887 .endif 5888 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5889 5890 mul w0, w1, w0 // w0<- op, w0-w3 changed 5891 GET_INST_OPCODE ip // extract opcode from rINST 5892 SET_VREG w0, w9 // vAA<- w0 5893 GOTO_OPCODE ip // jump to next instruction 5894 /* 10-13 instructions */ 5895 5896 5897/* ------------------------------ */ 5898 .balign 128 5899.L_op_div_int_lit16: /* 0xd3 */ 5900/* File: arm64/op_div_int_lit16.S */ 5901/* File: arm64/binopLit16.S */ 5902 /* 5903 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5904 * that specifies an instruction that performs "result = w0 op w1". 5905 * This could be an ARM instruction or a function call. (If the result 5906 * comes back in a register other than w0, you can override "result".) 5907 * 5908 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5909 * vCC (w1). Useful for integer division and modulus. 5910 * 5911 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5912 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5913 */ 5914 /* binop/lit16 vA, vB, #+CCCC */ 5915 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5916 lsr w2, wINST, #12 // w2<- B 5917 ubfx w9, wINST, #8, #4 // w9<- A 5918 GET_VREG w0, w2 // w0<- vB 5919 .if 1 5920 cbz w1, common_errDivideByZero 5921 .endif 5922 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5923 5924 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 5925 GET_INST_OPCODE ip // extract opcode from rINST 5926 SET_VREG w0, w9 // vAA<- w0 5927 GOTO_OPCODE ip // jump to next instruction 5928 /* 10-13 instructions */ 5929 5930 5931/* ------------------------------ */ 5932 .balign 128 5933.L_op_rem_int_lit16: /* 0xd4 */ 5934/* File: arm64/op_rem_int_lit16.S */ 5935/* File: arm64/binopLit16.S */ 5936 /* 5937 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5938 * that specifies an instruction that performs "result = w0 op w1". 5939 * This could be an ARM instruction or a function call. (If the result 5940 * comes back in a register other than w0, you can override "result".) 5941 * 5942 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5943 * vCC (w1). Useful for integer division and modulus. 5944 * 5945 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5946 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5947 */ 5948 /* binop/lit16 vA, vB, #+CCCC */ 5949 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5950 lsr w2, wINST, #12 // w2<- B 5951 ubfx w9, wINST, #8, #4 // w9<- A 5952 GET_VREG w0, w2 // w0<- vB 5953 .if 1 5954 cbz w1, common_errDivideByZero 5955 .endif 5956 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5957 sdiv w3, w0, w1 5958 msub w0, w3, w1, w0 // w0<- op, w0-w3 changed 5959 GET_INST_OPCODE ip // extract opcode from rINST 5960 SET_VREG w0, w9 // vAA<- w0 5961 GOTO_OPCODE ip // jump to next instruction 5962 /* 10-13 instructions */ 5963 5964 5965/* ------------------------------ */ 5966 .balign 128 5967.L_op_and_int_lit16: /* 0xd5 */ 5968/* File: arm64/op_and_int_lit16.S */ 5969/* File: arm64/binopLit16.S */ 5970 /* 5971 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 5972 * that specifies an instruction that performs "result = w0 op w1". 5973 * This could be an ARM instruction or a function call. (If the result 5974 * comes back in a register other than w0, you can override "result".) 5975 * 5976 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5977 * vCC (w1). Useful for integer division and modulus. 5978 * 5979 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 5980 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 5981 */ 5982 /* binop/lit16 vA, vB, #+CCCC */ 5983 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 5984 lsr w2, wINST, #12 // w2<- B 5985 ubfx w9, wINST, #8, #4 // w9<- A 5986 GET_VREG w0, w2 // w0<- vB 5987 .if 0 5988 cbz w1, common_errDivideByZero 5989 .endif 5990 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 5991 5992 and w0, w0, w1 // w0<- op, w0-w3 changed 5993 GET_INST_OPCODE ip // extract opcode from rINST 5994 SET_VREG w0, w9 // vAA<- w0 5995 GOTO_OPCODE ip // jump to next instruction 5996 /* 10-13 instructions */ 5997 5998 5999/* ------------------------------ */ 6000 .balign 128 6001.L_op_or_int_lit16: /* 0xd6 */ 6002/* File: arm64/op_or_int_lit16.S */ 6003/* File: arm64/binopLit16.S */ 6004 /* 6005 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6006 * that specifies an instruction that performs "result = w0 op w1". 6007 * This could be an ARM instruction or a function call. (If the result 6008 * comes back in a register other than w0, you can override "result".) 6009 * 6010 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6011 * vCC (w1). Useful for integer division and modulus. 6012 * 6013 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6014 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6015 */ 6016 /* binop/lit16 vA, vB, #+CCCC */ 6017 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 6018 lsr w2, wINST, #12 // w2<- B 6019 ubfx w9, wINST, #8, #4 // w9<- A 6020 GET_VREG w0, w2 // w0<- vB 6021 .if 0 6022 cbz w1, common_errDivideByZero 6023 .endif 6024 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6025 6026 orr w0, w0, w1 // w0<- op, w0-w3 changed 6027 GET_INST_OPCODE ip // extract opcode from rINST 6028 SET_VREG w0, w9 // vAA<- w0 6029 GOTO_OPCODE ip // jump to next instruction 6030 /* 10-13 instructions */ 6031 6032 6033/* ------------------------------ */ 6034 .balign 128 6035.L_op_xor_int_lit16: /* 0xd7 */ 6036/* File: arm64/op_xor_int_lit16.S */ 6037/* File: arm64/binopLit16.S */ 6038 /* 6039 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6040 * that specifies an instruction that performs "result = w0 op w1". 6041 * This could be an ARM instruction or a function call. (If the result 6042 * comes back in a register other than w0, you can override "result".) 6043 * 6044 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6045 * vCC (w1). Useful for integer division and modulus. 6046 * 6047 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6048 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6049 */ 6050 /* binop/lit16 vA, vB, #+CCCC */ 6051 FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) 6052 lsr w2, wINST, #12 // w2<- B 6053 ubfx w9, wINST, #8, #4 // w9<- A 6054 GET_VREG w0, w2 // w0<- vB 6055 .if 0 6056 cbz w1, common_errDivideByZero 6057 .endif 6058 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6059 6060 eor w0, w0, w1 // w0<- op, w0-w3 changed 6061 GET_INST_OPCODE ip // extract opcode from rINST 6062 SET_VREG w0, w9 // vAA<- w0 6063 GOTO_OPCODE ip // jump to next instruction 6064 /* 10-13 instructions */ 6065 6066 6067/* ------------------------------ */ 6068 .balign 128 6069.L_op_add_int_lit8: /* 0xd8 */ 6070/* File: arm64/op_add_int_lit8.S */ 6071/* File: arm64/binopLit8.S */ 6072 /* 6073 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6074 * that specifies an instruction that performs "result = w0 op w1". 6075 * This could be an ARM instruction or a function call. (If the result 6076 * comes back in a register other than w0, you can override "result".) 6077 * 6078 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6079 * vCC (w1). Useful for integer division and modulus. 6080 * 6081 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6082 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6083 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6084 */ 6085 /* binop/lit8 vAA, vBB, #+CC */ 6086 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6087 lsr w9, wINST, #8 // w9<- AA 6088 and w2, w3, #255 // w2<- BB 6089 GET_VREG w0, w2 // w0<- vBB 6090 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6091 .if 0 6092 cbz w1, common_errDivideByZero 6093 .endif 6094 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6095 // optional op; may set condition codes 6096 add w0, w0, w1 // w0<- op, w0-w3 changed 6097 GET_INST_OPCODE ip // extract opcode from rINST 6098 SET_VREG w0, w9 // vAA<- w0 6099 GOTO_OPCODE ip // jump to next instruction 6100 /* 10-12 instructions */ 6101 6102 6103/* ------------------------------ */ 6104 .balign 128 6105.L_op_rsub_int_lit8: /* 0xd9 */ 6106/* File: arm64/op_rsub_int_lit8.S */ 6107/* File: arm64/binopLit8.S */ 6108 /* 6109 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6110 * that specifies an instruction that performs "result = w0 op w1". 6111 * This could be an ARM instruction or a function call. (If the result 6112 * comes back in a register other than w0, you can override "result".) 6113 * 6114 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6115 * vCC (w1). Useful for integer division and modulus. 6116 * 6117 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6118 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6119 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6120 */ 6121 /* binop/lit8 vAA, vBB, #+CC */ 6122 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6123 lsr w9, wINST, #8 // w9<- AA 6124 and w2, w3, #255 // w2<- BB 6125 GET_VREG w0, w2 // w0<- vBB 6126 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6127 .if 0 6128 cbz w1, common_errDivideByZero 6129 .endif 6130 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6131 // optional op; may set condition codes 6132 sub w0, w1, w0 // w0<- op, w0-w3 changed 6133 GET_INST_OPCODE ip // extract opcode from rINST 6134 SET_VREG w0, w9 // vAA<- w0 6135 GOTO_OPCODE ip // jump to next instruction 6136 /* 10-12 instructions */ 6137 6138 6139/* ------------------------------ */ 6140 .balign 128 6141.L_op_mul_int_lit8: /* 0xda */ 6142/* File: arm64/op_mul_int_lit8.S */ 6143/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ 6144/* File: arm64/binopLit8.S */ 6145 /* 6146 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6147 * that specifies an instruction that performs "result = w0 op w1". 6148 * This could be an ARM instruction or a function call. (If the result 6149 * comes back in a register other than w0, you can override "result".) 6150 * 6151 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6152 * vCC (w1). Useful for integer division and modulus. 6153 * 6154 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6155 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6156 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6157 */ 6158 /* binop/lit8 vAA, vBB, #+CC */ 6159 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6160 lsr w9, wINST, #8 // w9<- AA 6161 and w2, w3, #255 // w2<- BB 6162 GET_VREG w0, w2 // w0<- vBB 6163 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6164 .if 0 6165 cbz w1, common_errDivideByZero 6166 .endif 6167 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6168 // optional op; may set condition codes 6169 mul w0, w1, w0 // w0<- op, w0-w3 changed 6170 GET_INST_OPCODE ip // extract opcode from rINST 6171 SET_VREG w0, w9 // vAA<- w0 6172 GOTO_OPCODE ip // jump to next instruction 6173 /* 10-12 instructions */ 6174 6175 6176/* ------------------------------ */ 6177 .balign 128 6178.L_op_div_int_lit8: /* 0xdb */ 6179/* File: arm64/op_div_int_lit8.S */ 6180/* File: arm64/binopLit8.S */ 6181 /* 6182 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6183 * that specifies an instruction that performs "result = w0 op w1". 6184 * This could be an ARM instruction or a function call. (If the result 6185 * comes back in a register other than w0, you can override "result".) 6186 * 6187 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6188 * vCC (w1). Useful for integer division and modulus. 6189 * 6190 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6191 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6192 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6193 */ 6194 /* binop/lit8 vAA, vBB, #+CC */ 6195 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6196 lsr w9, wINST, #8 // w9<- AA 6197 and w2, w3, #255 // w2<- BB 6198 GET_VREG w0, w2 // w0<- vBB 6199 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6200 .if 1 6201 cbz w1, common_errDivideByZero 6202 .endif 6203 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6204 // optional op; may set condition codes 6205 sdiv w0, w0, w1 // w0<- op, w0-w3 changed 6206 GET_INST_OPCODE ip // extract opcode from rINST 6207 SET_VREG w0, w9 // vAA<- w0 6208 GOTO_OPCODE ip // jump to next instruction 6209 /* 10-12 instructions */ 6210 6211 6212/* ------------------------------ */ 6213 .balign 128 6214.L_op_rem_int_lit8: /* 0xdc */ 6215/* File: arm64/op_rem_int_lit8.S */ 6216/* File: arm64/binopLit8.S */ 6217 /* 6218 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6219 * that specifies an instruction that performs "result = w0 op w1". 6220 * This could be an ARM instruction or a function call. (If the result 6221 * comes back in a register other than w0, you can override "result".) 6222 * 6223 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6224 * vCC (w1). Useful for integer division and modulus. 6225 * 6226 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6227 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6228 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6229 */ 6230 /* binop/lit8 vAA, vBB, #+CC */ 6231 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6232 lsr w9, wINST, #8 // w9<- AA 6233 and w2, w3, #255 // w2<- BB 6234 GET_VREG w0, w2 // w0<- vBB 6235 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6236 .if 1 6237 cbz w1, common_errDivideByZero 6238 .endif 6239 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6240 sdiv w3, w0, w1 // optional op; may set condition codes 6241 msub w0, w3, w1, w0 // w0<- op, w0-w3 changed 6242 GET_INST_OPCODE ip // extract opcode from rINST 6243 SET_VREG w0, w9 // vAA<- w0 6244 GOTO_OPCODE ip // jump to next instruction 6245 /* 10-12 instructions */ 6246 6247 6248/* ------------------------------ */ 6249 .balign 128 6250.L_op_and_int_lit8: /* 0xdd */ 6251/* File: arm64/op_and_int_lit8.S */ 6252/* File: arm64/binopLit8.S */ 6253 /* 6254 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6255 * that specifies an instruction that performs "result = w0 op w1". 6256 * This could be an ARM instruction or a function call. (If the result 6257 * comes back in a register other than w0, you can override "result".) 6258 * 6259 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6260 * vCC (w1). Useful for integer division and modulus. 6261 * 6262 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6263 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6264 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6265 */ 6266 /* binop/lit8 vAA, vBB, #+CC */ 6267 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6268 lsr w9, wINST, #8 // w9<- AA 6269 and w2, w3, #255 // w2<- BB 6270 GET_VREG w0, w2 // w0<- vBB 6271 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6272 .if 0 6273 cbz w1, common_errDivideByZero 6274 .endif 6275 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6276 // optional op; may set condition codes 6277 and w0, w0, w1 // w0<- op, w0-w3 changed 6278 GET_INST_OPCODE ip // extract opcode from rINST 6279 SET_VREG w0, w9 // vAA<- w0 6280 GOTO_OPCODE ip // jump to next instruction 6281 /* 10-12 instructions */ 6282 6283 6284/* ------------------------------ */ 6285 .balign 128 6286.L_op_or_int_lit8: /* 0xde */ 6287/* File: arm64/op_or_int_lit8.S */ 6288/* File: arm64/binopLit8.S */ 6289 /* 6290 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6291 * that specifies an instruction that performs "result = w0 op w1". 6292 * This could be an ARM instruction or a function call. (If the result 6293 * comes back in a register other than w0, you can override "result".) 6294 * 6295 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6296 * vCC (w1). Useful for integer division and modulus. 6297 * 6298 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6299 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6300 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6301 */ 6302 /* binop/lit8 vAA, vBB, #+CC */ 6303 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6304 lsr w9, wINST, #8 // w9<- AA 6305 and w2, w3, #255 // w2<- BB 6306 GET_VREG w0, w2 // w0<- vBB 6307 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6308 .if 0 6309 cbz w1, common_errDivideByZero 6310 .endif 6311 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6312 // optional op; may set condition codes 6313 orr w0, w0, w1 // w0<- op, w0-w3 changed 6314 GET_INST_OPCODE ip // extract opcode from rINST 6315 SET_VREG w0, w9 // vAA<- w0 6316 GOTO_OPCODE ip // jump to next instruction 6317 /* 10-12 instructions */ 6318 6319 6320/* ------------------------------ */ 6321 .balign 128 6322.L_op_xor_int_lit8: /* 0xdf */ 6323/* File: arm64/op_xor_int_lit8.S */ 6324/* File: arm64/binopLit8.S */ 6325 /* 6326 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6327 * that specifies an instruction that performs "result = w0 op w1". 6328 * This could be an ARM instruction or a function call. (If the result 6329 * comes back in a register other than w0, you can override "result".) 6330 * 6331 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6332 * vCC (w1). Useful for integer division and modulus. 6333 * 6334 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6335 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6336 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6337 */ 6338 /* binop/lit8 vAA, vBB, #+CC */ 6339 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6340 lsr w9, wINST, #8 // w9<- AA 6341 and w2, w3, #255 // w2<- BB 6342 GET_VREG w0, w2 // w0<- vBB 6343 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6344 .if 0 6345 cbz w1, common_errDivideByZero 6346 .endif 6347 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6348 // optional op; may set condition codes 6349 eor w0, w0, w1 // w0<- op, w0-w3 changed 6350 GET_INST_OPCODE ip // extract opcode from rINST 6351 SET_VREG w0, w9 // vAA<- w0 6352 GOTO_OPCODE ip // jump to next instruction 6353 /* 10-12 instructions */ 6354 6355 6356/* ------------------------------ */ 6357 .balign 128 6358.L_op_shl_int_lit8: /* 0xe0 */ 6359/* File: arm64/op_shl_int_lit8.S */ 6360/* File: arm64/binopLit8.S */ 6361 /* 6362 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6363 * that specifies an instruction that performs "result = w0 op w1". 6364 * This could be an ARM instruction or a function call. (If the result 6365 * comes back in a register other than w0, you can override "result".) 6366 * 6367 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6368 * vCC (w1). Useful for integer division and modulus. 6369 * 6370 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6371 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6372 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6373 */ 6374 /* binop/lit8 vAA, vBB, #+CC */ 6375 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6376 lsr w9, wINST, #8 // w9<- AA 6377 and w2, w3, #255 // w2<- BB 6378 GET_VREG w0, w2 // w0<- vBB 6379 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6380 .if 0 6381 cbz w1, common_errDivideByZero 6382 .endif 6383 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6384 and w1, w1, #31 // optional op; may set condition codes 6385 lsl w0, w0, w1 // w0<- op, w0-w3 changed 6386 GET_INST_OPCODE ip // extract opcode from rINST 6387 SET_VREG w0, w9 // vAA<- w0 6388 GOTO_OPCODE ip // jump to next instruction 6389 /* 10-12 instructions */ 6390 6391 6392/* ------------------------------ */ 6393 .balign 128 6394.L_op_shr_int_lit8: /* 0xe1 */ 6395/* File: arm64/op_shr_int_lit8.S */ 6396/* File: arm64/binopLit8.S */ 6397 /* 6398 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6399 * that specifies an instruction that performs "result = w0 op w1". 6400 * This could be an ARM instruction or a function call. (If the result 6401 * comes back in a register other than w0, you can override "result".) 6402 * 6403 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6404 * vCC (w1). Useful for integer division and modulus. 6405 * 6406 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6407 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6408 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6409 */ 6410 /* binop/lit8 vAA, vBB, #+CC */ 6411 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6412 lsr w9, wINST, #8 // w9<- AA 6413 and w2, w3, #255 // w2<- BB 6414 GET_VREG w0, w2 // w0<- vBB 6415 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6416 .if 0 6417 cbz w1, common_errDivideByZero 6418 .endif 6419 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6420 and w1, w1, #31 // optional op; may set condition codes 6421 asr w0, w0, w1 // w0<- op, w0-w3 changed 6422 GET_INST_OPCODE ip // extract opcode from rINST 6423 SET_VREG w0, w9 // vAA<- w0 6424 GOTO_OPCODE ip // jump to next instruction 6425 /* 10-12 instructions */ 6426 6427 6428/* ------------------------------ */ 6429 .balign 128 6430.L_op_ushr_int_lit8: /* 0xe2 */ 6431/* File: arm64/op_ushr_int_lit8.S */ 6432/* File: arm64/binopLit8.S */ 6433 /* 6434 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6435 * that specifies an instruction that performs "result = w0 op w1". 6436 * This could be an ARM instruction or a function call. (If the result 6437 * comes back in a register other than w0, you can override "result".) 6438 * 6439 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6440 * vCC (w1). Useful for integer division and modulus. 6441 * 6442 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6443 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6444 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6445 */ 6446 /* binop/lit8 vAA, vBB, #+CC */ 6447 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC 6448 lsr w9, wINST, #8 // w9<- AA 6449 and w2, w3, #255 // w2<- BB 6450 GET_VREG w0, w2 // w0<- vBB 6451 asr w1, w3, #8 // w1<- ssssssCC (sign extended) 6452 .if 0 6453 cbz w1, common_errDivideByZero 6454 .endif 6455 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6456 and w1, w1, #31 // optional op; may set condition codes 6457 lsr w0, w0, w1 // w0<- op, w0-w3 changed 6458 GET_INST_OPCODE ip // extract opcode from rINST 6459 SET_VREG w0, w9 // vAA<- w0 6460 GOTO_OPCODE ip // jump to next instruction 6461 /* 10-12 instructions */ 6462 6463 6464/* ------------------------------ */ 6465 .balign 128 6466.L_op_iget_quick: /* 0xe3 */ 6467/* File: arm64/op_iget_quick.S */ 6468 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6469 /* op vA, vB, offset//CCCC */ 6470 lsr w2, wINST, #12 // w2<- B 6471 FETCH w1, 1 // w1<- field byte offset 6472 GET_VREG w3, w2 // w3<- object we're operating on 6473 ubfx w2, wINST, #8, #4 // w2<- A 6474 cmp x3, #0 // check object for null 6475 beq common_errNullObject // object was null 6476 ldr w0, [x3, x1] // w0<- obj.field 6477 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6478 6479 SET_VREG w0, w2 // fp[A]<- w0 6480 GET_INST_OPCODE ip // extract opcode from rINST 6481 GOTO_OPCODE ip // jump to next instruction 6482 6483/* ------------------------------ */ 6484 .balign 128 6485.L_op_iget_wide_quick: /* 0xe4 */ 6486/* File: arm64/op_iget_wide_quick.S */ 6487 /* iget-wide-quick vA, vB, offset//CCCC */ 6488 lsr w2, wINST, #12 // w2<- B 6489 FETCH w4, 1 // w4<- field byte offset 6490 GET_VREG w3, w2 // w3<- object we're operating on 6491 ubfx w2, wINST, #8, #4 // w2<- A 6492 cbz w3, common_errNullObject // object was null 6493 add x4, x3, x4 // create direct pointer 6494 ldr x0, [x4] 6495 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 6496 SET_VREG_WIDE x0, w2 6497 GET_INST_OPCODE ip // extract opcode from wINST 6498 GOTO_OPCODE ip // jump to next instruction 6499 6500/* ------------------------------ */ 6501 .balign 128 6502.L_op_iget_object_quick: /* 0xe5 */ 6503/* File: arm64/op_iget_object_quick.S */ 6504 /* For: iget-object-quick */ 6505 /* op vA, vB, offset//CCCC */ 6506 lsr w2, wINST, #12 // w2<- B 6507 FETCH w1, 1 // w1<- field byte offset 6508 EXPORT_PC 6509 GET_VREG w0, w2 // w0<- object we're operating on 6510 bl artIGetObjectFromMterp // (obj, offset) 6511 ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] 6512 ubfx w2, wINST, #8, #4 // w2<- A 6513 PREFETCH_INST 2 6514 cbnz w3, MterpPossibleException // bail out 6515 SET_VREG_OBJECT w0, w2 // fp[A]<- w0 6516 ADVANCE 2 // advance rPC 6517 GET_INST_OPCODE ip // extract opcode from wINST 6518 GOTO_OPCODE ip // jump to next instruction 6519 6520/* ------------------------------ */ 6521 .balign 128 6522.L_op_iput_quick: /* 0xe6 */ 6523/* File: arm64/op_iput_quick.S */ 6524 /* For: iput-quick, iput-object-quick */ 6525 /* op vA, vB, offset//CCCC */ 6526 lsr w2, wINST, #12 // w2<- B 6527 FETCH w1, 1 // w1<- field byte offset 6528 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6529 ubfx w2, wINST, #8, #4 // w2<- A 6530 cmp w3, #0 // check object for null 6531 cbz w3, common_errNullObject // object was null 6532 GET_VREG w0, w2 // w0<- fp[A] 6533 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6534 str w0, [x3, x1] // obj.field<- w0 6535 GET_INST_OPCODE ip // extract opcode from rINST 6536 GOTO_OPCODE ip // jump to next instruction 6537 6538/* ------------------------------ */ 6539 .balign 128 6540.L_op_iput_wide_quick: /* 0xe7 */ 6541/* File: arm64/op_iput_wide_quick.S */ 6542 /* iput-wide-quick vA, vB, offset//CCCC */ 6543 lsr w2, wINST, #12 // w2<- B 6544 FETCH w3, 1 // w3<- field byte offset 6545 GET_VREG w2, w2 // w2<- fp[B], the object pointer 6546 ubfx w0, wINST, #8, #4 // w0<- A 6547 cmp w2, #0 // check object for null 6548 beq common_errNullObject // object was null 6549 GET_VREG_WIDE x0, w0 // x0-< fp[A] 6550 FETCH_ADVANCE_INST 2 // advance rPC, load wINST 6551 add x1, x2, x3 // create a direct pointer 6552 str x0, [x1] 6553 GET_INST_OPCODE ip // extract opcode from wINST 6554 GOTO_OPCODE ip // jump to next instruction 6555 6556/* ------------------------------ */ 6557 .balign 128 6558.L_op_iput_object_quick: /* 0xe8 */ 6559/* File: arm64/op_iput_object_quick.S */ 6560 EXPORT_PC 6561 add x0, xFP, #OFF_FP_SHADOWFRAME 6562 mov x1, xPC 6563 mov w2, wINST 6564 bl MterpIputObjectQuick 6565 cbz w0, MterpException 6566 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6567 GET_INST_OPCODE ip // extract opcode from rINST 6568 GOTO_OPCODE ip // jump to next instruction 6569 6570/* ------------------------------ */ 6571 .balign 128 6572.L_op_invoke_virtual_quick: /* 0xe9 */ 6573/* File: arm64/op_invoke_virtual_quick.S */ 6574/* File: arm64/invoke.S */ 6575 /* 6576 * Generic invoke handler wrapper. 6577 */ 6578 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6579 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6580 .extern MterpInvokeVirtualQuick 6581 EXPORT_PC 6582 mov x0, xSELF 6583 add x1, xFP, #OFF_FP_SHADOWFRAME 6584 mov x2, xPC 6585 mov x3, xINST 6586 bl MterpInvokeVirtualQuick 6587 cbz w0, MterpException 6588 FETCH_ADVANCE_INST 3 6589 bl MterpShouldSwitchInterpreters 6590 cbnz w0, MterpFallback 6591 GET_INST_OPCODE ip 6592 GOTO_OPCODE ip 6593 6594 6595 6596/* ------------------------------ */ 6597 .balign 128 6598.L_op_invoke_virtual_range_quick: /* 0xea */ 6599/* File: arm64/op_invoke_virtual_range_quick.S */ 6600/* File: arm64/invoke.S */ 6601 /* 6602 * Generic invoke handler wrapper. 6603 */ 6604 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6605 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6606 .extern MterpInvokeVirtualQuickRange 6607 EXPORT_PC 6608 mov x0, xSELF 6609 add x1, xFP, #OFF_FP_SHADOWFRAME 6610 mov x2, xPC 6611 mov x3, xINST 6612 bl MterpInvokeVirtualQuickRange 6613 cbz w0, MterpException 6614 FETCH_ADVANCE_INST 3 6615 bl MterpShouldSwitchInterpreters 6616 cbnz w0, MterpFallback 6617 GET_INST_OPCODE ip 6618 GOTO_OPCODE ip 6619 6620 6621 6622/* ------------------------------ */ 6623 .balign 128 6624.L_op_iput_boolean_quick: /* 0xeb */ 6625/* File: arm64/op_iput_boolean_quick.S */ 6626/* File: arm64/op_iput_quick.S */ 6627 /* For: iput-quick, iput-object-quick */ 6628 /* op vA, vB, offset//CCCC */ 6629 lsr w2, wINST, #12 // w2<- B 6630 FETCH w1, 1 // w1<- field byte offset 6631 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6632 ubfx w2, wINST, #8, #4 // w2<- A 6633 cmp w3, #0 // check object for null 6634 cbz w3, common_errNullObject // object was null 6635 GET_VREG w0, w2 // w0<- fp[A] 6636 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6637 strb w0, [x3, x1] // obj.field<- w0 6638 GET_INST_OPCODE ip // extract opcode from rINST 6639 GOTO_OPCODE ip // jump to next instruction 6640 6641 6642/* ------------------------------ */ 6643 .balign 128 6644.L_op_iput_byte_quick: /* 0xec */ 6645/* File: arm64/op_iput_byte_quick.S */ 6646/* File: arm64/op_iput_quick.S */ 6647 /* For: iput-quick, iput-object-quick */ 6648 /* op vA, vB, offset//CCCC */ 6649 lsr w2, wINST, #12 // w2<- B 6650 FETCH w1, 1 // w1<- field byte offset 6651 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6652 ubfx w2, wINST, #8, #4 // w2<- A 6653 cmp w3, #0 // check object for null 6654 cbz w3, common_errNullObject // object was null 6655 GET_VREG w0, w2 // w0<- fp[A] 6656 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6657 strb w0, [x3, x1] // obj.field<- w0 6658 GET_INST_OPCODE ip // extract opcode from rINST 6659 GOTO_OPCODE ip // jump to next instruction 6660 6661 6662/* ------------------------------ */ 6663 .balign 128 6664.L_op_iput_char_quick: /* 0xed */ 6665/* File: arm64/op_iput_char_quick.S */ 6666/* File: arm64/op_iput_quick.S */ 6667 /* For: iput-quick, iput-object-quick */ 6668 /* op vA, vB, offset//CCCC */ 6669 lsr w2, wINST, #12 // w2<- B 6670 FETCH w1, 1 // w1<- field byte offset 6671 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6672 ubfx w2, wINST, #8, #4 // w2<- A 6673 cmp w3, #0 // check object for null 6674 cbz w3, common_errNullObject // object was null 6675 GET_VREG w0, w2 // w0<- fp[A] 6676 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6677 strh w0, [x3, x1] // obj.field<- w0 6678 GET_INST_OPCODE ip // extract opcode from rINST 6679 GOTO_OPCODE ip // jump to next instruction 6680 6681 6682/* ------------------------------ */ 6683 .balign 128 6684.L_op_iput_short_quick: /* 0xee */ 6685/* File: arm64/op_iput_short_quick.S */ 6686/* File: arm64/op_iput_quick.S */ 6687 /* For: iput-quick, iput-object-quick */ 6688 /* op vA, vB, offset//CCCC */ 6689 lsr w2, wINST, #12 // w2<- B 6690 FETCH w1, 1 // w1<- field byte offset 6691 GET_VREG w3, w2 // w3<- fp[B], the object pointer 6692 ubfx w2, wINST, #8, #4 // w2<- A 6693 cmp w3, #0 // check object for null 6694 cbz w3, common_errNullObject // object was null 6695 GET_VREG w0, w2 // w0<- fp[A] 6696 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6697 strh w0, [x3, x1] // obj.field<- w0 6698 GET_INST_OPCODE ip // extract opcode from rINST 6699 GOTO_OPCODE ip // jump to next instruction 6700 6701 6702/* ------------------------------ */ 6703 .balign 128 6704.L_op_iget_boolean_quick: /* 0xef */ 6705/* File: arm64/op_iget_boolean_quick.S */ 6706/* File: arm64/op_iget_quick.S */ 6707 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6708 /* op vA, vB, offset//CCCC */ 6709 lsr w2, wINST, #12 // w2<- B 6710 FETCH w1, 1 // w1<- field byte offset 6711 GET_VREG w3, w2 // w3<- object we're operating on 6712 ubfx w2, wINST, #8, #4 // w2<- A 6713 cmp x3, #0 // check object for null 6714 beq common_errNullObject // object was null 6715 ldrb w0, [x3, x1] // w0<- obj.field 6716 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6717 6718 SET_VREG w0, w2 // fp[A]<- w0 6719 GET_INST_OPCODE ip // extract opcode from rINST 6720 GOTO_OPCODE ip // jump to next instruction 6721 6722 6723/* ------------------------------ */ 6724 .balign 128 6725.L_op_iget_byte_quick: /* 0xf0 */ 6726/* File: arm64/op_iget_byte_quick.S */ 6727/* File: arm64/op_iget_quick.S */ 6728 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6729 /* op vA, vB, offset//CCCC */ 6730 lsr w2, wINST, #12 // w2<- B 6731 FETCH w1, 1 // w1<- field byte offset 6732 GET_VREG w3, w2 // w3<- object we're operating on 6733 ubfx w2, wINST, #8, #4 // w2<- A 6734 cmp x3, #0 // check object for null 6735 beq common_errNullObject // object was null 6736 ldrsb w0, [x3, x1] // w0<- obj.field 6737 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6738 6739 SET_VREG w0, w2 // fp[A]<- w0 6740 GET_INST_OPCODE ip // extract opcode from rINST 6741 GOTO_OPCODE ip // jump to next instruction 6742 6743 6744/* ------------------------------ */ 6745 .balign 128 6746.L_op_iget_char_quick: /* 0xf1 */ 6747/* File: arm64/op_iget_char_quick.S */ 6748/* File: arm64/op_iget_quick.S */ 6749 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6750 /* op vA, vB, offset//CCCC */ 6751 lsr w2, wINST, #12 // w2<- B 6752 FETCH w1, 1 // w1<- field byte offset 6753 GET_VREG w3, w2 // w3<- object we're operating on 6754 ubfx w2, wINST, #8, #4 // w2<- A 6755 cmp x3, #0 // check object for null 6756 beq common_errNullObject // object was null 6757 ldrh w0, [x3, x1] // w0<- obj.field 6758 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6759 6760 SET_VREG w0, w2 // fp[A]<- w0 6761 GET_INST_OPCODE ip // extract opcode from rINST 6762 GOTO_OPCODE ip // jump to next instruction 6763 6764 6765/* ------------------------------ */ 6766 .balign 128 6767.L_op_iget_short_quick: /* 0xf2 */ 6768/* File: arm64/op_iget_short_quick.S */ 6769/* File: arm64/op_iget_quick.S */ 6770 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6771 /* op vA, vB, offset//CCCC */ 6772 lsr w2, wINST, #12 // w2<- B 6773 FETCH w1, 1 // w1<- field byte offset 6774 GET_VREG w3, w2 // w3<- object we're operating on 6775 ubfx w2, wINST, #8, #4 // w2<- A 6776 cmp x3, #0 // check object for null 6777 beq common_errNullObject // object was null 6778 ldrsh w0, [x3, x1] // w0<- obj.field 6779 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 6780 6781 SET_VREG w0, w2 // fp[A]<- w0 6782 GET_INST_OPCODE ip // extract opcode from rINST 6783 GOTO_OPCODE ip // jump to next instruction 6784 6785 6786/* ------------------------------ */ 6787 .balign 128 6788.L_op_invoke_lambda: /* 0xf3 */ 6789/* Transfer stub to alternate interpreter */ 6790 b MterpFallback 6791 6792 6793/* ------------------------------ */ 6794 .balign 128 6795.L_op_unused_f4: /* 0xf4 */ 6796/* File: arm64/op_unused_f4.S */ 6797/* File: arm64/unused.S */ 6798/* 6799 * Bail to reference interpreter to throw. 6800 */ 6801 b MterpFallback 6802 6803 6804/* ------------------------------ */ 6805 .balign 128 6806.L_op_capture_variable: /* 0xf5 */ 6807/* Transfer stub to alternate interpreter */ 6808 b MterpFallback 6809 6810 6811/* ------------------------------ */ 6812 .balign 128 6813.L_op_create_lambda: /* 0xf6 */ 6814/* Transfer stub to alternate interpreter */ 6815 b MterpFallback 6816 6817 6818/* ------------------------------ */ 6819 .balign 128 6820.L_op_liberate_variable: /* 0xf7 */ 6821/* Transfer stub to alternate interpreter */ 6822 b MterpFallback 6823 6824 6825/* ------------------------------ */ 6826 .balign 128 6827.L_op_box_lambda: /* 0xf8 */ 6828/* Transfer stub to alternate interpreter */ 6829 b MterpFallback 6830 6831 6832/* ------------------------------ */ 6833 .balign 128 6834.L_op_unbox_lambda: /* 0xf9 */ 6835/* Transfer stub to alternate interpreter */ 6836 b MterpFallback 6837 6838 6839/* ------------------------------ */ 6840 .balign 128 6841.L_op_unused_fa: /* 0xfa */ 6842/* File: arm64/op_unused_fa.S */ 6843/* File: arm64/unused.S */ 6844/* 6845 * Bail to reference interpreter to throw. 6846 */ 6847 b MterpFallback 6848 6849 6850/* ------------------------------ */ 6851 .balign 128 6852.L_op_unused_fb: /* 0xfb */ 6853/* File: arm64/op_unused_fb.S */ 6854/* File: arm64/unused.S */ 6855/* 6856 * Bail to reference interpreter to throw. 6857 */ 6858 b MterpFallback 6859 6860 6861/* ------------------------------ */ 6862 .balign 128 6863.L_op_unused_fc: /* 0xfc */ 6864/* File: arm64/op_unused_fc.S */ 6865/* File: arm64/unused.S */ 6866/* 6867 * Bail to reference interpreter to throw. 6868 */ 6869 b MterpFallback 6870 6871 6872/* ------------------------------ */ 6873 .balign 128 6874.L_op_unused_fd: /* 0xfd */ 6875/* File: arm64/op_unused_fd.S */ 6876/* File: arm64/unused.S */ 6877/* 6878 * Bail to reference interpreter to throw. 6879 */ 6880 b MterpFallback 6881 6882 6883/* ------------------------------ */ 6884 .balign 128 6885.L_op_unused_fe: /* 0xfe */ 6886/* File: arm64/op_unused_fe.S */ 6887/* File: arm64/unused.S */ 6888/* 6889 * Bail to reference interpreter to throw. 6890 */ 6891 b MterpFallback 6892 6893 6894/* ------------------------------ */ 6895 .balign 128 6896.L_op_unused_ff: /* 0xff */ 6897/* File: arm64/op_unused_ff.S */ 6898/* File: arm64/unused.S */ 6899/* 6900 * Bail to reference interpreter to throw. 6901 */ 6902 b MterpFallback 6903 6904 6905 .balign 128 6906 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 6907 .global artMterpAsmInstructionEnd 6908artMterpAsmInstructionEnd: 6909 6910/* 6911 * =========================================================================== 6912 * Sister implementations 6913 * =========================================================================== 6914 */ 6915 .global artMterpAsmSisterStart 6916 .type artMterpAsmSisterStart, %function 6917 .text 6918 .balign 4 6919artMterpAsmSisterStart: 6920 6921 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 6922 .global artMterpAsmSisterEnd 6923artMterpAsmSisterEnd: 6924 6925 6926 .global artMterpAsmAltInstructionStart 6927 .type artMterpAsmAltInstructionStart, %function 6928 .text 6929 6930artMterpAsmAltInstructionStart = .L_ALT_op_nop 6931/* ------------------------------ */ 6932 .balign 128 6933.L_ALT_op_nop: /* 0x00 */ 6934/* File: arm64/alt_stub.S */ 6935/* 6936 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 6937 * any interesting requests and then jump to the real instruction 6938 * handler. Note that the call to MterpCheckBefore is done as a tail call. 6939 */ 6940 .extern MterpCheckBefore 6941 EXPORT_PC 6942 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 6943 adr lr, artMterpAsmInstructionStart + (0 * 128) // Addr of primary handler. 6944 mov x0, xSELF 6945 add x1, xFP, #OFF_FP_SHADOWFRAME 6946 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 6947 6948/* ------------------------------ */ 6949 .balign 128 6950.L_ALT_op_move: /* 0x01 */ 6951/* File: arm64/alt_stub.S */ 6952/* 6953 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 6954 * any interesting requests and then jump to the real instruction 6955 * handler. Note that the call to MterpCheckBefore is done as a tail call. 6956 */ 6957 .extern MterpCheckBefore 6958 EXPORT_PC 6959 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 6960 adr lr, artMterpAsmInstructionStart + (1 * 128) // Addr of primary handler. 6961 mov x0, xSELF 6962 add x1, xFP, #OFF_FP_SHADOWFRAME 6963 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 6964 6965/* ------------------------------ */ 6966 .balign 128 6967.L_ALT_op_move_from16: /* 0x02 */ 6968/* File: arm64/alt_stub.S */ 6969/* 6970 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 6971 * any interesting requests and then jump to the real instruction 6972 * handler. Note that the call to MterpCheckBefore is done as a tail call. 6973 */ 6974 .extern MterpCheckBefore 6975 EXPORT_PC 6976 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 6977 adr lr, artMterpAsmInstructionStart + (2 * 128) // Addr of primary handler. 6978 mov x0, xSELF 6979 add x1, xFP, #OFF_FP_SHADOWFRAME 6980 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 6981 6982/* ------------------------------ */ 6983 .balign 128 6984.L_ALT_op_move_16: /* 0x03 */ 6985/* File: arm64/alt_stub.S */ 6986/* 6987 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 6988 * any interesting requests and then jump to the real instruction 6989 * handler. Note that the call to MterpCheckBefore is done as a tail call. 6990 */ 6991 .extern MterpCheckBefore 6992 EXPORT_PC 6993 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 6994 adr lr, artMterpAsmInstructionStart + (3 * 128) // Addr of primary handler. 6995 mov x0, xSELF 6996 add x1, xFP, #OFF_FP_SHADOWFRAME 6997 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 6998 6999/* ------------------------------ */ 7000 .balign 128 7001.L_ALT_op_move_wide: /* 0x04 */ 7002/* File: arm64/alt_stub.S */ 7003/* 7004 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7005 * any interesting requests and then jump to the real instruction 7006 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7007 */ 7008 .extern MterpCheckBefore 7009 EXPORT_PC 7010 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7011 adr lr, artMterpAsmInstructionStart + (4 * 128) // Addr of primary handler. 7012 mov x0, xSELF 7013 add x1, xFP, #OFF_FP_SHADOWFRAME 7014 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7015 7016/* ------------------------------ */ 7017 .balign 128 7018.L_ALT_op_move_wide_from16: /* 0x05 */ 7019/* File: arm64/alt_stub.S */ 7020/* 7021 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7022 * any interesting requests and then jump to the real instruction 7023 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7024 */ 7025 .extern MterpCheckBefore 7026 EXPORT_PC 7027 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7028 adr lr, artMterpAsmInstructionStart + (5 * 128) // Addr of primary handler. 7029 mov x0, xSELF 7030 add x1, xFP, #OFF_FP_SHADOWFRAME 7031 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7032 7033/* ------------------------------ */ 7034 .balign 128 7035.L_ALT_op_move_wide_16: /* 0x06 */ 7036/* File: arm64/alt_stub.S */ 7037/* 7038 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7039 * any interesting requests and then jump to the real instruction 7040 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7041 */ 7042 .extern MterpCheckBefore 7043 EXPORT_PC 7044 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7045 adr lr, artMterpAsmInstructionStart + (6 * 128) // Addr of primary handler. 7046 mov x0, xSELF 7047 add x1, xFP, #OFF_FP_SHADOWFRAME 7048 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7049 7050/* ------------------------------ */ 7051 .balign 128 7052.L_ALT_op_move_object: /* 0x07 */ 7053/* File: arm64/alt_stub.S */ 7054/* 7055 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7056 * any interesting requests and then jump to the real instruction 7057 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7058 */ 7059 .extern MterpCheckBefore 7060 EXPORT_PC 7061 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7062 adr lr, artMterpAsmInstructionStart + (7 * 128) // Addr of primary handler. 7063 mov x0, xSELF 7064 add x1, xFP, #OFF_FP_SHADOWFRAME 7065 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7066 7067/* ------------------------------ */ 7068 .balign 128 7069.L_ALT_op_move_object_from16: /* 0x08 */ 7070/* File: arm64/alt_stub.S */ 7071/* 7072 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7073 * any interesting requests and then jump to the real instruction 7074 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7075 */ 7076 .extern MterpCheckBefore 7077 EXPORT_PC 7078 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7079 adr lr, artMterpAsmInstructionStart + (8 * 128) // Addr of primary handler. 7080 mov x0, xSELF 7081 add x1, xFP, #OFF_FP_SHADOWFRAME 7082 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7083 7084/* ------------------------------ */ 7085 .balign 128 7086.L_ALT_op_move_object_16: /* 0x09 */ 7087/* File: arm64/alt_stub.S */ 7088/* 7089 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7090 * any interesting requests and then jump to the real instruction 7091 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7092 */ 7093 .extern MterpCheckBefore 7094 EXPORT_PC 7095 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7096 adr lr, artMterpAsmInstructionStart + (9 * 128) // Addr of primary handler. 7097 mov x0, xSELF 7098 add x1, xFP, #OFF_FP_SHADOWFRAME 7099 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7100 7101/* ------------------------------ */ 7102 .balign 128 7103.L_ALT_op_move_result: /* 0x0a */ 7104/* File: arm64/alt_stub.S */ 7105/* 7106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7107 * any interesting requests and then jump to the real instruction 7108 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7109 */ 7110 .extern MterpCheckBefore 7111 EXPORT_PC 7112 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7113 adr lr, artMterpAsmInstructionStart + (10 * 128) // Addr of primary handler. 7114 mov x0, xSELF 7115 add x1, xFP, #OFF_FP_SHADOWFRAME 7116 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7117 7118/* ------------------------------ */ 7119 .balign 128 7120.L_ALT_op_move_result_wide: /* 0x0b */ 7121/* File: arm64/alt_stub.S */ 7122/* 7123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7124 * any interesting requests and then jump to the real instruction 7125 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7126 */ 7127 .extern MterpCheckBefore 7128 EXPORT_PC 7129 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7130 adr lr, artMterpAsmInstructionStart + (11 * 128) // Addr of primary handler. 7131 mov x0, xSELF 7132 add x1, xFP, #OFF_FP_SHADOWFRAME 7133 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7134 7135/* ------------------------------ */ 7136 .balign 128 7137.L_ALT_op_move_result_object: /* 0x0c */ 7138/* File: arm64/alt_stub.S */ 7139/* 7140 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7141 * any interesting requests and then jump to the real instruction 7142 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7143 */ 7144 .extern MterpCheckBefore 7145 EXPORT_PC 7146 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7147 adr lr, artMterpAsmInstructionStart + (12 * 128) // Addr of primary handler. 7148 mov x0, xSELF 7149 add x1, xFP, #OFF_FP_SHADOWFRAME 7150 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7151 7152/* ------------------------------ */ 7153 .balign 128 7154.L_ALT_op_move_exception: /* 0x0d */ 7155/* File: arm64/alt_stub.S */ 7156/* 7157 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7158 * any interesting requests and then jump to the real instruction 7159 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7160 */ 7161 .extern MterpCheckBefore 7162 EXPORT_PC 7163 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7164 adr lr, artMterpAsmInstructionStart + (13 * 128) // Addr of primary handler. 7165 mov x0, xSELF 7166 add x1, xFP, #OFF_FP_SHADOWFRAME 7167 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7168 7169/* ------------------------------ */ 7170 .balign 128 7171.L_ALT_op_return_void: /* 0x0e */ 7172/* File: arm64/alt_stub.S */ 7173/* 7174 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7175 * any interesting requests and then jump to the real instruction 7176 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7177 */ 7178 .extern MterpCheckBefore 7179 EXPORT_PC 7180 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7181 adr lr, artMterpAsmInstructionStart + (14 * 128) // Addr of primary handler. 7182 mov x0, xSELF 7183 add x1, xFP, #OFF_FP_SHADOWFRAME 7184 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7185 7186/* ------------------------------ */ 7187 .balign 128 7188.L_ALT_op_return: /* 0x0f */ 7189/* File: arm64/alt_stub.S */ 7190/* 7191 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7192 * any interesting requests and then jump to the real instruction 7193 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7194 */ 7195 .extern MterpCheckBefore 7196 EXPORT_PC 7197 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7198 adr lr, artMterpAsmInstructionStart + (15 * 128) // Addr of primary handler. 7199 mov x0, xSELF 7200 add x1, xFP, #OFF_FP_SHADOWFRAME 7201 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7202 7203/* ------------------------------ */ 7204 .balign 128 7205.L_ALT_op_return_wide: /* 0x10 */ 7206/* File: arm64/alt_stub.S */ 7207/* 7208 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7209 * any interesting requests and then jump to the real instruction 7210 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7211 */ 7212 .extern MterpCheckBefore 7213 EXPORT_PC 7214 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7215 adr lr, artMterpAsmInstructionStart + (16 * 128) // Addr of primary handler. 7216 mov x0, xSELF 7217 add x1, xFP, #OFF_FP_SHADOWFRAME 7218 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7219 7220/* ------------------------------ */ 7221 .balign 128 7222.L_ALT_op_return_object: /* 0x11 */ 7223/* File: arm64/alt_stub.S */ 7224/* 7225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7226 * any interesting requests and then jump to the real instruction 7227 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7228 */ 7229 .extern MterpCheckBefore 7230 EXPORT_PC 7231 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7232 adr lr, artMterpAsmInstructionStart + (17 * 128) // Addr of primary handler. 7233 mov x0, xSELF 7234 add x1, xFP, #OFF_FP_SHADOWFRAME 7235 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7236 7237/* ------------------------------ */ 7238 .balign 128 7239.L_ALT_op_const_4: /* 0x12 */ 7240/* File: arm64/alt_stub.S */ 7241/* 7242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7243 * any interesting requests and then jump to the real instruction 7244 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7245 */ 7246 .extern MterpCheckBefore 7247 EXPORT_PC 7248 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7249 adr lr, artMterpAsmInstructionStart + (18 * 128) // Addr of primary handler. 7250 mov x0, xSELF 7251 add x1, xFP, #OFF_FP_SHADOWFRAME 7252 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7253 7254/* ------------------------------ */ 7255 .balign 128 7256.L_ALT_op_const_16: /* 0x13 */ 7257/* File: arm64/alt_stub.S */ 7258/* 7259 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7260 * any interesting requests and then jump to the real instruction 7261 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7262 */ 7263 .extern MterpCheckBefore 7264 EXPORT_PC 7265 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7266 adr lr, artMterpAsmInstructionStart + (19 * 128) // Addr of primary handler. 7267 mov x0, xSELF 7268 add x1, xFP, #OFF_FP_SHADOWFRAME 7269 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7270 7271/* ------------------------------ */ 7272 .balign 128 7273.L_ALT_op_const: /* 0x14 */ 7274/* File: arm64/alt_stub.S */ 7275/* 7276 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7277 * any interesting requests and then jump to the real instruction 7278 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7279 */ 7280 .extern MterpCheckBefore 7281 EXPORT_PC 7282 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7283 adr lr, artMterpAsmInstructionStart + (20 * 128) // Addr of primary handler. 7284 mov x0, xSELF 7285 add x1, xFP, #OFF_FP_SHADOWFRAME 7286 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7287 7288/* ------------------------------ */ 7289 .balign 128 7290.L_ALT_op_const_high16: /* 0x15 */ 7291/* File: arm64/alt_stub.S */ 7292/* 7293 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7294 * any interesting requests and then jump to the real instruction 7295 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7296 */ 7297 .extern MterpCheckBefore 7298 EXPORT_PC 7299 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7300 adr lr, artMterpAsmInstructionStart + (21 * 128) // Addr of primary handler. 7301 mov x0, xSELF 7302 add x1, xFP, #OFF_FP_SHADOWFRAME 7303 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7304 7305/* ------------------------------ */ 7306 .balign 128 7307.L_ALT_op_const_wide_16: /* 0x16 */ 7308/* File: arm64/alt_stub.S */ 7309/* 7310 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7311 * any interesting requests and then jump to the real instruction 7312 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7313 */ 7314 .extern MterpCheckBefore 7315 EXPORT_PC 7316 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7317 adr lr, artMterpAsmInstructionStart + (22 * 128) // Addr of primary handler. 7318 mov x0, xSELF 7319 add x1, xFP, #OFF_FP_SHADOWFRAME 7320 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7321 7322/* ------------------------------ */ 7323 .balign 128 7324.L_ALT_op_const_wide_32: /* 0x17 */ 7325/* File: arm64/alt_stub.S */ 7326/* 7327 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7328 * any interesting requests and then jump to the real instruction 7329 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7330 */ 7331 .extern MterpCheckBefore 7332 EXPORT_PC 7333 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7334 adr lr, artMterpAsmInstructionStart + (23 * 128) // Addr of primary handler. 7335 mov x0, xSELF 7336 add x1, xFP, #OFF_FP_SHADOWFRAME 7337 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7338 7339/* ------------------------------ */ 7340 .balign 128 7341.L_ALT_op_const_wide: /* 0x18 */ 7342/* File: arm64/alt_stub.S */ 7343/* 7344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7345 * any interesting requests and then jump to the real instruction 7346 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7347 */ 7348 .extern MterpCheckBefore 7349 EXPORT_PC 7350 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7351 adr lr, artMterpAsmInstructionStart + (24 * 128) // Addr of primary handler. 7352 mov x0, xSELF 7353 add x1, xFP, #OFF_FP_SHADOWFRAME 7354 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7355 7356/* ------------------------------ */ 7357 .balign 128 7358.L_ALT_op_const_wide_high16: /* 0x19 */ 7359/* File: arm64/alt_stub.S */ 7360/* 7361 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7362 * any interesting requests and then jump to the real instruction 7363 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7364 */ 7365 .extern MterpCheckBefore 7366 EXPORT_PC 7367 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7368 adr lr, artMterpAsmInstructionStart + (25 * 128) // Addr of primary handler. 7369 mov x0, xSELF 7370 add x1, xFP, #OFF_FP_SHADOWFRAME 7371 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7372 7373/* ------------------------------ */ 7374 .balign 128 7375.L_ALT_op_const_string: /* 0x1a */ 7376/* File: arm64/alt_stub.S */ 7377/* 7378 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7379 * any interesting requests and then jump to the real instruction 7380 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7381 */ 7382 .extern MterpCheckBefore 7383 EXPORT_PC 7384 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7385 adr lr, artMterpAsmInstructionStart + (26 * 128) // Addr of primary handler. 7386 mov x0, xSELF 7387 add x1, xFP, #OFF_FP_SHADOWFRAME 7388 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7389 7390/* ------------------------------ */ 7391 .balign 128 7392.L_ALT_op_const_string_jumbo: /* 0x1b */ 7393/* File: arm64/alt_stub.S */ 7394/* 7395 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7396 * any interesting requests and then jump to the real instruction 7397 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7398 */ 7399 .extern MterpCheckBefore 7400 EXPORT_PC 7401 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7402 adr lr, artMterpAsmInstructionStart + (27 * 128) // Addr of primary handler. 7403 mov x0, xSELF 7404 add x1, xFP, #OFF_FP_SHADOWFRAME 7405 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7406 7407/* ------------------------------ */ 7408 .balign 128 7409.L_ALT_op_const_class: /* 0x1c */ 7410/* File: arm64/alt_stub.S */ 7411/* 7412 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7413 * any interesting requests and then jump to the real instruction 7414 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7415 */ 7416 .extern MterpCheckBefore 7417 EXPORT_PC 7418 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7419 adr lr, artMterpAsmInstructionStart + (28 * 128) // Addr of primary handler. 7420 mov x0, xSELF 7421 add x1, xFP, #OFF_FP_SHADOWFRAME 7422 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7423 7424/* ------------------------------ */ 7425 .balign 128 7426.L_ALT_op_monitor_enter: /* 0x1d */ 7427/* File: arm64/alt_stub.S */ 7428/* 7429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7430 * any interesting requests and then jump to the real instruction 7431 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7432 */ 7433 .extern MterpCheckBefore 7434 EXPORT_PC 7435 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7436 adr lr, artMterpAsmInstructionStart + (29 * 128) // Addr of primary handler. 7437 mov x0, xSELF 7438 add x1, xFP, #OFF_FP_SHADOWFRAME 7439 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7440 7441/* ------------------------------ */ 7442 .balign 128 7443.L_ALT_op_monitor_exit: /* 0x1e */ 7444/* File: arm64/alt_stub.S */ 7445/* 7446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7447 * any interesting requests and then jump to the real instruction 7448 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7449 */ 7450 .extern MterpCheckBefore 7451 EXPORT_PC 7452 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7453 adr lr, artMterpAsmInstructionStart + (30 * 128) // Addr of primary handler. 7454 mov x0, xSELF 7455 add x1, xFP, #OFF_FP_SHADOWFRAME 7456 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7457 7458/* ------------------------------ */ 7459 .balign 128 7460.L_ALT_op_check_cast: /* 0x1f */ 7461/* File: arm64/alt_stub.S */ 7462/* 7463 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7464 * any interesting requests and then jump to the real instruction 7465 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7466 */ 7467 .extern MterpCheckBefore 7468 EXPORT_PC 7469 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7470 adr lr, artMterpAsmInstructionStart + (31 * 128) // Addr of primary handler. 7471 mov x0, xSELF 7472 add x1, xFP, #OFF_FP_SHADOWFRAME 7473 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7474 7475/* ------------------------------ */ 7476 .balign 128 7477.L_ALT_op_instance_of: /* 0x20 */ 7478/* File: arm64/alt_stub.S */ 7479/* 7480 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7481 * any interesting requests and then jump to the real instruction 7482 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7483 */ 7484 .extern MterpCheckBefore 7485 EXPORT_PC 7486 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7487 adr lr, artMterpAsmInstructionStart + (32 * 128) // Addr of primary handler. 7488 mov x0, xSELF 7489 add x1, xFP, #OFF_FP_SHADOWFRAME 7490 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7491 7492/* ------------------------------ */ 7493 .balign 128 7494.L_ALT_op_array_length: /* 0x21 */ 7495/* File: arm64/alt_stub.S */ 7496/* 7497 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7498 * any interesting requests and then jump to the real instruction 7499 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7500 */ 7501 .extern MterpCheckBefore 7502 EXPORT_PC 7503 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7504 adr lr, artMterpAsmInstructionStart + (33 * 128) // Addr of primary handler. 7505 mov x0, xSELF 7506 add x1, xFP, #OFF_FP_SHADOWFRAME 7507 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7508 7509/* ------------------------------ */ 7510 .balign 128 7511.L_ALT_op_new_instance: /* 0x22 */ 7512/* File: arm64/alt_stub.S */ 7513/* 7514 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7515 * any interesting requests and then jump to the real instruction 7516 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7517 */ 7518 .extern MterpCheckBefore 7519 EXPORT_PC 7520 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7521 adr lr, artMterpAsmInstructionStart + (34 * 128) // Addr of primary handler. 7522 mov x0, xSELF 7523 add x1, xFP, #OFF_FP_SHADOWFRAME 7524 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7525 7526/* ------------------------------ */ 7527 .balign 128 7528.L_ALT_op_new_array: /* 0x23 */ 7529/* File: arm64/alt_stub.S */ 7530/* 7531 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7532 * any interesting requests and then jump to the real instruction 7533 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7534 */ 7535 .extern MterpCheckBefore 7536 EXPORT_PC 7537 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7538 adr lr, artMterpAsmInstructionStart + (35 * 128) // Addr of primary handler. 7539 mov x0, xSELF 7540 add x1, xFP, #OFF_FP_SHADOWFRAME 7541 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7542 7543/* ------------------------------ */ 7544 .balign 128 7545.L_ALT_op_filled_new_array: /* 0x24 */ 7546/* File: arm64/alt_stub.S */ 7547/* 7548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7549 * any interesting requests and then jump to the real instruction 7550 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7551 */ 7552 .extern MterpCheckBefore 7553 EXPORT_PC 7554 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7555 adr lr, artMterpAsmInstructionStart + (36 * 128) // Addr of primary handler. 7556 mov x0, xSELF 7557 add x1, xFP, #OFF_FP_SHADOWFRAME 7558 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7559 7560/* ------------------------------ */ 7561 .balign 128 7562.L_ALT_op_filled_new_array_range: /* 0x25 */ 7563/* File: arm64/alt_stub.S */ 7564/* 7565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7566 * any interesting requests and then jump to the real instruction 7567 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7568 */ 7569 .extern MterpCheckBefore 7570 EXPORT_PC 7571 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7572 adr lr, artMterpAsmInstructionStart + (37 * 128) // Addr of primary handler. 7573 mov x0, xSELF 7574 add x1, xFP, #OFF_FP_SHADOWFRAME 7575 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7576 7577/* ------------------------------ */ 7578 .balign 128 7579.L_ALT_op_fill_array_data: /* 0x26 */ 7580/* File: arm64/alt_stub.S */ 7581/* 7582 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7583 * any interesting requests and then jump to the real instruction 7584 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7585 */ 7586 .extern MterpCheckBefore 7587 EXPORT_PC 7588 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7589 adr lr, artMterpAsmInstructionStart + (38 * 128) // Addr of primary handler. 7590 mov x0, xSELF 7591 add x1, xFP, #OFF_FP_SHADOWFRAME 7592 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7593 7594/* ------------------------------ */ 7595 .balign 128 7596.L_ALT_op_throw: /* 0x27 */ 7597/* File: arm64/alt_stub.S */ 7598/* 7599 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7600 * any interesting requests and then jump to the real instruction 7601 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7602 */ 7603 .extern MterpCheckBefore 7604 EXPORT_PC 7605 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7606 adr lr, artMterpAsmInstructionStart + (39 * 128) // Addr of primary handler. 7607 mov x0, xSELF 7608 add x1, xFP, #OFF_FP_SHADOWFRAME 7609 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7610 7611/* ------------------------------ */ 7612 .balign 128 7613.L_ALT_op_goto: /* 0x28 */ 7614/* File: arm64/alt_stub.S */ 7615/* 7616 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7617 * any interesting requests and then jump to the real instruction 7618 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7619 */ 7620 .extern MterpCheckBefore 7621 EXPORT_PC 7622 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7623 adr lr, artMterpAsmInstructionStart + (40 * 128) // Addr of primary handler. 7624 mov x0, xSELF 7625 add x1, xFP, #OFF_FP_SHADOWFRAME 7626 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7627 7628/* ------------------------------ */ 7629 .balign 128 7630.L_ALT_op_goto_16: /* 0x29 */ 7631/* File: arm64/alt_stub.S */ 7632/* 7633 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7634 * any interesting requests and then jump to the real instruction 7635 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7636 */ 7637 .extern MterpCheckBefore 7638 EXPORT_PC 7639 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7640 adr lr, artMterpAsmInstructionStart + (41 * 128) // Addr of primary handler. 7641 mov x0, xSELF 7642 add x1, xFP, #OFF_FP_SHADOWFRAME 7643 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7644 7645/* ------------------------------ */ 7646 .balign 128 7647.L_ALT_op_goto_32: /* 0x2a */ 7648/* File: arm64/alt_stub.S */ 7649/* 7650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7651 * any interesting requests and then jump to the real instruction 7652 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7653 */ 7654 .extern MterpCheckBefore 7655 EXPORT_PC 7656 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7657 adr lr, artMterpAsmInstructionStart + (42 * 128) // Addr of primary handler. 7658 mov x0, xSELF 7659 add x1, xFP, #OFF_FP_SHADOWFRAME 7660 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7661 7662/* ------------------------------ */ 7663 .balign 128 7664.L_ALT_op_packed_switch: /* 0x2b */ 7665/* File: arm64/alt_stub.S */ 7666/* 7667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7668 * any interesting requests and then jump to the real instruction 7669 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7670 */ 7671 .extern MterpCheckBefore 7672 EXPORT_PC 7673 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7674 adr lr, artMterpAsmInstructionStart + (43 * 128) // Addr of primary handler. 7675 mov x0, xSELF 7676 add x1, xFP, #OFF_FP_SHADOWFRAME 7677 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7678 7679/* ------------------------------ */ 7680 .balign 128 7681.L_ALT_op_sparse_switch: /* 0x2c */ 7682/* File: arm64/alt_stub.S */ 7683/* 7684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7685 * any interesting requests and then jump to the real instruction 7686 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7687 */ 7688 .extern MterpCheckBefore 7689 EXPORT_PC 7690 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7691 adr lr, artMterpAsmInstructionStart + (44 * 128) // Addr of primary handler. 7692 mov x0, xSELF 7693 add x1, xFP, #OFF_FP_SHADOWFRAME 7694 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7695 7696/* ------------------------------ */ 7697 .balign 128 7698.L_ALT_op_cmpl_float: /* 0x2d */ 7699/* File: arm64/alt_stub.S */ 7700/* 7701 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7702 * any interesting requests and then jump to the real instruction 7703 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7704 */ 7705 .extern MterpCheckBefore 7706 EXPORT_PC 7707 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7708 adr lr, artMterpAsmInstructionStart + (45 * 128) // Addr of primary handler. 7709 mov x0, xSELF 7710 add x1, xFP, #OFF_FP_SHADOWFRAME 7711 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7712 7713/* ------------------------------ */ 7714 .balign 128 7715.L_ALT_op_cmpg_float: /* 0x2e */ 7716/* File: arm64/alt_stub.S */ 7717/* 7718 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7719 * any interesting requests and then jump to the real instruction 7720 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7721 */ 7722 .extern MterpCheckBefore 7723 EXPORT_PC 7724 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7725 adr lr, artMterpAsmInstructionStart + (46 * 128) // Addr of primary handler. 7726 mov x0, xSELF 7727 add x1, xFP, #OFF_FP_SHADOWFRAME 7728 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7729 7730/* ------------------------------ */ 7731 .balign 128 7732.L_ALT_op_cmpl_double: /* 0x2f */ 7733/* File: arm64/alt_stub.S */ 7734/* 7735 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7736 * any interesting requests and then jump to the real instruction 7737 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7738 */ 7739 .extern MterpCheckBefore 7740 EXPORT_PC 7741 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7742 adr lr, artMterpAsmInstructionStart + (47 * 128) // Addr of primary handler. 7743 mov x0, xSELF 7744 add x1, xFP, #OFF_FP_SHADOWFRAME 7745 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7746 7747/* ------------------------------ */ 7748 .balign 128 7749.L_ALT_op_cmpg_double: /* 0x30 */ 7750/* File: arm64/alt_stub.S */ 7751/* 7752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7753 * any interesting requests and then jump to the real instruction 7754 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7755 */ 7756 .extern MterpCheckBefore 7757 EXPORT_PC 7758 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7759 adr lr, artMterpAsmInstructionStart + (48 * 128) // Addr of primary handler. 7760 mov x0, xSELF 7761 add x1, xFP, #OFF_FP_SHADOWFRAME 7762 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7763 7764/* ------------------------------ */ 7765 .balign 128 7766.L_ALT_op_cmp_long: /* 0x31 */ 7767/* File: arm64/alt_stub.S */ 7768/* 7769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7770 * any interesting requests and then jump to the real instruction 7771 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7772 */ 7773 .extern MterpCheckBefore 7774 EXPORT_PC 7775 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7776 adr lr, artMterpAsmInstructionStart + (49 * 128) // Addr of primary handler. 7777 mov x0, xSELF 7778 add x1, xFP, #OFF_FP_SHADOWFRAME 7779 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7780 7781/* ------------------------------ */ 7782 .balign 128 7783.L_ALT_op_if_eq: /* 0x32 */ 7784/* File: arm64/alt_stub.S */ 7785/* 7786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7787 * any interesting requests and then jump to the real instruction 7788 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7789 */ 7790 .extern MterpCheckBefore 7791 EXPORT_PC 7792 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7793 adr lr, artMterpAsmInstructionStart + (50 * 128) // Addr of primary handler. 7794 mov x0, xSELF 7795 add x1, xFP, #OFF_FP_SHADOWFRAME 7796 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7797 7798/* ------------------------------ */ 7799 .balign 128 7800.L_ALT_op_if_ne: /* 0x33 */ 7801/* File: arm64/alt_stub.S */ 7802/* 7803 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7804 * any interesting requests and then jump to the real instruction 7805 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7806 */ 7807 .extern MterpCheckBefore 7808 EXPORT_PC 7809 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7810 adr lr, artMterpAsmInstructionStart + (51 * 128) // Addr of primary handler. 7811 mov x0, xSELF 7812 add x1, xFP, #OFF_FP_SHADOWFRAME 7813 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7814 7815/* ------------------------------ */ 7816 .balign 128 7817.L_ALT_op_if_lt: /* 0x34 */ 7818/* File: arm64/alt_stub.S */ 7819/* 7820 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7821 * any interesting requests and then jump to the real instruction 7822 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7823 */ 7824 .extern MterpCheckBefore 7825 EXPORT_PC 7826 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7827 adr lr, artMterpAsmInstructionStart + (52 * 128) // Addr of primary handler. 7828 mov x0, xSELF 7829 add x1, xFP, #OFF_FP_SHADOWFRAME 7830 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7831 7832/* ------------------------------ */ 7833 .balign 128 7834.L_ALT_op_if_ge: /* 0x35 */ 7835/* File: arm64/alt_stub.S */ 7836/* 7837 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7838 * any interesting requests and then jump to the real instruction 7839 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7840 */ 7841 .extern MterpCheckBefore 7842 EXPORT_PC 7843 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7844 adr lr, artMterpAsmInstructionStart + (53 * 128) // Addr of primary handler. 7845 mov x0, xSELF 7846 add x1, xFP, #OFF_FP_SHADOWFRAME 7847 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7848 7849/* ------------------------------ */ 7850 .balign 128 7851.L_ALT_op_if_gt: /* 0x36 */ 7852/* File: arm64/alt_stub.S */ 7853/* 7854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7855 * any interesting requests and then jump to the real instruction 7856 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7857 */ 7858 .extern MterpCheckBefore 7859 EXPORT_PC 7860 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7861 adr lr, artMterpAsmInstructionStart + (54 * 128) // Addr of primary handler. 7862 mov x0, xSELF 7863 add x1, xFP, #OFF_FP_SHADOWFRAME 7864 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7865 7866/* ------------------------------ */ 7867 .balign 128 7868.L_ALT_op_if_le: /* 0x37 */ 7869/* File: arm64/alt_stub.S */ 7870/* 7871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7872 * any interesting requests and then jump to the real instruction 7873 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7874 */ 7875 .extern MterpCheckBefore 7876 EXPORT_PC 7877 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7878 adr lr, artMterpAsmInstructionStart + (55 * 128) // Addr of primary handler. 7879 mov x0, xSELF 7880 add x1, xFP, #OFF_FP_SHADOWFRAME 7881 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7882 7883/* ------------------------------ */ 7884 .balign 128 7885.L_ALT_op_if_eqz: /* 0x38 */ 7886/* File: arm64/alt_stub.S */ 7887/* 7888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7889 * any interesting requests and then jump to the real instruction 7890 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7891 */ 7892 .extern MterpCheckBefore 7893 EXPORT_PC 7894 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7895 adr lr, artMterpAsmInstructionStart + (56 * 128) // Addr of primary handler. 7896 mov x0, xSELF 7897 add x1, xFP, #OFF_FP_SHADOWFRAME 7898 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7899 7900/* ------------------------------ */ 7901 .balign 128 7902.L_ALT_op_if_nez: /* 0x39 */ 7903/* File: arm64/alt_stub.S */ 7904/* 7905 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7906 * any interesting requests and then jump to the real instruction 7907 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7908 */ 7909 .extern MterpCheckBefore 7910 EXPORT_PC 7911 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7912 adr lr, artMterpAsmInstructionStart + (57 * 128) // Addr of primary handler. 7913 mov x0, xSELF 7914 add x1, xFP, #OFF_FP_SHADOWFRAME 7915 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7916 7917/* ------------------------------ */ 7918 .balign 128 7919.L_ALT_op_if_ltz: /* 0x3a */ 7920/* File: arm64/alt_stub.S */ 7921/* 7922 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7923 * any interesting requests and then jump to the real instruction 7924 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7925 */ 7926 .extern MterpCheckBefore 7927 EXPORT_PC 7928 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7929 adr lr, artMterpAsmInstructionStart + (58 * 128) // Addr of primary handler. 7930 mov x0, xSELF 7931 add x1, xFP, #OFF_FP_SHADOWFRAME 7932 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7933 7934/* ------------------------------ */ 7935 .balign 128 7936.L_ALT_op_if_gez: /* 0x3b */ 7937/* File: arm64/alt_stub.S */ 7938/* 7939 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7940 * any interesting requests and then jump to the real instruction 7941 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7942 */ 7943 .extern MterpCheckBefore 7944 EXPORT_PC 7945 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7946 adr lr, artMterpAsmInstructionStart + (59 * 128) // Addr of primary handler. 7947 mov x0, xSELF 7948 add x1, xFP, #OFF_FP_SHADOWFRAME 7949 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7950 7951/* ------------------------------ */ 7952 .balign 128 7953.L_ALT_op_if_gtz: /* 0x3c */ 7954/* File: arm64/alt_stub.S */ 7955/* 7956 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7957 * any interesting requests and then jump to the real instruction 7958 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7959 */ 7960 .extern MterpCheckBefore 7961 EXPORT_PC 7962 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7963 adr lr, artMterpAsmInstructionStart + (60 * 128) // Addr of primary handler. 7964 mov x0, xSELF 7965 add x1, xFP, #OFF_FP_SHADOWFRAME 7966 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7967 7968/* ------------------------------ */ 7969 .balign 128 7970.L_ALT_op_if_lez: /* 0x3d */ 7971/* File: arm64/alt_stub.S */ 7972/* 7973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7974 * any interesting requests and then jump to the real instruction 7975 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7976 */ 7977 .extern MterpCheckBefore 7978 EXPORT_PC 7979 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7980 adr lr, artMterpAsmInstructionStart + (61 * 128) // Addr of primary handler. 7981 mov x0, xSELF 7982 add x1, xFP, #OFF_FP_SHADOWFRAME 7983 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 7984 7985/* ------------------------------ */ 7986 .balign 128 7987.L_ALT_op_unused_3e: /* 0x3e */ 7988/* File: arm64/alt_stub.S */ 7989/* 7990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7991 * any interesting requests and then jump to the real instruction 7992 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7993 */ 7994 .extern MterpCheckBefore 7995 EXPORT_PC 7996 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 7997 adr lr, artMterpAsmInstructionStart + (62 * 128) // Addr of primary handler. 7998 mov x0, xSELF 7999 add x1, xFP, #OFF_FP_SHADOWFRAME 8000 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8001 8002/* ------------------------------ */ 8003 .balign 128 8004.L_ALT_op_unused_3f: /* 0x3f */ 8005/* File: arm64/alt_stub.S */ 8006/* 8007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8008 * any interesting requests and then jump to the real instruction 8009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8010 */ 8011 .extern MterpCheckBefore 8012 EXPORT_PC 8013 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8014 adr lr, artMterpAsmInstructionStart + (63 * 128) // Addr of primary handler. 8015 mov x0, xSELF 8016 add x1, xFP, #OFF_FP_SHADOWFRAME 8017 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8018 8019/* ------------------------------ */ 8020 .balign 128 8021.L_ALT_op_unused_40: /* 0x40 */ 8022/* File: arm64/alt_stub.S */ 8023/* 8024 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8025 * any interesting requests and then jump to the real instruction 8026 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8027 */ 8028 .extern MterpCheckBefore 8029 EXPORT_PC 8030 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8031 adr lr, artMterpAsmInstructionStart + (64 * 128) // Addr of primary handler. 8032 mov x0, xSELF 8033 add x1, xFP, #OFF_FP_SHADOWFRAME 8034 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8035 8036/* ------------------------------ */ 8037 .balign 128 8038.L_ALT_op_unused_41: /* 0x41 */ 8039/* File: arm64/alt_stub.S */ 8040/* 8041 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8042 * any interesting requests and then jump to the real instruction 8043 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8044 */ 8045 .extern MterpCheckBefore 8046 EXPORT_PC 8047 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8048 adr lr, artMterpAsmInstructionStart + (65 * 128) // Addr of primary handler. 8049 mov x0, xSELF 8050 add x1, xFP, #OFF_FP_SHADOWFRAME 8051 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8052 8053/* ------------------------------ */ 8054 .balign 128 8055.L_ALT_op_unused_42: /* 0x42 */ 8056/* File: arm64/alt_stub.S */ 8057/* 8058 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8059 * any interesting requests and then jump to the real instruction 8060 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8061 */ 8062 .extern MterpCheckBefore 8063 EXPORT_PC 8064 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8065 adr lr, artMterpAsmInstructionStart + (66 * 128) // Addr of primary handler. 8066 mov x0, xSELF 8067 add x1, xFP, #OFF_FP_SHADOWFRAME 8068 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8069 8070/* ------------------------------ */ 8071 .balign 128 8072.L_ALT_op_unused_43: /* 0x43 */ 8073/* File: arm64/alt_stub.S */ 8074/* 8075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8076 * any interesting requests and then jump to the real instruction 8077 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8078 */ 8079 .extern MterpCheckBefore 8080 EXPORT_PC 8081 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8082 adr lr, artMterpAsmInstructionStart + (67 * 128) // Addr of primary handler. 8083 mov x0, xSELF 8084 add x1, xFP, #OFF_FP_SHADOWFRAME 8085 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8086 8087/* ------------------------------ */ 8088 .balign 128 8089.L_ALT_op_aget: /* 0x44 */ 8090/* File: arm64/alt_stub.S */ 8091/* 8092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8093 * any interesting requests and then jump to the real instruction 8094 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8095 */ 8096 .extern MterpCheckBefore 8097 EXPORT_PC 8098 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8099 adr lr, artMterpAsmInstructionStart + (68 * 128) // Addr of primary handler. 8100 mov x0, xSELF 8101 add x1, xFP, #OFF_FP_SHADOWFRAME 8102 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8103 8104/* ------------------------------ */ 8105 .balign 128 8106.L_ALT_op_aget_wide: /* 0x45 */ 8107/* File: arm64/alt_stub.S */ 8108/* 8109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8110 * any interesting requests and then jump to the real instruction 8111 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8112 */ 8113 .extern MterpCheckBefore 8114 EXPORT_PC 8115 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8116 adr lr, artMterpAsmInstructionStart + (69 * 128) // Addr of primary handler. 8117 mov x0, xSELF 8118 add x1, xFP, #OFF_FP_SHADOWFRAME 8119 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8120 8121/* ------------------------------ */ 8122 .balign 128 8123.L_ALT_op_aget_object: /* 0x46 */ 8124/* File: arm64/alt_stub.S */ 8125/* 8126 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8127 * any interesting requests and then jump to the real instruction 8128 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8129 */ 8130 .extern MterpCheckBefore 8131 EXPORT_PC 8132 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8133 adr lr, artMterpAsmInstructionStart + (70 * 128) // Addr of primary handler. 8134 mov x0, xSELF 8135 add x1, xFP, #OFF_FP_SHADOWFRAME 8136 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8137 8138/* ------------------------------ */ 8139 .balign 128 8140.L_ALT_op_aget_boolean: /* 0x47 */ 8141/* File: arm64/alt_stub.S */ 8142/* 8143 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8144 * any interesting requests and then jump to the real instruction 8145 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8146 */ 8147 .extern MterpCheckBefore 8148 EXPORT_PC 8149 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8150 adr lr, artMterpAsmInstructionStart + (71 * 128) // Addr of primary handler. 8151 mov x0, xSELF 8152 add x1, xFP, #OFF_FP_SHADOWFRAME 8153 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8154 8155/* ------------------------------ */ 8156 .balign 128 8157.L_ALT_op_aget_byte: /* 0x48 */ 8158/* File: arm64/alt_stub.S */ 8159/* 8160 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8161 * any interesting requests and then jump to the real instruction 8162 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8163 */ 8164 .extern MterpCheckBefore 8165 EXPORT_PC 8166 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8167 adr lr, artMterpAsmInstructionStart + (72 * 128) // Addr of primary handler. 8168 mov x0, xSELF 8169 add x1, xFP, #OFF_FP_SHADOWFRAME 8170 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8171 8172/* ------------------------------ */ 8173 .balign 128 8174.L_ALT_op_aget_char: /* 0x49 */ 8175/* File: arm64/alt_stub.S */ 8176/* 8177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8178 * any interesting requests and then jump to the real instruction 8179 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8180 */ 8181 .extern MterpCheckBefore 8182 EXPORT_PC 8183 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8184 adr lr, artMterpAsmInstructionStart + (73 * 128) // Addr of primary handler. 8185 mov x0, xSELF 8186 add x1, xFP, #OFF_FP_SHADOWFRAME 8187 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8188 8189/* ------------------------------ */ 8190 .balign 128 8191.L_ALT_op_aget_short: /* 0x4a */ 8192/* File: arm64/alt_stub.S */ 8193/* 8194 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8195 * any interesting requests and then jump to the real instruction 8196 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8197 */ 8198 .extern MterpCheckBefore 8199 EXPORT_PC 8200 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8201 adr lr, artMterpAsmInstructionStart + (74 * 128) // Addr of primary handler. 8202 mov x0, xSELF 8203 add x1, xFP, #OFF_FP_SHADOWFRAME 8204 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8205 8206/* ------------------------------ */ 8207 .balign 128 8208.L_ALT_op_aput: /* 0x4b */ 8209/* File: arm64/alt_stub.S */ 8210/* 8211 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8212 * any interesting requests and then jump to the real instruction 8213 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8214 */ 8215 .extern MterpCheckBefore 8216 EXPORT_PC 8217 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8218 adr lr, artMterpAsmInstructionStart + (75 * 128) // Addr of primary handler. 8219 mov x0, xSELF 8220 add x1, xFP, #OFF_FP_SHADOWFRAME 8221 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8222 8223/* ------------------------------ */ 8224 .balign 128 8225.L_ALT_op_aput_wide: /* 0x4c */ 8226/* File: arm64/alt_stub.S */ 8227/* 8228 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8229 * any interesting requests and then jump to the real instruction 8230 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8231 */ 8232 .extern MterpCheckBefore 8233 EXPORT_PC 8234 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8235 adr lr, artMterpAsmInstructionStart + (76 * 128) // Addr of primary handler. 8236 mov x0, xSELF 8237 add x1, xFP, #OFF_FP_SHADOWFRAME 8238 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8239 8240/* ------------------------------ */ 8241 .balign 128 8242.L_ALT_op_aput_object: /* 0x4d */ 8243/* File: arm64/alt_stub.S */ 8244/* 8245 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8246 * any interesting requests and then jump to the real instruction 8247 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8248 */ 8249 .extern MterpCheckBefore 8250 EXPORT_PC 8251 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8252 adr lr, artMterpAsmInstructionStart + (77 * 128) // Addr of primary handler. 8253 mov x0, xSELF 8254 add x1, xFP, #OFF_FP_SHADOWFRAME 8255 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8256 8257/* ------------------------------ */ 8258 .balign 128 8259.L_ALT_op_aput_boolean: /* 0x4e */ 8260/* File: arm64/alt_stub.S */ 8261/* 8262 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8263 * any interesting requests and then jump to the real instruction 8264 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8265 */ 8266 .extern MterpCheckBefore 8267 EXPORT_PC 8268 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8269 adr lr, artMterpAsmInstructionStart + (78 * 128) // Addr of primary handler. 8270 mov x0, xSELF 8271 add x1, xFP, #OFF_FP_SHADOWFRAME 8272 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8273 8274/* ------------------------------ */ 8275 .balign 128 8276.L_ALT_op_aput_byte: /* 0x4f */ 8277/* File: arm64/alt_stub.S */ 8278/* 8279 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8280 * any interesting requests and then jump to the real instruction 8281 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8282 */ 8283 .extern MterpCheckBefore 8284 EXPORT_PC 8285 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8286 adr lr, artMterpAsmInstructionStart + (79 * 128) // Addr of primary handler. 8287 mov x0, xSELF 8288 add x1, xFP, #OFF_FP_SHADOWFRAME 8289 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8290 8291/* ------------------------------ */ 8292 .balign 128 8293.L_ALT_op_aput_char: /* 0x50 */ 8294/* File: arm64/alt_stub.S */ 8295/* 8296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8297 * any interesting requests and then jump to the real instruction 8298 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8299 */ 8300 .extern MterpCheckBefore 8301 EXPORT_PC 8302 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8303 adr lr, artMterpAsmInstructionStart + (80 * 128) // Addr of primary handler. 8304 mov x0, xSELF 8305 add x1, xFP, #OFF_FP_SHADOWFRAME 8306 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8307 8308/* ------------------------------ */ 8309 .balign 128 8310.L_ALT_op_aput_short: /* 0x51 */ 8311/* File: arm64/alt_stub.S */ 8312/* 8313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8314 * any interesting requests and then jump to the real instruction 8315 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8316 */ 8317 .extern MterpCheckBefore 8318 EXPORT_PC 8319 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8320 adr lr, artMterpAsmInstructionStart + (81 * 128) // Addr of primary handler. 8321 mov x0, xSELF 8322 add x1, xFP, #OFF_FP_SHADOWFRAME 8323 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8324 8325/* ------------------------------ */ 8326 .balign 128 8327.L_ALT_op_iget: /* 0x52 */ 8328/* File: arm64/alt_stub.S */ 8329/* 8330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8331 * any interesting requests and then jump to the real instruction 8332 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8333 */ 8334 .extern MterpCheckBefore 8335 EXPORT_PC 8336 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8337 adr lr, artMterpAsmInstructionStart + (82 * 128) // Addr of primary handler. 8338 mov x0, xSELF 8339 add x1, xFP, #OFF_FP_SHADOWFRAME 8340 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8341 8342/* ------------------------------ */ 8343 .balign 128 8344.L_ALT_op_iget_wide: /* 0x53 */ 8345/* File: arm64/alt_stub.S */ 8346/* 8347 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8348 * any interesting requests and then jump to the real instruction 8349 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8350 */ 8351 .extern MterpCheckBefore 8352 EXPORT_PC 8353 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8354 adr lr, artMterpAsmInstructionStart + (83 * 128) // Addr of primary handler. 8355 mov x0, xSELF 8356 add x1, xFP, #OFF_FP_SHADOWFRAME 8357 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8358 8359/* ------------------------------ */ 8360 .balign 128 8361.L_ALT_op_iget_object: /* 0x54 */ 8362/* File: arm64/alt_stub.S */ 8363/* 8364 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8365 * any interesting requests and then jump to the real instruction 8366 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8367 */ 8368 .extern MterpCheckBefore 8369 EXPORT_PC 8370 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8371 adr lr, artMterpAsmInstructionStart + (84 * 128) // Addr of primary handler. 8372 mov x0, xSELF 8373 add x1, xFP, #OFF_FP_SHADOWFRAME 8374 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8375 8376/* ------------------------------ */ 8377 .balign 128 8378.L_ALT_op_iget_boolean: /* 0x55 */ 8379/* File: arm64/alt_stub.S */ 8380/* 8381 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8382 * any interesting requests and then jump to the real instruction 8383 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8384 */ 8385 .extern MterpCheckBefore 8386 EXPORT_PC 8387 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8388 adr lr, artMterpAsmInstructionStart + (85 * 128) // Addr of primary handler. 8389 mov x0, xSELF 8390 add x1, xFP, #OFF_FP_SHADOWFRAME 8391 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8392 8393/* ------------------------------ */ 8394 .balign 128 8395.L_ALT_op_iget_byte: /* 0x56 */ 8396/* File: arm64/alt_stub.S */ 8397/* 8398 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8399 * any interesting requests and then jump to the real instruction 8400 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8401 */ 8402 .extern MterpCheckBefore 8403 EXPORT_PC 8404 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8405 adr lr, artMterpAsmInstructionStart + (86 * 128) // Addr of primary handler. 8406 mov x0, xSELF 8407 add x1, xFP, #OFF_FP_SHADOWFRAME 8408 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8409 8410/* ------------------------------ */ 8411 .balign 128 8412.L_ALT_op_iget_char: /* 0x57 */ 8413/* File: arm64/alt_stub.S */ 8414/* 8415 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8416 * any interesting requests and then jump to the real instruction 8417 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8418 */ 8419 .extern MterpCheckBefore 8420 EXPORT_PC 8421 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8422 adr lr, artMterpAsmInstructionStart + (87 * 128) // Addr of primary handler. 8423 mov x0, xSELF 8424 add x1, xFP, #OFF_FP_SHADOWFRAME 8425 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8426 8427/* ------------------------------ */ 8428 .balign 128 8429.L_ALT_op_iget_short: /* 0x58 */ 8430/* File: arm64/alt_stub.S */ 8431/* 8432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8433 * any interesting requests and then jump to the real instruction 8434 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8435 */ 8436 .extern MterpCheckBefore 8437 EXPORT_PC 8438 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8439 adr lr, artMterpAsmInstructionStart + (88 * 128) // Addr of primary handler. 8440 mov x0, xSELF 8441 add x1, xFP, #OFF_FP_SHADOWFRAME 8442 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8443 8444/* ------------------------------ */ 8445 .balign 128 8446.L_ALT_op_iput: /* 0x59 */ 8447/* File: arm64/alt_stub.S */ 8448/* 8449 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8450 * any interesting requests and then jump to the real instruction 8451 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8452 */ 8453 .extern MterpCheckBefore 8454 EXPORT_PC 8455 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8456 adr lr, artMterpAsmInstructionStart + (89 * 128) // Addr of primary handler. 8457 mov x0, xSELF 8458 add x1, xFP, #OFF_FP_SHADOWFRAME 8459 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8460 8461/* ------------------------------ */ 8462 .balign 128 8463.L_ALT_op_iput_wide: /* 0x5a */ 8464/* File: arm64/alt_stub.S */ 8465/* 8466 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8467 * any interesting requests and then jump to the real instruction 8468 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8469 */ 8470 .extern MterpCheckBefore 8471 EXPORT_PC 8472 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8473 adr lr, artMterpAsmInstructionStart + (90 * 128) // Addr of primary handler. 8474 mov x0, xSELF 8475 add x1, xFP, #OFF_FP_SHADOWFRAME 8476 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8477 8478/* ------------------------------ */ 8479 .balign 128 8480.L_ALT_op_iput_object: /* 0x5b */ 8481/* File: arm64/alt_stub.S */ 8482/* 8483 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8484 * any interesting requests and then jump to the real instruction 8485 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8486 */ 8487 .extern MterpCheckBefore 8488 EXPORT_PC 8489 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8490 adr lr, artMterpAsmInstructionStart + (91 * 128) // Addr of primary handler. 8491 mov x0, xSELF 8492 add x1, xFP, #OFF_FP_SHADOWFRAME 8493 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8494 8495/* ------------------------------ */ 8496 .balign 128 8497.L_ALT_op_iput_boolean: /* 0x5c */ 8498/* File: arm64/alt_stub.S */ 8499/* 8500 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8501 * any interesting requests and then jump to the real instruction 8502 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8503 */ 8504 .extern MterpCheckBefore 8505 EXPORT_PC 8506 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8507 adr lr, artMterpAsmInstructionStart + (92 * 128) // Addr of primary handler. 8508 mov x0, xSELF 8509 add x1, xFP, #OFF_FP_SHADOWFRAME 8510 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8511 8512/* ------------------------------ */ 8513 .balign 128 8514.L_ALT_op_iput_byte: /* 0x5d */ 8515/* File: arm64/alt_stub.S */ 8516/* 8517 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8518 * any interesting requests and then jump to the real instruction 8519 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8520 */ 8521 .extern MterpCheckBefore 8522 EXPORT_PC 8523 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8524 adr lr, artMterpAsmInstructionStart + (93 * 128) // Addr of primary handler. 8525 mov x0, xSELF 8526 add x1, xFP, #OFF_FP_SHADOWFRAME 8527 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8528 8529/* ------------------------------ */ 8530 .balign 128 8531.L_ALT_op_iput_char: /* 0x5e */ 8532/* File: arm64/alt_stub.S */ 8533/* 8534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8535 * any interesting requests and then jump to the real instruction 8536 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8537 */ 8538 .extern MterpCheckBefore 8539 EXPORT_PC 8540 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8541 adr lr, artMterpAsmInstructionStart + (94 * 128) // Addr of primary handler. 8542 mov x0, xSELF 8543 add x1, xFP, #OFF_FP_SHADOWFRAME 8544 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8545 8546/* ------------------------------ */ 8547 .balign 128 8548.L_ALT_op_iput_short: /* 0x5f */ 8549/* File: arm64/alt_stub.S */ 8550/* 8551 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8552 * any interesting requests and then jump to the real instruction 8553 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8554 */ 8555 .extern MterpCheckBefore 8556 EXPORT_PC 8557 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8558 adr lr, artMterpAsmInstructionStart + (95 * 128) // Addr of primary handler. 8559 mov x0, xSELF 8560 add x1, xFP, #OFF_FP_SHADOWFRAME 8561 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8562 8563/* ------------------------------ */ 8564 .balign 128 8565.L_ALT_op_sget: /* 0x60 */ 8566/* File: arm64/alt_stub.S */ 8567/* 8568 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8569 * any interesting requests and then jump to the real instruction 8570 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8571 */ 8572 .extern MterpCheckBefore 8573 EXPORT_PC 8574 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8575 adr lr, artMterpAsmInstructionStart + (96 * 128) // Addr of primary handler. 8576 mov x0, xSELF 8577 add x1, xFP, #OFF_FP_SHADOWFRAME 8578 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8579 8580/* ------------------------------ */ 8581 .balign 128 8582.L_ALT_op_sget_wide: /* 0x61 */ 8583/* File: arm64/alt_stub.S */ 8584/* 8585 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8586 * any interesting requests and then jump to the real instruction 8587 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8588 */ 8589 .extern MterpCheckBefore 8590 EXPORT_PC 8591 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8592 adr lr, artMterpAsmInstructionStart + (97 * 128) // Addr of primary handler. 8593 mov x0, xSELF 8594 add x1, xFP, #OFF_FP_SHADOWFRAME 8595 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8596 8597/* ------------------------------ */ 8598 .balign 128 8599.L_ALT_op_sget_object: /* 0x62 */ 8600/* File: arm64/alt_stub.S */ 8601/* 8602 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8603 * any interesting requests and then jump to the real instruction 8604 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8605 */ 8606 .extern MterpCheckBefore 8607 EXPORT_PC 8608 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8609 adr lr, artMterpAsmInstructionStart + (98 * 128) // Addr of primary handler. 8610 mov x0, xSELF 8611 add x1, xFP, #OFF_FP_SHADOWFRAME 8612 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8613 8614/* ------------------------------ */ 8615 .balign 128 8616.L_ALT_op_sget_boolean: /* 0x63 */ 8617/* File: arm64/alt_stub.S */ 8618/* 8619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8620 * any interesting requests and then jump to the real instruction 8621 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8622 */ 8623 .extern MterpCheckBefore 8624 EXPORT_PC 8625 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8626 adr lr, artMterpAsmInstructionStart + (99 * 128) // Addr of primary handler. 8627 mov x0, xSELF 8628 add x1, xFP, #OFF_FP_SHADOWFRAME 8629 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8630 8631/* ------------------------------ */ 8632 .balign 128 8633.L_ALT_op_sget_byte: /* 0x64 */ 8634/* File: arm64/alt_stub.S */ 8635/* 8636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8637 * any interesting requests and then jump to the real instruction 8638 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8639 */ 8640 .extern MterpCheckBefore 8641 EXPORT_PC 8642 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8643 adr lr, artMterpAsmInstructionStart + (100 * 128) // Addr of primary handler. 8644 mov x0, xSELF 8645 add x1, xFP, #OFF_FP_SHADOWFRAME 8646 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8647 8648/* ------------------------------ */ 8649 .balign 128 8650.L_ALT_op_sget_char: /* 0x65 */ 8651/* File: arm64/alt_stub.S */ 8652/* 8653 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8654 * any interesting requests and then jump to the real instruction 8655 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8656 */ 8657 .extern MterpCheckBefore 8658 EXPORT_PC 8659 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8660 adr lr, artMterpAsmInstructionStart + (101 * 128) // Addr of primary handler. 8661 mov x0, xSELF 8662 add x1, xFP, #OFF_FP_SHADOWFRAME 8663 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8664 8665/* ------------------------------ */ 8666 .balign 128 8667.L_ALT_op_sget_short: /* 0x66 */ 8668/* File: arm64/alt_stub.S */ 8669/* 8670 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8671 * any interesting requests and then jump to the real instruction 8672 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8673 */ 8674 .extern MterpCheckBefore 8675 EXPORT_PC 8676 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8677 adr lr, artMterpAsmInstructionStart + (102 * 128) // Addr of primary handler. 8678 mov x0, xSELF 8679 add x1, xFP, #OFF_FP_SHADOWFRAME 8680 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8681 8682/* ------------------------------ */ 8683 .balign 128 8684.L_ALT_op_sput: /* 0x67 */ 8685/* File: arm64/alt_stub.S */ 8686/* 8687 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8688 * any interesting requests and then jump to the real instruction 8689 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8690 */ 8691 .extern MterpCheckBefore 8692 EXPORT_PC 8693 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8694 adr lr, artMterpAsmInstructionStart + (103 * 128) // Addr of primary handler. 8695 mov x0, xSELF 8696 add x1, xFP, #OFF_FP_SHADOWFRAME 8697 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8698 8699/* ------------------------------ */ 8700 .balign 128 8701.L_ALT_op_sput_wide: /* 0x68 */ 8702/* File: arm64/alt_stub.S */ 8703/* 8704 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8705 * any interesting requests and then jump to the real instruction 8706 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8707 */ 8708 .extern MterpCheckBefore 8709 EXPORT_PC 8710 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8711 adr lr, artMterpAsmInstructionStart + (104 * 128) // Addr of primary handler. 8712 mov x0, xSELF 8713 add x1, xFP, #OFF_FP_SHADOWFRAME 8714 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8715 8716/* ------------------------------ */ 8717 .balign 128 8718.L_ALT_op_sput_object: /* 0x69 */ 8719/* File: arm64/alt_stub.S */ 8720/* 8721 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8722 * any interesting requests and then jump to the real instruction 8723 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8724 */ 8725 .extern MterpCheckBefore 8726 EXPORT_PC 8727 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8728 adr lr, artMterpAsmInstructionStart + (105 * 128) // Addr of primary handler. 8729 mov x0, xSELF 8730 add x1, xFP, #OFF_FP_SHADOWFRAME 8731 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8732 8733/* ------------------------------ */ 8734 .balign 128 8735.L_ALT_op_sput_boolean: /* 0x6a */ 8736/* File: arm64/alt_stub.S */ 8737/* 8738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8739 * any interesting requests and then jump to the real instruction 8740 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8741 */ 8742 .extern MterpCheckBefore 8743 EXPORT_PC 8744 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8745 adr lr, artMterpAsmInstructionStart + (106 * 128) // Addr of primary handler. 8746 mov x0, xSELF 8747 add x1, xFP, #OFF_FP_SHADOWFRAME 8748 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8749 8750/* ------------------------------ */ 8751 .balign 128 8752.L_ALT_op_sput_byte: /* 0x6b */ 8753/* File: arm64/alt_stub.S */ 8754/* 8755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8756 * any interesting requests and then jump to the real instruction 8757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8758 */ 8759 .extern MterpCheckBefore 8760 EXPORT_PC 8761 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8762 adr lr, artMterpAsmInstructionStart + (107 * 128) // Addr of primary handler. 8763 mov x0, xSELF 8764 add x1, xFP, #OFF_FP_SHADOWFRAME 8765 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8766 8767/* ------------------------------ */ 8768 .balign 128 8769.L_ALT_op_sput_char: /* 0x6c */ 8770/* File: arm64/alt_stub.S */ 8771/* 8772 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8773 * any interesting requests and then jump to the real instruction 8774 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8775 */ 8776 .extern MterpCheckBefore 8777 EXPORT_PC 8778 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8779 adr lr, artMterpAsmInstructionStart + (108 * 128) // Addr of primary handler. 8780 mov x0, xSELF 8781 add x1, xFP, #OFF_FP_SHADOWFRAME 8782 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8783 8784/* ------------------------------ */ 8785 .balign 128 8786.L_ALT_op_sput_short: /* 0x6d */ 8787/* File: arm64/alt_stub.S */ 8788/* 8789 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8790 * any interesting requests and then jump to the real instruction 8791 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8792 */ 8793 .extern MterpCheckBefore 8794 EXPORT_PC 8795 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8796 adr lr, artMterpAsmInstructionStart + (109 * 128) // Addr of primary handler. 8797 mov x0, xSELF 8798 add x1, xFP, #OFF_FP_SHADOWFRAME 8799 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8800 8801/* ------------------------------ */ 8802 .balign 128 8803.L_ALT_op_invoke_virtual: /* 0x6e */ 8804/* File: arm64/alt_stub.S */ 8805/* 8806 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8807 * any interesting requests and then jump to the real instruction 8808 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8809 */ 8810 .extern MterpCheckBefore 8811 EXPORT_PC 8812 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8813 adr lr, artMterpAsmInstructionStart + (110 * 128) // Addr of primary handler. 8814 mov x0, xSELF 8815 add x1, xFP, #OFF_FP_SHADOWFRAME 8816 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8817 8818/* ------------------------------ */ 8819 .balign 128 8820.L_ALT_op_invoke_super: /* 0x6f */ 8821/* File: arm64/alt_stub.S */ 8822/* 8823 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8824 * any interesting requests and then jump to the real instruction 8825 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8826 */ 8827 .extern MterpCheckBefore 8828 EXPORT_PC 8829 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8830 adr lr, artMterpAsmInstructionStart + (111 * 128) // Addr of primary handler. 8831 mov x0, xSELF 8832 add x1, xFP, #OFF_FP_SHADOWFRAME 8833 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8834 8835/* ------------------------------ */ 8836 .balign 128 8837.L_ALT_op_invoke_direct: /* 0x70 */ 8838/* File: arm64/alt_stub.S */ 8839/* 8840 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8841 * any interesting requests and then jump to the real instruction 8842 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8843 */ 8844 .extern MterpCheckBefore 8845 EXPORT_PC 8846 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8847 adr lr, artMterpAsmInstructionStart + (112 * 128) // Addr of primary handler. 8848 mov x0, xSELF 8849 add x1, xFP, #OFF_FP_SHADOWFRAME 8850 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8851 8852/* ------------------------------ */ 8853 .balign 128 8854.L_ALT_op_invoke_static: /* 0x71 */ 8855/* File: arm64/alt_stub.S */ 8856/* 8857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8858 * any interesting requests and then jump to the real instruction 8859 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8860 */ 8861 .extern MterpCheckBefore 8862 EXPORT_PC 8863 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8864 adr lr, artMterpAsmInstructionStart + (113 * 128) // Addr of primary handler. 8865 mov x0, xSELF 8866 add x1, xFP, #OFF_FP_SHADOWFRAME 8867 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8868 8869/* ------------------------------ */ 8870 .balign 128 8871.L_ALT_op_invoke_interface: /* 0x72 */ 8872/* File: arm64/alt_stub.S */ 8873/* 8874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8875 * any interesting requests and then jump to the real instruction 8876 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8877 */ 8878 .extern MterpCheckBefore 8879 EXPORT_PC 8880 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8881 adr lr, artMterpAsmInstructionStart + (114 * 128) // Addr of primary handler. 8882 mov x0, xSELF 8883 add x1, xFP, #OFF_FP_SHADOWFRAME 8884 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8885 8886/* ------------------------------ */ 8887 .balign 128 8888.L_ALT_op_return_void_no_barrier: /* 0x73 */ 8889/* File: arm64/alt_stub.S */ 8890/* 8891 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8892 * any interesting requests and then jump to the real instruction 8893 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8894 */ 8895 .extern MterpCheckBefore 8896 EXPORT_PC 8897 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8898 adr lr, artMterpAsmInstructionStart + (115 * 128) // Addr of primary handler. 8899 mov x0, xSELF 8900 add x1, xFP, #OFF_FP_SHADOWFRAME 8901 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8902 8903/* ------------------------------ */ 8904 .balign 128 8905.L_ALT_op_invoke_virtual_range: /* 0x74 */ 8906/* File: arm64/alt_stub.S */ 8907/* 8908 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8909 * any interesting requests and then jump to the real instruction 8910 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8911 */ 8912 .extern MterpCheckBefore 8913 EXPORT_PC 8914 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8915 adr lr, artMterpAsmInstructionStart + (116 * 128) // Addr of primary handler. 8916 mov x0, xSELF 8917 add x1, xFP, #OFF_FP_SHADOWFRAME 8918 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8919 8920/* ------------------------------ */ 8921 .balign 128 8922.L_ALT_op_invoke_super_range: /* 0x75 */ 8923/* File: arm64/alt_stub.S */ 8924/* 8925 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8926 * any interesting requests and then jump to the real instruction 8927 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8928 */ 8929 .extern MterpCheckBefore 8930 EXPORT_PC 8931 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8932 adr lr, artMterpAsmInstructionStart + (117 * 128) // Addr of primary handler. 8933 mov x0, xSELF 8934 add x1, xFP, #OFF_FP_SHADOWFRAME 8935 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8936 8937/* ------------------------------ */ 8938 .balign 128 8939.L_ALT_op_invoke_direct_range: /* 0x76 */ 8940/* File: arm64/alt_stub.S */ 8941/* 8942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8943 * any interesting requests and then jump to the real instruction 8944 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8945 */ 8946 .extern MterpCheckBefore 8947 EXPORT_PC 8948 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8949 adr lr, artMterpAsmInstructionStart + (118 * 128) // Addr of primary handler. 8950 mov x0, xSELF 8951 add x1, xFP, #OFF_FP_SHADOWFRAME 8952 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8953 8954/* ------------------------------ */ 8955 .balign 128 8956.L_ALT_op_invoke_static_range: /* 0x77 */ 8957/* File: arm64/alt_stub.S */ 8958/* 8959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8960 * any interesting requests and then jump to the real instruction 8961 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8962 */ 8963 .extern MterpCheckBefore 8964 EXPORT_PC 8965 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8966 adr lr, artMterpAsmInstructionStart + (119 * 128) // Addr of primary handler. 8967 mov x0, xSELF 8968 add x1, xFP, #OFF_FP_SHADOWFRAME 8969 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8970 8971/* ------------------------------ */ 8972 .balign 128 8973.L_ALT_op_invoke_interface_range: /* 0x78 */ 8974/* File: arm64/alt_stub.S */ 8975/* 8976 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8977 * any interesting requests and then jump to the real instruction 8978 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8979 */ 8980 .extern MterpCheckBefore 8981 EXPORT_PC 8982 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 8983 adr lr, artMterpAsmInstructionStart + (120 * 128) // Addr of primary handler. 8984 mov x0, xSELF 8985 add x1, xFP, #OFF_FP_SHADOWFRAME 8986 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 8987 8988/* ------------------------------ */ 8989 .balign 128 8990.L_ALT_op_unused_79: /* 0x79 */ 8991/* File: arm64/alt_stub.S */ 8992/* 8993 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8994 * any interesting requests and then jump to the real instruction 8995 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8996 */ 8997 .extern MterpCheckBefore 8998 EXPORT_PC 8999 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9000 adr lr, artMterpAsmInstructionStart + (121 * 128) // Addr of primary handler. 9001 mov x0, xSELF 9002 add x1, xFP, #OFF_FP_SHADOWFRAME 9003 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9004 9005/* ------------------------------ */ 9006 .balign 128 9007.L_ALT_op_unused_7a: /* 0x7a */ 9008/* File: arm64/alt_stub.S */ 9009/* 9010 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9011 * any interesting requests and then jump to the real instruction 9012 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9013 */ 9014 .extern MterpCheckBefore 9015 EXPORT_PC 9016 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9017 adr lr, artMterpAsmInstructionStart + (122 * 128) // Addr of primary handler. 9018 mov x0, xSELF 9019 add x1, xFP, #OFF_FP_SHADOWFRAME 9020 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9021 9022/* ------------------------------ */ 9023 .balign 128 9024.L_ALT_op_neg_int: /* 0x7b */ 9025/* File: arm64/alt_stub.S */ 9026/* 9027 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9028 * any interesting requests and then jump to the real instruction 9029 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9030 */ 9031 .extern MterpCheckBefore 9032 EXPORT_PC 9033 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9034 adr lr, artMterpAsmInstructionStart + (123 * 128) // Addr of primary handler. 9035 mov x0, xSELF 9036 add x1, xFP, #OFF_FP_SHADOWFRAME 9037 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9038 9039/* ------------------------------ */ 9040 .balign 128 9041.L_ALT_op_not_int: /* 0x7c */ 9042/* File: arm64/alt_stub.S */ 9043/* 9044 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9045 * any interesting requests and then jump to the real instruction 9046 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9047 */ 9048 .extern MterpCheckBefore 9049 EXPORT_PC 9050 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9051 adr lr, artMterpAsmInstructionStart + (124 * 128) // Addr of primary handler. 9052 mov x0, xSELF 9053 add x1, xFP, #OFF_FP_SHADOWFRAME 9054 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9055 9056/* ------------------------------ */ 9057 .balign 128 9058.L_ALT_op_neg_long: /* 0x7d */ 9059/* File: arm64/alt_stub.S */ 9060/* 9061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9062 * any interesting requests and then jump to the real instruction 9063 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9064 */ 9065 .extern MterpCheckBefore 9066 EXPORT_PC 9067 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9068 adr lr, artMterpAsmInstructionStart + (125 * 128) // Addr of primary handler. 9069 mov x0, xSELF 9070 add x1, xFP, #OFF_FP_SHADOWFRAME 9071 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9072 9073/* ------------------------------ */ 9074 .balign 128 9075.L_ALT_op_not_long: /* 0x7e */ 9076/* File: arm64/alt_stub.S */ 9077/* 9078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9079 * any interesting requests and then jump to the real instruction 9080 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9081 */ 9082 .extern MterpCheckBefore 9083 EXPORT_PC 9084 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9085 adr lr, artMterpAsmInstructionStart + (126 * 128) // Addr of primary handler. 9086 mov x0, xSELF 9087 add x1, xFP, #OFF_FP_SHADOWFRAME 9088 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9089 9090/* ------------------------------ */ 9091 .balign 128 9092.L_ALT_op_neg_float: /* 0x7f */ 9093/* File: arm64/alt_stub.S */ 9094/* 9095 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9096 * any interesting requests and then jump to the real instruction 9097 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9098 */ 9099 .extern MterpCheckBefore 9100 EXPORT_PC 9101 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9102 adr lr, artMterpAsmInstructionStart + (127 * 128) // Addr of primary handler. 9103 mov x0, xSELF 9104 add x1, xFP, #OFF_FP_SHADOWFRAME 9105 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9106 9107/* ------------------------------ */ 9108 .balign 128 9109.L_ALT_op_neg_double: /* 0x80 */ 9110/* File: arm64/alt_stub.S */ 9111/* 9112 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9113 * any interesting requests and then jump to the real instruction 9114 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9115 */ 9116 .extern MterpCheckBefore 9117 EXPORT_PC 9118 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9119 adr lr, artMterpAsmInstructionStart + (128 * 128) // Addr of primary handler. 9120 mov x0, xSELF 9121 add x1, xFP, #OFF_FP_SHADOWFRAME 9122 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9123 9124/* ------------------------------ */ 9125 .balign 128 9126.L_ALT_op_int_to_long: /* 0x81 */ 9127/* File: arm64/alt_stub.S */ 9128/* 9129 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9130 * any interesting requests and then jump to the real instruction 9131 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9132 */ 9133 .extern MterpCheckBefore 9134 EXPORT_PC 9135 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9136 adr lr, artMterpAsmInstructionStart + (129 * 128) // Addr of primary handler. 9137 mov x0, xSELF 9138 add x1, xFP, #OFF_FP_SHADOWFRAME 9139 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9140 9141/* ------------------------------ */ 9142 .balign 128 9143.L_ALT_op_int_to_float: /* 0x82 */ 9144/* File: arm64/alt_stub.S */ 9145/* 9146 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9147 * any interesting requests and then jump to the real instruction 9148 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9149 */ 9150 .extern MterpCheckBefore 9151 EXPORT_PC 9152 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9153 adr lr, artMterpAsmInstructionStart + (130 * 128) // Addr of primary handler. 9154 mov x0, xSELF 9155 add x1, xFP, #OFF_FP_SHADOWFRAME 9156 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9157 9158/* ------------------------------ */ 9159 .balign 128 9160.L_ALT_op_int_to_double: /* 0x83 */ 9161/* File: arm64/alt_stub.S */ 9162/* 9163 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9164 * any interesting requests and then jump to the real instruction 9165 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9166 */ 9167 .extern MterpCheckBefore 9168 EXPORT_PC 9169 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9170 adr lr, artMterpAsmInstructionStart + (131 * 128) // Addr of primary handler. 9171 mov x0, xSELF 9172 add x1, xFP, #OFF_FP_SHADOWFRAME 9173 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9174 9175/* ------------------------------ */ 9176 .balign 128 9177.L_ALT_op_long_to_int: /* 0x84 */ 9178/* File: arm64/alt_stub.S */ 9179/* 9180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9181 * any interesting requests and then jump to the real instruction 9182 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9183 */ 9184 .extern MterpCheckBefore 9185 EXPORT_PC 9186 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9187 adr lr, artMterpAsmInstructionStart + (132 * 128) // Addr of primary handler. 9188 mov x0, xSELF 9189 add x1, xFP, #OFF_FP_SHADOWFRAME 9190 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9191 9192/* ------------------------------ */ 9193 .balign 128 9194.L_ALT_op_long_to_float: /* 0x85 */ 9195/* File: arm64/alt_stub.S */ 9196/* 9197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9198 * any interesting requests and then jump to the real instruction 9199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9200 */ 9201 .extern MterpCheckBefore 9202 EXPORT_PC 9203 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9204 adr lr, artMterpAsmInstructionStart + (133 * 128) // Addr of primary handler. 9205 mov x0, xSELF 9206 add x1, xFP, #OFF_FP_SHADOWFRAME 9207 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9208 9209/* ------------------------------ */ 9210 .balign 128 9211.L_ALT_op_long_to_double: /* 0x86 */ 9212/* File: arm64/alt_stub.S */ 9213/* 9214 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9215 * any interesting requests and then jump to the real instruction 9216 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9217 */ 9218 .extern MterpCheckBefore 9219 EXPORT_PC 9220 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9221 adr lr, artMterpAsmInstructionStart + (134 * 128) // Addr of primary handler. 9222 mov x0, xSELF 9223 add x1, xFP, #OFF_FP_SHADOWFRAME 9224 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9225 9226/* ------------------------------ */ 9227 .balign 128 9228.L_ALT_op_float_to_int: /* 0x87 */ 9229/* File: arm64/alt_stub.S */ 9230/* 9231 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9232 * any interesting requests and then jump to the real instruction 9233 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9234 */ 9235 .extern MterpCheckBefore 9236 EXPORT_PC 9237 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9238 adr lr, artMterpAsmInstructionStart + (135 * 128) // Addr of primary handler. 9239 mov x0, xSELF 9240 add x1, xFP, #OFF_FP_SHADOWFRAME 9241 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9242 9243/* ------------------------------ */ 9244 .balign 128 9245.L_ALT_op_float_to_long: /* 0x88 */ 9246/* File: arm64/alt_stub.S */ 9247/* 9248 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9249 * any interesting requests and then jump to the real instruction 9250 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9251 */ 9252 .extern MterpCheckBefore 9253 EXPORT_PC 9254 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9255 adr lr, artMterpAsmInstructionStart + (136 * 128) // Addr of primary handler. 9256 mov x0, xSELF 9257 add x1, xFP, #OFF_FP_SHADOWFRAME 9258 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9259 9260/* ------------------------------ */ 9261 .balign 128 9262.L_ALT_op_float_to_double: /* 0x89 */ 9263/* File: arm64/alt_stub.S */ 9264/* 9265 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9266 * any interesting requests and then jump to the real instruction 9267 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9268 */ 9269 .extern MterpCheckBefore 9270 EXPORT_PC 9271 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9272 adr lr, artMterpAsmInstructionStart + (137 * 128) // Addr of primary handler. 9273 mov x0, xSELF 9274 add x1, xFP, #OFF_FP_SHADOWFRAME 9275 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9276 9277/* ------------------------------ */ 9278 .balign 128 9279.L_ALT_op_double_to_int: /* 0x8a */ 9280/* File: arm64/alt_stub.S */ 9281/* 9282 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9283 * any interesting requests and then jump to the real instruction 9284 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9285 */ 9286 .extern MterpCheckBefore 9287 EXPORT_PC 9288 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9289 adr lr, artMterpAsmInstructionStart + (138 * 128) // Addr of primary handler. 9290 mov x0, xSELF 9291 add x1, xFP, #OFF_FP_SHADOWFRAME 9292 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9293 9294/* ------------------------------ */ 9295 .balign 128 9296.L_ALT_op_double_to_long: /* 0x8b */ 9297/* File: arm64/alt_stub.S */ 9298/* 9299 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9300 * any interesting requests and then jump to the real instruction 9301 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9302 */ 9303 .extern MterpCheckBefore 9304 EXPORT_PC 9305 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9306 adr lr, artMterpAsmInstructionStart + (139 * 128) // Addr of primary handler. 9307 mov x0, xSELF 9308 add x1, xFP, #OFF_FP_SHADOWFRAME 9309 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9310 9311/* ------------------------------ */ 9312 .balign 128 9313.L_ALT_op_double_to_float: /* 0x8c */ 9314/* File: arm64/alt_stub.S */ 9315/* 9316 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9317 * any interesting requests and then jump to the real instruction 9318 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9319 */ 9320 .extern MterpCheckBefore 9321 EXPORT_PC 9322 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9323 adr lr, artMterpAsmInstructionStart + (140 * 128) // Addr of primary handler. 9324 mov x0, xSELF 9325 add x1, xFP, #OFF_FP_SHADOWFRAME 9326 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9327 9328/* ------------------------------ */ 9329 .balign 128 9330.L_ALT_op_int_to_byte: /* 0x8d */ 9331/* File: arm64/alt_stub.S */ 9332/* 9333 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9334 * any interesting requests and then jump to the real instruction 9335 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9336 */ 9337 .extern MterpCheckBefore 9338 EXPORT_PC 9339 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9340 adr lr, artMterpAsmInstructionStart + (141 * 128) // Addr of primary handler. 9341 mov x0, xSELF 9342 add x1, xFP, #OFF_FP_SHADOWFRAME 9343 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9344 9345/* ------------------------------ */ 9346 .balign 128 9347.L_ALT_op_int_to_char: /* 0x8e */ 9348/* File: arm64/alt_stub.S */ 9349/* 9350 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9351 * any interesting requests and then jump to the real instruction 9352 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9353 */ 9354 .extern MterpCheckBefore 9355 EXPORT_PC 9356 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9357 adr lr, artMterpAsmInstructionStart + (142 * 128) // Addr of primary handler. 9358 mov x0, xSELF 9359 add x1, xFP, #OFF_FP_SHADOWFRAME 9360 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9361 9362/* ------------------------------ */ 9363 .balign 128 9364.L_ALT_op_int_to_short: /* 0x8f */ 9365/* File: arm64/alt_stub.S */ 9366/* 9367 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9368 * any interesting requests and then jump to the real instruction 9369 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9370 */ 9371 .extern MterpCheckBefore 9372 EXPORT_PC 9373 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9374 adr lr, artMterpAsmInstructionStart + (143 * 128) // Addr of primary handler. 9375 mov x0, xSELF 9376 add x1, xFP, #OFF_FP_SHADOWFRAME 9377 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9378 9379/* ------------------------------ */ 9380 .balign 128 9381.L_ALT_op_add_int: /* 0x90 */ 9382/* File: arm64/alt_stub.S */ 9383/* 9384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9385 * any interesting requests and then jump to the real instruction 9386 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9387 */ 9388 .extern MterpCheckBefore 9389 EXPORT_PC 9390 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9391 adr lr, artMterpAsmInstructionStart + (144 * 128) // Addr of primary handler. 9392 mov x0, xSELF 9393 add x1, xFP, #OFF_FP_SHADOWFRAME 9394 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9395 9396/* ------------------------------ */ 9397 .balign 128 9398.L_ALT_op_sub_int: /* 0x91 */ 9399/* File: arm64/alt_stub.S */ 9400/* 9401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9402 * any interesting requests and then jump to the real instruction 9403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9404 */ 9405 .extern MterpCheckBefore 9406 EXPORT_PC 9407 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9408 adr lr, artMterpAsmInstructionStart + (145 * 128) // Addr of primary handler. 9409 mov x0, xSELF 9410 add x1, xFP, #OFF_FP_SHADOWFRAME 9411 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9412 9413/* ------------------------------ */ 9414 .balign 128 9415.L_ALT_op_mul_int: /* 0x92 */ 9416/* File: arm64/alt_stub.S */ 9417/* 9418 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9419 * any interesting requests and then jump to the real instruction 9420 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9421 */ 9422 .extern MterpCheckBefore 9423 EXPORT_PC 9424 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9425 adr lr, artMterpAsmInstructionStart + (146 * 128) // Addr of primary handler. 9426 mov x0, xSELF 9427 add x1, xFP, #OFF_FP_SHADOWFRAME 9428 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9429 9430/* ------------------------------ */ 9431 .balign 128 9432.L_ALT_op_div_int: /* 0x93 */ 9433/* File: arm64/alt_stub.S */ 9434/* 9435 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9436 * any interesting requests and then jump to the real instruction 9437 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9438 */ 9439 .extern MterpCheckBefore 9440 EXPORT_PC 9441 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9442 adr lr, artMterpAsmInstructionStart + (147 * 128) // Addr of primary handler. 9443 mov x0, xSELF 9444 add x1, xFP, #OFF_FP_SHADOWFRAME 9445 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9446 9447/* ------------------------------ */ 9448 .balign 128 9449.L_ALT_op_rem_int: /* 0x94 */ 9450/* File: arm64/alt_stub.S */ 9451/* 9452 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9453 * any interesting requests and then jump to the real instruction 9454 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9455 */ 9456 .extern MterpCheckBefore 9457 EXPORT_PC 9458 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9459 adr lr, artMterpAsmInstructionStart + (148 * 128) // Addr of primary handler. 9460 mov x0, xSELF 9461 add x1, xFP, #OFF_FP_SHADOWFRAME 9462 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9463 9464/* ------------------------------ */ 9465 .balign 128 9466.L_ALT_op_and_int: /* 0x95 */ 9467/* File: arm64/alt_stub.S */ 9468/* 9469 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9470 * any interesting requests and then jump to the real instruction 9471 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9472 */ 9473 .extern MterpCheckBefore 9474 EXPORT_PC 9475 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9476 adr lr, artMterpAsmInstructionStart + (149 * 128) // Addr of primary handler. 9477 mov x0, xSELF 9478 add x1, xFP, #OFF_FP_SHADOWFRAME 9479 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9480 9481/* ------------------------------ */ 9482 .balign 128 9483.L_ALT_op_or_int: /* 0x96 */ 9484/* File: arm64/alt_stub.S */ 9485/* 9486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9487 * any interesting requests and then jump to the real instruction 9488 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9489 */ 9490 .extern MterpCheckBefore 9491 EXPORT_PC 9492 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9493 adr lr, artMterpAsmInstructionStart + (150 * 128) // Addr of primary handler. 9494 mov x0, xSELF 9495 add x1, xFP, #OFF_FP_SHADOWFRAME 9496 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9497 9498/* ------------------------------ */ 9499 .balign 128 9500.L_ALT_op_xor_int: /* 0x97 */ 9501/* File: arm64/alt_stub.S */ 9502/* 9503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9504 * any interesting requests and then jump to the real instruction 9505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9506 */ 9507 .extern MterpCheckBefore 9508 EXPORT_PC 9509 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9510 adr lr, artMterpAsmInstructionStart + (151 * 128) // Addr of primary handler. 9511 mov x0, xSELF 9512 add x1, xFP, #OFF_FP_SHADOWFRAME 9513 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9514 9515/* ------------------------------ */ 9516 .balign 128 9517.L_ALT_op_shl_int: /* 0x98 */ 9518/* File: arm64/alt_stub.S */ 9519/* 9520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9521 * any interesting requests and then jump to the real instruction 9522 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9523 */ 9524 .extern MterpCheckBefore 9525 EXPORT_PC 9526 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9527 adr lr, artMterpAsmInstructionStart + (152 * 128) // Addr of primary handler. 9528 mov x0, xSELF 9529 add x1, xFP, #OFF_FP_SHADOWFRAME 9530 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9531 9532/* ------------------------------ */ 9533 .balign 128 9534.L_ALT_op_shr_int: /* 0x99 */ 9535/* File: arm64/alt_stub.S */ 9536/* 9537 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9538 * any interesting requests and then jump to the real instruction 9539 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9540 */ 9541 .extern MterpCheckBefore 9542 EXPORT_PC 9543 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9544 adr lr, artMterpAsmInstructionStart + (153 * 128) // Addr of primary handler. 9545 mov x0, xSELF 9546 add x1, xFP, #OFF_FP_SHADOWFRAME 9547 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9548 9549/* ------------------------------ */ 9550 .balign 128 9551.L_ALT_op_ushr_int: /* 0x9a */ 9552/* File: arm64/alt_stub.S */ 9553/* 9554 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9555 * any interesting requests and then jump to the real instruction 9556 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9557 */ 9558 .extern MterpCheckBefore 9559 EXPORT_PC 9560 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9561 adr lr, artMterpAsmInstructionStart + (154 * 128) // Addr of primary handler. 9562 mov x0, xSELF 9563 add x1, xFP, #OFF_FP_SHADOWFRAME 9564 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9565 9566/* ------------------------------ */ 9567 .balign 128 9568.L_ALT_op_add_long: /* 0x9b */ 9569/* File: arm64/alt_stub.S */ 9570/* 9571 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9572 * any interesting requests and then jump to the real instruction 9573 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9574 */ 9575 .extern MterpCheckBefore 9576 EXPORT_PC 9577 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9578 adr lr, artMterpAsmInstructionStart + (155 * 128) // Addr of primary handler. 9579 mov x0, xSELF 9580 add x1, xFP, #OFF_FP_SHADOWFRAME 9581 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9582 9583/* ------------------------------ */ 9584 .balign 128 9585.L_ALT_op_sub_long: /* 0x9c */ 9586/* File: arm64/alt_stub.S */ 9587/* 9588 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9589 * any interesting requests and then jump to the real instruction 9590 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9591 */ 9592 .extern MterpCheckBefore 9593 EXPORT_PC 9594 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9595 adr lr, artMterpAsmInstructionStart + (156 * 128) // Addr of primary handler. 9596 mov x0, xSELF 9597 add x1, xFP, #OFF_FP_SHADOWFRAME 9598 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9599 9600/* ------------------------------ */ 9601 .balign 128 9602.L_ALT_op_mul_long: /* 0x9d */ 9603/* File: arm64/alt_stub.S */ 9604/* 9605 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9606 * any interesting requests and then jump to the real instruction 9607 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9608 */ 9609 .extern MterpCheckBefore 9610 EXPORT_PC 9611 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9612 adr lr, artMterpAsmInstructionStart + (157 * 128) // Addr of primary handler. 9613 mov x0, xSELF 9614 add x1, xFP, #OFF_FP_SHADOWFRAME 9615 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9616 9617/* ------------------------------ */ 9618 .balign 128 9619.L_ALT_op_div_long: /* 0x9e */ 9620/* File: arm64/alt_stub.S */ 9621/* 9622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9623 * any interesting requests and then jump to the real instruction 9624 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9625 */ 9626 .extern MterpCheckBefore 9627 EXPORT_PC 9628 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9629 adr lr, artMterpAsmInstructionStart + (158 * 128) // Addr of primary handler. 9630 mov x0, xSELF 9631 add x1, xFP, #OFF_FP_SHADOWFRAME 9632 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9633 9634/* ------------------------------ */ 9635 .balign 128 9636.L_ALT_op_rem_long: /* 0x9f */ 9637/* File: arm64/alt_stub.S */ 9638/* 9639 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9640 * any interesting requests and then jump to the real instruction 9641 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9642 */ 9643 .extern MterpCheckBefore 9644 EXPORT_PC 9645 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9646 adr lr, artMterpAsmInstructionStart + (159 * 128) // Addr of primary handler. 9647 mov x0, xSELF 9648 add x1, xFP, #OFF_FP_SHADOWFRAME 9649 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9650 9651/* ------------------------------ */ 9652 .balign 128 9653.L_ALT_op_and_long: /* 0xa0 */ 9654/* File: arm64/alt_stub.S */ 9655/* 9656 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9657 * any interesting requests and then jump to the real instruction 9658 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9659 */ 9660 .extern MterpCheckBefore 9661 EXPORT_PC 9662 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9663 adr lr, artMterpAsmInstructionStart + (160 * 128) // Addr of primary handler. 9664 mov x0, xSELF 9665 add x1, xFP, #OFF_FP_SHADOWFRAME 9666 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9667 9668/* ------------------------------ */ 9669 .balign 128 9670.L_ALT_op_or_long: /* 0xa1 */ 9671/* File: arm64/alt_stub.S */ 9672/* 9673 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9674 * any interesting requests and then jump to the real instruction 9675 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9676 */ 9677 .extern MterpCheckBefore 9678 EXPORT_PC 9679 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9680 adr lr, artMterpAsmInstructionStart + (161 * 128) // Addr of primary handler. 9681 mov x0, xSELF 9682 add x1, xFP, #OFF_FP_SHADOWFRAME 9683 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9684 9685/* ------------------------------ */ 9686 .balign 128 9687.L_ALT_op_xor_long: /* 0xa2 */ 9688/* File: arm64/alt_stub.S */ 9689/* 9690 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9691 * any interesting requests and then jump to the real instruction 9692 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9693 */ 9694 .extern MterpCheckBefore 9695 EXPORT_PC 9696 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9697 adr lr, artMterpAsmInstructionStart + (162 * 128) // Addr of primary handler. 9698 mov x0, xSELF 9699 add x1, xFP, #OFF_FP_SHADOWFRAME 9700 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9701 9702/* ------------------------------ */ 9703 .balign 128 9704.L_ALT_op_shl_long: /* 0xa3 */ 9705/* File: arm64/alt_stub.S */ 9706/* 9707 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9708 * any interesting requests and then jump to the real instruction 9709 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9710 */ 9711 .extern MterpCheckBefore 9712 EXPORT_PC 9713 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9714 adr lr, artMterpAsmInstructionStart + (163 * 128) // Addr of primary handler. 9715 mov x0, xSELF 9716 add x1, xFP, #OFF_FP_SHADOWFRAME 9717 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9718 9719/* ------------------------------ */ 9720 .balign 128 9721.L_ALT_op_shr_long: /* 0xa4 */ 9722/* File: arm64/alt_stub.S */ 9723/* 9724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9725 * any interesting requests and then jump to the real instruction 9726 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9727 */ 9728 .extern MterpCheckBefore 9729 EXPORT_PC 9730 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9731 adr lr, artMterpAsmInstructionStart + (164 * 128) // Addr of primary handler. 9732 mov x0, xSELF 9733 add x1, xFP, #OFF_FP_SHADOWFRAME 9734 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9735 9736/* ------------------------------ */ 9737 .balign 128 9738.L_ALT_op_ushr_long: /* 0xa5 */ 9739/* File: arm64/alt_stub.S */ 9740/* 9741 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9742 * any interesting requests and then jump to the real instruction 9743 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9744 */ 9745 .extern MterpCheckBefore 9746 EXPORT_PC 9747 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9748 adr lr, artMterpAsmInstructionStart + (165 * 128) // Addr of primary handler. 9749 mov x0, xSELF 9750 add x1, xFP, #OFF_FP_SHADOWFRAME 9751 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9752 9753/* ------------------------------ */ 9754 .balign 128 9755.L_ALT_op_add_float: /* 0xa6 */ 9756/* File: arm64/alt_stub.S */ 9757/* 9758 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9759 * any interesting requests and then jump to the real instruction 9760 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9761 */ 9762 .extern MterpCheckBefore 9763 EXPORT_PC 9764 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9765 adr lr, artMterpAsmInstructionStart + (166 * 128) // Addr of primary handler. 9766 mov x0, xSELF 9767 add x1, xFP, #OFF_FP_SHADOWFRAME 9768 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9769 9770/* ------------------------------ */ 9771 .balign 128 9772.L_ALT_op_sub_float: /* 0xa7 */ 9773/* File: arm64/alt_stub.S */ 9774/* 9775 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9776 * any interesting requests and then jump to the real instruction 9777 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9778 */ 9779 .extern MterpCheckBefore 9780 EXPORT_PC 9781 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9782 adr lr, artMterpAsmInstructionStart + (167 * 128) // Addr of primary handler. 9783 mov x0, xSELF 9784 add x1, xFP, #OFF_FP_SHADOWFRAME 9785 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9786 9787/* ------------------------------ */ 9788 .balign 128 9789.L_ALT_op_mul_float: /* 0xa8 */ 9790/* File: arm64/alt_stub.S */ 9791/* 9792 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9793 * any interesting requests and then jump to the real instruction 9794 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9795 */ 9796 .extern MterpCheckBefore 9797 EXPORT_PC 9798 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9799 adr lr, artMterpAsmInstructionStart + (168 * 128) // Addr of primary handler. 9800 mov x0, xSELF 9801 add x1, xFP, #OFF_FP_SHADOWFRAME 9802 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9803 9804/* ------------------------------ */ 9805 .balign 128 9806.L_ALT_op_div_float: /* 0xa9 */ 9807/* File: arm64/alt_stub.S */ 9808/* 9809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9810 * any interesting requests and then jump to the real instruction 9811 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9812 */ 9813 .extern MterpCheckBefore 9814 EXPORT_PC 9815 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9816 adr lr, artMterpAsmInstructionStart + (169 * 128) // Addr of primary handler. 9817 mov x0, xSELF 9818 add x1, xFP, #OFF_FP_SHADOWFRAME 9819 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9820 9821/* ------------------------------ */ 9822 .balign 128 9823.L_ALT_op_rem_float: /* 0xaa */ 9824/* File: arm64/alt_stub.S */ 9825/* 9826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9827 * any interesting requests and then jump to the real instruction 9828 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9829 */ 9830 .extern MterpCheckBefore 9831 EXPORT_PC 9832 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9833 adr lr, artMterpAsmInstructionStart + (170 * 128) // Addr of primary handler. 9834 mov x0, xSELF 9835 add x1, xFP, #OFF_FP_SHADOWFRAME 9836 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9837 9838/* ------------------------------ */ 9839 .balign 128 9840.L_ALT_op_add_double: /* 0xab */ 9841/* File: arm64/alt_stub.S */ 9842/* 9843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9844 * any interesting requests and then jump to the real instruction 9845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9846 */ 9847 .extern MterpCheckBefore 9848 EXPORT_PC 9849 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9850 adr lr, artMterpAsmInstructionStart + (171 * 128) // Addr of primary handler. 9851 mov x0, xSELF 9852 add x1, xFP, #OFF_FP_SHADOWFRAME 9853 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9854 9855/* ------------------------------ */ 9856 .balign 128 9857.L_ALT_op_sub_double: /* 0xac */ 9858/* File: arm64/alt_stub.S */ 9859/* 9860 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9861 * any interesting requests and then jump to the real instruction 9862 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9863 */ 9864 .extern MterpCheckBefore 9865 EXPORT_PC 9866 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9867 adr lr, artMterpAsmInstructionStart + (172 * 128) // Addr of primary handler. 9868 mov x0, xSELF 9869 add x1, xFP, #OFF_FP_SHADOWFRAME 9870 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9871 9872/* ------------------------------ */ 9873 .balign 128 9874.L_ALT_op_mul_double: /* 0xad */ 9875/* File: arm64/alt_stub.S */ 9876/* 9877 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9878 * any interesting requests and then jump to the real instruction 9879 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9880 */ 9881 .extern MterpCheckBefore 9882 EXPORT_PC 9883 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9884 adr lr, artMterpAsmInstructionStart + (173 * 128) // Addr of primary handler. 9885 mov x0, xSELF 9886 add x1, xFP, #OFF_FP_SHADOWFRAME 9887 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9888 9889/* ------------------------------ */ 9890 .balign 128 9891.L_ALT_op_div_double: /* 0xae */ 9892/* File: arm64/alt_stub.S */ 9893/* 9894 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9895 * any interesting requests and then jump to the real instruction 9896 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9897 */ 9898 .extern MterpCheckBefore 9899 EXPORT_PC 9900 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9901 adr lr, artMterpAsmInstructionStart + (174 * 128) // Addr of primary handler. 9902 mov x0, xSELF 9903 add x1, xFP, #OFF_FP_SHADOWFRAME 9904 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9905 9906/* ------------------------------ */ 9907 .balign 128 9908.L_ALT_op_rem_double: /* 0xaf */ 9909/* File: arm64/alt_stub.S */ 9910/* 9911 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9912 * any interesting requests and then jump to the real instruction 9913 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9914 */ 9915 .extern MterpCheckBefore 9916 EXPORT_PC 9917 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9918 adr lr, artMterpAsmInstructionStart + (175 * 128) // Addr of primary handler. 9919 mov x0, xSELF 9920 add x1, xFP, #OFF_FP_SHADOWFRAME 9921 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9922 9923/* ------------------------------ */ 9924 .balign 128 9925.L_ALT_op_add_int_2addr: /* 0xb0 */ 9926/* File: arm64/alt_stub.S */ 9927/* 9928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9929 * any interesting requests and then jump to the real instruction 9930 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9931 */ 9932 .extern MterpCheckBefore 9933 EXPORT_PC 9934 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9935 adr lr, artMterpAsmInstructionStart + (176 * 128) // Addr of primary handler. 9936 mov x0, xSELF 9937 add x1, xFP, #OFF_FP_SHADOWFRAME 9938 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9939 9940/* ------------------------------ */ 9941 .balign 128 9942.L_ALT_op_sub_int_2addr: /* 0xb1 */ 9943/* File: arm64/alt_stub.S */ 9944/* 9945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9946 * any interesting requests and then jump to the real instruction 9947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9948 */ 9949 .extern MterpCheckBefore 9950 EXPORT_PC 9951 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9952 adr lr, artMterpAsmInstructionStart + (177 * 128) // Addr of primary handler. 9953 mov x0, xSELF 9954 add x1, xFP, #OFF_FP_SHADOWFRAME 9955 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9956 9957/* ------------------------------ */ 9958 .balign 128 9959.L_ALT_op_mul_int_2addr: /* 0xb2 */ 9960/* File: arm64/alt_stub.S */ 9961/* 9962 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9963 * any interesting requests and then jump to the real instruction 9964 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9965 */ 9966 .extern MterpCheckBefore 9967 EXPORT_PC 9968 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9969 adr lr, artMterpAsmInstructionStart + (178 * 128) // Addr of primary handler. 9970 mov x0, xSELF 9971 add x1, xFP, #OFF_FP_SHADOWFRAME 9972 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9973 9974/* ------------------------------ */ 9975 .balign 128 9976.L_ALT_op_div_int_2addr: /* 0xb3 */ 9977/* File: arm64/alt_stub.S */ 9978/* 9979 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9980 * any interesting requests and then jump to the real instruction 9981 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9982 */ 9983 .extern MterpCheckBefore 9984 EXPORT_PC 9985 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 9986 adr lr, artMterpAsmInstructionStart + (179 * 128) // Addr of primary handler. 9987 mov x0, xSELF 9988 add x1, xFP, #OFF_FP_SHADOWFRAME 9989 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 9990 9991/* ------------------------------ */ 9992 .balign 128 9993.L_ALT_op_rem_int_2addr: /* 0xb4 */ 9994/* File: arm64/alt_stub.S */ 9995/* 9996 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9997 * any interesting requests and then jump to the real instruction 9998 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9999 */ 10000 .extern MterpCheckBefore 10001 EXPORT_PC 10002 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10003 adr lr, artMterpAsmInstructionStart + (180 * 128) // Addr of primary handler. 10004 mov x0, xSELF 10005 add x1, xFP, #OFF_FP_SHADOWFRAME 10006 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10007 10008/* ------------------------------ */ 10009 .balign 128 10010.L_ALT_op_and_int_2addr: /* 0xb5 */ 10011/* File: arm64/alt_stub.S */ 10012/* 10013 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10014 * any interesting requests and then jump to the real instruction 10015 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10016 */ 10017 .extern MterpCheckBefore 10018 EXPORT_PC 10019 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10020 adr lr, artMterpAsmInstructionStart + (181 * 128) // Addr of primary handler. 10021 mov x0, xSELF 10022 add x1, xFP, #OFF_FP_SHADOWFRAME 10023 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10024 10025/* ------------------------------ */ 10026 .balign 128 10027.L_ALT_op_or_int_2addr: /* 0xb6 */ 10028/* File: arm64/alt_stub.S */ 10029/* 10030 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10031 * any interesting requests and then jump to the real instruction 10032 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10033 */ 10034 .extern MterpCheckBefore 10035 EXPORT_PC 10036 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10037 adr lr, artMterpAsmInstructionStart + (182 * 128) // Addr of primary handler. 10038 mov x0, xSELF 10039 add x1, xFP, #OFF_FP_SHADOWFRAME 10040 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10041 10042/* ------------------------------ */ 10043 .balign 128 10044.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10045/* File: arm64/alt_stub.S */ 10046/* 10047 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10048 * any interesting requests and then jump to the real instruction 10049 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10050 */ 10051 .extern MterpCheckBefore 10052 EXPORT_PC 10053 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10054 adr lr, artMterpAsmInstructionStart + (183 * 128) // Addr of primary handler. 10055 mov x0, xSELF 10056 add x1, xFP, #OFF_FP_SHADOWFRAME 10057 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10058 10059/* ------------------------------ */ 10060 .balign 128 10061.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10062/* File: arm64/alt_stub.S */ 10063/* 10064 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10065 * any interesting requests and then jump to the real instruction 10066 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10067 */ 10068 .extern MterpCheckBefore 10069 EXPORT_PC 10070 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10071 adr lr, artMterpAsmInstructionStart + (184 * 128) // Addr of primary handler. 10072 mov x0, xSELF 10073 add x1, xFP, #OFF_FP_SHADOWFRAME 10074 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10075 10076/* ------------------------------ */ 10077 .balign 128 10078.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10079/* File: arm64/alt_stub.S */ 10080/* 10081 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10082 * any interesting requests and then jump to the real instruction 10083 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10084 */ 10085 .extern MterpCheckBefore 10086 EXPORT_PC 10087 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10088 adr lr, artMterpAsmInstructionStart + (185 * 128) // Addr of primary handler. 10089 mov x0, xSELF 10090 add x1, xFP, #OFF_FP_SHADOWFRAME 10091 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10092 10093/* ------------------------------ */ 10094 .balign 128 10095.L_ALT_op_ushr_int_2addr: /* 0xba */ 10096/* File: arm64/alt_stub.S */ 10097/* 10098 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10099 * any interesting requests and then jump to the real instruction 10100 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10101 */ 10102 .extern MterpCheckBefore 10103 EXPORT_PC 10104 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10105 adr lr, artMterpAsmInstructionStart + (186 * 128) // Addr of primary handler. 10106 mov x0, xSELF 10107 add x1, xFP, #OFF_FP_SHADOWFRAME 10108 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10109 10110/* ------------------------------ */ 10111 .balign 128 10112.L_ALT_op_add_long_2addr: /* 0xbb */ 10113/* File: arm64/alt_stub.S */ 10114/* 10115 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10116 * any interesting requests and then jump to the real instruction 10117 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10118 */ 10119 .extern MterpCheckBefore 10120 EXPORT_PC 10121 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10122 adr lr, artMterpAsmInstructionStart + (187 * 128) // Addr of primary handler. 10123 mov x0, xSELF 10124 add x1, xFP, #OFF_FP_SHADOWFRAME 10125 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10126 10127/* ------------------------------ */ 10128 .balign 128 10129.L_ALT_op_sub_long_2addr: /* 0xbc */ 10130/* File: arm64/alt_stub.S */ 10131/* 10132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10133 * any interesting requests and then jump to the real instruction 10134 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10135 */ 10136 .extern MterpCheckBefore 10137 EXPORT_PC 10138 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10139 adr lr, artMterpAsmInstructionStart + (188 * 128) // Addr of primary handler. 10140 mov x0, xSELF 10141 add x1, xFP, #OFF_FP_SHADOWFRAME 10142 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10143 10144/* ------------------------------ */ 10145 .balign 128 10146.L_ALT_op_mul_long_2addr: /* 0xbd */ 10147/* File: arm64/alt_stub.S */ 10148/* 10149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10150 * any interesting requests and then jump to the real instruction 10151 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10152 */ 10153 .extern MterpCheckBefore 10154 EXPORT_PC 10155 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10156 adr lr, artMterpAsmInstructionStart + (189 * 128) // Addr of primary handler. 10157 mov x0, xSELF 10158 add x1, xFP, #OFF_FP_SHADOWFRAME 10159 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10160 10161/* ------------------------------ */ 10162 .balign 128 10163.L_ALT_op_div_long_2addr: /* 0xbe */ 10164/* File: arm64/alt_stub.S */ 10165/* 10166 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10167 * any interesting requests and then jump to the real instruction 10168 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10169 */ 10170 .extern MterpCheckBefore 10171 EXPORT_PC 10172 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10173 adr lr, artMterpAsmInstructionStart + (190 * 128) // Addr of primary handler. 10174 mov x0, xSELF 10175 add x1, xFP, #OFF_FP_SHADOWFRAME 10176 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10177 10178/* ------------------------------ */ 10179 .balign 128 10180.L_ALT_op_rem_long_2addr: /* 0xbf */ 10181/* File: arm64/alt_stub.S */ 10182/* 10183 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10184 * any interesting requests and then jump to the real instruction 10185 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10186 */ 10187 .extern MterpCheckBefore 10188 EXPORT_PC 10189 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10190 adr lr, artMterpAsmInstructionStart + (191 * 128) // Addr of primary handler. 10191 mov x0, xSELF 10192 add x1, xFP, #OFF_FP_SHADOWFRAME 10193 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10194 10195/* ------------------------------ */ 10196 .balign 128 10197.L_ALT_op_and_long_2addr: /* 0xc0 */ 10198/* File: arm64/alt_stub.S */ 10199/* 10200 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10201 * any interesting requests and then jump to the real instruction 10202 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10203 */ 10204 .extern MterpCheckBefore 10205 EXPORT_PC 10206 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10207 adr lr, artMterpAsmInstructionStart + (192 * 128) // Addr of primary handler. 10208 mov x0, xSELF 10209 add x1, xFP, #OFF_FP_SHADOWFRAME 10210 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10211 10212/* ------------------------------ */ 10213 .balign 128 10214.L_ALT_op_or_long_2addr: /* 0xc1 */ 10215/* File: arm64/alt_stub.S */ 10216/* 10217 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10218 * any interesting requests and then jump to the real instruction 10219 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10220 */ 10221 .extern MterpCheckBefore 10222 EXPORT_PC 10223 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10224 adr lr, artMterpAsmInstructionStart + (193 * 128) // Addr of primary handler. 10225 mov x0, xSELF 10226 add x1, xFP, #OFF_FP_SHADOWFRAME 10227 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10228 10229/* ------------------------------ */ 10230 .balign 128 10231.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10232/* File: arm64/alt_stub.S */ 10233/* 10234 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10235 * any interesting requests and then jump to the real instruction 10236 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10237 */ 10238 .extern MterpCheckBefore 10239 EXPORT_PC 10240 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10241 adr lr, artMterpAsmInstructionStart + (194 * 128) // Addr of primary handler. 10242 mov x0, xSELF 10243 add x1, xFP, #OFF_FP_SHADOWFRAME 10244 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10245 10246/* ------------------------------ */ 10247 .balign 128 10248.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10249/* File: arm64/alt_stub.S */ 10250/* 10251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10252 * any interesting requests and then jump to the real instruction 10253 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10254 */ 10255 .extern MterpCheckBefore 10256 EXPORT_PC 10257 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10258 adr lr, artMterpAsmInstructionStart + (195 * 128) // Addr of primary handler. 10259 mov x0, xSELF 10260 add x1, xFP, #OFF_FP_SHADOWFRAME 10261 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10262 10263/* ------------------------------ */ 10264 .balign 128 10265.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10266/* File: arm64/alt_stub.S */ 10267/* 10268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10269 * any interesting requests and then jump to the real instruction 10270 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10271 */ 10272 .extern MterpCheckBefore 10273 EXPORT_PC 10274 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10275 adr lr, artMterpAsmInstructionStart + (196 * 128) // Addr of primary handler. 10276 mov x0, xSELF 10277 add x1, xFP, #OFF_FP_SHADOWFRAME 10278 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10279 10280/* ------------------------------ */ 10281 .balign 128 10282.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10283/* File: arm64/alt_stub.S */ 10284/* 10285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10286 * any interesting requests and then jump to the real instruction 10287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10288 */ 10289 .extern MterpCheckBefore 10290 EXPORT_PC 10291 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10292 adr lr, artMterpAsmInstructionStart + (197 * 128) // Addr of primary handler. 10293 mov x0, xSELF 10294 add x1, xFP, #OFF_FP_SHADOWFRAME 10295 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10296 10297/* ------------------------------ */ 10298 .balign 128 10299.L_ALT_op_add_float_2addr: /* 0xc6 */ 10300/* File: arm64/alt_stub.S */ 10301/* 10302 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10303 * any interesting requests and then jump to the real instruction 10304 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10305 */ 10306 .extern MterpCheckBefore 10307 EXPORT_PC 10308 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10309 adr lr, artMterpAsmInstructionStart + (198 * 128) // Addr of primary handler. 10310 mov x0, xSELF 10311 add x1, xFP, #OFF_FP_SHADOWFRAME 10312 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10313 10314/* ------------------------------ */ 10315 .balign 128 10316.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10317/* File: arm64/alt_stub.S */ 10318/* 10319 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10320 * any interesting requests and then jump to the real instruction 10321 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10322 */ 10323 .extern MterpCheckBefore 10324 EXPORT_PC 10325 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10326 adr lr, artMterpAsmInstructionStart + (199 * 128) // Addr of primary handler. 10327 mov x0, xSELF 10328 add x1, xFP, #OFF_FP_SHADOWFRAME 10329 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10330 10331/* ------------------------------ */ 10332 .balign 128 10333.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10334/* File: arm64/alt_stub.S */ 10335/* 10336 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10337 * any interesting requests and then jump to the real instruction 10338 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10339 */ 10340 .extern MterpCheckBefore 10341 EXPORT_PC 10342 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10343 adr lr, artMterpAsmInstructionStart + (200 * 128) // Addr of primary handler. 10344 mov x0, xSELF 10345 add x1, xFP, #OFF_FP_SHADOWFRAME 10346 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10347 10348/* ------------------------------ */ 10349 .balign 128 10350.L_ALT_op_div_float_2addr: /* 0xc9 */ 10351/* File: arm64/alt_stub.S */ 10352/* 10353 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10354 * any interesting requests and then jump to the real instruction 10355 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10356 */ 10357 .extern MterpCheckBefore 10358 EXPORT_PC 10359 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10360 adr lr, artMterpAsmInstructionStart + (201 * 128) // Addr of primary handler. 10361 mov x0, xSELF 10362 add x1, xFP, #OFF_FP_SHADOWFRAME 10363 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10364 10365/* ------------------------------ */ 10366 .balign 128 10367.L_ALT_op_rem_float_2addr: /* 0xca */ 10368/* File: arm64/alt_stub.S */ 10369/* 10370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10371 * any interesting requests and then jump to the real instruction 10372 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10373 */ 10374 .extern MterpCheckBefore 10375 EXPORT_PC 10376 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10377 adr lr, artMterpAsmInstructionStart + (202 * 128) // Addr of primary handler. 10378 mov x0, xSELF 10379 add x1, xFP, #OFF_FP_SHADOWFRAME 10380 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10381 10382/* ------------------------------ */ 10383 .balign 128 10384.L_ALT_op_add_double_2addr: /* 0xcb */ 10385/* File: arm64/alt_stub.S */ 10386/* 10387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10388 * any interesting requests and then jump to the real instruction 10389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10390 */ 10391 .extern MterpCheckBefore 10392 EXPORT_PC 10393 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10394 adr lr, artMterpAsmInstructionStart + (203 * 128) // Addr of primary handler. 10395 mov x0, xSELF 10396 add x1, xFP, #OFF_FP_SHADOWFRAME 10397 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10398 10399/* ------------------------------ */ 10400 .balign 128 10401.L_ALT_op_sub_double_2addr: /* 0xcc */ 10402/* File: arm64/alt_stub.S */ 10403/* 10404 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10405 * any interesting requests and then jump to the real instruction 10406 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10407 */ 10408 .extern MterpCheckBefore 10409 EXPORT_PC 10410 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10411 adr lr, artMterpAsmInstructionStart + (204 * 128) // Addr of primary handler. 10412 mov x0, xSELF 10413 add x1, xFP, #OFF_FP_SHADOWFRAME 10414 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10415 10416/* ------------------------------ */ 10417 .balign 128 10418.L_ALT_op_mul_double_2addr: /* 0xcd */ 10419/* File: arm64/alt_stub.S */ 10420/* 10421 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10422 * any interesting requests and then jump to the real instruction 10423 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10424 */ 10425 .extern MterpCheckBefore 10426 EXPORT_PC 10427 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10428 adr lr, artMterpAsmInstructionStart + (205 * 128) // Addr of primary handler. 10429 mov x0, xSELF 10430 add x1, xFP, #OFF_FP_SHADOWFRAME 10431 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10432 10433/* ------------------------------ */ 10434 .balign 128 10435.L_ALT_op_div_double_2addr: /* 0xce */ 10436/* File: arm64/alt_stub.S */ 10437/* 10438 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10439 * any interesting requests and then jump to the real instruction 10440 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10441 */ 10442 .extern MterpCheckBefore 10443 EXPORT_PC 10444 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10445 adr lr, artMterpAsmInstructionStart + (206 * 128) // Addr of primary handler. 10446 mov x0, xSELF 10447 add x1, xFP, #OFF_FP_SHADOWFRAME 10448 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10449 10450/* ------------------------------ */ 10451 .balign 128 10452.L_ALT_op_rem_double_2addr: /* 0xcf */ 10453/* File: arm64/alt_stub.S */ 10454/* 10455 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10456 * any interesting requests and then jump to the real instruction 10457 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10458 */ 10459 .extern MterpCheckBefore 10460 EXPORT_PC 10461 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10462 adr lr, artMterpAsmInstructionStart + (207 * 128) // Addr of primary handler. 10463 mov x0, xSELF 10464 add x1, xFP, #OFF_FP_SHADOWFRAME 10465 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10466 10467/* ------------------------------ */ 10468 .balign 128 10469.L_ALT_op_add_int_lit16: /* 0xd0 */ 10470/* File: arm64/alt_stub.S */ 10471/* 10472 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10473 * any interesting requests and then jump to the real instruction 10474 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10475 */ 10476 .extern MterpCheckBefore 10477 EXPORT_PC 10478 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10479 adr lr, artMterpAsmInstructionStart + (208 * 128) // Addr of primary handler. 10480 mov x0, xSELF 10481 add x1, xFP, #OFF_FP_SHADOWFRAME 10482 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10483 10484/* ------------------------------ */ 10485 .balign 128 10486.L_ALT_op_rsub_int: /* 0xd1 */ 10487/* File: arm64/alt_stub.S */ 10488/* 10489 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10490 * any interesting requests and then jump to the real instruction 10491 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10492 */ 10493 .extern MterpCheckBefore 10494 EXPORT_PC 10495 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10496 adr lr, artMterpAsmInstructionStart + (209 * 128) // Addr of primary handler. 10497 mov x0, xSELF 10498 add x1, xFP, #OFF_FP_SHADOWFRAME 10499 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10500 10501/* ------------------------------ */ 10502 .balign 128 10503.L_ALT_op_mul_int_lit16: /* 0xd2 */ 10504/* File: arm64/alt_stub.S */ 10505/* 10506 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10507 * any interesting requests and then jump to the real instruction 10508 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10509 */ 10510 .extern MterpCheckBefore 10511 EXPORT_PC 10512 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10513 adr lr, artMterpAsmInstructionStart + (210 * 128) // Addr of primary handler. 10514 mov x0, xSELF 10515 add x1, xFP, #OFF_FP_SHADOWFRAME 10516 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10517 10518/* ------------------------------ */ 10519 .balign 128 10520.L_ALT_op_div_int_lit16: /* 0xd3 */ 10521/* File: arm64/alt_stub.S */ 10522/* 10523 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10524 * any interesting requests and then jump to the real instruction 10525 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10526 */ 10527 .extern MterpCheckBefore 10528 EXPORT_PC 10529 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10530 adr lr, artMterpAsmInstructionStart + (211 * 128) // Addr of primary handler. 10531 mov x0, xSELF 10532 add x1, xFP, #OFF_FP_SHADOWFRAME 10533 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10534 10535/* ------------------------------ */ 10536 .balign 128 10537.L_ALT_op_rem_int_lit16: /* 0xd4 */ 10538/* File: arm64/alt_stub.S */ 10539/* 10540 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10541 * any interesting requests and then jump to the real instruction 10542 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10543 */ 10544 .extern MterpCheckBefore 10545 EXPORT_PC 10546 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10547 adr lr, artMterpAsmInstructionStart + (212 * 128) // Addr of primary handler. 10548 mov x0, xSELF 10549 add x1, xFP, #OFF_FP_SHADOWFRAME 10550 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10551 10552/* ------------------------------ */ 10553 .balign 128 10554.L_ALT_op_and_int_lit16: /* 0xd5 */ 10555/* File: arm64/alt_stub.S */ 10556/* 10557 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10558 * any interesting requests and then jump to the real instruction 10559 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10560 */ 10561 .extern MterpCheckBefore 10562 EXPORT_PC 10563 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10564 adr lr, artMterpAsmInstructionStart + (213 * 128) // Addr of primary handler. 10565 mov x0, xSELF 10566 add x1, xFP, #OFF_FP_SHADOWFRAME 10567 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10568 10569/* ------------------------------ */ 10570 .balign 128 10571.L_ALT_op_or_int_lit16: /* 0xd6 */ 10572/* File: arm64/alt_stub.S */ 10573/* 10574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10575 * any interesting requests and then jump to the real instruction 10576 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10577 */ 10578 .extern MterpCheckBefore 10579 EXPORT_PC 10580 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10581 adr lr, artMterpAsmInstructionStart + (214 * 128) // Addr of primary handler. 10582 mov x0, xSELF 10583 add x1, xFP, #OFF_FP_SHADOWFRAME 10584 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10585 10586/* ------------------------------ */ 10587 .balign 128 10588.L_ALT_op_xor_int_lit16: /* 0xd7 */ 10589/* File: arm64/alt_stub.S */ 10590/* 10591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10592 * any interesting requests and then jump to the real instruction 10593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10594 */ 10595 .extern MterpCheckBefore 10596 EXPORT_PC 10597 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10598 adr lr, artMterpAsmInstructionStart + (215 * 128) // Addr of primary handler. 10599 mov x0, xSELF 10600 add x1, xFP, #OFF_FP_SHADOWFRAME 10601 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10602 10603/* ------------------------------ */ 10604 .balign 128 10605.L_ALT_op_add_int_lit8: /* 0xd8 */ 10606/* File: arm64/alt_stub.S */ 10607/* 10608 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10609 * any interesting requests and then jump to the real instruction 10610 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10611 */ 10612 .extern MterpCheckBefore 10613 EXPORT_PC 10614 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10615 adr lr, artMterpAsmInstructionStart + (216 * 128) // Addr of primary handler. 10616 mov x0, xSELF 10617 add x1, xFP, #OFF_FP_SHADOWFRAME 10618 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10619 10620/* ------------------------------ */ 10621 .balign 128 10622.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 10623/* File: arm64/alt_stub.S */ 10624/* 10625 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10626 * any interesting requests and then jump to the real instruction 10627 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10628 */ 10629 .extern MterpCheckBefore 10630 EXPORT_PC 10631 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10632 adr lr, artMterpAsmInstructionStart + (217 * 128) // Addr of primary handler. 10633 mov x0, xSELF 10634 add x1, xFP, #OFF_FP_SHADOWFRAME 10635 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10636 10637/* ------------------------------ */ 10638 .balign 128 10639.L_ALT_op_mul_int_lit8: /* 0xda */ 10640/* File: arm64/alt_stub.S */ 10641/* 10642 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10643 * any interesting requests and then jump to the real instruction 10644 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10645 */ 10646 .extern MterpCheckBefore 10647 EXPORT_PC 10648 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10649 adr lr, artMterpAsmInstructionStart + (218 * 128) // Addr of primary handler. 10650 mov x0, xSELF 10651 add x1, xFP, #OFF_FP_SHADOWFRAME 10652 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10653 10654/* ------------------------------ */ 10655 .balign 128 10656.L_ALT_op_div_int_lit8: /* 0xdb */ 10657/* File: arm64/alt_stub.S */ 10658/* 10659 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10660 * any interesting requests and then jump to the real instruction 10661 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10662 */ 10663 .extern MterpCheckBefore 10664 EXPORT_PC 10665 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10666 adr lr, artMterpAsmInstructionStart + (219 * 128) // Addr of primary handler. 10667 mov x0, xSELF 10668 add x1, xFP, #OFF_FP_SHADOWFRAME 10669 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10670 10671/* ------------------------------ */ 10672 .balign 128 10673.L_ALT_op_rem_int_lit8: /* 0xdc */ 10674/* File: arm64/alt_stub.S */ 10675/* 10676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10677 * any interesting requests and then jump to the real instruction 10678 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10679 */ 10680 .extern MterpCheckBefore 10681 EXPORT_PC 10682 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10683 adr lr, artMterpAsmInstructionStart + (220 * 128) // Addr of primary handler. 10684 mov x0, xSELF 10685 add x1, xFP, #OFF_FP_SHADOWFRAME 10686 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10687 10688/* ------------------------------ */ 10689 .balign 128 10690.L_ALT_op_and_int_lit8: /* 0xdd */ 10691/* File: arm64/alt_stub.S */ 10692/* 10693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10694 * any interesting requests and then jump to the real instruction 10695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10696 */ 10697 .extern MterpCheckBefore 10698 EXPORT_PC 10699 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10700 adr lr, artMterpAsmInstructionStart + (221 * 128) // Addr of primary handler. 10701 mov x0, xSELF 10702 add x1, xFP, #OFF_FP_SHADOWFRAME 10703 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10704 10705/* ------------------------------ */ 10706 .balign 128 10707.L_ALT_op_or_int_lit8: /* 0xde */ 10708/* File: arm64/alt_stub.S */ 10709/* 10710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10711 * any interesting requests and then jump to the real instruction 10712 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10713 */ 10714 .extern MterpCheckBefore 10715 EXPORT_PC 10716 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10717 adr lr, artMterpAsmInstructionStart + (222 * 128) // Addr of primary handler. 10718 mov x0, xSELF 10719 add x1, xFP, #OFF_FP_SHADOWFRAME 10720 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10721 10722/* ------------------------------ */ 10723 .balign 128 10724.L_ALT_op_xor_int_lit8: /* 0xdf */ 10725/* File: arm64/alt_stub.S */ 10726/* 10727 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10728 * any interesting requests and then jump to the real instruction 10729 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10730 */ 10731 .extern MterpCheckBefore 10732 EXPORT_PC 10733 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10734 adr lr, artMterpAsmInstructionStart + (223 * 128) // Addr of primary handler. 10735 mov x0, xSELF 10736 add x1, xFP, #OFF_FP_SHADOWFRAME 10737 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10738 10739/* ------------------------------ */ 10740 .balign 128 10741.L_ALT_op_shl_int_lit8: /* 0xe0 */ 10742/* File: arm64/alt_stub.S */ 10743/* 10744 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10745 * any interesting requests and then jump to the real instruction 10746 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10747 */ 10748 .extern MterpCheckBefore 10749 EXPORT_PC 10750 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10751 adr lr, artMterpAsmInstructionStart + (224 * 128) // Addr of primary handler. 10752 mov x0, xSELF 10753 add x1, xFP, #OFF_FP_SHADOWFRAME 10754 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10755 10756/* ------------------------------ */ 10757 .balign 128 10758.L_ALT_op_shr_int_lit8: /* 0xe1 */ 10759/* File: arm64/alt_stub.S */ 10760/* 10761 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10762 * any interesting requests and then jump to the real instruction 10763 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10764 */ 10765 .extern MterpCheckBefore 10766 EXPORT_PC 10767 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10768 adr lr, artMterpAsmInstructionStart + (225 * 128) // Addr of primary handler. 10769 mov x0, xSELF 10770 add x1, xFP, #OFF_FP_SHADOWFRAME 10771 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10772 10773/* ------------------------------ */ 10774 .balign 128 10775.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 10776/* File: arm64/alt_stub.S */ 10777/* 10778 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10779 * any interesting requests and then jump to the real instruction 10780 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10781 */ 10782 .extern MterpCheckBefore 10783 EXPORT_PC 10784 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10785 adr lr, artMterpAsmInstructionStart + (226 * 128) // Addr of primary handler. 10786 mov x0, xSELF 10787 add x1, xFP, #OFF_FP_SHADOWFRAME 10788 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10789 10790/* ------------------------------ */ 10791 .balign 128 10792.L_ALT_op_iget_quick: /* 0xe3 */ 10793/* File: arm64/alt_stub.S */ 10794/* 10795 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10796 * any interesting requests and then jump to the real instruction 10797 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10798 */ 10799 .extern MterpCheckBefore 10800 EXPORT_PC 10801 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10802 adr lr, artMterpAsmInstructionStart + (227 * 128) // Addr of primary handler. 10803 mov x0, xSELF 10804 add x1, xFP, #OFF_FP_SHADOWFRAME 10805 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10806 10807/* ------------------------------ */ 10808 .balign 128 10809.L_ALT_op_iget_wide_quick: /* 0xe4 */ 10810/* File: arm64/alt_stub.S */ 10811/* 10812 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10813 * any interesting requests and then jump to the real instruction 10814 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10815 */ 10816 .extern MterpCheckBefore 10817 EXPORT_PC 10818 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10819 adr lr, artMterpAsmInstructionStart + (228 * 128) // Addr of primary handler. 10820 mov x0, xSELF 10821 add x1, xFP, #OFF_FP_SHADOWFRAME 10822 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10823 10824/* ------------------------------ */ 10825 .balign 128 10826.L_ALT_op_iget_object_quick: /* 0xe5 */ 10827/* File: arm64/alt_stub.S */ 10828/* 10829 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10830 * any interesting requests and then jump to the real instruction 10831 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10832 */ 10833 .extern MterpCheckBefore 10834 EXPORT_PC 10835 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10836 adr lr, artMterpAsmInstructionStart + (229 * 128) // Addr of primary handler. 10837 mov x0, xSELF 10838 add x1, xFP, #OFF_FP_SHADOWFRAME 10839 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10840 10841/* ------------------------------ */ 10842 .balign 128 10843.L_ALT_op_iput_quick: /* 0xe6 */ 10844/* File: arm64/alt_stub.S */ 10845/* 10846 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10847 * any interesting requests and then jump to the real instruction 10848 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10849 */ 10850 .extern MterpCheckBefore 10851 EXPORT_PC 10852 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10853 adr lr, artMterpAsmInstructionStart + (230 * 128) // Addr of primary handler. 10854 mov x0, xSELF 10855 add x1, xFP, #OFF_FP_SHADOWFRAME 10856 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10857 10858/* ------------------------------ */ 10859 .balign 128 10860.L_ALT_op_iput_wide_quick: /* 0xe7 */ 10861/* File: arm64/alt_stub.S */ 10862/* 10863 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10864 * any interesting requests and then jump to the real instruction 10865 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10866 */ 10867 .extern MterpCheckBefore 10868 EXPORT_PC 10869 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10870 adr lr, artMterpAsmInstructionStart + (231 * 128) // Addr of primary handler. 10871 mov x0, xSELF 10872 add x1, xFP, #OFF_FP_SHADOWFRAME 10873 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10874 10875/* ------------------------------ */ 10876 .balign 128 10877.L_ALT_op_iput_object_quick: /* 0xe8 */ 10878/* File: arm64/alt_stub.S */ 10879/* 10880 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10881 * any interesting requests and then jump to the real instruction 10882 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10883 */ 10884 .extern MterpCheckBefore 10885 EXPORT_PC 10886 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10887 adr lr, artMterpAsmInstructionStart + (232 * 128) // Addr of primary handler. 10888 mov x0, xSELF 10889 add x1, xFP, #OFF_FP_SHADOWFRAME 10890 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10891 10892/* ------------------------------ */ 10893 .balign 128 10894.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 10895/* File: arm64/alt_stub.S */ 10896/* 10897 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10898 * any interesting requests and then jump to the real instruction 10899 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10900 */ 10901 .extern MterpCheckBefore 10902 EXPORT_PC 10903 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10904 adr lr, artMterpAsmInstructionStart + (233 * 128) // Addr of primary handler. 10905 mov x0, xSELF 10906 add x1, xFP, #OFF_FP_SHADOWFRAME 10907 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10908 10909/* ------------------------------ */ 10910 .balign 128 10911.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 10912/* File: arm64/alt_stub.S */ 10913/* 10914 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10915 * any interesting requests and then jump to the real instruction 10916 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10917 */ 10918 .extern MterpCheckBefore 10919 EXPORT_PC 10920 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10921 adr lr, artMterpAsmInstructionStart + (234 * 128) // Addr of primary handler. 10922 mov x0, xSELF 10923 add x1, xFP, #OFF_FP_SHADOWFRAME 10924 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10925 10926/* ------------------------------ */ 10927 .balign 128 10928.L_ALT_op_iput_boolean_quick: /* 0xeb */ 10929/* File: arm64/alt_stub.S */ 10930/* 10931 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10932 * any interesting requests and then jump to the real instruction 10933 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10934 */ 10935 .extern MterpCheckBefore 10936 EXPORT_PC 10937 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10938 adr lr, artMterpAsmInstructionStart + (235 * 128) // Addr of primary handler. 10939 mov x0, xSELF 10940 add x1, xFP, #OFF_FP_SHADOWFRAME 10941 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10942 10943/* ------------------------------ */ 10944 .balign 128 10945.L_ALT_op_iput_byte_quick: /* 0xec */ 10946/* File: arm64/alt_stub.S */ 10947/* 10948 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10949 * any interesting requests and then jump to the real instruction 10950 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10951 */ 10952 .extern MterpCheckBefore 10953 EXPORT_PC 10954 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10955 adr lr, artMterpAsmInstructionStart + (236 * 128) // Addr of primary handler. 10956 mov x0, xSELF 10957 add x1, xFP, #OFF_FP_SHADOWFRAME 10958 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10959 10960/* ------------------------------ */ 10961 .balign 128 10962.L_ALT_op_iput_char_quick: /* 0xed */ 10963/* File: arm64/alt_stub.S */ 10964/* 10965 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10966 * any interesting requests and then jump to the real instruction 10967 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10968 */ 10969 .extern MterpCheckBefore 10970 EXPORT_PC 10971 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10972 adr lr, artMterpAsmInstructionStart + (237 * 128) // Addr of primary handler. 10973 mov x0, xSELF 10974 add x1, xFP, #OFF_FP_SHADOWFRAME 10975 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10976 10977/* ------------------------------ */ 10978 .balign 128 10979.L_ALT_op_iput_short_quick: /* 0xee */ 10980/* File: arm64/alt_stub.S */ 10981/* 10982 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10983 * any interesting requests and then jump to the real instruction 10984 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10985 */ 10986 .extern MterpCheckBefore 10987 EXPORT_PC 10988 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 10989 adr lr, artMterpAsmInstructionStart + (238 * 128) // Addr of primary handler. 10990 mov x0, xSELF 10991 add x1, xFP, #OFF_FP_SHADOWFRAME 10992 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 10993 10994/* ------------------------------ */ 10995 .balign 128 10996.L_ALT_op_iget_boolean_quick: /* 0xef */ 10997/* File: arm64/alt_stub.S */ 10998/* 10999 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11000 * any interesting requests and then jump to the real instruction 11001 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11002 */ 11003 .extern MterpCheckBefore 11004 EXPORT_PC 11005 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11006 adr lr, artMterpAsmInstructionStart + (239 * 128) // Addr of primary handler. 11007 mov x0, xSELF 11008 add x1, xFP, #OFF_FP_SHADOWFRAME 11009 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11010 11011/* ------------------------------ */ 11012 .balign 128 11013.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11014/* File: arm64/alt_stub.S */ 11015/* 11016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11017 * any interesting requests and then jump to the real instruction 11018 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11019 */ 11020 .extern MterpCheckBefore 11021 EXPORT_PC 11022 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11023 adr lr, artMterpAsmInstructionStart + (240 * 128) // Addr of primary handler. 11024 mov x0, xSELF 11025 add x1, xFP, #OFF_FP_SHADOWFRAME 11026 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11027 11028/* ------------------------------ */ 11029 .balign 128 11030.L_ALT_op_iget_char_quick: /* 0xf1 */ 11031/* File: arm64/alt_stub.S */ 11032/* 11033 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11034 * any interesting requests and then jump to the real instruction 11035 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11036 */ 11037 .extern MterpCheckBefore 11038 EXPORT_PC 11039 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11040 adr lr, artMterpAsmInstructionStart + (241 * 128) // Addr of primary handler. 11041 mov x0, xSELF 11042 add x1, xFP, #OFF_FP_SHADOWFRAME 11043 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11044 11045/* ------------------------------ */ 11046 .balign 128 11047.L_ALT_op_iget_short_quick: /* 0xf2 */ 11048/* File: arm64/alt_stub.S */ 11049/* 11050 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11051 * any interesting requests and then jump to the real instruction 11052 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11053 */ 11054 .extern MterpCheckBefore 11055 EXPORT_PC 11056 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11057 adr lr, artMterpAsmInstructionStart + (242 * 128) // Addr of primary handler. 11058 mov x0, xSELF 11059 add x1, xFP, #OFF_FP_SHADOWFRAME 11060 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11061 11062/* ------------------------------ */ 11063 .balign 128 11064.L_ALT_op_invoke_lambda: /* 0xf3 */ 11065/* File: arm64/alt_stub.S */ 11066/* 11067 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11068 * any interesting requests and then jump to the real instruction 11069 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11070 */ 11071 .extern MterpCheckBefore 11072 EXPORT_PC 11073 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11074 adr lr, artMterpAsmInstructionStart + (243 * 128) // Addr of primary handler. 11075 mov x0, xSELF 11076 add x1, xFP, #OFF_FP_SHADOWFRAME 11077 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11078 11079/* ------------------------------ */ 11080 .balign 128 11081.L_ALT_op_unused_f4: /* 0xf4 */ 11082/* File: arm64/alt_stub.S */ 11083/* 11084 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11085 * any interesting requests and then jump to the real instruction 11086 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11087 */ 11088 .extern MterpCheckBefore 11089 EXPORT_PC 11090 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11091 adr lr, artMterpAsmInstructionStart + (244 * 128) // Addr of primary handler. 11092 mov x0, xSELF 11093 add x1, xFP, #OFF_FP_SHADOWFRAME 11094 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11095 11096/* ------------------------------ */ 11097 .balign 128 11098.L_ALT_op_capture_variable: /* 0xf5 */ 11099/* File: arm64/alt_stub.S */ 11100/* 11101 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11102 * any interesting requests and then jump to the real instruction 11103 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11104 */ 11105 .extern MterpCheckBefore 11106 EXPORT_PC 11107 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11108 adr lr, artMterpAsmInstructionStart + (245 * 128) // Addr of primary handler. 11109 mov x0, xSELF 11110 add x1, xFP, #OFF_FP_SHADOWFRAME 11111 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11112 11113/* ------------------------------ */ 11114 .balign 128 11115.L_ALT_op_create_lambda: /* 0xf6 */ 11116/* File: arm64/alt_stub.S */ 11117/* 11118 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11119 * any interesting requests and then jump to the real instruction 11120 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11121 */ 11122 .extern MterpCheckBefore 11123 EXPORT_PC 11124 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11125 adr lr, artMterpAsmInstructionStart + (246 * 128) // Addr of primary handler. 11126 mov x0, xSELF 11127 add x1, xFP, #OFF_FP_SHADOWFRAME 11128 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11129 11130/* ------------------------------ */ 11131 .balign 128 11132.L_ALT_op_liberate_variable: /* 0xf7 */ 11133/* File: arm64/alt_stub.S */ 11134/* 11135 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11136 * any interesting requests and then jump to the real instruction 11137 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11138 */ 11139 .extern MterpCheckBefore 11140 EXPORT_PC 11141 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11142 adr lr, artMterpAsmInstructionStart + (247 * 128) // Addr of primary handler. 11143 mov x0, xSELF 11144 add x1, xFP, #OFF_FP_SHADOWFRAME 11145 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11146 11147/* ------------------------------ */ 11148 .balign 128 11149.L_ALT_op_box_lambda: /* 0xf8 */ 11150/* File: arm64/alt_stub.S */ 11151/* 11152 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11153 * any interesting requests and then jump to the real instruction 11154 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11155 */ 11156 .extern MterpCheckBefore 11157 EXPORT_PC 11158 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11159 adr lr, artMterpAsmInstructionStart + (248 * 128) // Addr of primary handler. 11160 mov x0, xSELF 11161 add x1, xFP, #OFF_FP_SHADOWFRAME 11162 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11163 11164/* ------------------------------ */ 11165 .balign 128 11166.L_ALT_op_unbox_lambda: /* 0xf9 */ 11167/* File: arm64/alt_stub.S */ 11168/* 11169 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11170 * any interesting requests and then jump to the real instruction 11171 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11172 */ 11173 .extern MterpCheckBefore 11174 EXPORT_PC 11175 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11176 adr lr, artMterpAsmInstructionStart + (249 * 128) // Addr of primary handler. 11177 mov x0, xSELF 11178 add x1, xFP, #OFF_FP_SHADOWFRAME 11179 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11180 11181/* ------------------------------ */ 11182 .balign 128 11183.L_ALT_op_unused_fa: /* 0xfa */ 11184/* File: arm64/alt_stub.S */ 11185/* 11186 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11187 * any interesting requests and then jump to the real instruction 11188 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11189 */ 11190 .extern MterpCheckBefore 11191 EXPORT_PC 11192 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11193 adr lr, artMterpAsmInstructionStart + (250 * 128) // Addr of primary handler. 11194 mov x0, xSELF 11195 add x1, xFP, #OFF_FP_SHADOWFRAME 11196 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11197 11198/* ------------------------------ */ 11199 .balign 128 11200.L_ALT_op_unused_fb: /* 0xfb */ 11201/* File: arm64/alt_stub.S */ 11202/* 11203 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11204 * any interesting requests and then jump to the real instruction 11205 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11206 */ 11207 .extern MterpCheckBefore 11208 EXPORT_PC 11209 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11210 adr lr, artMterpAsmInstructionStart + (251 * 128) // Addr of primary handler. 11211 mov x0, xSELF 11212 add x1, xFP, #OFF_FP_SHADOWFRAME 11213 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11214 11215/* ------------------------------ */ 11216 .balign 128 11217.L_ALT_op_unused_fc: /* 0xfc */ 11218/* File: arm64/alt_stub.S */ 11219/* 11220 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11221 * any interesting requests and then jump to the real instruction 11222 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11223 */ 11224 .extern MterpCheckBefore 11225 EXPORT_PC 11226 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11227 adr lr, artMterpAsmInstructionStart + (252 * 128) // Addr of primary handler. 11228 mov x0, xSELF 11229 add x1, xFP, #OFF_FP_SHADOWFRAME 11230 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11231 11232/* ------------------------------ */ 11233 .balign 128 11234.L_ALT_op_unused_fd: /* 0xfd */ 11235/* File: arm64/alt_stub.S */ 11236/* 11237 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11238 * any interesting requests and then jump to the real instruction 11239 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11240 */ 11241 .extern MterpCheckBefore 11242 EXPORT_PC 11243 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11244 adr lr, artMterpAsmInstructionStart + (253 * 128) // Addr of primary handler. 11245 mov x0, xSELF 11246 add x1, xFP, #OFF_FP_SHADOWFRAME 11247 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11248 11249/* ------------------------------ */ 11250 .balign 128 11251.L_ALT_op_unused_fe: /* 0xfe */ 11252/* File: arm64/alt_stub.S */ 11253/* 11254 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11255 * any interesting requests and then jump to the real instruction 11256 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11257 */ 11258 .extern MterpCheckBefore 11259 EXPORT_PC 11260 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11261 adr lr, artMterpAsmInstructionStart + (254 * 128) // Addr of primary handler. 11262 mov x0, xSELF 11263 add x1, xFP, #OFF_FP_SHADOWFRAME 11264 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11265 11266/* ------------------------------ */ 11267 .balign 128 11268.L_ALT_op_unused_ff: /* 0xff */ 11269/* File: arm64/alt_stub.S */ 11270/* 11271 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11272 * any interesting requests and then jump to the real instruction 11273 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11274 */ 11275 .extern MterpCheckBefore 11276 EXPORT_PC 11277 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. 11278 adr lr, artMterpAsmInstructionStart + (255 * 128) // Addr of primary handler. 11279 mov x0, xSELF 11280 add x1, xFP, #OFF_FP_SHADOWFRAME 11281 b MterpCheckBefore // (self, shadow_frame) Note: tail call. 11282 11283 .balign 128 11284 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 11285 .global artMterpAsmAltInstructionEnd 11286artMterpAsmAltInstructionEnd: 11287/* File: arm64/footer.S */ 11288/* 11289 * =========================================================================== 11290 * Common subroutines and data 11291 * =========================================================================== 11292 */ 11293 11294 11295/* 11296 * We've detected a condition that will result in an exception, but the exception 11297 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 11298 * TUNING: for consistency, we may want to just go ahead and handle these here. 11299 */ 11300common_errDivideByZero: 11301 EXPORT_PC 11302#if MTERP_LOGGING 11303 mov x0, xSELF 11304 add x1, xFP, #OFF_FP_SHADOWFRAME 11305 bl MterpLogDivideByZeroException 11306#endif 11307 b MterpCommonFallback 11308 11309common_errArrayIndex: 11310 EXPORT_PC 11311#if MTERP_LOGGING 11312 mov x0, xSELF 11313 add x1, xFP, #OFF_FP_SHADOWFRAME 11314 bl MterpLogArrayIndexException 11315#endif 11316 b MterpCommonFallback 11317 11318common_errNegativeArraySize: 11319 EXPORT_PC 11320#if MTERP_LOGGING 11321 mov x0, xSELF 11322 add x1, xFP, #OFF_FP_SHADOWFRAME 11323 bl MterpLogNegativeArraySizeException 11324#endif 11325 b MterpCommonFallback 11326 11327common_errNoSuchMethod: 11328 EXPORT_PC 11329#if MTERP_LOGGING 11330 mov x0, xSELF 11331 add x1, xFP, #OFF_FP_SHADOWFRAME 11332 bl MterpLogNoSuchMethodException 11333#endif 11334 b MterpCommonFallback 11335 11336common_errNullObject: 11337 EXPORT_PC 11338#if MTERP_LOGGING 11339 mov x0, xSELF 11340 add x1, xFP, #OFF_FP_SHADOWFRAME 11341 bl MterpLogNullObjectException 11342#endif 11343 b MterpCommonFallback 11344 11345common_exceptionThrown: 11346 EXPORT_PC 11347#if MTERP_LOGGING 11348 mov x0, xSELF 11349 add x1, xFP, #OFF_FP_SHADOWFRAME 11350 bl MterpLogExceptionThrownException 11351#endif 11352 b MterpCommonFallback 11353 11354MterpSuspendFallback: 11355 EXPORT_PC 11356#if MTERP_LOGGING 11357 mov x0, xSELF 11358 add x1, xFP, #OFF_FP_SHADOWFRAME 11359 ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] 11360 bl MterpLogSuspendFallback 11361#endif 11362 b MterpCommonFallback 11363 11364/* 11365 * If we're here, something is out of the ordinary. If there is a pending 11366 * exception, handle it. Otherwise, roll back and retry with the reference 11367 * interpreter. 11368 */ 11369MterpPossibleException: 11370 ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] 11371 cbz x0, MterpFallback // If not, fall back to reference interpreter. 11372 /* intentional fallthrough - handle pending exception. */ 11373/* 11374 * On return from a runtime helper routine, we've found a pending exception. 11375 * Can we handle it here - or need to bail out to caller? 11376 * 11377 */ 11378MterpException: 11379 mov x0, xSELF 11380 add x1, xFP, #OFF_FP_SHADOWFRAME 11381 bl MterpHandleException // (self, shadow_frame) 11382 cbz w0, MterpExceptionReturn // no local catch, back to caller. 11383 ldr x0, [xFP, #OFF_FP_CODE_ITEM] 11384 ldr w1, [xFP, #OFF_FP_DEX_PC] 11385 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] 11386 add xPC, x0, #CODEITEM_INSNS_OFFSET 11387 add xPC, xPC, x1, lsl #1 // generate new dex_pc_ptr 11388 /* Do we need to switch interpreters? */ 11389 bl MterpShouldSwitchInterpreters 11390 cbnz w0, MterpFallback 11391 /* resume execution at catch block */ 11392 EXPORT_PC 11393 FETCH_INST 11394 GET_INST_OPCODE ip 11395 GOTO_OPCODE ip 11396 /* NOTE: no fallthrough */ 11397/* 11398 * Common handling for branches with support for Jit profiling. 11399 * On entry: 11400 * wINST <= signed offset 11401 * wPROFILE <= signed hotness countdown (expanded to 32 bits) 11402 * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) 11403 * 11404 * We have quite a few different cases for branch profiling, OSR detection and 11405 * suspend check support here. 11406 * 11407 * Taken backward branches: 11408 * If profiling active, do hotness countdown and report if we hit zero. 11409 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 11410 * Is there a pending suspend request? If so, suspend. 11411 * 11412 * Taken forward branches and not-taken backward branches: 11413 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 11414 * 11415 * Our most common case is expected to be a taken backward branch with active jit profiling, 11416 * but no full OSR check and no pending suspend request. 11417 * Next most common case is not-taken branch with no full OSR check. 11418 * 11419 */ 11420MterpCommonTakenBranchNoFlags: 11421 cmp wINST, #0 11422 b.gt .L_forward_branch // don't add forward branches to hotness 11423 tbnz wPROFILE, #31, .L_no_count_backwards // go if negative 11424 subs wPROFILE, wPROFILE, #1 // countdown 11425 b.eq .L_add_batch // counted down to zero - report 11426.L_resume_backward_branch: 11427 ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] 11428 add w2, wINST, wINST // w2<- byte offset 11429 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST 11430 REFRESH_IBASE 11431 ands lr, lr, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 11432 b.ne .L_suspend_request_pending 11433 GET_INST_OPCODE ip // extract opcode from wINST 11434 GOTO_OPCODE ip // jump to next instruction 11435 11436.L_suspend_request_pending: 11437 EXPORT_PC 11438 mov x0, xSELF 11439 bl MterpSuspendCheck // (self) 11440 cbnz x0, MterpFallback 11441 REFRESH_IBASE // might have changed during suspend 11442 GET_INST_OPCODE ip // extract opcode from wINST 11443 GOTO_OPCODE ip // jump to next instruction 11444 11445.L_no_count_backwards: 11446 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 11447 b.ne .L_resume_backward_branch 11448 mov x0, xSELF 11449 add x1, xFP, #OFF_FP_SHADOWFRAME 11450 mov x2, xINST 11451 EXPORT_PC 11452 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 11453 cbnz x0, MterpOnStackReplacement 11454 b .L_resume_backward_branch 11455 11456.L_forward_branch: 11457 cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? 11458 b.eq .L_check_osr_forward 11459.L_resume_forward_branch: 11460 add w2, wINST, wINST // w2<- byte offset 11461 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST 11462 GET_INST_OPCODE ip // extract opcode from wINST 11463 GOTO_OPCODE ip // jump to next instruction 11464 11465.L_check_osr_forward: 11466 mov x0, xSELF 11467 add x1, xFP, #OFF_FP_SHADOWFRAME 11468 mov x2, xINST 11469 EXPORT_PC 11470 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 11471 cbnz x0, MterpOnStackReplacement 11472 b .L_resume_forward_branch 11473 11474.L_add_batch: 11475 add x1, xFP, #OFF_FP_SHADOWFRAME 11476 strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 11477 ldr x0, [xFP, #OFF_FP_METHOD] 11478 mov x2, xSELF 11479 bl MterpAddHotnessBatch // (method, shadow_frame, self) 11480 mov wPROFILE, w0 // restore new hotness countdown to wPROFILE 11481 b .L_no_count_backwards 11482 11483/* 11484 * Entered from the conditional branch handlers when OSR check request active on 11485 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 11486 */ 11487.L_check_not_taken_osr: 11488 mov x0, xSELF 11489 add x1, xFP, #OFF_FP_SHADOWFRAME 11490 mov x2, #2 11491 EXPORT_PC 11492 bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) 11493 cbnz x0, MterpOnStackReplacement 11494 FETCH_ADVANCE_INST 2 11495 GET_INST_OPCODE ip // extract opcode from wINST 11496 GOTO_OPCODE ip // jump to next instruction 11497 11498 11499/* 11500 * Check for suspend check request. Assumes wINST already loaded, xPC advanced and 11501 * still needs to get the opcode and branch to it, and flags are in lr. 11502 */ 11503MterpCheckSuspendAndContinue: 11504 ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE 11505 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 11506 b.ne check1 11507 GET_INST_OPCODE ip // extract opcode from wINST 11508 GOTO_OPCODE ip // jump to next instruction 11509check1: 11510 EXPORT_PC 11511 mov x0, xSELF 11512 bl MterpSuspendCheck // (self) 11513 cbnz x0, MterpFallback // Something in the environment changed, switch interpreters 11514 GET_INST_OPCODE ip // extract opcode from wINST 11515 GOTO_OPCODE ip // jump to next instruction 11516 11517/* 11518 * On-stack replacement has happened, and now we've returned from the compiled method. 11519 */ 11520MterpOnStackReplacement: 11521#if MTERP_LOGGING 11522 mov x0, xSELF 11523 add x1, xFP, #OFF_FP_SHADOWFRAME 11524 sbfm x2, xINST, 0, 31 11525 bl MterpLogOSR 11526#endif 11527 mov x0, #1 // Signal normal return 11528 b MterpDone 11529 11530/* 11531 * Bail out to reference interpreter. 11532 */ 11533MterpFallback: 11534 EXPORT_PC 11535#if MTERP_LOGGING 11536 mov x0, xSELF 11537 add x1, xFP, #OFF_FP_SHADOWFRAME 11538 bl MterpLogFallback 11539#endif 11540MterpCommonFallback: 11541 mov x0, #0 // signal retry with reference interpreter. 11542 b MterpDone 11543 11544/* 11545 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 11546 * SP and LR. Here we restore SP, restore the registers, and then restore 11547 * LR to PC. 11548 * 11549 * On entry: 11550 * uint32_t* xFP (should still be live, pointer to base of vregs) 11551 */ 11552MterpExceptionReturn: 11553 mov x0, #1 // signal return to caller. 11554 b MterpDone 11555MterpReturn: 11556 ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] 11557 str x0, [x2] 11558 mov x0, #1 // signal return to caller. 11559MterpDone: 11560/* 11561 * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're 11562 * checking for OSR. If greater than zero, we might have unreported hotness to register 11563 * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE 11564 * should only reach zero immediately after a hotness decrement, and is then reset to either 11565 * a negative special state or the new non-zero countdown value. 11566 */ 11567 cmp wPROFILE, #0 11568 bgt MterpProfileActive // if > 0, we may have some counts to report. 11569 ldp fp, lr, [sp, #64] 11570 ldp xPC, xFP, [sp, #48] 11571 ldp xSELF, xINST, [sp, #32] 11572 ldp xIBASE, xREFS, [sp, #16] 11573 ldp xPROFILE, x27, [sp], #80 11574 ret 11575 11576MterpProfileActive: 11577 mov xINST, x0 // stash return value 11578 /* Report cached hotness counts */ 11579 ldr x0, [xFP, #OFF_FP_METHOD] 11580 add x1, xFP, #OFF_FP_SHADOWFRAME 11581 mov x2, xSELF 11582 strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 11583 bl MterpAddHotnessBatch // (method, shadow_frame, self) 11584 mov x0, xINST // restore return value 11585 ldp fp, lr, [sp, #64] 11586 ldp xPC, xFP, [sp, #48] 11587 ldp xSELF, xINST, [sp, #32] 11588 ldp xIBASE, xREFS, [sp, #16] 11589 ldp xPROFILE, x27, [sp], #80 11590 ret 11591 11592 .cfi_endproc 11593 .size ExecuteMterpImpl, .-ExecuteMterpImpl 11594 11595 11596